Real-time dynamic calibration system for digital-to-time converters

Abstract

The present invention discloses a real-time dynamic calibration system for a digital time converter, comprising: a first multi-mode frequency divider for dividing and outputting a clock inputted by a first multiplexing switch according to a frequency division ratio corresponding to a frequency division control word; a second multi-mode frequency divider for dividing and outputting a clock inputted by a second multiplexing switch according to a frequency division ratio corresponding to a frequency division control word; a third multiplexing switch for switching two outputs; a first digital time converter for delaying the output of the inputted clock; a second digital time converter for delaying the output of the inputted clock; and a feedback unit for performing feedback adjustment on the first and second digital time converters. The real-time dynamic calibration system for a digital time converter provided by the present invention does not affect the normal operation of the DTC during the DTC circuit calibration process. Furthermore, by introducing switching between two circuit channels, calibration errors introduced by calibration circuit mismatch are minimized to the greatest extent possible.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit design, and in particular relates to a real-time dynamic calibration system for a digital-to-time converter. Background Art

[0002] Affected by PVT (process, voltage, temperature), the threshold voltage, transconductance, and inverter flip threshold of MOS transistors may shift. Corresponding to the DTC (Digital-Time Converter) circuit, there is a certain mismatch between the DTC's digital control code value and the DTC's time delay. Therefore, time calibration is required when using DTC for time delay.

[0003] In traditional architectures, a time-to-digital converter (TDC) is used to measure the DTC. This TDC is then normalized to determine the actual DTC delay and generate a calibration coefficient. This is then used to modify the delay control word to achieve calibration. However, due to the TDC's limited time resolution and large quantization error, its use in DTC calibration inevitably introduces quantization noise, resulting in limited calibration accuracy. Furthermore, the TDC circuitry increases circuit complexity and lengthens the signal chain, impacting power consumption and reliability. Summary of the Invention

[0004] The present invention provides a real-time dynamic calibration system for a digital time converter to solve the above-mentioned technical problems, specifically adopting the following technical solutions:

[0005] A real-time dynamic calibration system for a digital-to-time converter, comprising:

[0006] A pre-divider is used to divide the input high-frequency clock into multiple clocks with different phases.

[0007] a first multiplexing switch connected to the pre-divider, wherein the first multiplexing switch selects a clock with a phase other than 0° from a plurality of clocks with different phases for output;

[0008] a second multiplexing switch connected to the prescaler, wherein the second multiplexing switch selects a clock with a phase of 0° from a plurality of clocks with different phases for output;

[0009] a first multi-mode frequency divider connected to the first multiplexing switch, the first multi-mode frequency divider dividing the clock input by the first multiplexing switch according to the frequency division ratio corresponding to the frequency division control word and outputting the divided clock;

[0010] a second multi-mode frequency divider connected to the second multiplexing switch, the second multi-mode frequency divider dividing the clock input by the second multiplexing switch according to the frequency division ratio corresponding to the frequency division control word and outputting the divided clock;

[0011] a third multiplexing switch connected to the first multi-mode frequency divider and the second multi-mode frequency divider, the third multiplexing switch being configured to perform an exchange connection between two outputs and two outputs;

[0012] a first digital-to-time converter connected to the third multiplexing switch, wherein the first digital-to-time converter delays and outputs an input clock according to a digital delay control code;

[0013] a second digital-to-time converter connected to the third multiplexing switch, wherein the second digital-to-time converter delays and outputs an input clock according to a digital delay control code;

[0014] A feedback unit is connected to the first digital-to-time converter and the second digital-to-time converter to perform feedback adjustment on the first digital-to-time converter and the second digital-to-time converter.

[0015] Furthermore, the feedback unit includes:

[0016] a phase detector connected to the first digital-to-time converter and the second digital-to-time converter, the phase detector being configured to detect a phase difference between two clocks input to the first digital-to-time converter and the second digital-to-time converter, and convert the phase difference into clocks with corresponding different duty cycles;

[0017] A low-pass filter is connected to the phase detector, and performs low-pass filtering on clocks with different duty cycles representing phase differences.

[0018] Furthermore, the low-pass filter outputs a DC level signal.

[0019] Furthermore, the real-time dynamic calibration system of the digital-to-time converter further comprises:

[0020] a fourth multiplexing switch connected to the first digital-to-time converter and the second digital-to-time converter, the fourth multiplexing switch being configured to select one of the inputs of the first digital-to-time converter and the second digital-to-time converter for output;

[0021] A driver is connected to the fourth multiplexing switch, and is used to improve the capacitive load driving capability of the input signal.

[0022] Furthermore, the real-time dynamic calibration system of the digital-to-time converter further comprises:

[0023] Sigma-Delta modulator, accumulates the input decimals;

[0024] A first adder is connected to the Sigma-Delta modulator, the first multi-mode frequency divider and the second multi-mode frequency divider. The first adder receives the accumulated integer sent by the Sigma-Delta modulator, adds the accumulated integer to the integer part of the division ratio, and then sends the superimposed division ratio to the first multi-mode frequency divider and the second multi-mode frequency divider.

[0025] Furthermore, the real-time dynamic calibration system of the digital-to-time converter further comprises:

[0026] A DTC decoding module is connected to the Sigma-Delta modulator, and receives the accumulated decimal sent by the Sigma-Delta modulator and converts the decimal phase into a digital delay control codeword corresponding to the DTC;

[0027] a fifth multiplexing switch, configured to select DTC delay control codewords corresponding to different phase delays;

[0028] a second adder connected to the DTC decoding module and the fifth multiplexing switch, the second adder being configured to superimpose the digital delay control codeword and the DTC delay control codeword output by the DTC decoding module and the fifth multiplexing switch;

[0029] A sixth multiplexing switch is connected to the DTC decoding module, the second adder, the first digital-to-time converter, and the second digital-to-time converter, and is used to exchange the two outputs with the two outputs.

[0030] Furthermore, the pre-divider divides the input high-frequency clock to output clocks with phases of 0°, 90°, 180° and 270°.

[0031] Furthermore, the first multiplexing switch selects one clock from the clocks with phases of 90°, 180° and 270° for output;

[0032] The second multiplexing switch selects the clock with a phase of 0° for output.

[0033] Furthermore, the fifth multiplexing switch is used to select DTC delay control codewords corresponding to phase delays of 90°, 180°, and 270°.

[0034] The present invention is beneficial in that it provides a real-time dynamic calibration system for a digital-to-time converter (DTC). This system does not affect the normal operation of the DTC during the calibration process. Furthermore, by switching between two circuit channels, it minimizes calibration errors introduced by calibration circuit mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 It is a schematic diagram of a real-time dynamic calibration system of a digital-to-time converter of the present invention. DETAILED DESCRIPTION

[0037] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] like Figure 1 The system is shown as a real-time dynamic calibration system for a digital-to-time converter according to the present application, which mainly includes: a pre-divider (PRE_DIV), a first multiplexing switch (MUX1), a second multiplexing switch (MUX2), a first multi-mode divider (MMD1), a second multi-mode divider (MMD2), a third multiplexing switch (MUX3), a first digital-to-time converter (DTC1), a second digital-to-time converter (DTC2), and a feedback unit.

[0039] The prescaler is used to divide the input high-frequency clock into multiple clocks with different phases. Specifically, the prescaler divides the input high-frequency clock into multiple clocks with different phases.

[0040] A first multiplexing switch is connected to a prescaler. The first multiplexing switch selects a clock with a phase other than 0° from among multiple clocks with different phases and outputs it. Specifically, the first multiplexing switch selects a clock from among clocks with phases of 90°, 180°, and 270° and outputs it. A second multiplexing switch is connected to the prescaler. The second multiplexing switch selects a clock with a phase of 0° from among multiple clocks with different phases and outputs it. Specifically, the second multiplexing switch selects a clock with a phase of 0° and outputs it. The first multiplexing switch and the second multiplexing switch are identical.

[0041] A first multi-mode frequency divider is connected to a first multiplexing switch. The first multi-mode frequency divider divides the clock input to the first multiplexing switch according to a frequency division ratio corresponding to a frequency division control word and outputs the divided clock. A second multi-mode frequency divider is connected to a second multiplexing switch. The second multi-mode frequency divider divides the clock input to the second multiplexing switch according to a frequency division ratio corresponding to the frequency division control word and outputs the divided clock.

[0042] The third multiplexing switch is connected to the first multi-mode frequency divider and the second multi-mode frequency divider, and is used for switching the two outputs and the two outputs.

[0043] Specifically, a first digital time converter is connected to the third multiplexing switch, and the first digital time converter delays the input clock according to the digital delay control code and outputs the clock. A second digital time converter is connected to the third multiplexing switch, and the second digital time converter delays the input clock according to the digital delay control code and outputs the clock. The first digital time converter and the second digital time converter are identical.

[0044] The third multiplexing switch is used to interchangeably connect the first multi-mode frequency divider and the second multi-mode frequency divider with the first digital-to-time converter and the second digital-to-time converter. Specifically, the third multiplexing switch connects the first multi-mode frequency divider with the first digital-to-time converter and the second multi-mode frequency divider with the second digital-to-time converter, or connects the first multi-mode frequency divider with the second digital-to-time converter and the second multi-mode frequency divider with the first digital-to-time converter.

[0045] The feedback unit is connected to the first digital-to-time converter and the second digital-to-time converter to perform feedback adjustment on the first digital-to-time converter and the second digital-to-time converter.

[0046] In an embodiment of the present application, the feedback unit includes a phase detector (PD) and a low-pass filter (LPF).

[0047] A phase detector is connected to the first digital-to-time converter and the second digital-to-time converter. The phase detector is configured to detect the phase difference between the two clocks input to the first and second digital-to-time converters and convert the phase difference into corresponding clocks with different duty cycles. A low-pass filter is connected to the phase detector and performs low-pass filtering on the clocks with different duty cycles representing the phase difference. Specifically, the low-pass filter outputs a DC level signal. This is regulated by negative feedback from the feedback unit.

[0048] As a preferred embodiment, the real-time dynamic calibration system of the digital-to-time converter further includes: a fourth multiplexing switch (MUX4) and a driver (DRV).

[0049] A fourth multiplexing switch is connected to the first digital-to-time converter and the second digital-to-time converter, and is configured to select one of the inputs of the first digital-to-time converter and the second digital-to-time converter for output. A driver is connected to the fourth multiplexing switch, and is configured to increase the capacitive load driving capability of the input signal.

[0050] As a preferred embodiment, the real-time dynamic calibration system of the digital-to-time converter further includes: a Sigma-Delta modulator (ΔΣmod) and a first adder (adder1).

[0051] The Sigma-Delta modulator is used to accumulate input decimals. A first adder is connected to the Sigma-Delta modulator, the first multi-mode frequency divider, and the second multi-mode frequency divider. The first adder receives the accumulated integer sent by the Sigma-Delta modulator, adds the accumulated integer to the integer portion of the division ratio, and then sends the added division ratio to the first multi-mode frequency divider and the second multi-mode frequency divider.

[0052] As a preferred embodiment, the real-time dynamic calibration system of the digital-to-time converter further includes: a DTC decoding module (dtc_encode), a fifth multiplexing switch (MUX5), a second adder (adder2) and a sixth multiplexing switch (MUX6).

[0053] The DTC decoding module is connected to the Sigma-Delta modulator. The DTC decoding module receives the accumulated fractional number sent by the Sigma-Delta modulator and converts the fractional phase into a digital delay control codeword corresponding to the DTC. The fifth multiplexer is used to select the DTC delay control codeword corresponding to different phase delays. Specifically, the fifth multiplexer is used to select the DTC delay control codeword corresponding to 90°, 180°, and 270° phase delays.

[0054] The second adder is connected to the DTC decoding module and the fifth multiplexing switch, and is used to superimpose the digital delay control codeword and the DTC delay control codeword output by the DTC decoding module and the fifth multiplexing switch.

[0055] The sixth multiplexing switch is connected to the DTC decoding module, the second adder, the first digital-to-time converter and the second digital-to-time converter, and is used to exchange the two outputs and the two outputs.

[0056] Specifically, the sixth multiplexing switch is used to connect the two inputs of the DTC decoding module to the first digital-to-time converter and the second digital-to-time converter in an exchange manner.

[0057] Specifically, a prescaler generates fixed phase differences (such as 90°, 180°, and 270°), which correspond to fixed time differences at specific frequencies (such as T / 4, T / 2, and 3*T / 4, where T is the period corresponding to the specific frequency). A first multiplexer then selects one of these three delayed outputs, with the output signal denoted as f1. f1 is then fed to a first multimode divider for frequency division by div_ratio (where div_ratio is the division ratio, with M representing the division ratio here). The first multimode divider then outputs f1_div = f1 / M, resulting in a total phase delay of tdealy1 = tdealy_mux1 + T / 4 + tdealy_MMD1, where tdealy_mux1 is the delay introduced by the first multiplexer, T / 4 indicates that the first multimode divider selects a 90° phase clock, and tdealy_MMD1 is the delay introduced by the first multimode divider. The following illustrates the principle using a 90° phase difference.

[0058] The clock corresponding to the 0° phase (the clock with a delay of 0) is sent to the second multiplexing switch. The output f2 of the second multiplexing switch is sent to the second multi-mode divider for div_ratio division, and f2_div=f2 / M is obtained. The total phase delay is tdealy2=tdealy_mux2+tdealy_MMD2, where tdealy_mux2 is the delay time caused by the second multiplexing switch, and tdealy_MMD2 is the delay time caused by the second multi-mode divider.

[0059] Since tdealy_mux1=tdealy_mux2 and tdealy_MMD1=tdealy_MMD2, f1_div lags behind f2_div by a delay time of T / 4.

[0060] If the clock corresponding to 90° is the working clock, and the third multiplexing switch selects f_div_1=f1_div, f_div_2=f2_div, then f_div_1 is delayed by code_dtc1*Kdtc1 after passing through the first digital time converter (where code_dtc1 is the digital delay control code word of the first digital time converter, and the code value is the delay control code value required for the normal operation of the DTC in the system). The total delay of f_dtc_1 output by the first digital time converter is tdealy3=tdealy_mux1+T / 4+tdealy_MMD1+tdealy_MUX4+ code_dtc1*Kdtc1, f_div_2 is delayed by code_dtc2*Kdtc2 after passing through the second digital-to-time converter (code_dtc2 is the digital delay control codeword of the second digital-to-time converter. Code_dtc2 consists of two parts: code_dtc1, which is used to offset the delay of the first digital-to-time converter, and code_90, which is used to offset the T / 2 delay difference). tdelay4=tdealy_mux2+tdealy_MMD2+tdealy_MUX4+code_dtc1*Kdtc2+code_90*Kdtc2.

[0061] Since Kdtc1=Kdtc2=Kdtc, f_dtc_1 lags behind f_dtc_2 by a delay time of T / 4-code_90*Kdtc.

[0062] The phase difference T / 4-code_90*Kdtc between f_dtc_1 and f_dtc_2 is detected by the phase detector and converted into a clock with a corresponding different duty cycle. The clock signal is converted into a DC signal phase_lpf through a low-pass filter, which is used to adjust the gain Kdtc of the first digital-to-time converter and the second digital-to-time converter.

[0063] If T / 4 - code_90 * Kdtc is greater than 0, phase_lpf increases, thereby increasing Kdtc, forcing T / 4 - code_90 * Kdtc to approach 0. Similarly, if T / 4 - code_90 * Kdtc is less than 0, phase_lpf decreases, thereby decreasing Kdtc, forcing T / 4 - code_90 * Kdtc to approach 0. Ultimately, through the negative feedback regulation of the loop, we obtain T / 4 = code_90 * Kdtc, and Kdtc = T / 4 ÷ code_90. Because T / 4 and code_90 are parameters unrelated to PVT, Kdtc does not change with PVT.

[0064] Because DTC is affected by PVT (process, voltage, and temperature), the same delay control codeword produces different DTC time delays under different PVT conditions. That is, the DTC gain, Kdtc, varies with PVT. Therefore, the DTC needs to be calibrated to maintain the same gain, Kdtc, under different PVT conditions. This allows the clock to be delayed for a specific time using a specific delay control word. In other words, there is a one-to-one correspondence between the delay control word and the corresponding time delay.

[0065] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation fall within the scope of protection of the present invention.

Claims

1. A real-time dynamic calibration system for a digital-to-time converter, characterized in that: Include: A pre-divider is used to divide the input high-frequency clock into multiple clocks with different phases. a first multiplexing switch connected to the pre-divider, wherein the first multiplexing switch selects a clock with a phase other than 0° from a plurality of clocks with different phases for output; a second multiplexing switch connected to the prescaler, wherein the second multiplexing switch selects a clock with a phase of 0° from a plurality of clocks with different phases for output; a first multi-mode frequency divider connected to the first multiplexing switch, the first multi-mode frequency divider dividing the clock input by the first multiplexing switch according to the frequency division ratio corresponding to the frequency division control word and outputting the divided clock; a second multi-mode frequency divider connected to the second multiplexing switch, the second multi-mode frequency divider dividing the clock input by the second multiplexing switch according to the frequency division ratio corresponding to the frequency division control word and outputting the divided clock; a third multiplexing switch connected to the first multi-mode frequency divider and the second multi-mode frequency divider, the third multiplexing switch being configured to perform an exchange connection between two outputs and two outputs; a first digital-to-time converter connected to the third multiplexing switch, wherein the first digital-to-time converter delays and outputs an input clock according to a digital delay control code; a second digital-to-time converter connected to the third multiplexing switch, wherein the second digital-to-time converter delays and outputs an input clock according to a digital delay control code; A feedback unit is connected to the first digital-to-time converter and the second digital-to-time converter to perform feedback adjustment on the first digital-to-time converter and the second digital-to-time converter.

2. The real-time dynamic calibration system for a digital-to-time converter according to claim 1, characterized in that: The feedback unit comprises: a phase detector connected to the first digital-to-time converter and the second digital-to-time converter, the phase detector being configured to detect a phase difference between two clocks input to the first digital-to-time converter and the second digital-to-time converter, and convert the phase difference into clocks with corresponding different duty cycles; A low-pass filter is connected to the phase detector, and performs low-pass filtering on clocks with different duty cycles representing phase differences.

3. The real-time dynamic calibration system for a digital-to-time converter according to claim 2, characterized in that: The low-pass filter outputs a DC level signal.

4. The real-time dynamic calibration system for a digital-to-time converter according to claim 2, wherein: The real-time dynamic calibration system of the digital-to-time converter further comprises: a fourth multiplexing switch connected to the first digital-to-time converter and the second digital-to-time converter, the fourth multiplexing switch being configured to select one of the inputs of the first digital-to-time converter and the second digital-to-time converter for output; A driver is connected to the fourth multiplexing switch, and is used to improve the capacitive load driving capability of the input signal.

5. The real-time dynamic calibration system for a digital-to-time converter according to claim 4, characterized in that: The real-time dynamic calibration system of the digital-to-time converter further comprises: Sigma-Delta modulator, accumulates the input decimals; A first adder is connected to the Sigma-Delta modulator, the first multi-mode frequency divider and the second multi-mode frequency divider. The first adder receives the accumulated integer sent by the Sigma-Delta modulator, adds the accumulated integer to the integer part of the division ratio, and then sends the superimposed division ratio to the first multi-mode frequency divider and the second multi-mode frequency divider.

6. The real-time dynamic calibration system for a digital-to-time converter according to claim 5, characterized in that: The real-time dynamic calibration system of the digital-to-time converter further comprises: A DTC decoding module is connected to the Sigma-Delta modulator, and receives the accumulated decimal sent by the Sigma-Delta modulator and converts the decimal phase into a digital delay control codeword corresponding to the DTC; a fifth multiplexing switch, configured to select DTC delay control codewords corresponding to different phase delays; a second adder connected to the DTC decoding module and the fifth multiplexing switch, the second adder being configured to superimpose the digital delay control codeword and the DTC delay control codeword output by the DTC decoding module and the fifth multiplexing switch; A sixth multiplexing switch is connected to the DTC decoding module, the second adder, the first digital-to-time converter, and the second digital-to-time converter, and is used to exchange the two outputs with the two outputs.

7. The real-time dynamic calibration system for a digital-to-time converter according to claim 6, characterized in that: The pre-divider divides the input high-frequency clock to output clocks with phases of 0°, 90°, 180° and 270°.

8. The real-time dynamic calibration system for a digital-to-time converter according to claim 7, characterized in that: The first multiplexing switch selects one clock from the clocks with phases of 90°, 180° and 270° for output; The second multiplexing switch selects the clock with a phase of 0° for output.

9. The real-time dynamic calibration system for a digital-to-time converter according to claim 8, characterized in that: The fifth multiplexing switch is used to select the DTC delay control codewords corresponding to the phase delays of 90°, 180° and 270°.

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