Data communication method, microprocessor and electronic equipment

Abstract

The embodiments of the present application provide a data communication method, a microprocessor, and an electronic device, relating to the field of data communication technology, and capable of improving data communication capabilities while ensuring data transmission reliability between multiple processor cores. A first processor core controls M data to be transmitted to be stored sequentially at physical addresses corresponding to N array units; after at least one frame of data to be transmitted is stored at the physical address corresponding to the first array unit, the physical address corresponding to the first array unit is controlled to be changed to state information having a target identifier, where the first array unit is any one of the N array units; a first interrupt instruction is sent to a second processor core, so that after receiving the first interrupt instruction, the second processor core obtains a target array unit having a target identifier from the N array units, obtains target physical addresses corresponding to the target array units in sequence according to an association relationship, and reads the data to be transmitted from the target physical addresses in sequence.

Description

Technical Field

[0001] The present application relates to the field of data communication technology, and in particular to a data communication method, a microprocessor, and an electronic device. Background Art

[0002] Currently, multiple processor cores in embedded systems typically utilize an asymmetric multi-processor (AMP) architecture. In an AMP architecture, the embedded system includes multiple processor cores, each with different hardware parameters. Each core independently executes different tasks and can run different operating systems. Therefore, an efficient and reliable data communication method is required between the multiple cores in an AMP architecture to meet the practical needs of data exchange between the different cores.

[0003] In existing technologies, data communication between multiple processor cores typically relies on a Mailbox hardware controller to exchange data between the processor cores. However, due to limitations in the Mailbox peripheral hardware, such as bandwidth and channel count, data transmission performance cannot meet actual requirements and data transmission reliability is low. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present application is to provide a data communication method, a microprocessor, and an electronic device that can improve data communication capabilities while ensuring the reliability of data transmission between multiple processor cores.

[0005] To achieve the above-mentioned objectives, a first aspect of an embodiment of the present application provides a data communication method, which is applied to a microprocessor, the microprocessor including a first processor core, a second processor core, and a memory, the memory being communicatively connected to the first processor core and the second processor core, respectively, the memory including a first memory space and a second memory space, the first memory space being a memory space accessible to both the first processor core and the second processor core; the second memory space being a memory space accessible to the second processor core; the first memory space including N array units, where N is a positive integer; each of the N array units is associated with a corresponding physical address, each physical address being within an address range of the first memory space, and the second memory space storing an association relationship between the physical addresses corresponding to each array unit; the method comprising:

[0006] Controlling, by the first processor core, M data to be transmitted to be stored sequentially in physical addresses corresponding to N array units, where M is a positive integer and M≤N;

[0007] After at least one frame of data to be transmitted is stored in the physical address corresponding to the first array unit, controlling the physical address corresponding to the first array unit to be changed to state information having a target identifier, the first array unit being any one of the N array units;

[0008] When preset conditions are met, a first interrupt instruction is sent to the second processor core, so that after receiving the first interrupt instruction, the second processor core obtains a target array unit with a target identifier from the N array units, and obtains the target physical address corresponding to the target array unit in sequence according to the association relationship, and reads the data to be transmitted from the target physical address in sequence.

[0009] The microprocessor's memory is divided into a first memory space accessible to both the first and second processor cores, and a second memory space accessible only to the second processor core. At least one array unit is stored in the first memory space, each array unit being associated with a corresponding physical address, and these physical addresses all fall within the address range of the first memory space. Meanwhile, the second memory space stores the association relationship between the physical addresses corresponding to each array unit. Thus, when the first processor core and the second processor core in the microprocessor communicate, the first processor core controls the sequential storage of data to be transmitted at the physical address corresponding to at least one array unit. After at least one frame of data to be transmitted is stored at the physical address corresponding to the array unit, the first processor core controls the physical address corresponding to the array unit to be changed to state information having a target identifier. Then, under preset conditions, a first interrupt instruction is sent to the second processor core. Upon receiving the first interrupt instruction, the second processor core obtains a target array unit having a target identifier from the at least one array unit, obtains a target physical address corresponding to the target array unit based on the association relationship between the physical addresses corresponding to each array unit, and finally reads the data to be transmitted sequentially from the target physical addresses. Since the data bandwidth and performance of memory are far greater than those of other peripheral Mailbox hardware controllers, using memory as a communication channel between processor cores can improve data communication capabilities while ensuring data transmission reliability.

[0010] In a possible implementation, the first memory space further stores shared resource information, and the shared resource information includes the storage space size of the N array units;

[0011] Before controlling the first processor core to sequentially store the M data to be transmitted into the physical addresses corresponding to the N array units, the method further includes:

[0012] A second interrupt instruction is sent to the second processor core, so that after receiving the second interrupt instruction, the second processor core configures a corresponding physical address for each array unit from the first memory space based on the storage space size, and obtains an association relationship between the physical addresses corresponding to each array unit.

[0013] The second processor core configures a corresponding physical address for each array unit from the first memory space, so that the data to be transmitted can be directly stored in the first memory space. The second processor core can obtain the data to be transmitted only based on the association relationship between the physical addresses corresponding to each array unit, which can improve the data communication capability between processor cores.

[0014] In a possible implementation, the microprocessor further includes a sensor and a controller, the controller is communicatively connected to the sensor and the first processor core respectively, and the controller includes a register corresponding to the sensor;

[0015] Before controlling the first processor core to sequentially store the M data to be transmitted into the physical addresses corresponding to the N array units, the method further includes:

[0016] Configure the physical addresses corresponding to N array units into registers;

[0017] Controlling, by the first processor core, M data to be transmitted to be stored sequentially in physical addresses corresponding to N array units, including:

[0018] A start command is sent to the sensor, so that after receiving the start command, the sensor collects the data to be transmitted, obtains the physical addresses corresponding to the N array units from the register, and stores the data to be transmitted in the physical addresses corresponding to the N array units in sequence.

[0019] A second aspect of an embodiment of the present application provides a data communication method, which is applied to a microprocessor. The microprocessor includes: a first processor core, a second processor core, and a memory, the memory being communicatively connected to the first processor core and the second processor core respectively, the memory including a first memory space and a second memory space, the first memory space being a memory space accessible to both the first processor core and the second processor core; the second memory space being a memory space accessible to the second processor; the first memory space including N array units, where N is a positive integer; each of the N array units is associated with a corresponding physical address, each physical address being within an address range of the first memory space, and the second memory space storing an association relationship between the physical addresses corresponding to each array unit; data to be transmitted is sequentially stored in the storage space corresponding to the physical addresses of the N array units, and the array units storing the data to be transmitted are state information having a target identifier; the method includes:

[0020] After receiving the first interrupt instruction sent by the first processor core, the second processor core obtains a target array unit with a target identifier from the N array units;

[0021] The target physical addresses corresponding to the target array units are obtained in sequence according to the association relationship, and the data to be transmitted are read in sequence from the target physical addresses.

[0022] In a possible implementation, after sequentially reading the data to be transmitted from the target physical address, the method further includes: clearing status information in the target array unit, and reconfiguring the physical address for the target array unit from the free storage space of the first memory space.

[0023] The second processor core reconfigures the physical address for the target array unit from the free storage space of the first memory space, which can be used for data storage in the next data communication process, thereby preventing the space occupied by the previous physical address from being insufficient, resulting in a problem of insufficient storage space.

[0024] In a possible implementation, after sequentially reading the data to be transmitted from the target physical address, the method further includes:

[0025] The array unit at the end position of reading the data to be transmitted is obtained, and a prompt mark is configured in the array unit at the end position, the prompt mark being used to indicate the starting reading position of the data to be transmitted read next time by the second processor core.

[0026] The second processor core configures a hint mark in the array unit at the end position of the data read this time, so as to facilitate data reading from the array with the hint mark next time, thereby improving the efficiency of data reading.

[0027] In a possible implementation, the shared resource information includes a preset polling quantity M, where M is a positive integer;

[0028] Read the data to be transmitted from the target physical address, including:

[0029] Get the polling quantity M from the shared resource information;

[0030] The data to be transmitted is read sequentially from the target physical address according to the preset polling quantity M.

[0031] When the second processor core reads data to be transmitted, it can simultaneously poll and read multiple data packets in the event of an interrupt, which can reduce the overhead of the second processor core in handling interrupt exceptions and greatly improve the data processing capability of the second processor core.

[0032] In one possible implementation, the microprocessor further includes a display controller, and the display controller is communicatively connected to the second processor core;

[0033] After reading the data to be transmitted from the target physical address, the method further includes:

[0034] The data to be transmitted is processed and the processing result is sent to the display controller so that the display controller displays the processing result.

[0035] In a third aspect of an embodiment of the present application, a microprocessor is provided, which includes a first processor core, a second processor core, and a memory, wherein the memory is communicatively connected to the first processor core and the second processor core respectively, and the memory includes a first memory space and a second memory space, wherein the first memory space is a memory space accessible to both the first processor core and the second processor core; the second memory space is a memory space accessible to the second processor core; the first memory space includes N array units, wherein N is a positive integer; each of the N array units is associated with a corresponding physical address, and each physical address is within an address range of the first memory space, and the second memory space stores an association relationship between the physical addresses corresponding to each array unit; wherein,

[0036] A first processor core, used in the data communication method provided in the first aspect of the embodiment of the present application;

[0037] The second processor core is used in the data communication method provided in the second aspect of the embodiment of the present application.

[0038] According to a fourth aspect of the embodiments of the present application, an electronic device is provided. The electronic device includes the microprocessor in the embodiments of the present application, and the microprocessor is used to execute the data communication method provided in the embodiments of the present application.

[0039] In a fifth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the data communication method provided in the embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of a microprocessor provided in an embodiment of the present application Figure 1 ;

[0041] Figure 2 A data communication method according to an embodiment of the present invention Figure 1 ;

[0042] Figure 3 A schematic diagram of the structure of a microprocessor provided in an embodiment of the present application Figure 2 ;

[0043] Figure 4 A data communication method according to an embodiment of the present invention Figure 2 ;

[0044] Figure 5 A schematic diagram of the structure of a microprocessor provided in an embodiment of the present application Figure 3 ;

[0045] Figure 6 A data communication method according to an embodiment of the present invention Figure 3 . DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0047] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way. In the description of the embodiments of the present application, unless otherwise specified, "at least one" means one or more, and "a plurality of" means two or more.

[0048] Currently, the multiple processor core architecture in embedded systems usually adopts the asymmetric multi-processor architecture (AMP). In the AMP architecture, the embedded system includes multiple processor cores, each of which has different hardware parameters. Each processor core runs different tasks relatively independently, and each processor core can run a different operating system.

[0049] This application scenario differs significantly from the typical server-based multi-core architecture, which is typically a symmetric multi-processor (SMP) architecture. In an SMP architecture, each processor core has identical hardware parameters and all run on the same operating system. In an AMP architecture, efficient and reliable data communication between multiple cores is required to meet the practical needs of data exchange between them.

[0050] In the prior art, data communication between multiple processor cores typically utilizes a Mailbox hardware controller for data communication and exchange. A Mailbox is a hardware controller on a SoC chip, typically consisting of one or more transmit channels, receive channels, and a set of control registers. Mailbox is a commonly used technology in the industry for data communication between processor cores, essentially enabling inter-core data communication using hardware transmit and receive channels. However, this technology is limited by hardware performance bandwidth limitations and channel count limitations of the Mailbox peripheral. Hardware bandwidth limitations can lead to poor communication performance, particularly in the multimedia audio and video field. Due to the large volumes of data collected and analyzed in this field, traditional mailbox methods struggle to meet communication performance requirements and can also result in data loss. Furthermore, the limited number of hardware channels restricts application data flows, requiring large amounts of data to be queued and processed by the hardware, severely impacting data processing capabilities.

[0051] In order to solve the above problems, an embodiment of the present application provides a data communication method, which uses a memory space accessible to multiple processor cores as a communication channel between processor cores, instead of using a Mailbox hardware controller as a communication channel between processor cores. Since the data bandwidth and performance of the memory are far greater than those of other hardware controllers, using the memory as a communication channel between processor cores can improve data communication capabilities while ensuring data transmission reliability.

[0052] The data communication method provided in the embodiment of the present application is applied to a microprocessor. Figure 1 A schematic diagram of the structure of a microprocessor is provided for the embodiment of the present application. Figure 1 As shown, the microprocessor includes a first processor core 11, a second processor core 12 and a memory 13, and the memory 13 is communicatively connected to the first processor core 11 and the second processor core 12 respectively.

[0053] The memory includes a first memory space and a second memory space. The first memory space is a memory space accessible to both the first processor core and the second processor core, and the second memory space is a memory space accessible to the second processor core.

[0054] The first memory space includes N array units, where N is a positive integer; each of the N array units is associated with a corresponding physical address, and each physical address is located in the address range of the first memory space. The second memory space stores the association relationship between the physical addresses corresponding to each array unit.

[0055] In addition, the microprocessor's memory also includes a third memory space, which is a memory space accessible to the first processor core. The third memory space stores a first program, which can be called a data acquisition program. The execution steps of the first processor core in the following embodiments of the present application are all performed by the first processor core loading the first program during the specific implementation process. The second memory space stores a second program, which can be called a data analysis program. The execution steps of the second processor core in the following embodiments of the present application are all performed by the second processor core loading the second program during the specific implementation process.

[0056] It should be noted that the data communication method provided in the embodiment of the present application abandons the complex Linux operating system, and reduces the scheduling overhead brought by the Linux operating system by allowing the data acquisition program to run directly on the first processor core and the data analysis program to run directly on the second processor core. This is because the applications running on the traditional Linux operating system are all running at the low security level of the hardware, while the Linux operating system itself runs at a high security level. For example, in the armv8 architecture, the application runs at the low-privilege level EL0, while the Linux operating system runs at the high-privilege level EL1. In this way, when the application obtains the service of the high-privilege level EL1 of the Linux operating system from the low-privilege level EL0, it is necessary to trigger the processor hardware exception mechanism, which will generate a series of software and hardware exception switching overheads. However, by running the data acquisition program and the data analysis program directly in the high-privilege level EL1 of the hardware, the embodiment of the present application can avoid the occurrence of the processor hardware exception mechanism and significantly improve the data processing capability of the processor core.

[0057] Based on the above introduction to the hardware architecture and software architecture of the microprocessor, the embodiment of the present application provides a data communication method. The data communication method provided by the embodiment of the present application is described below in conjunction with the accompanying drawings. Figure 2 As shown, the data communication method includes the following steps:

[0058] Step 201: Control, through the first processor core, M data to be transmitted to be stored in sequence in physical addresses corresponding to N array units.

[0059] Wherein, M is a positive integer, and M≤N, and a piece of data to be transmitted can be a frame of image or a data packet.

[0060] A physical address refers to the storage of information in bytes in memory. To correctly store or retrieve information, each byte unit is assigned a unique memory address, which is called a physical address. In the embodiments of the present application, the physical address corresponding to each array unit can be a single physical address or a range of physical addresses, which are not specifically limited in the embodiments of the present application.

[0061] Optional, such as Figure 3 As shown, the microprocessor further includes a sensor 14 and a controller 15. The controller 15 is in communication with the sensor 14 and the first processor core 11, respectively. The controller 15 includes a register 151 corresponding to the sensor 14. Before executing step 201, the first processor core pre-configures the physical addresses corresponding to the N array units into the register.

[0062] In actual execution, the implementation process of the above step 201 of controlling the first processor core to sequentially store the M data to be transmitted into the physical addresses corresponding to the N array units may be:

[0063] A start command is sent to the sensor. After receiving the start command, the sensor collects the data to be transmitted, obtains the physical addresses corresponding to the N array units from the register, and stores the data to be transmitted in the physical addresses corresponding to the N array units in sequence. In this way, the M data to be transmitted can be controlled to be stored in the physical addresses corresponding to the N array units in sequence.

[0064] The sensor may be an image acquisition sensor, a temperature sensor, a voltage sensor, etc., and correspondingly, the data to be transmitted may be an image, temperature data, pressure data, etc.

[0065] Step 202 : After at least one frame of data to be transmitted is stored in the physical address corresponding to the first array unit, the first processor core controls the physical address corresponding to the first array unit to be changed to state information having a target identifier.

[0066] Among them, the first array unit is any one of the N array units, the status information is 64 bytes of information, and one byte of information in the status information is used to indicate whether the data to be transmitted is stored in the physical address corresponding to the array unit. If the data to be transmitted is stored in the physical address corresponding to the array unit, the control changes the byte information to the target identifier.

[0067] In a specific implementation, the third storage space also includes a management program, which can also be called a "meta-ring". The first processor core monitors the usage of the physical addresses in each array unit by loading the management program, and after monitoring that at least one frame of data to be transmitted is stored in the physical address corresponding to the first array unit, controls the physical address corresponding to the first array unit to be changed to status information with a target identifier.

[0068] Step 203: The first processor core sends a first interrupt instruction to the second processor core when a preset condition is met;

[0069] The preset conditions include: a preset time interval or a condition where the storage space corresponding to the physical address of the array unit is greater than a preset space size, etc., which are not specifically limited in the present embodiment. An interrupt instruction is an action during normal operation of the processor to stop the current operation and perform other special operations. It is called an interrupt and is responsible for jumping instructions.

[0070] Step 204: After receiving the first interrupt instruction, the second processor core obtains a target array unit with a target identifier from the N array units, obtains the target physical address corresponding to the target array unit in sequence according to the association relationship, and reads the data to be transmitted from the target physical address in sequence.

[0071] The data communication method provided in an embodiment of the present application is a method for dividing a memory of a microprocessor into a first memory space accessible to both a first processor core and a second processor core, and a second memory space accessible only to the second processor core. The method stores at least one array unit in the first memory space, each array unit being associated with a corresponding physical address, and each of these physical addresses falling within the address range of the first memory space. Furthermore, the method stores the association relationship between the physical addresses corresponding to each array unit in the second memory space. Thus, when the first processor core and the second processor core in the microprocessor communicate, the first processor core controls the sequential storage of data to be transmitted at the physical address corresponding to the at least one array unit. After at least one frame of data to be transmitted is stored at the physical address corresponding to the array unit, the first processor core controls the physical address corresponding to the array unit to be changed to state information having a target identifier. Then, under a preset condition, the method sends a first interrupt instruction to the second processor core. Upon receiving the first interrupt instruction, the second processor core obtains a target array unit having a target identifier from the at least one array unit, obtains a target physical address corresponding to the target array unit based on the association relationship between the physical addresses corresponding to each array unit, and finally reads the data to be transmitted sequentially from the target physical addresses. Since the data bandwidth and performance of memory are far greater than those of other hardware controllers, using memory as a communication channel between processor cores can improve data communication capabilities while ensuring data transmission reliability.

[0072] At the same time, the data communication method provided in the embodiments of the present application can be widely applied in the embedded field, and can significantly improve the communication performance between processor cores in embedded systems, system stability, and data reliability. At the same time, the standard application programming interface (API) in embedded systems is used to reduce the difficulty of software development, achieve standardized communication between processor cores in an AMP architecture, reduce the time cost and complexity of software development, and significantly improve software development efficiency. Furthermore, the data communication method provided in the embodiments of the present application can also be used for communication between processor cores in an SMP architecture, similarly ensuring data transmission reliability while improving data communication capabilities.

[0073] Optionally, the first memory space also stores shared resource information, which includes the storage space size of N array units. Figure 4 As shown, before the above step 201 controls the first processor core to sequentially store the M data to be transmitted into the physical addresses corresponding to the N array units, it also includes:

[0074] Step 401: The first processor core sends a second interrupt instruction to the second processor core.

[0075] Step 402: After receiving the second interrupt instruction, the second processor core configures a corresponding physical address for each array unit from the first memory space based on the storage space size, and obtains an association relationship between the physical addresses corresponding to each array unit.

[0076] Among them, the storage space size of the N array units in the shared resource information is pre-configured. The storage space size here can be configured according to the application scenario of data communication. If the scenario is a large amount of data transmission, a higher storage space size can be configured; if the scenario is a large amount of data transmission, a higher storage space size can be configured; or a smaller storage space size can be configured.

[0077] For example, if the storage space size of N array units in the shared resource information is 2GB, the second processor core allocates a 2GB space address range from the first memory space, and then configures a corresponding physical address for each array unit from the allocated 2GB space address range.

[0078] The second processor core configures a corresponding physical address for each array unit from the first memory space, so that the data to be transmitted can be directly stored in the first memory space. The second processor core can obtain the data to be transmitted based solely on the association between the physical addresses corresponding to each array unit, thereby improving the data communication capabilities between processor cores. In addition, the shared resource information also includes memory configuration data, such as the size of the first memory space, the size of the second memory space, the size of the third memory space, the storage space size of the array unit, the size of the buffer-ring software queue, etc., and also includes some control information, such as the polling quantity of the second processor core and the preset conditions for the first processor core to send the first interrupt instruction.

[0079] It should be noted that after the second processor core configures the corresponding physical address for each array unit, it will also store the physical address corresponding to each array unit in the first memory space for calling by the first processor core, and at the same time store the association relationship between the physical addresses corresponding to each array unit in the second memory space for reading the data to be transmitted. In the specific implementation process, a software queue is stored in the second memory space, which can be called a "buffer-ring". Each node of the software queue stores a continuous physical address. After receiving the first mid-end instruction, the second processor core will configure the physical address stored in each node into the array unit.

[0080] The software queue can employ a dual-circular queue design, and its size can be flexibly configured within the shared resource information. Adjusting the software queue size when data transmission volume is high can effectively improve data reliability and prevent data loss when the second processor core's processing power is insufficient. Furthermore, the second memory space also includes a second hypervisor, which the second processor core loads to maintain and manage the software queue.

[0081] Optionally, after executing step 204, the method further includes: the second processor core clearing status information in the target array unit, and reconfiguring a physical address for the target array unit from the free storage space of the first memory space.

[0082] It is understandable that, in order to carry out the next data communication process, the second processor core will reconfigure the physical address for the target array unit from the storage space in the first memory space after reading the data to be transmitted this time.

[0083] Optionally, after executing step 204 , the second processor core further obtains the array unit at the end position of reading the data to be transmitted, and configures a prompt mark in the array unit at the end position.

[0084] The hint identifier is used to indicate the starting reading position of the next data to be transmitted by the second processor core. It is understandable that the second processor core configures the hint identifier in the array cell at the end position of the data read this time, so that the next data read can start from the array with the hint identifier, thereby improving data reading efficiency.

[0085] Optionally, the shared resource information includes a preset polling quantity M, where M is a positive integer;

[0086] Reading the data to be transmitted from the target physical address includes: obtaining a polling quantity M from the shared resource information, and then sequentially reading the data to be transmitted from the target physical address according to the preset polling quantity M.

[0087] When the second processor core reads the data to be transmitted, it adopts an interrupt polling mechanism to read the data. This ensures that the second processor core can poll and read multiple data packets at the same time in the case of an interrupt, which can reduce the overhead of the second processor core in handling interrupt exceptions and greatly improve the data processing capability of the second processor core.

[0088] Optional, such as Figure 5 As shown, the microprocessor further includes a display controller 16 , which is communicatively connected to the second processor core.

[0089] After executing step 204 , the second processor core further performs computation processing on the data to be transmitted, and sends the processing result to the display controller so that the display controller displays the processing result.

[0090] As can be seen from the execution methods of the first and second processor cores described above, different processor cores perform different types of tasks depending on the nature of the tasks performed by the microprocessor. In the embodiments of the present application, the first processor core primarily performs tasks such as data acquisition, while the second processor core primarily handles tasks such as data analysis and calculation. This has the following advantages: a. Different processor cores handle different tasks, maximizing the utilization of processor resources, memory resources, and input / output (IO) resources. b. This significantly improves IO throughput and maximizes the utilization of hardware resources of the sensor's external devices. Because a dedicated application is always available to process the raw data collected by the device, the device will not be forced into a waiting state due to the current processor core performing other tasks, such as calculations. This ensures timely acquisition of device data, significantly improving IO data throughput. This also maximizes the real-time and security of the data, avoiding data loss due to waiting for processor resources. c. It significantly enhances the processor core's ability to analyze and process raw data. The dedicated data analysis application only performs calculations and analysis on the raw data and does not handle other IO-related tasks. This ensures that program execution is not interrupted by interrupts from external IO devices, thereby significantly improving the processor core's ability to process data concurrently.

[0091] Based on the hardware architecture and software architecture provided in the above embodiments, the present application also provides a data communication method, such as Figure 6 As shown, the method includes the following steps:

[0092] Step 601: The first processor core sends a second interrupt instruction to the second processor core;

[0093] Step 602: After receiving the second interrupt instruction, the second processor core configures a corresponding physical address for each array unit from the first memory space based on the storage space size, and obtains an association relationship between the physical addresses corresponding to each array unit.

[0094] Step 603: The first processor core configures the physical addresses corresponding to the N array units into a register;

[0095] Step 604: The first processor core sends a start instruction to the sensor, so that after receiving the start instruction, the sensor collects the data to be transmitted, obtains the physical addresses corresponding to the N array units from the register, and stores the data to be transmitted in the physical addresses corresponding to the N array units in sequence.

[0096] Step 605: After at least one frame of data to be transmitted is stored in the physical address corresponding to the first array unit, the first processor core controls the physical address corresponding to the first array unit to be changed to state information having a target identifier, where the first array unit is any one of the N array units.

[0097] Step 606: The first processor core sends a first interrupt instruction to the second processor core when a preset condition is met.

[0098] Step 607: After receiving the first interrupt instruction, the second processor core obtains a target array unit having a target identifier from the N array units;

[0099] Step 608: The second processor core sequentially obtains the target physical address corresponding to the target array unit according to the association relationship;

[0100] Step 609: The second processor core obtains the polling number M from the shared resource information, and sequentially reads the data to be transmitted from the target physical address according to the preset polling number M.

[0101] Step 610: The second processor core clears the status information in the target array unit and reconfigures the physical address for the target array unit from the free storage space in the first memory space.

[0102] Step 611: The second processor core obtains the array unit at the end position of reading the data to be transmitted, and configures a prompt mark in the array unit at the end position, the prompt mark is used to indicate the starting reading position of the data to be transmitted next time read by the second processor core.

[0103] Step 612: The second processor core performs computation processing on the data to be transmitted, and sends the processing result to the display controller so that the display controller displays the processing result.

[0104] The specific execution process of the above steps 601 to 612 can be found in the description of the above embodiment. The implementation principles and technical effects are similar and will not be repeated here.

[0105] It should be noted that, before step 601, the data communication method further includes the following process:

[0106] (1) Insert the sensor into the corresponding physical interface on the microprocessor motherboard, and power on the motherboard to start the commonly used embedded boot program (uboot);

[0107] (2) Set the boot parameters in the uboot command line. The main parameters include the location of the image program in the Linux kernel on the disk, the location of the device description data block, the serial port parameters of the serial port controller, the disk partition of the root file system, etc.

[0108] (3) Execute the booti command of uboot to start the Linux operating system from the first processor core.

[0109] (4) Log in to the first processor core through the serial port of the first processor core.

[0110] (5) Start the program of the first processor core and the program of the second processor core respectively: the first processor core starts the data acquisition program, and the second processor core starts the data analysis program.

[0111] (6) The data acquisition program initializes the shared resource table, including: setting the first memory space to a memory type accessible to both the first processor core and the second processor core, configuring the memory size of N array units, etc.

[0112] It should be noted that the above process is the startup process of the hardware and software in the microprocessor before the data communication method is executed. In the startup process of the above-mentioned data acquisition program and data analysis program, uboot is used as the boot program before the system starts to guide the application to execute directly on the hardware. Uboot uses the first processor core as the boot core and starts the data acquisition application on the boot core. The running logic of the acquisition application is: calling the assembly SMC instruction to initiate a command to start the second processor core to the BIOS. After the second processor core is started by the first processor core, it is first in a standby state. The first processor core loads the binary image of the data analysis program of the second processor core; the first processor core sends an inter-core interrupt to the second processor core, and the second processor core receives the inter-core interrupt of the first processor core and starts to execute the data analysis application. The embodiment of the present application effectively and reasonably solves the startup problem of the application of the second processor core through this change in the boot method, and avoids the complicated operation process of starting the second processor core from uboot.

[0113] It should be understood that the various steps in the step flow chart in the above embodiment are shown in sequence according to the indications of the arrows, but these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the above flow chart may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0114] Another embodiment of the present application also provides a microprocessor, which includes a first processor core, a second processor core and a memory, the memory is respectively connected to the first processor core and the second processor core, the memory includes a first memory space and a second memory space, the first memory space is a memory space accessible to both the first processor core and the second processor core; the second memory space is a memory space accessible to the second processor core; the first memory space includes N array units, where N is a positive integer; each of the N array units is associated with a corresponding physical address, each physical address is within the address range of the first memory space, and the second memory space stores the association relationship between the physical addresses corresponding to each array unit. For the specific definition of the first processor core and the second processor core, please refer to the definition of the first processor core and the second processor core in the above-mentioned data communication method, which will not be repeated here.

[0115] Another embodiment of the present application further provides an electronic device, which includes the microprocessor provided in the embodiment of the present application, and the microprocessor is used to execute each step in the data communication method process provided in the above method embodiment.

[0116] In another embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, each step in the data communication method process of the embodiment of the present application is implemented.

[0117] In another embodiment of the present application, a computer program product is provided. The computer program product includes computer instructions. When the computer instructions are executed on a microprocessor, the microprocessor executes each step of the data communication method flow in the method flow shown in the above method embodiment.

[0118] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer-executable instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more servers that can be integrated with the medium. The available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media (eg, solid state disks (SSDs)).

[0119] The above are only specific embodiments of the present application. Those skilled in the art may conceive of variations or replacements based on the specific embodiments provided in this application, and all such variations or replacements shall fall within the scope of protection of this application.

Claims

1. A data communication method, characterized in that: Applied to a microprocessor, the microprocessor comprising a first processor core, a second processor core, and a memory, the memory being communicatively connected to the first processor core and the second processor core respectively, the memory comprising a first memory space and a second memory space, the first memory space being a memory space accessible to both the first processor core and the second processor core; The second memory space is a memory space accessible to the second processor core; the first memory space includes N array units, where N is a positive integer; each of the N array units is associated with a corresponding physical address, and each of the physical addresses is within an address range of the first memory space; the second memory space stores an association relationship between the physical addresses corresponding to each array unit; the method includes: Controlling, by the first processor core, M data to be transmitted to be stored sequentially in physical addresses corresponding to the N array units, where M is a positive integer and M≤N; After at least one frame of data to be transmitted is stored in a physical address corresponding to a first array unit, controlling the physical address corresponding to the first array unit to be changed to state information having a target identifier, the first array unit being any one of the N array units; Under preset conditions, a first interrupt instruction is sent to the second processor core, so that after receiving the first interrupt instruction, the second processor core obtains a target array unit with the target identifier from the N array units, and obtains the target physical address corresponding to the target array unit in sequence according to the association relationship, and reads the data to be transmitted from the target physical address in sequence.

2. The method according to claim 1, characterized in that The first memory space also stores shared resource information, wherein the shared resource information includes the storage space size of the N array units; Before controlling the first processor core to sequentially store the M data to be transmitted into the physical addresses corresponding to the N array units, the method further includes: A second interrupt instruction is sent to the second processor core, so that after receiving the second interrupt instruction, the second processor core configures a corresponding physical address for each of the array units from the first memory space based on the size of the storage space, and obtains an association relationship between the physical addresses corresponding to each array unit.

3. The method according to claim 1 or 2, characterized in that The microprocessor further includes a sensor and a controller, wherein the controller is communicatively connected to the sensor and the first processor core respectively, and the controller includes a register corresponding to the sensor; Before controlling the first processor core to sequentially store the M data to be transmitted into the physical addresses corresponding to the N array units, the method further includes: Configuring the physical addresses corresponding to the N array units into the register; The controlling, by the first processor core, the M data to be transmitted to be stored sequentially in the physical addresses corresponding to the N array units includes: A start instruction is sent to the sensor so that after receiving the start instruction, the sensor collects the data to be transmitted, obtains the physical addresses corresponding to the N array units from the register, and stores the data to be transmitted in the physical addresses corresponding to the N array units in sequence.

4. A data communication method, characterized in that: The invention is applied to a microprocessor, the microprocessor comprising: a first processor core, a second processor core and a memory, the memory being communicatively connected to the first processor core and the second processor core respectively, the memory comprising a first memory space and a second memory space, the first memory space being a memory space accessible to both the first processor core and the second processor core; the second memory space being a memory space accessible to the second processor; the first memory space comprising N array units, wherein N is a positive integer; each of the N array units is associated with a corresponding physical address, each of the physical addresses being within an address range of the first memory space, and the second memory space storing an association relationship between the physical addresses corresponding to each of the array units; the first processor core controls data to be transmitted to be sequentially stored in the storage space corresponding to the physical addresses of the N array units, and the array units storing the data to be transmitted are state information having a target identifier; the method comprising: After receiving the first interrupt instruction sent by the first processor core, the second processor core obtains the target array unit having the target identifier from the N array units; The target physical addresses corresponding to the target array units are sequentially acquired according to the association relationship, and the data to be transmitted are sequentially read from the target physical addresses.

5. The method according to claim 4, characterized in that After sequentially reading the data to be transmitted from the target physical address, the method further includes: The state information in the target array unit is cleared, and a physical address is reconfigured for the target array unit from the free storage space of the first memory space.

6. The method according to claim 4, characterized in that After sequentially reading the data to be transmitted from the target physical address, the method further includes: An array unit at an end position for reading the data to be transmitted is obtained, and a prompt mark is configured in the array unit at the end position, wherein the prompt mark is used to indicate a starting reading position for the second processor core to read the data to be transmitted next time.

7. The method according to claim 4, characterized in that The first memory space also stores shared resource information, wherein the shared resource information includes a preset polling quantity M, where M is a positive integer; The reading the data to be transmitted from the target physical address includes: Obtaining the polling quantity M from the shared resource information; The data to be transmitted is read sequentially from the target physical address according to the preset polling quantity M.

8. The method according to any one of claims 4 to 7, characterized in that: The microprocessor further includes a display controller, wherein the display controller is communicatively connected to the second processor core; After reading the data to be transmitted from the target physical address, the method further includes: The data to be transmitted is subjected to computational processing, and the processing result is sent to the display controller so that the display controller displays the processing result.

9. A microprocessor, characterized in that: The system comprises a first processor core, a second processor core, and a memory, wherein the memory is communicatively connected to the first processor core and the second processor core respectively, and the memory comprises a first memory space and a second memory space, wherein the first memory space is a memory space accessible to both the first processor core and the second processor core; The second memory space is a memory space accessible to the second processor core; the first memory space includes N array units, where N is a positive integer; each of the N array units is associated with a corresponding physical address, and each of the physical addresses is within the address range of the first memory space, and the second memory space stores the association relationship between the physical addresses corresponding to each array unit; wherein, The first processor core is configured to execute the data communication method according to any one of claims 1 to 3; The second processor core is used to execute the data communication method according to any one of claims 4 to 8.

10. An electronic device, characterized in that: The method comprises the microprocessor according to claim 9, wherein the microprocessor is configured to execute the data communication method according to any one of claims 1 to 8.

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