A method for determining the transient temperature of interconnects based on tensor analysis networks

Abstract

The present invention discloses a method for determining the transient temperature of interconnection based on a tensor analysis network, which mainly solves the problem of low efficiency of the prior art interconnection electrothermal transient temperature simulation. The implementation scheme is: constructing an equivalent thermal circuit of a single-layer interconnection structure; cascading the equivalent thermal circuits of a single-layer interconnection structure to form a thermal circuit model of a multi-layer interconnection structure; splitting the thermal circuit model of the multi-layer interconnection structure to obtain different thermal circuit units; cascading the impedance matrix of the thermal circuit units to obtain the impedance matrix of the multi-layer interconnection equivalent thermal circuit; porting the impedance matrix of the thermal circuit; porting the preprocessed impedance matrix; multiplying the ported impedance matrix with the excitation to obtain the temperature response in the frequency domain; performing a Laplace numerical inverse transform on the frequency domain temperature response to obtain the final determined temperature that changes with time. Compared with the prior art, the present invention saves 99% of the operation time at the same accuracy, improves the efficiency of transient temperature solution, and can be used for integrated circuit interconnection and package interconnection.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a method for determining transient temperature response of interconnection, which can be used for interconnection of integrated circuits and interconnection of packages. Background Art

[0002] Since the emergence of circuits, electricity and heat have always been accompanied. When current flows through a conductor, the conductor will generate heat. This phenomenon is called the thermal effect of current. Joule's law also quantitatively explains the phenomenon that the conduction current converts electrical energy into thermal energy, that is, the heat generated by the conductor is proportional to the square of the current, proportional to the resistance of the conductor, and proportional to the time of power supply. In the last century when the demand for miniaturization and portability was not obvious, the size of the circuit was relatively large, the resistance of the interconnection line was relatively small, and the heat generated by the conduction current was also relatively small. The larger circuit size also increased the contact area for heat exchange with the air, so that the small amount of heat generated was quickly dissipated into the air, and the temperature change was not obvious. In addition, because the data transmission rate of electronic equipment is low and the stability of interconnection transmission is strong, the impact of temperature change on signal transmission can be ignored.

[0003] With the continuous progress and development of integrated circuits and the need for miniaturization, the impact of the increase in conductor resistivity caused by the reduction in interconnect size and size effect has become increasingly prominent. When the transmitted electrical signal is the same, the current density in the small-sized conductor will inevitably increase, which will bring serious heating problems. In addition, since the number of interconnect layers is still increasing on the basis of size limitations, the spacing and layer spacing between interconnect lines are getting smaller and smaller. In order to avoid the serious signal integrity problems caused by crosstalk caused by the close distance between lines, designers prefer to use low dielectric constant materials in the selection of dielectric materials. However, low dielectric constant materials often do not have good thermal conductivity compared to traditional silicon oxides, which further aggravates the heating problem of interconnects. The increase in interconnect temperature will lead to an increase in metal resistivity and a change in the dielectric constant of the dielectric material. The increase in metal resistivity will increase the power consumed on the interconnect line, and the change in the dielectric constant of the dielectric material will change the transmission characteristics of the interconnect transmission line, causing the transmission characteristics to deviate from the original design requirements. In addition, at high clock rates, slight changes in interconnect characteristics and parameters will lead to signal integrity problems, affecting the overall performance and reliability of the system. In extreme cases, the circuit may be damaged because the temperature exceeds the melting point of the metal. Therefore, to improve the performance of integrated circuits, it is necessary to study and solve the heating problem of interconnections.

[0004] There are two main types of methods for existing electrothermal research:

[0005] The first method is to obtain experimental data by measuring actual circuits in a laboratory environment. For example, K. Banerjee et al. published a paper titled "Characterization of VLSI circuit interconnect heating and failure under ESD conditions" in the journal Reliability Physics Symposium. The paper analyzed the measured data to guide the electrothermal design of the circuit. However, this method requires making a test board for each circuit to perform a series of measurements. The advantage is that real data of the actual circuit operation can be obtained. The disadvantage is that a new test circuit needs to be made to obtain new test data after each modification, which consumes a lot of time and resources.

[0006] The second method is to obtain the electrothermal temperature response of the circuit through theoretical analysis and calculation. This method can perform detailed simulation analysis before the circuit is manufactured, solve and optimize most problems from the perspective of theoretical calculation, so that the actual circuit only needs a few proof tests or even one test to meet the design requirements. This method can be further divided into two categories: thermal field analysis method and equivalent model method.

[0007] The thermal field analysis method is to first mesh the physical structure of the complete circuit, and then iteratively solve the two-dimensional or three-dimensional heat conduction equation, and finally obtain the global thermal field map and temperature conditions. For example, S. Rzepka et al. published a paper titled "Characterization of self-heating in advanced VLSI interconnectlines based on thermal finite element simulation" in the IEEE Transactions on Components, Packaging, and Manufacturing Technology journal. The paper uses the finite element method to solve the thermal field of the interconnection line to obtain the temperature response of the line. Although this method has strong accuracy, it is also applicable to circuit structures of various complex physical models. At the same time, due to the very mature and general meshing and calculation methods, it is not necessary to optimize and process each situation separately. However, its calculation time is very long and the computing resources consumed are very large. In particular, the calculation of the temperature response of the complex interconnection structure has higher requirements on the equipment performance and requires longer calculation time.

[0008] The equivalent model method is to obtain the thermal response equation of the entire system by modeling the equivalent thermal circuit of the chip, package, and interconnect, extracting the thermal resistance and thermal capacity of each material and each layer, so as to quickly calculate and solve their temperature response. For example, Pascal Salome et al. published a paper entitled "Investigations on the thermal behavior of interconnects under ESD transientsusing a simplified thermal RC network" in the Microelectronics Reliability journal. The paper uses the RC model to model the equivalent thermal circuit and calculates the transient temperature of the interconnect under ESD excitation. The advantage of this method is that it uses an analytical calculation method, and the performance requirements of the computing device are not high. Even an ordinary personal computer can quickly and efficiently complete the calculation of the temperature response, effectively shortening the thermal design cycle. However, this method is extremely dependent on the accuracy of the equivalent thermal circuit model used, and the accuracy of the existing model needs to be further improved. At the same time, the corresponding equivalent model needs to be rebuilt for each new interconnect structure, and it is impossible to complete the thermal coupling and parallel calculation between multi-excitation and multi-layer interconnect structures. Summary of the invention

[0009] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a method for determining the transient temperature of interconnections based on a tensor analysis network, so as to reduce the calculation time when calculating the transient temperature of interconnections, reduce the performance requirements for computing equipment, and improve the thermal coupling and parallel computing capabilities between multi-excitation and multi-layer interconnection structures.

[0010] To achieve the above object, the technical solution of the present invention includes the following implementation steps:

[0011] (1) Constructing the equivalent thermal path of a single-layer interconnect structure:

[0012] Each layer of the single-layer interconnect structure of the integrated circuit or package is first equivalent using a first-order or multi-order RC model, and then the RC models of each layer are cascaded to obtain a single-layer interconnect thermal circuit model consisting of a heat capacitance C as a network shunt wall and a mixed connection with a thermal resistance R;

[0013] (2) Constructing a thermal circuit model for a multi-layer interconnect structure:

[0014] The thermal circuit models of single-layer interconnect structures are cascaded to obtain a universal equivalent thermal circuit model of multi-layer, multi-excitation complex interconnect structures, and some parameters of the model are adjusted according to the actual interconnect structure to complete the construction of the thermal circuit model of the multi-layer interconnect structure.

[0015] (3) The thermal circuit model of the multi-layer interconnection structure is split to obtain different thermal circuit units:

[0016] Treat the first conductor layer to the first dielectric layer as a unit;

[0017] The last conductor layer to the last dielectric layer is considered as a unit;

[0018] The conductor layer between the two dielectric layers is regarded as a unit;

[0019] (4) Obtain the impedance matrix of the multi-layer thermal circuit:

[0020] 4a) converting the topology of each thermal circuit unit into a tensor analysis network;

[0021] 4b) Obtain the impedance matrix Zunit of each thermal circuit unit through vector analysis of network space n ;

[0022] 4c) Impedance matrix of each unit Zunit n Cascade to obtain the impedance matrix Z of the multi-layer thermal circuit N ;

[0023] (5) Impedance matrix Z for thermal circuit N Perform port preprocessing:

[0024] The target layer for transient temperature response calculation is taken as the port. The impedance matrix Z of the thermal circuit is first calculated. N Perform row-column transformation to transform the port elements to the P-order principal minor of the matrix, and obtain the transformed matrix Z' N , and then transform the transformed matrix Z' N Divided into four sub-matrices, expressed as follows:

[0025]

[0026] Among them, Z a is a P×P submatrix, where P is the number of ports; Z b is a P×(MP) submatrix, Z c is a (MP)×P submatrix, Z d is a (MP)×(MP) submatrix, M is the number of meshes in the network space corresponding to the equivalent thermal path;

[0027] (6) The four sub-matrices are converted into impedance matrices to obtain the port impedance matrix Zp of the equivalent thermal circuit:

[0028] Zp=Z a -Z b ×Z d -1 ×Z c

[0029] (7) Multiply the frequency domain port impedance matrix Z(s) by the known excitation matrix E(s) to obtain the frequency domain temperature response expression T(s) at each port:

[0030] T(s)=Z(s)·E(s)

[0031] (8) The frequency domain temperature response expression T(s) is subjected to an inverse Laplace numerical transform to obtain the temperature T that changes with time d (t), and finally the determination of the transient temperature of the interconnect is completed.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] First, the present invention uses an equivalent circuit model to model the thermal path of the interconnect structure and solve the temperature response, thereby increasing the speed of temperature response calculation, reducing resource usage, and lowering the performance requirements for computing devices;

[0034] Second, the present invention uses a single-layer interconnected thermal circuit model to cascade and construct a multi-layer interconnected thermal circuit model, thereby expanding the scope of application of the model, reducing the complexity of model construction, and saving the time cost of model construction;

[0035] Third, the present invention first splits the thermal circuit into thermal circuit units to obtain the impedance matrices of the thermal circuit units respectively, and then cascades the matrices to obtain the impedance matrix of the multi-layer interconnection, thereby reducing the time cost of obtaining the impedance matrix of the multi-layer interconnection model;

[0036] Fourthly, the present invention uses a tensor analysis network to perform vector operations to obtain a transient temperature response that changes with time. Since vector operations have the characteristics of matrix parallel computing, the thermal coupling and parallel computing capabilities between multi-excitation and multi-layer interconnection structures are improved;

[0037] Fifth, since the present invention uses numerical methods to transform the temperature response from the frequency domain to the time domain, the difficulty of the transformation solution is reduced, the solution speed is increased, and the ability to solve the temperature response of complex interconnected structures is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flow chart for realizing the present invention;

[0039] Figure 2 is a schematic cross-sectional view of a single-layer interconnect structure in the present invention;

[0040] Figure 3 is an equivalent thermal circuit model of a single-layer interconnect structure in the present invention;

[0041] Figure 4 is a schematic cross-sectional view of a multi-layer interconnection structure in the present invention;

[0042] Figure 5 is a general equivalent thermal circuit model of the multi-layer interconnect structure in the present invention;

[0043] Figure 6 is a schematic cross-sectional view of a double-layer interconnection structure in the present invention;

[0044] Figure 7 Schematic diagram of equivalent thermal path decomposition of the double-layer interconnect structure in the present invention;

[0045] Figure 8 This is the temperature response result on the first signal layer of the double-layer interconnect structure under multiple excitations in the present invention. DETAILED DESCRIPTION

[0046] The embodiments and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0047] Reference Figure 1 The implementation steps of this example are as follows:

[0048] Step 1: Construct a single-layer interconnect equivalent thermal circuit model.

[0049] This example uses Figure 2 Taking the single-layer interconnect structure shown in the figure as an example, a single-layer interconnect equivalent thermal circuit model is constructed. The structure is an interconnect transmission line structure with uniform width and thickness of each layer. The signal is transmitted in the conductor layer. The specific implementation is as follows:

[0050] 1.1) The single-layer interconnect structure is divided into layers according to the vertical stacking, and each layer is equivalent to a first-order or multi-order RC model. The heat capacity C in the RC model is used as a shunt wall and a thermal resistance R mixed in series;

[0051] 1.2) All layers are cascaded using the RC model to form an equivalent thermal circuit model of a single-layer interconnect structure, such as Figure 3 As shown, the conductor of the interconnection structure is located in the middle layer of the structure, and the generated heat will be transferred to the upper and lower layers of the conductor layer respectively. The three ports of the equivalent thermal circuit model are a signal layer port port 1 and two dielectric layer ports port 2 and port 3 in contact with the air, wherein the signal layer port port 1 is used to input the excitation signal, and the two dielectric layer ports port 2 and port 3 are both used to input the ambient temperature;

[0052] 1.3) Calculate the thermal capacitance C and thermal resistance R in each layer RC model through the dimensions and material parameters of the interconnected structure stack:

[0053] C=ρ·c p ·h·L·W

[0054]

[0055] Where ρ is the density of each stacked material, c p is the specific heat capacity of each stacked material, K is the thermal conductivity of each stacked material, L is the length of the interconnect structure, W is the width of the thermal interconnect structure, and h is the thickness of the thermal interconnect structure.

[0056] Step 2: Construct an equivalent thermal circuit model of a multi-layer interconnect structure.

[0057] 2.1) The equivalent thermal circuits of multiple single-layer interconnect structures are cascaded to obtain the equivalent thermal circuit of the multi-layer interconnect structure, and the dielectric layer port port 3 in the single-layer thermal circuit is sequentially connected with the dielectric layer port port 2 in the next adjacent thermal circuit to form the equivalent thermal circuit of the multi-layer interconnect structure. Figure 4 The general equivalent thermal circuit model of multi-layer interconnection is shown in FIG. The actual interconnection structure corresponding to the equivalent thermal circuit model is as follows: Figure 5 As shown;

[0058] 2.2) According to the stacking arrangement, number of conductor layers, number of ports, and number of dielectric layers of the actual interconnect structure, the parameters in the general equivalent thermal circuit model of the multilayer interconnection and the order of the RC model are adjusted to obtain the corresponding equivalent thermal circuit model.

[0059] Step 3: split the thermal path model of the double-layer interconnect structure.

[0060] This example uses Figure 6 Taking the double-layer interconnect structure shown as an example, the double-layer interconnect structure is stacked with two signal layers and eight dielectric and auxiliary layers, which are, from bottom to top, the first SiO2 layer, the Ti layer, the first TiN layer, the first signal layer AlCu, the second TiN layer, the second SiO2 layer, the third TiN layer, the second signal layer AlCu, the fourth TiN layer, and the third SiO2 layer.

[0061] The specific implementation of this step to determine the transient temperature response of the double-layer interconnect structure is as follows:

[0062] 3.1) Use step 2 to construct the equivalent thermal circuit of the double-layer interconnect structure, such as Figure 7 As shown, it uses the equivalent thermal circuit cascade of two single-layer interconnect structures to obtain the general model of the double-layer thermal circuit, and then adjusts the parameters in the general equivalent thermal circuit model of the double-layer interconnection and the order of the RC model according to the stacking arrangement, the number of conductor layers, the number of ports, and the number of dielectric layers of the double-layer interconnection structure, thereby obtaining the equivalent thermal circuit of the double-layer interconnection structure, reducing the complexity of its model;

[0063] 3.2) The first conductor layer to the first dielectric layer, the last conductor layer to the last dielectric layer, and the conductor layer between two dielectric layers in the equivalent thermal circuit of the double-layer interconnect structure are respectively regarded as a unit, and the thermal circuit model of the double-layer interconnect structure is decomposed to obtain thermal circuit units Z1, Z2, and Z3, as shown in Figure 7 shown.

[0064] Step 4: Obtain the impedance matrix Z3 of the double-layer thermal circuit

[0065] 4.1) Convert the thermal circuit unit obtained in step 3 to the vector space of the tensor analysis network, and form vectors of the grid voltages and currents in the circuit network space of each thermal circuit unit according to the grid order, and obtain the covariant tensor U and inverse tensor I of the thermal circuit unit:

[0066] U=[u1 u2 u3 … u l … u k ]

[0067]

[0068] Among them, u l is the voltage on the lth grid, i l is the current on the lth grid, l = 1, 2, 3…, k, k is the number of grids in the thermal circuit unit;

[0069] 4.2) The impedances on the grid branches in the circuit network space of each thermal circuit unit are combined into a matrix according to the grid order to obtain the quadratic covariant tensor zk of the thermal circuit unit:

[0070]

[0071] Among them, z ll is the self-impedance of the lth grid, and the remaining elements are the mutual impedances between the lth grid and other grids;

[0072] 4.3) Sum the impedances of the branches on the same grid in the quadratic covariant tensor zk, and use the summation result as the element on the diagonal of the matrix. Then, negate the impedances on the branches shared by the two grids as the elements above and below the diagonal zc l , the rest of the elements are 0, and the impedance matrix Zunit of each thermal circuit unit is obtained:

[0073]

[0074] Among them, z l is the sum of the impedances of each branch on the lth grid;

[0075] 4.4) Obtain the thermal circuit unit quadratic covariant tensors zk1, zk2, zk3 of thermal circuit units Z1, Z2, Z3 according to step 4.2)

[0076] 4.5) According to step 4.3), the impedances of each branch on the same grid in the quadratic covariant tensor zk1, zk2, and zk3 of the thermal circuit unit are summed, and the summation result is used as the element on the matrix diagonal. Then, the impedance on the common branch of the two grids is inverted as the elements above and below the diagonal, and the remaining elements are all 0, and the impedance matrices Zunit1, Zunti2, and Zunit3 of the thermal circuit units Z1, Z2, and Z3 are obtained:

[0077]

[0078]

[0079]

[0080] Among them, s is the independent variable in the complex frequency domain; R and C are Figure 6 The thermal resistance and thermal capacitance of the two signal layers and each dielectric layer of the double-layer interconnect structure shown are calculated by step 1.3), as shown in the table:

[0081] layer Heat capacity C / pF Thermal resistance R / Ω <![CDATA[AlCu1]]> 133.59 20.55 <![CDATA[AlCu2]]> 133.59 20.55 <![CDATA[TiN1]]> 12.85 18.18 <![CDATA[TiN2]]> 10.28 14.55 <![CDATA[TiN3]]> 10.28 14.55 <![CDATA[TiN4]]> 10.28 14.55 Ti 9.21 16.60 <![CDATA[SiO21]]> 57.18 649.35 <![CDATA[SiO22]]> 34.31 389.61 <![CDATA[SiO23]]> 34.31 389.61

[0082] 4.6) The unit impedance matrices Zunit1, Zunti2, and Zunit3 are cascaded to form the diagonal elements of the impedance matrix Z3 of the double-layer interconnect structure, and then the coupling impedance between the thermal circuit units is added to obtain the impedance matrix Z3 of the double-layer interconnect structure:

[0083]

[0084] Among them, Zc1 and Zc2 are the coupling impedances between the thermal circuit units:

[0085]

[0086]

[0087] Step 5, perform port preprocessing on the impedance matrix Z3 of the double-layer interconnect structure thermal path.

[0088] 5.1) The two signal layers are used as port 1 and port 2 respectively, and the two dielectric layers in contact with the air are used as port 3 and port 4 respectively;

[0089] 5.2) The impedance matrix Z3 of the double-layer interconnected thermal circuit is transformed into rows and columns, so that the port elements are transformed to the P-order principal minor of the matrix, and the transformed matrix Z'3 is obtained. The transformed matrix Z'3 is then divided into four sub-matrices, which are expressed as follows:

[0090]

[0091] Among them, Z a is a P×P submatrix, where P is the number of ports; Z b is a P×(MP) submatrix, Z c is a (MP)×P submatrix, Z d is a (MP)×(MP) submatrix, and M is the number of meshes in the network space corresponding to the double-layer interconnected equivalent thermal path.

[0092] Step 6: Obtain the port impedance matrix Zp of the equivalent thermal circuit of the double-layer interconnect structure.

[0093] The four sub-matrices Z obtained in step 5 a , Z b , Z c , Z d Substitute the port formula Zp=Z a -Z b ×Z d -1 ×Z c , the port impedance matrix Zp of the equivalent thermal circuit of the double-layer interconnect structure is obtained:

[0094]

[0095] The port impedance matrix Zp is a square matrix with a rank equal to the number of ports P. The main diagonal elements in the square matrix are the self-impedances at the corresponding ports, and the other elements outside the diagonal are the coupling impedances between the corresponding two ports.

[0096] Step 7: Obtain the frequency domain response expression T(s) of the temperature response of the first signal layer in the double-layer interconnect under two excitations at different layers according to Zp.

[0097] This example uses human body discharge pulse ESD as excitation. The first ESD pulse is added to the first signal layer 1 in the double-layer interconnect structure. 400ns after the first pulse is added, the second ESD pulse is added to the second signal layer 2. The frequency domain response expression T(s) of the temperature response of the first signal layer in the double-layer interconnect under multiple excitations is solved. The specific implementation is as follows:

[0098] 7.1) The form of use is The ESD pulse is used as the stimulus, and the excitation signal is calculated at the resistor R t The power on the interconnection line is:

[0099] E(t)=I(t) 2 R t

[0100] Among them, V ESD is the discharge voltage of the human body, V ESD =1000V; RHBM is the equivalent discharge resistance of the human body, R HBM =1500Ω; C HBM is the equivalent capacitance of the human body, C HBM =100pF; L p is the equivalent inductance, L p =7.5μH;

[0101] 7.2) Perform Laplace transform on the power E(t) on the interconnection line to obtain the power expression in the frequency domain:

[0102]

[0103] Among them, α, β, and γ are three different intermediate variables, which are expressed as follows:

[0104]

[0105] 7.3) The self-impedance Zp of the first signal layer of the double-layer interconnect structure 11 Multiplying the power frequency domain expression E1(s) of the ESD excitation, the coupling impedance Zp from the second signal layer to the first signal layer is 21 Multiply it by the power frequency domain expression E2(s) of the ESD stimulus after a 400ns delay;

[0106] 7.4) Sum the two multiplication results of 7.3) to obtain the frequency domain response expression T(s) of the temperature response of the first signal layer in the double-layer interconnect under two excitations of different layers:

[0107] T(s)=Zp 11 (s)·E1(s)+Zp 21 (s)·E2(s).

[0108] Step 8, finalize the interconnect transient temperature.

[0109] Substitute the frequency domain temperature response expression T(s) of the temperature response of the first signal layer in the two-layer interconnect under two excitations of different layers obtained in step 7 into the Laplace numerical inverse transform formula Perform the Laplace numerical inverse transform, where t is time, e is a natural number, n is the series item number, a is the adjustment parameter for error control, T(s) is the frequency domain temperature response expression, and the variable of the expression is The final determined temperature T varying with time is obtained d (t).

[0110] The effect of the present invention can be further illustrated by the following simulation results:

[0111] 1. Simulation conditions

[0112] The hardware of the simulation device uses an AMD R7 5700G processor, 16G DDR4 memory, and an Nvidia RTX 3060 graphics card.

[0113] For example Figure 6 The double-layer interconnect structure shown uses human body discharge pulse ESD as excitation, adds the first ESD pulse to the first signal layer 1 in the double-layer interconnect structure, and adds the second ESD pulse to the second signal layer 2 400ns after the first pulse is added.

[0114] 2. Simulation Content

[0115] Under the above simulation conditions, the present invention and the existing thermal field calculation method are used to perform parallel calculation of multi-layer and multi-excitation transient temperatures of the double-layer interconnect structure, and the transient temperature simulation result of the first signal layer is obtained, as shown in FIG. Figure 8 As shown, the time consumption comparison of simulation parallel computing is shown in Table 1:

[0116] Table 1 Comparison of parallel computing time between the present invention and the prior art

[0117] method Method of the present invention Thermal Field Calculation Method Running time / s 643 3

[0118] from Figure 8 It can be seen that the method of the present invention and the prior art have a maximum error of only 1.8% at the trough of the transient temperature result; but as can be seen from Table 1, the parallel calculation of the prior art takes 643 seconds, while the total parallel calculation time of the present invention is only 3 seconds, indicating that the method of the present invention saves 99% of the calculation time compared with the prior art under the condition of equivalent accuracy.

Claims

1. A method for determining the transient temperature of an interconnect based on a tensor analysis network, characterized in that: These include: (1) Constructing the equivalent thermal path of a single-layer interconnect structure: Each layer of the single-layer interconnect structure of the integrated circuit or package is first equivalent using a first-order or multi-order RC model, and then the RC models of each layer are cascaded to obtain a single-layer interconnect thermal circuit model consisting of a heat capacitance C as a network shunt wall and a mixed connection with a thermal resistance R; (2) Constructing a thermal circuit model for a multi-layer interconnect structure: The thermal circuit models of single-layer interconnect structures are cascaded to obtain a universal equivalent thermal circuit model of multi-layer, multi-excitation complex interconnect structures, and some parameters of the model are adjusted according to the actual interconnect structure to complete the construction of the thermal circuit model of the multi-layer interconnect structure. (3) The thermal circuit model of the multi-layer interconnection structure is split to obtain different thermal circuit units: Treat the first conductor layer to the first dielectric layer as a unit; The last conductor layer to the last dielectric layer is considered as a unit; The conductor layer between the two dielectric layers is regarded as a unit; (4) Obtain the impedance matrix of the multi-layer thermal circuit: 4a) converting the topology of each thermal circuit unit into a tensor analysis network; 4b) Obtain the impedance matrix Zunit of each thermal circuit unit through vector analysis of network space n ; 4c) Impedance matrix of each unit Zunit n Cascade to obtain the impedance matrix Z of the multi-layer thermal circuit N ; (5) Impedance matrix Z for thermal circuit N Perform port preprocessing: The target layer for transient temperature response calculation is taken as the port. The impedance matrix Z of the thermal circuit is first calculated. N Perform row-column transformation to transform the port elements to the P-order principal minor of the matrix, and obtain the transformed matrix Z' N , and then transform the transformed matrix Z' N Divided into four sub-matrices, expressed as follows: Among them, Z a is a P×P submatrix, where P is the number of ports; Z b is a P×(MP) submatrix, Z c is a (MP)×P submatrix, Z d is a (MP)×(MP) submatrix, M is the number of meshes in the network space corresponding to the equivalent thermal path; (6) The four sub-matrices are converted into impedance matrices to obtain the port impedance matrix Zp of the equivalent thermal circuit: Zp=Z a -WITH b ×Z d -1 ×Z c (7) Multiply the frequency domain port impedance matrix Z(s) by the known excitation matrix E(s) to obtain the frequency domain temperature response expression T(s) at each port: T(s)=Z(s)·E(s) (8) The frequency domain temperature response expression T(s) is subjected to an inverse Laplace numerical transform to obtain the temperature T that changes with time d (t), and finally the determination of the transient temperature of the interconnect is completed.

2. The method according to claim 1, characterized in that In step 4a), the topology of each heat circuit unit is converted into a tensor analysis network, which is implemented as follows: The grid voltages in the circuit network space are formed into vectors according to the grid order to obtain the covariant tensor of the thermal circuit unit; The grid currents in the circuit network space are formed into vectors according to the grid order to obtain the inverse tensor of the thermal circuit unit; The impedances on the grid branches in the circuit network space are organized into matrices according to the grid order to obtain the quadratic covariant tensor of the thermal circuit unit; The above three tensors are the three necessary elements of the tensor analysis network, and together constitute a complete tensor analysis network.

3. The method according to claim 1, characterized in that In step 4b), the impedance matrix of each thermal circuit unit is obtained by vector analysis in network space, which is implemented as follows: 4b1) Sum the impedance of each branch on the circuit grid and use the sum as the element z on the diagonal of the matrix n ; 4b2) Take the impedance of the common branch of the two grids and take it as the element zc above and below the diagonal n , the rest of the elements are 0, and the impedance matrix Zunit of each unit is obtained: Among them, z l is the sum of the impedances of each branch on the lth grid.

4. The method according to claim 1, characterized in that: Step 4c) Obtain the impedance matrix Z of the multi-layer thermal circuit N , which is expressed as follows: Where N is the number of heat circuit units, Zc n It is the coupling between each unit, which is obtained by inverting the impedance of the common branch of each thermal circuit.

5. The method according to claim 1, characterized in that The port impedance matrix Zp in step 6) is a square matrix with a rank equal to the number of ports P. The diagonal elements in the square matrix are the self-impedances at the corresponding ports, and the other elements outside the diagonal are the coupling impedances between the corresponding two ports.

6. The method according to claim 1, characterized in that Step 8) Get the temperature T that changes with time d (t), expressed as follows: Where t is time, e is a natural number, n is the series item number, a is the adjustment parameter used to control the error, T(s) is the frequency domain temperature response expression, and the variable of the expression is

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