Chip simulation verification system and method

Abstract

Embodiments of the present application provide a chip simulation verification system and method, the chip simulation verification system comprising: a front-end server, a hardware simulation accelerator and at least one interface extender; the front-end server is provided with at least one first interface, the first interface is configured to be connected with a second interface on an interface extender, each interface extender comprises a second interface and at least two third interfaces connected with the second interface; the hardware simulation accelerator comprises at least two simulation units, each simulation unit is connected with a third interface, and different simulation units are connected with different third interfaces; the simulation unit is used for simulating a chip to be verified; the front-end server is used for communicating with each simulation unit through the interface extender respectively, and verifying the chip to be verified simulated by each simulation unit. The present scheme can improve the applicability of chip simulation verification.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip simulation and verification system and method. Background Technology

[0002] In the chip design and development process, hardware simulation accelerators are used to simulate and verify the chip's hardware code. This allows for early verification of the accuracy of the circuit design within the chip, enabling iterative iteration of the hardware code based on the verification results, thereby improving chip design and development efficiency. When simulating and verifying certain chips, it's necessary to verify whether the operation of multiple interconnected chips meets design requirements. For example, verifying whether the data bandwidth of eight interconnected chips matches the architecture design. In simulating and verifying multi-chip interconnects, the hardware simulation accelerator simulates multiple chips, and a front-end server controls the accelerator to verify the chip interconnect functionality.

[0003] Currently, when simulating and verifying multi-chip interconnects, it is necessary to select a front-end server with a corresponding number of interfaces based on the number of interconnected chips, so that each chip simulated by the hardware simulation accelerator can be connected to the front-end server through an interface.

[0004] However, when performing simulation verification of different numbers of interconnected chips for the same chip, such as performing simulation verification of 2 / 4 / 8 interconnected chips for the same chip, the number of interconnected chips may exceed the interface limit of the front-end server. For example, if the front-end server has 4 interfaces that can be connected to the hardware simulation accelerator, then the front-end server can be used to perform simulation verification of interconnected chips with 4 or fewer interconnected chips, but it cannot be used to perform simulation verification of 8 interconnected chips. Therefore, the applicability of the chip simulation verification system is poor. Summary of the Invention

[0005] In view of this, embodiments of this application provide a chip simulation verification system and method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a chip simulation verification system is provided, comprising: a front-end server, a hardware simulation accelerator, and at least one interface extender; the front-end server is provided with at least one first interface, the first interface being configured to connect to a second interface on one of the interface extenders, each interface extender including one second interface and at least two third interfaces connected to the second interface; the hardware simulation accelerator includes at least two simulation units, each simulation unit being connected to one of the third interfaces, and different simulation units being connected to different third interfaces; the simulation units are used to simulate a chip to be verified; the front-end server is used to communicate with each of the simulation units through the interface extender to verify the chip to be verified simulated by each simulation unit.

[0007] According to a second aspect of the embodiments of this application, a chip simulation verification method is provided, comprising: a hardware simulation accelerator including at least two simulation units simulating at least two chips to be verified; a front-end server communicating with each of the simulation units respectively through an interface extender to verify the chips to be verified simulated by each simulation unit, wherein the front-end server is provided with at least one first interface, the first interface being configured to be connected to a second interface on an interface extender, each interface extender including a second interface and at least two third interfaces connected to the second interface, each simulation unit being connected to a third interface, and different simulation units being connected to different third interfaces.

[0008] According to the chip simulation verification scheme provided in the embodiments of this application, the front-end server includes at least one first interface. Each first interface can be connected to a second interface on an interface expander. Each interface expander is provided with multiple third interfaces, and each third interface can be connected to a simulation unit included in the hardware simulation accelerator. Each simulation unit can simulate a simulated chip to be verified. The front-end server communicates with each simulation unit through the interface expander to verify the simulated chip to be verified by each simulation unit. The interface expander can expand each first interface on the front-end server into multiple third interfaces, and each third interface can connect to a simulation unit. By increasing the number of simulation units that the front-end server can connect to, the number of simulation units that the front-end server can connect to is greater than the number of first interfaces on the front-end server. Therefore, according to the simulation verification requirements, a larger number of interconnected chips can be simulated and verified, improving the applicability of the chip simulation verification system. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0010] Figure 1 This is a schematic diagram of a chip simulation and verification system according to an embodiment of this application;

[0011] Figure 2 This is a schematic diagram of a chip simulation and verification system according to another embodiment of this application;

[0012] Figure 3 This is a schematic diagram of an interface extender according to an embodiment of this application;

[0013] Figure 4 This is a schematic diagram of an interface extender according to another embodiment of this application;

[0014] Figure 5 This is a schematic diagram of a chip simulation and verification system according to yet another embodiment of this application;

[0015] Figure 6 This is a flowchart of a chip simulation verification method according to an embodiment of this application. Detailed Implementation

[0016] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0017] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0018] Hardware simulation: In integrated circuit design, hardware simulation is the process of using another piece of hardware (usually a dedicated simulation system) to simulate the behavior of one or more hardware components (typically the system under design). For example, a hardware simulation accelerator can be used to simulate the designed chip to verify whether the circuit structure of the designed chip can achieve the preset design goals.

[0019] Hardware simulation accelerator: During the hardware simulation of the chip in the design, the hardware simulation accelerator can simulate the chip in the design to perform data processing based on the chip's hardware code and return the corresponding processing results.

[0020] Front-end server: During the hardware simulation of the chip in the design, the front-end server can simulate the scheduling unit of the chip in the design, send scheduling instructions to the hardware simulation accelerator of the simulated chip, so that the hardware simulation accelerator can perform corresponding processing, and receive the processing results of the hardware simulation accelerator.

[0021] Chip simulation and verification system

[0022] Figure 1 This is a schematic block diagram of a chip simulation and verification system according to this application. Figure 1 As shown, the chip simulation verification system 10 includes a front-end server 11, a hardware simulation accelerator 13, and at least one interface expander 12. The front-end server 11 is provided with at least one first interface 111, which can be connected to a second interface 121 on an interface expander 12. Each interface expander 12 includes one second interface 121 and at least two third interfaces 122, with the second interface 121 connected to each of the third interfaces 122 within the same interface expander 12. The hardware simulation accelerator 13 includes at least two simulation units 131, each of which can be connected to a third interface 122, with different simulation units 131 connected to different third interfaces 122. The simulation units 131 can simulate the chip to be verified. The front-end server 11 can communicate with each simulation unit 131 through the interface expander 12 to verify the chip to be verified simulated by each simulation unit 131.

[0023] The front-end server 11 is provided with at least one first interface 111, for example, two first interfaces 111. Each first interface 111 can connect to one interface expander 12, and each expander 12 can connect to multiple simulation units 131. Each simulation unit 131 can simulate one chip to be verified. Depending on the number of interconnected chips to be verified, if the number of simulation units 131 that one interface expander 12 can connect to is greater than or equal to the number of interconnected chips to be verified, the front-end server 11 can connect to one interface expander 12 through one first interface 111. If the number of simulation units 131 that one interface expander 12 can connect to is less than the number of interconnected chips to be verified, the front-end server 11 can connect to multiple interface expanders 12 through multiple first interfaces 111.

[0024] The interface expander 12 includes a second interface 121 and multiple third interfaces 122, each of which is connected to the second interface 121. Each third interface 122 can be connected to a simulation unit 131. The second interface 121 on the interface expander 12 can be connected to the first interface 111 on the front-end server 11. Through the interface expander 12, one first interface on the front-end server 11 can be expanded into multiple third interfaces 122. Thus, the front-end server 11 can be connected to multiple simulation units 131 through one first interface 111, meeting the requirement of verifying multi-chip interconnection by connecting multiple simulation units 131.

[0025] After converting the hardware code of the chip to be verified into a database that the hardware emulation accelerator 13 can recognize, the hardware emulation accelerator 13 can load the converted database and run it. Each simulation unit 131 included in the hardware emulation accelerator 13 can simulate the chip to be verified based on the loaded database, so as to execute the instructions sent by the front-end server 11 using the circuit operation logic of the chip to be verified.

[0026] The circuit to be verified can be a general-purpose computing on graphics processing units (GPGPU).

[0027] In this embodiment, the front-end server 11 includes at least one first interface 111. Each first interface 111 can be connected to a second interface 121 on an interface expander 12. Each interface expander 12 is provided with multiple third interfaces 122, and each third interface 122 can be connected to a simulation unit 131. Each simulation unit 131 can simulate a chip to be verified. The front-end server 11 communicates with each simulation unit 131 through the interface expander 12 to verify the chip to be verified simulated by each simulation unit 131. The interface expander 12 can expand each first interface 111 on the front-end server 11 into multiple third interfaces 122. Each third interface 122 can connect to a simulation unit 131. The interface expander 12 increases the number of simulation units 131 that the front-end server 11 can connect to, making the number of simulation units 131 that the front-end server 11 can connect to greater than the number of first interfaces 111 on the front-end server 11. Therefore, according to the simulation verification requirements, a larger number of interconnected chips can be simulated and verified, improving the applicability of the chip simulation verification system.

[0028] Figure 2 This is a schematic block diagram of a chip simulation and verification system according to another embodiment of this application. Figure 2As shown, the chip simulation verification system 10 also includes at least two rate conversion units 14. Each third interface 122 is connected to one rate conversion unit 14, and different third interfaces 122 are connected to different rate conversion units 14. Each rate conversion unit 14 can be connected to one analog unit 131, and different rate conversion units 14 are connected to different analog units 131. The rate conversion unit 14 can buffer the communication data between the connected analog unit 131 and the front-end server 11.

[0029] When simulating the chip under test using simulation unit 131, the clock frequency of simulation unit 131 is lower than the clock frequency of the actual chip. For example, when simulating the chip under test, the frequency of simulation unit 131 is at the MHz level, while the clock frequency of the actual chip is at the GHz level. When simulating and verifying the chip under test, the clock frequency of front-end server 11 is at the same level as the clock frequency of the actual chip, that is, the clock frequency of front-end server 11 is also at the GHz level. Therefore, the clock frequency of front-end server 11 is higher than the clock frequency of simulation unit 131. For this reason, a rate conversion unit 14 is set between front-end server 11 and simulation unit 131. The rate conversion unit 14 can realize the synchronization between front-end server 11 and simulation unit 131, buffer the data sent by front-end server 11 to simulation unit 131, and adapt the data exchange between front-end server 11 and simulation unit 131.

[0030] In this embodiment, since the clock frequencies of the front-end server 11 and the simulation unit 131 are different, a rate conversion unit 14 is set between the interface expander 12 and the simulation unit 131. Data sent from the front-end server 11 to the simulation unit 131 arrives at the rate conversion unit 14 via the interface expander 12. The rate conversion unit 14 buffers the data from the front-end server 11 and sends the buffered data to the simulation unit 131 according to the clock frequency of the simulation unit 131. After the data sent from the simulation unit 131 to the front-end server 11 arrives at the rate conversion unit 14, the rate conversion unit 14 sends the data from the simulation unit 131 to the front-end server 11 via the interface expander 12 according to the operating frequency of the front-end server 11. By setting up the rate conversion unit 14 between the front-end server 11 and the simulation unit 131 and buffering the data sent from the front-end server 11 to the simulation unit 131, the problem of the different clock frequencies between the front-end server 11 and the simulation unit 131 is solved, ensuring that the front-end server 11 and the simulation unit 131 can communicate normally, thereby ensuring the reliability of the chip simulation verification.

[0031] Figure 3 This is a schematic block diagram of an interface extender according to one embodiment of this application. Figure 3As shown, the interface extender 12 includes an expansion board 31, at least one connection board 32, and at least two connection cables 33. The expansion board 31 has one second interface 121 and at least two first connection cable interfaces 311, each of which is connected to the second interface 121. Each connection board 32 has at least one second connection cable interface 321 and at least one third interface 122, with different second connection cable interfaces 321 connected to different third interfaces 122. Each first connection cable interface 311 is connected to a second connection cable interface 321 via a connection cable 33, and different first connection cable interfaces 311 are connected to different second connection cable interfaces 321.

[0032] The expansion board 31 includes a second interface 121 and multiple first connection interfaces 311, each of which is connected to the second interface 121. The connection board 32 includes one or more sets of connected second connection interfaces 321 and third interfaces 122. Each first connection interface 311 is connected to a second connection interface 321 via a connection cable 33, and different first connection interfaces 311 are connected to different second connection interfaces 321. The second interface 121 can be connected to the first interface 111 in the front-end server 11, and each third interface 122 can be connected to an analog unit 131. Specifically, each third interface 122 can be connected to a rate conversion unit 14, and each rate conversion unit 14 is connected to an analog unit 131.

[0033] In this embodiment, the interface expander 12 includes an expansion board 31, a connection board 32, and a connection cable 33. The expansion board 31 is connected to the first interface 111 in the front-end server 11 via a second interface 121. The first connection cable interface 311 in the expansion board 31 is connected to the second connection cable interface 321 in the connection board 32 via the connection cable 33. The third interface 122 in the connection board 32 is connected to the simulation unit 131. Since the first connection cable interface 311 and the second connection cable interface 321 are connected via the connection cable 33, the spatial position between the expansion board 31 and the connection board 32 can be changed, facilitating the connection of the second interface 121 to the first interface 111 in the front-end server 11 and the connection of the third interface 122 to the simulation unit 131, thereby improving the convenience of chip simulation verification through the chip simulation verification system 10.

[0034] Figure 4 This is a schematic block diagram of an interface extender according to another embodiment of this application. Figure 4 As shown, each connection board 32 is provided with at least two second connection cable interfaces 321 and at least two third interfaces 122, and different second connection cable interfaces 321 are connected to different third interfaces 122.

[0035] In this embodiment, each connection board 32 is provided with a plurality of second connection line interfaces 321 and a plurality of third interfaces 122. Each second connection line interface 321 is connected to a third interface 122, and different second connection line interfaces 321 are connected to different third interfaces 122. The plurality of second connection line interfaces 321 and the plurality of third interfaces 122 share a single connection board 32, which can reduce the number of connection boards 32, facilitate the chip simulation process, and reduce the cost of the chip simulation verification system 10.

[0036] In one possible implementation, when the number of first connection line interfaces 311 on each expansion board 31 is n, where n is a positive integer greater than or equal to 2, the bandwidth of each first connection line interface 311 is equal to 1 / n of the bandwidth of the second interface 121.

[0037] For example, the bandwidth of the first interface 111 and the second interface 121 is 16 lanes. Each expansion board 31 is equipped with 4 first connection interface 311, so the bandwidth of each first connection interface 311 is 4 lanes. However, the communication protocol and data type of each first connection interface 311 are the same as those of the first interface 111 and the second interface 121.

[0038] In this embodiment, the expansion board 31 includes n first connection interface 311s, the bandwidth of each first connection interface 311 is equal to 1 / n of the bandwidth of the second interface 121, but the communication protocol and data type of each first connection interface 311 are the same as those of the first interface 111 and the second interface 121. That is, the interface expander 12 can expand the first interface 111 into n third interfaces 122 with a bandwidth equal to 1 / n of the bandwidth of the first interface 111. Under the premise that the front-end server 11 can connect to multiple simulation units 131 through one first interface 111, the front-end server 11 can communicate normally with the simulation unit 131, and the chip simulation verification process can be carried out normally.

[0039] In one possible implementation, such as Figure 3 and Figure 4 As shown, the first interface 111, the second interface 121 and the third interface 122 are all high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interfaces.

[0040] In this embodiment, since the motherboard of the front-end server 11 is equipped with a PCIe interface, and the simulation unit 131 can also communicate via the PCIe interface, when the first interface 111, the second interface 121, and the third interface 122 are all PCIe interfaces, the chip simulation verification system 10 can be constructed using the PCIe interfaces provided by the front-end server 11 and the hardware simulation accelerator 13. This eliminates the need for dedicated interfaces in the front-end server 11 and the hardware simulation accelerator 13, further reducing the cost of the chip simulation verification system 10. Furthermore, the PCIe interface offers stable communication and fast data transmission. The communication between the front-end server 11, the interface expander 12, and the hardware simulation accelerator 13 via the PCIe interface ensures the reliability of the chip simulation verification system 10 and the efficiency of chip simulation verification.

[0041] In one possible implementation, such as Figure 3 and Figure 4 As shown, the first connection interface 311 and the second connection interface 321 can be Mini SAS interfaces, and the connection cable 33 is a Mini SAS connection cable.

[0042] In this embodiment, when the first interface 111, the second interface 121, and the third interface 122 are all PCIe interfaces, the first connection interface 311 and the second connection interface 321 can adopt Mini SAS interfaces, and the corresponding connection cables can be Mini SAS connection cables. The Mini SAS interface has a smaller size. Using Mini SAS interfaces for the first connection interface 311 and the second connection interface 321 can reduce the area occupied by the first connection interface 311 and the second connection interface 321 on the expansion board 31 and the connection board 32, facilitating the deployment of the chip simulation and verification system 10.

[0043] Figure 5 This is a schematic diagram of a chip simulation and verification system according to another embodiment of this application. Figure 5 As shown, simulation unit 131 can simulate parallel processing unit 501 and inter-chip communication unit 502, which are connected. Each simulation unit 131 simulates an inter-chip communication unit 502 which is connected to at least one other simulation unit 131 simulating an inter-chip communication unit 502. Parallel processing unit 501 can simulate the chip to be verified, and inter-chip communication unit 502 can transmit communication data between the connected simulation units 131.

[0044] As the core of the chip under test, the parallel processing unit 501 can simulate the circuit structure of the chip under test, support the simultaneous execution of multiple threads, and perform parallel data processing in conjunction with other parallel processing units 501. When verifying the multi-chip interconnection function, the parallel processing units 501 simulated by different simulation units 131 need to exchange data. Each simulation unit 131 can simulate an inter-chip communication unit 502 connected to the parallel processing unit 501. The inter-chip communication units 502 simulated by different simulation units 131 can be connected to each other, forming an inter-chip communication network. This inter-chip communication network allows for the transmission of communication data between the parallel processing units 501 simulated by different simulation units 131.

[0045] Each inter-chip communication unit 502 can be connected to multiple other inter-chip communication units 502. Depending on the chip simulation and verification requirements, each inter-chip communication unit 502 can be connected to one, two, three, four, or more other inter-chip communication units 502. Different inter-chip communication units 502 can be interconnected through analog channels, which are defined by hardware code. For example, when there are eight analog units 131, these eight analog units 131 can be interconnected through inter-chip communication units 502, meaning that the inter-chip communication unit 502 in each analog unit 131 is connected to the inter-chip communication units 502 in the other seven analog units 131.

[0046] When verifying the interconnect functionality of a fixed number of chips, different analog units 131 can be connected while ensuring that the number of connected analog units 131 is the same as the number of interconnected chips. For example, when verifying the interconnect functionality of four chips, the connection structure of the eight analog units 131 can be changed to change the connection of the four analog units 131. In one example, the connection structure of the analog units 131 can be changed in real time by configuring registers. Specifically, a piece of code can be added at the top level of the hardware code that acts on the registers to switch the connection of different analog units 131.

[0047] In this embodiment, the simulation unit 131 can simulate a parallel processing unit 501 and an inter-chip communication unit 502. The inter-chip communication units 502 simulated by different simulation units 131 are connected to form an inter-chip communication network. The parallel processing units 501 simulated by different simulation units 131 can communicate through this network, thereby enabling verification of interconnections of different numbers of chips and ensuring the applicability of the chip simulation verification system 10. Different inter-chip communication units 502 are interconnected through simulation channels, and the connection relationships between them can be easily changed through network configuration, making it suitable for the simulation verification needs of different chips.

[0048] In one possible implementation, such as Figure 5 As shown, the simulation unit 131 includes a format conversion unit 503. Each simulation unit 131 can simulate an interface IP core 504. For the same simulation unit 131, the format conversion unit 503 is connected to the simulated interface IP core 504, and the interface IP core 504 is connected to the parallel processing unit 501. Each format conversion unit 503 can be connected to a rate conversion unit 14 to perform format conversion on the data transmitted between the connected rate conversion unit 14 and the interface IP core 504.

[0049] After the format conversion unit 503 converts the received data into data that conforms to the protocol corresponding to the interface IP core, the interface IP core can realize the protocol interface signal conversion from the physical layer to the data link layer and then to the transaction layer. When the interface extender 12 communicates with the front-end server 11 through the PCIe interface, that is, when the first interface 111, the second interface 121 and the third interface 122 are all PCIe interfaces, the interface IP core 504 is also a PCIe IP core.

[0050] In this embodiment, the parallel processing unit 501 exchanges data with the rate conversion unit 14 through the format conversion unit 503 and the interface IP core 504. By connecting the format conversion unit 503 between the interface IP core 504 and the rate conversion unit 14, the format conversion unit 503 can convert the data from the interface IP core 504 into data that conforms to the rate conversion unit 14, ensuring that the rate conversion unit 14 and the parallel processing unit 501 can exchange data normally, thereby ensuring that the chip simulation verification process can proceed smoothly.

[0051] Chip simulation verification methods

[0052] Figure 6 This is a flowchart of a chip simulation verification method according to an embodiment of this application. This chip simulation verification method can be executed by the chip simulation verification system 10 in the above embodiment. Figure 6 As shown, the chip simulation verification method includes the following steps:

[0053] Step 601: The hardware simulation accelerator includes at least two simulation units that simulate at least two chips to be verified;

[0054] Step 602: The front-end server communicates with each simulation unit through the interface expander to verify the chip to be verified simulated by each simulation unit. The front-end server is provided with at least one first interface, which is configured to connect to a second interface on an interface expander. Each interface expander includes a second interface and at least two third interfaces connected to the second interface. Each simulation unit is connected to a third interface, and different simulation units are connected to different third interfaces.

[0055] In this embodiment, the front-end server includes at least one first interface. Each first interface can be connected to a second interface on an interface expander. Each interface expander has multiple third interfaces, each of which can be connected to a simulation unit. Each simulation unit can simulate a chip to be verified. The front-end server communicates with each simulation unit through the interface expander to verify the chip to be verified simulated by each simulation unit. The interface expander can expand each first interface on the front-end server into multiple third interfaces, and each third interface can connect to a simulation unit. This allows one or more simulation units to be connected to the front-end server according to the chip verification requirements, enabling the verification of different numbers of interconnected chips through the same front-end server, thus improving the applicability of the chip simulation verification system.

[0056] It should be noted that the details of the chip simulation verification method have been described in detail in conjunction with the structural diagram in the chip simulation verification system section of the above embodiments. For the specific process, please refer to the description in the aforementioned chip simulation verification system embodiments, and will not be repeated here.

[0057] The commercial value of the embodiments in this application

[0058] In this embodiment, the front-end server is connected to an interface expander. The interface expander can be connected to multiple rate conversion units, each of which can be connected to a simulation unit. Each simulation unit can simulate a chip, and the simulation units can be connected to each other to simulate multi-chip interconnection. The interface expander can expand a first interface on the front-end server into multiple third interfaces, each of which can connect to a simulation unit. This allows one or more simulation units to be connected to the front-end server according to the chip verification requirements, enabling the verification of different numbers of interconnected chips through the same front-end server, thus improving the applicability of the chip simulation verification system. Expanding the interfaces on the front-end server through the interface expander, with technical support provided by the suppliers of the front-end server and hardware simulation accelerator, ensures high efficiency and low cost in chip simulation verification.

[0059] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0060] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0061] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0062] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A chip simulation and verification system, comprising: A front-end server, a hardware emulation accelerator, and at least one interface extender; The front-end server is provided with at least one first interface, which is configured to connect to a second interface on one of the interface extenders. Each interface extender includes a second interface and at least two third interfaces connected to the second interface. The hardware simulation accelerator includes at least two simulation units, each of which is connected to one of the third interfaces, and different simulation units are connected to different third interfaces. The simulation unit is used to simulate the chip to be verified; The front-end server is used to communicate with each of the simulation units through the interface extender to verify the chip to be verified simulated by each of the simulation units. The chip simulation and verification system also includes: at least two rate conversion units; Each of the third interfaces is connected to one of the rate conversion units, and different third interfaces are connected to different rate conversion units; The rate conversion unit is configured to be connected to one of the analog units, and different rate conversion units are connected to different analog units; The rate conversion unit is used to cache the communication data between the connected simulation unit and the front-end server.

2. The chip simulation and verification system according to claim 1, wherein, The interface extender includes: an expansion board, at least one connection board, and at least two connection cables; The expansion board is provided with a second interface and at least two first connection line interfaces connected to the second interface; The connection board is provided with at least one second connection cable interface and at least one third interface, and different second connection cable interfaces are connected to different third interfaces; Each of the first connection cable interfaces is connected to a second connection cable interface via a connection cable, and different first connection cable interfaces are connected to different second connection cable interfaces.

3. The chip simulation and verification system according to claim 2, wherein, Each of the connection boards is provided with at least two second connection cable interfaces and at least two third interfaces, with different second connection cable interfaces connected to different third interfaces.

4. The chip simulation and verification system according to claim 2, wherein, The number of first connection cable interfaces on each expansion board is n, and the bandwidth of each first connection cable interface is equal to 1 / n of the bandwidth of the second interface.

5. The chip simulation and verification system according to claim 2, wherein, The first interface, the second interface, and the third interface are all standard interfaces of high-speed serial computer expansion bus.

6. The chip simulation and verification system according to claim 5, wherein, Both the first and second connection cable interfaces are Mini SAS interfaces, and the connection cable is a Mini SAS connection cable.

7. The chip simulation and verification system according to any one of claims 1-6, wherein, Each of the simulation units simulates a parallel processing unit and an inter-chip communication unit that are connected; The inter-chip communication unit simulated by each of the simulation units is connected to the inter-chip communication unit simulated by at least one other simulation unit; The parallel processing unit is used to execute the parallel processing tasks sent by the front-end server; The inter-chip communication unit is used to transmit communication data between the connected parallel processing units.

8. The chip simulation and verification system according to claim 7, wherein, The simulation unit includes: a format conversion unit; The format conversion unit is connected to the interface IP core simulated by the simulation unit, and the interface IP core is connected to the parallel processing unit; The format conversion unit is configured to be connected to one of the rate conversion units to perform format conversion on the data transmitted between the connected rate conversion unit and the interface IP core.

9. A chip simulation and verification method, comprising: The hardware simulation accelerator includes at least two simulation units that simulate at least two chips to be verified; The front-end server communicates with each of the simulation units through an interface extender to verify the chip to be verified simulated by each simulation unit. The front-end server has at least one first interface configured to connect to a second interface on one of the interface extenders. Each interface extender includes one second interface and at least two third interfaces connected to the second interface. Each third interface is connected to a rate conversion unit, and different third interfaces are connected to different rate conversion units. Each rate conversion unit is connected to one of the simulation units, and different rate conversion units are connected to different simulation units. The rate conversion unit is used to cache the communication data between the connected simulation units and the front-end server.

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