Electronic device with alignment marks

Abstract

An electronic device with alignment marks includes a conductive via array substrate, an outer layer board, and an alignment substrate. The conductive via array substrate has a plurality of first conductive vias. The outer layer board has a plurality of second conductive vias and is disposed on one side of the conductive via array substrate. The first conductive vias have a higher density or number than the second conductive vias. Some of the first conductive vias are electrically connected to the second conductive vias, and others are electrically floating. The alignment substrate includes a core layer disposed on the outer layer board, a plurality of conductive traces disposed in the core layer, a plurality of inner connection pads, and a plurality of alignment mark pads. The inner connection pads and the alignment mark pads are disposed on a surface of the core layer that is distal from the outer layer board. Some of the conductive traces are electrically connected to some of the inner connection pads and some of the first conductive vias. Each of the alignment mark pads has a different pattern than each of the inner connection pads.

Description

TECHNICAL FIELD

[0001] The present invention relates to an electronic device with alignment marks. BACKGROUND

[0002] In the past, electronic components are usually arranged on a conductive via substrate, and the external electrical parts are operated by applying a specified potential to the conductive via substrate. The conductive via substrate has a plurality of conductive vias. The developers of the conductive via substrate usually design the number and position of the plurality of conductive vias according to the electrical configuration of the external electrical parts to be arranged.

[0003] Therefore, for different electrical configurations of the external electrical parts, the developers of the conductive via substrate design different configurations of the conductive vias of the conductive via substrate to match the different external electrical parts. However, in order to match the different external electrical parts, a large amount of additional manpower and resources are usually consumed in the design of the structure and manufacturing process of the different specifications of the conductive via substrate. SUMMARY

[0004] In view of the above problems, one object of the present invention is to provide an electronic device with alignment marks, wherein the conductive via array substrate can be flexibly used for most types of external electrical parts.

[0005] One embodiment of the present invention provides an electronic device with alignment marks, which comprises a conductive via array substrate, an outer layer board and an alignment substrate. The conductive via array substrate has a plurality of first conductive vias. The outer layer board has a plurality of second conductive vias. The outer layer board is arranged on one side of the conductive via array substrate. The distribution density or number of the first conductive vias is greater than that of the second conductive vias, so that a part of the first conductive vias are electrically connected to the second conductive vias, and another part of the first conductive vias are electrically floating. The alignment substrate comprises a core layer, a plurality of conductive traces, a plurality of inner connection pads and a plurality of alignment mark pads. The core layer has a first surface and a second surface. The core layer is arranged on the outer layer board. The first surface faces the outer layer board. The conductive traces are arranged in the core layer. The inner connection pads are arranged on the second surface of the core layer. A part of the conductive traces are electrically connected to a part of the inner connection pads and a part of the first conductive vias. The alignment mark pads are arranged on the second surface of the core layer. The pattern of each alignment mark pad is different from that of each inner connection pad.

[0006] Another embodiment of the present invention provides an electronic device with alignment marks, comprising: a conductive via array substrate, an outer layer plate, and an alignment substrate. The conductive via array substrate has a plurality of first conductive vias. The outer layer plate has a plurality of second conductive vias. The outer layer plate is disposed on one side of the conductive via array substrate. The distribution density or number of the first conductive vias is greater than the distribution density or number of the second conductive vias, such that a portion of the first conductive vias are electrically connected to the second conductive vias. Another portion of the first conductive vias are electrically floating. The alignment substrate includes: a core layer, a plurality of conductive traces, a plurality of internal connection pads, a plurality of alignment mark pads, and a passivation layer. The core layer has a first surface and a second surface. The core layer is disposed on the outer layer plate. The first surface faces the outer layer plate. The conductive traces are disposed within the core layer. The internal connection pads are disposed on the second surface of the core layer. A portion of the conductive traces are electrically connected to a portion of the internal connection pads and a portion of the first conductive vias. The alignment mark pads are disposed on the second surface of the core layer. The passivation layer covers the core layer and has a plurality of first openings and a plurality of second openings. The passivation layer is opaque. Each first opening exposes a portion of the inner connecting pad. Each second opening exposes a portion of the alignment mark pad. The size or shape of the pattern in each first opening differs from the size or shape of the pattern in each second opening.

[0007] According to an embodiment of the present invention, an electronic device with alignment marks, by having a greater distribution density or number of first conductive vias than a greater distribution density or number of second conductive vias, allows most types of external electrical components to be disposed on the conductive via array substrate via the second conductive vias when mounted on the alignment substrate, thereby causing some of the first conductive vias to be electrically floating. Furthermore, manufacturers of the electronic device can easily mount external electrical components onto the alignment substrate using the alignment mark pads. Therefore, most types of external electrical components can be disposed in electronic devices with alignment marks of uniform specifications, thus saving manpower and resources in the design of the structure and manufacturing process of electronic devices with alignment marks.

[0008] The above description of the invention and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the invention, and to provide a further explanation of the claims of the invention. Attached Figure Description

[0009] Figure 1 This is a side cross-sectional view of an electronic device with alignment marks according to an embodiment of the present invention;

[0010] Figure 2 for Figure 1 A top view of an electronic device with alignment marks;

[0011] Figure 3 for Figure 1 A partial side cross-sectional view of an electronic device with alignment marks;

[0012] Figure 4 Partial side view cross-sectional schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0013] Figure 5 Partial side view cross-sectional schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0014] Figure 6 Partial side view cross-sectional schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0015] Figure 7 Top view schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0016] Figure 8 Top view schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0017] Figure 9 Partial top view schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0018] Figure 10 Partial side view cross-sectional schematic taken along line I-I of Figure 9 ;

[0019] Figure 11 Partial side view cross-sectional schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0020] Figure 12 Partial top view schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0021] Figure 13 Partial side view cross-sectional schematic taken along line II-II of Figure 12 ;

[0022] Figure 14 Partial top view schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0023] Figure 15 Partial side view cross-sectional schematic taken along line III-III of Figure 14 ;

[0024] Figure 16 Partial top view schematic of an electronic device with alignment marks according to another embodiment of the present invention;

[0025] Figure 17 Partial side view cross-sectional schematic taken along line IV-IV of Figure 16 ;

[0026] Figure 18 Partial side view cross-sectional schematic of an electronic device with alignment marks for another embodiment of the present invention;

[0027] Figure 19 Top view schematic of an alignment substrate of an electronic device with alignment marks for another embodiment of the present invention;

[0028] Figure 20 Top view schematic of an alignment substrate of an electronic device with alignment marks for another embodiment of the present invention;

[0029] Figure 21 Top view schematic of an alignment substrate of an electronic device with alignment marks for another embodiment of the present invention;

[0030] Figure 22 Top view schematic of an alignment substrate of an electronic device with alignment marks for another embodiment of the present invention;

[0031] Figure 23 Top view schematic of an alignment substrate of an electronic device with alignment marks for another embodiment of the present invention.

[0032] Legend

[0033] 1, 2, 3, 4, 5, 6, 7: electronic device

[0034] 11: array substrate of conductive vias

[0035] 11a: surface

[0036] 111: first conductive via

[0037] 12: outer layer board

[0038] 121: second conductive via

[0039] 13, 23, 33, 43, 53, 63, 73, 83, 83', 83", 83'", 93: alignment substrate

[0040] 13a: first surface

[0041] 13b, 43b, 53b, 63b, 73b: second surface

[0042] 130, 430, 530, 630, 730, 930: core layer

[0043] 131: conductive trace

[0044] 132, 232a, 232b, 332, 432, 532, 632, 732, 832, 932: inner connection pad

[0045] 133, 233a, 233b, 333a, 333b, 433, 533, 633, 733, 733', 833a, 833b, 933: alignment mark pad

[0046] 14, 24a, 24b, 34: electronic component

[0047] 141, 241a, 241b, 341a, 341b: mark

[0048] 142, 242a, 242b: conductive pad

[0049] 15, 45, 55, 65, 75, 95: passivation layer

[0050] 150, 450, 750, 950a, 950b: opening

[0051] 16: switchable circuit chip

[0052] 17, 47, 57, 67, 77: inner connection bump

[0053] 18, 18', 68: alignment bump

[0054] 19: external connection point

[0055] 439: conductive trace

[0056] 9: solder

[0057] A, B: region

[0058] D1, D2, D3, D4, D5, D6, D7, D8, D9, D10: distance

[0059] N: normal direction

[0060] P1, P2, P3, P4, P5, P6, P7, P8, P9: pattern DETAILED DESCRIPTION

[0061] The detailed features and advantages of the embodiments of the present application are described in detail in the embodiments below, which are sufficient to enable any person with ordinary knowledge in the art to understand the technical content of the embodiments of the present application and to implement the same, and according to the content disclosed in the specification, claims and drawings, any person with ordinary knowledge in the art can easily understand the related purposes and advantages of the present application. The following embodiments are further detailed to illustrate the concept of the present application, but not to limit the scope of the present application in any way.

[0062] In the so-called schematic drawings of the present specification, exaggeration of dimensions, proportions and angles, etc. can be present for the purpose of illustration, but are not intended to limit the present application. Various modifications can be made without departing from the spirit of the present application. The up, down, front and back orientations mentioned in the description of the embodiments and the drawings are for the purpose of illustration, but are not intended to limit the present application.

[0063] Please refer to Figure 1 , Figure 2 and Figure 3 . Figure 1 A side view cross-sectional schematic diagram of an alignment mark-equipped electronic device according to an embodiment of the present application is shown. Figure 2 A top view schematic diagram of the alignment mark-equipped electronic device of Figure 1 is shown. Figure 3 A partial side view cross-sectional schematic diagram of the alignment mark-equipped electronic device of Figure 1 is shown.

[0064] As shown in Figure 1 , in the present embodiment, the alignment mark-equipped electronic device 1 includes a conductive via array substrate 11, an outer layer plate 12, an alignment substrate 13, an electronic component 14, a switchable circuit chip 16, a plurality of external connection pads 19 and a plurality of solders 9.

[0065] The conductive via array substrate 11 has a plurality of first conductive vias 111. The switchable circuit chip 16 is disposed on the conductive via array substrate 11 and is electrically connected to the plurality of first conductive vias 111. The outer layer plate 12 is disposed on one side of the conductive via array substrate 11 and surrounds the switchable circuit chip 16. The outer layer plate 12 has a plurality of second conductive vias 121. The distribution density or number of the first conductive vias 111 is greater than that of the second conductive vias 121, so that a part of the plurality of first conductive vias 111 is electrically connected to the plurality of second conductive vias 121, and another part of the plurality of first conductive vias 111 is electrically floating.

[0066] The alignment substrate 13 includes a core layer 130, a plurality of conductive traces 131, a plurality of inner connection pads 132, a plurality of alignment mark pads 133, and a passivation layer 15. The core layer 130 has a first surface 13a and a second surface 13b. The core layer 130 is disposed on the outer layer board 12. The first surface 13a faces the outer layer board 12. The conductive traces 131 are disposed in the core layer 130. The inner connection pads 132 are disposed on the second surface 13b of the core layer 130. A portion of the plurality of conductive traces 131 are electrically connected to the plurality of alignment mark pads 133. A portion of the plurality of conductive traces 131 are electrically connected to a portion of the plurality of second conductive vias 121. In other words, a portion of the plurality of inner connection pads 132 are electrically connected to a portion of the plurality of first conductive vias 111 via a portion of the plurality of conductive traces 131 and a portion of the plurality of second conductive vias 121. A portion of the plurality of conductive traces 131 are electrically connected to the switchable circuit chip 16. The switchable circuit chip 16 is used to control the electrical connection relationship between a portion of the plurality of inner connection pads 132 and the plurality of first conductive vias 111. The plurality of alignment mark pads 133 are disposed on the second surface 13b of the core layer 130. The plurality of alignment mark pads 133 and the plurality of inner connection pads 132 do not overlap in the normal direction N of the second surface 13b.

[0067] As shown in FIG. 1A, the pattern of each alignment mark pad 133 is different from the pattern of each inner connection pad 132. Specifically, the size, shape, or color of the pattern of each alignment mark pad 133 is different from the size, shape, or color of the pattern of each inner connection pad 132. In the present embodiment, the pattern of each alignment mark pad 133 is a square, and the pattern of each inner connection pad 132 is a circle. The density of the arrangement of the plurality of inner connection pads 132 is greater than the density of the arrangement of the plurality of alignment mark pads 133. The plurality of alignment mark pads 133 are arranged in a square array. The plurality of inner connection pads 132 are arranged in a square array excluding the positions of the alignment mark pads 133. Figure 2 As shown in FIG. 1A, the pattern of each alignment mark pad 133 is different from the pattern of each inner connection pad 132. Specifically, the size, shape, or color of the pattern of each alignment mark pad 133 is different from the size, shape, or color of the pattern of each inner connection pad 132. In the present embodiment, the pattern of each alignment mark pad 133 is a square, and the pattern of each inner connection pad 132 is a circle. The density of the arrangement of the plurality of inner connection pads 132 is greater than the density of the arrangement of the plurality of alignment mark pads 133. The plurality of alignment mark pads 133 are arranged in a square array. The plurality of inner connection pads 132 are arranged in a square array excluding the positions of the alignment mark pads 133.

[0068] Figure 1 As shown in FIG. 1A, the pattern of each alignment mark pad 133 is different from the pattern of each inner connection pad 132. Specifically, the size, shape, or color of the pattern of each alignment mark pad 133 is different from the size, shape, or color of the pattern of each inner connection pad 132. In the present embodiment, the pattern of each alignment mark pad 133 is a square, and the pattern of each inner connection pad 132 is a circle. The density of the arrangement of the plurality of inner connection pads 132 is greater than the density of the arrangement of the plurality of alignment mark pads 133. The plurality of alignment mark pads 133 are arranged in a square array. The plurality of inner connection pads 132 are arranged in a square array excluding the positions of the alignment mark pads 133. Figure 3 As shown in FIG. 1A, the pattern of each alignment mark pad 133 is different from the pattern of each inner connection pad 132. Specifically, the size, shape, or color of the pattern of each alignment mark pad 133 is different from the size, shape, or color of the pattern of each inner connection pad 132. In the present embodiment, the pattern of each alignment mark pad 133 is a square, and the pattern of each inner connection pad 132 is a circle. The density of the arrangement of the plurality of inner connection pads 132 is greater than the density of the arrangement of the plurality of alignment mark pads 133. The plurality of alignment mark pads 133 are arranged in a square array. The plurality of inner connection pads 132 are arranged in a square array excluding the positions of the alignment mark pads 133. Figure 3 The conductive traces 131 of the alignment substrate 13 are omitted from illustration.

[0069] ​Electronic component 14 is disposed on alignment substrate 13. Electronic component 14 is electrically connected to multiple first conductive vias 111 via multiple solder pads 9, a portion of multiple internal connection pads 132, a portion of multiple conductive traces 131, and a switchable circuit chip 16. Electronic component 14 includes multiple markers 141 and multiple conductive pads 142. The multiple markers 141 are aligned with a portion of multiple alignment marker pads 133. The multiple conductive pads 142 are electrically connected to a portion of the multiple internal connection pads 132. Figure 2 As shown, the number of alignment pads 133 is greater than the number of markings 141 on the electronic component 14.

[0070] like Figure 1 As shown, multiple external contact points 19 are disposed on a surface 11a of the conductive via array substrate 11 that is away from the alignment substrate 13 and are electrically connected to multiple first conductive vias 111.

[0071] In this embodiment, multiple alignment mark pads 133 and multiple inner connection pads 132 can be formed together. Therefore, the electronic device 1 does not need to form alignment marks by painting or other means.

[0072] Please refer to Figure 4 . Figure 4 A partial side cross-sectional view of an electronic device with alignment marks according to another embodiment of the present invention is illustrated.

[0073] In this embodiment, Figure 1 and Figure 3 Based on the electronic device 1 shown, the electronic device of this embodiment further includes a plurality of internal connection bumps 17. The plurality of internal connection bumps 17 are respectively disposed on a plurality of internal connection pads 132. The pattern P1 projected onto the second surface 13b by each internal connection bump 17 is larger than the pattern P2 projected onto the second surface 13b by each internal connection pad 132.

[0074] Please refer to Figure 5 . Figure 5 A partial side cross-sectional view of an electronic device with alignment marks according to another embodiment of the present invention is illustrated.

[0075] In this embodiment, Figure 1 and Figure 3Based on the electronic device 1 shown, the electronic device of this embodiment further includes a plurality of internal connection bumps 17 and a plurality of alignment bumps 18. The plurality of internal connection bumps 17 are respectively disposed on a plurality of internal connection pads 132. The plurality of alignment bumps 18 are respectively disposed on a plurality of alignment mark pads 133. The pattern P1 projected onto the second surface 13b by each internal connection bump 17 is smaller than the pattern P3 projected onto the second surface 13b by each alignment bump 18. The pattern P3 projected onto the second surface 13b by each alignment bump 18 is substantially equal to the pattern P4 projected onto the second surface 13b by each alignment mark pad 133.

[0076] Please refer to Figure 6 . Figure 6 A partial side cross-sectional view of an electronic device with alignment marks according to another embodiment of the present invention is illustrated.

[0077] In this embodiment, Figure 1 and Figure 3 Based on the electronic device 1 shown, the electronic device of this embodiment further includes a plurality of internal connecting bumps 17 and a plurality of alignment bumps 18'. The plurality of internal connecting bumps 17 are respectively disposed on a plurality of internal connecting pads 132. The plurality of alignment bumps 18' are respectively disposed on a plurality of alignment mark pads 133. The pattern P1 projected onto the second surface 13b by each internal connecting bump 17 is substantially equal to the pattern P5 projected onto the second surface 13b by each alignment bump 18'. The pattern P5 projected onto the second surface 13b by each alignment bump 18' is smaller than the pattern P4 projected onto the second surface 13b by each alignment mark pad 133.

[0078] Please refer to Figure 7 . Figure 7 A top view schematic diagram of an electronic device with alignment marks according to another embodiment of the present invention is shown.

[0079] In this embodiment, electronic device 2 and Figure 1 and Figure 2 The electronic device shown is similar to 1. The difference is that the alignment substrate 23 can be divided into region A and region B. The density of the plurality of inner connecting pads 232a in region A is less than the density of the plurality of inner connecting pads 232b in region B. The density of the plurality of alignment mark pads 233a in region A is less than the density of the plurality of alignment mark pads 233b in region B.

[0080] In region A, electronic component 24a is disposed on alignment substrate 23. Electronic component 24a includes a plurality of marks 241a and a plurality of conductive pads 242a. The plurality of marks 241a are aligned with a plurality of alignment mark pads 233a in a portion. Each conductive pad 242a is electrically connected to a plurality of internal connection pads 232a in a portion.

[0081] In region B, electronic elements 24b are disposed on alignment substrate 23. Electronic elements 24b include a plurality of marks 241b and a plurality of conductive pads 242b. The plurality of marks 241b align with a portion of the plurality of alignment mark pads 233b. Each conductive pad 242b is electrically connected to a portion of the plurality of inner connection pads 232b.

[0082] Please refer to Figure 8 . Figure 8 A top view schematic diagram of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0083] In this embodiment, electronic device 3 is similar to electronic device 1 shown in Figure 1 and Figure 2 , with the difference being alignment substrate 33 and electronic elements 34. The following omits other redundant descriptions.

[0084] In this embodiment, alignment substrate 33 includes a plurality of inner connection pads 332, a plurality of first alignment mark pads 333a, and a plurality of second alignment mark pads 333b. The pattern of each first alignment mark pad 333a is different from the pattern of each second alignment mark pad 333b. The pattern of each first alignment mark pad 333a is different from the pattern of each inner connection pad 332. The pattern of each second alignment mark pad 333b is different from the pattern of each inner connection pad 332. Specifically, the pattern of each first alignment mark pad 333a is a square, the pattern of each second alignment mark pad 333b is a rhombus, and the pattern of each inner connection pad 332 is a circle.

[0085] The density of the arrangement of the plurality of first alignment mark pads 333a is substantially equal to the density of the arrangement of the plurality of second alignment mark pads 333b. The density of the arrangement of the plurality of inner connection pads 332 is greater than the density of the arrangement of the plurality of first alignment mark pads 333a, and is greater than the density of the arrangement of the plurality of second alignment mark pads 333b.

[0086] The plurality of first alignment mark pads 333a are arranged in a square array. The plurality of second alignment mark pads 333b are arranged in a square array. The plurality of first alignment mark pads 333a and the plurality of second alignment mark pads 333b are staggered with each other. Two adjacent columns of first alignment mark pads 333a are sandwiched with one column of second alignment mark pads 333b. Two adjacent columns of second alignment mark pads 333b are sandwiched with one column of first alignment mark pads 333a. Two adjacent rows of first alignment mark pads 333a are sandwiched with one row of second alignment mark pads 333b. Two adjacent rows of second alignment mark pads 333b are sandwiched with one row of first alignment mark pads 333a. The plurality of inner connection pads 332 are arranged in a square array excluding the positions of the first alignment mark pads 333a and excluding the positions of the second alignment mark pads 333b.

[0087] The electronic device 4 is similar to the electronic device 1 shown in FIG. 1 except for the alignment substrate 43 and the inner connection bumps 47. The other descriptions are omitted.

[0088] Please refer to Figure 9 and Figure 10 . Figure 9 FIG. 6 shows a top view of a partial alignment mark-equipped electronic device according to another embodiment of the present application. Figure 10 FIG. 7 shows a side view of the electronic device of FIG. 6. Figure 9 FIG. 8 shows a cross-sectional view of the electronic device of FIG. 6 taken along the line I-I.

[0089] In this embodiment, the electronic device 4 is similar to the electronic device 1 shown in FIG. 1 except for the alignment substrate 43 and the inner connection bumps 47. The other descriptions are omitted. Figure 1 and Figure 2 In this embodiment, the electronic device 4 is similar to the electronic device 1 shown in FIG. 1 except for the alignment substrate 43 and the inner connection bumps 47. The other descriptions are omitted.

[0090] In this embodiment, the alignment substrate 43 includes a core layer 430, a plurality of inner connection pads 432, a plurality of alignment mark pads 433, and a passivation layer 45. The passivation layer 45 covers the plurality of alignment mark pads 433 and the core layer 430 and has a plurality of openings 450. The plurality of openings 450 expose the plurality of inner connection pads 432. The distance Dl from each of the alignment mark pads 433 to the second surface 43b of the core layer 430 is less than the distance D2 from each of the inner connection pads 432 to the second surface 43b. The plurality of inner connection pads 432 and the plurality of alignment mark pads 433 are respectively in different layers.

[0091] The plurality of inner connection bumps 47 are respectively disposed on the plurality of inner connection pads 432. The pattern P6 of each of the inner connection bumps 47 projected to the second surface 43b is substantially equal to the pattern P7 of each of the inner connection pads 432 projected to the second surface 43b.

[0092] The density of the arrangement of the plurality of inner connection pads 432 is greater than the density of the arrangement of the plurality of alignment mark pads 433. The plurality of alignment mark pads 433 are arranged in a square array. The plurality of inner connection pads 432 are also arranged in a square array. One of the alignment mark pads 433 overlaps five of the inner connection pads 432 in the normal direction N of the second surface 43b. Most of the inner connection pads 432 do not overlap the alignment mark pads 433 in the normal direction N. The pattern of each of the alignment mark pads 433 is larger than the pattern of each of the inner connection pads 432. The pattern of each of the alignment mark pads 433 is different from the pattern of each of the inner connection pads 432. Specifically, the pattern of each of the alignment mark pads 433 is a cross, and the pattern of each of the inner connection pads 432 is a circle. The passivation layer 45 is transparent or translucent. Thus, each of the alignment mark pads 433 can be optically recognized even though it is covered by the passivation layer 45 in a top view.

[0093] Please refer to Figure 11 . Figure 11 A partial side view cross-sectional schematic diagram of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0094] In this embodiment, the alignment substrate 43 of the electronic device is further provided with a plurality of conductive traces 439 based on the electronic device 4 shown in Figure 9 and Figure 10 . Each of the alignment mark pads 433 is electrically connected to the overlapped inner connection pads 432 via the plurality of conductive traces 439. In this embodiment, at least one of the inner connection pads 432 that overlaps the alignment mark pad 433 is not electrically connected to the alignment mark pad 433.

[0095] Please refer to Figure 12 and Figure 13 . Figure 12 A partial top view schematic diagram of an electronic device with alignment marks according to another embodiment of the present application is shown. Figure 13 A side view cross-sectional schematic diagram taken along line II-II of Figure 12 is shown.

[0096] In this embodiment, the electronic device 5 is similar to the electronic device 1 shown in Figure 1 and Figure 2 , except for the alignment substrate 53 and the inner connection bumps 57. The following description omits other redundant descriptions.

[0097] In this embodiment, the alignment substrate 53 includes a core layer 530, a plurality of inner connection pads 532, a plurality of alignment mark pads 533, and a passivation layer 55. The passivation layer 55 covers the core layer 530 and exposes the plurality of inner connection pads 532 and the plurality of alignment mark pads 533. The distance D3 from each alignment mark pad 533 to the second surface 53b of the core layer 530 is substantially equal to the distance D4 from each inner connection pad 532 to the second surface 53b. The plurality of inner connection pads 532 and the plurality of alignment mark pads 533 are in the same layer. A plurality of inner connection bumps 57 are respectively disposed on the plurality of inner connection pads 532.

[0098] The density of the arrangement of the plurality of inner connection pads 532 is greater than the density of the arrangement of the plurality of alignment mark pads 533. The plurality of alignment mark pads 533 are arranged in a square array. The plurality of inner connection pads 532 are also arranged in a square array. One alignment mark pad 533 surrounds five inner connection pads 532. The alignment mark pads 533 and the inner connection pads 532 do not overlap each other in the normal direction N of the second surface 53b. The pattern of each alignment mark pad 533 is larger in size than the pattern of each inner connection pad 532. The pattern of each alignment mark pad 533 is different from the pattern of each inner connection pad 532. Specifically, the pattern of each alignment mark pad 533 is a cross shape, and the pattern of each inner connection pad 532 is a circle shape.

[0099] Please refer to Figure 14 and Figure 15 . Figure 14 A top view schematic diagram of a portion of an electronic device with alignment marks according to another embodiment of the present application is shown. Figure 15 A side view schematic diagram taken along the III-III line of Figure 14 is shown.

[0100] In this embodiment, the electronic device 6 is similar to the electronic device 1 shown in Figure 1 and Figure 2 , except for the alignment substrate 63, the inner connection bumps 67, and the alignment bumps 68. The following description omits other redundant descriptions.

[0101] In this embodiment, the alignment substrate 63 includes a core layer 630, a plurality of inner connection pads 632, a plurality of alignment mark pads 633, and a passivation layer 65. The passivation layer 65 covers the core layer 630 and exposes the plurality of inner connection pads 632 and the plurality of alignment mark pads 633. The distance D5 from each alignment mark pad 633 to the second surface 63b of the core layer 630 is substantially equal to the distance D6 from each inner connection pad 632 to the second surface 63b. The plurality of inner connection pads 632 and the plurality of alignment mark pads 633 are in the same layer. A plurality of inner connection bumps 67 are respectively disposed on the plurality of inner connection pads 632. Five alignment bumps 68 are disposed on one alignment mark pad 633.

[0102] The density of the arrangement of the plurality of inner connection pads 632 is greater than the density of the arrangement of the plurality of alignment mark pads 633. The plurality of alignment mark pads 633 are arranged in a square array. The plurality of inner connection pads 632 are arranged in a square array excluding the positions of the alignment mark pads 633. The plurality of inner connection bumps 67 and the plurality of alignment bumps 68 are arranged together in a square array. The alignment mark pads 633 and the inner connection pads 632 do not overlap each other in the normal direction N of the second surface 63b. The size of the pattern of each alignment mark pad 633 is greater than the size of the pattern of five inner connection pads 632. The pattern of each alignment mark pad 633 is different from the pattern of each inner connection pad 632. Specifically, the pattern of each alignment mark pad 633 is a cross shape, and the pattern of each inner connection pad 632 is a circular shape.

[0103] Please refer to Figure 16 and Figure 17 . Figure 16 A top view schematic diagram of a portion of an electronic device with alignment marks according to another embodiment of the present application is shown. Figure 17 A side view cross-sectional schematic diagram taken along the IV-IV line of Figure 16 is shown.

[0104] In this embodiment, the electronic device 7 is similar to the electronic device 1 shown in Figure 1 and Figure 2 , except for the alignment substrate 73 and the inner connection bumps 77. The other descriptions are omitted below.

[0105] In this embodiment, the alignment substrate 73 includes a core layer 730, a plurality of inner connection pads 732, a plurality of alignment mark pads 733, and a passivation layer 75. The passivation layer 75 covers the plurality of alignment mark pads 733 and the core layer 730 and has a plurality of openings 750. The plurality of openings 750 expose the plurality of inner connection pads 732. The distance D7 from each alignment mark pad 733 to the second surface 73b of the core layer 730 is substantially equal to the distance D8 from each inner connection pad 732 to the second surface 73b. The plurality of inner connection pads 732 and the plurality of alignment mark pads 733 are in the same layer.

[0106] The plurality of inner connection bumps 77 are respectively disposed on the plurality of inner connection pads 732. The pattern P8 of each inner connection bump 77 projected to the second surface 73b is smaller than the pattern P9 of each inner connection pad 732 projected to the second surface 73b.

[0107] The density of the plurality of inner connection pads 732 is greater than the density of the plurality of alignment mark pads 733. The plurality of inner connection pads 732 is arranged in a square array. The plurality of alignment mark pads 733 is also arranged in a square array. Each alignment mark pad 733 is located in a gap between the plurality of inner connection pads 732. The plurality of alignment mark pads 733 and the plurality of inner connection pads 732 do not overlap each other in the normal direction N of the second surface 73b. The pattern of each alignment mark pad 733 is different from the pattern of each inner connection pad 732. Specifically, the pattern of each alignment mark pad 733 is a cross shape, and the pattern of each inner connection pad 732 is a circular shape. The passivation layer 75 is transparent or translucent. Thus, under a top-down view, each alignment mark pad 733 can be optically recognized even though it is covered by the passivation layer 75.

[0108] Please refer to Figure 18 . Figure 18 A partial side view cross-sectional schematic diagram of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0109] The electronic device of the present embodiment is similar to the electronic device 7 shown in Figure 16 and Figure 17 , except for the plurality of inner connection pads 732 and the plurality of alignment mark pads 733' of the alignment substrate 73. The following omits other redundant descriptions.

[0110] The distance D9 of each alignment mark pad 733 to the second surface 73b of the core layer 730 is less than the distance D10 of each inner connection pad 732 to the second surface 73b. The plurality of inner connection pads 732 and the plurality of alignment mark pads 733' are respectively in different layers. The plurality of inner connection pads 732 and the plurality of alignment mark pads 733' do not overlap each other in the normal direction N of the second surface 73b. The passivation layer 75 is transparent or translucent. Thus, under a top-down view, each alignment mark pad 733' can be optically recognized even though it is covered by the passivation layer 75.

[0111] Please refer to Figure 19 . Figure 19 A top view schematic diagram of an alignment substrate of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0112] In this embodiment, the alignment substrate 83 includes a plurality of inner connection pads 832, a plurality of first alignment mark pads 833a, and a plurality of second alignment mark pads 833b. The patterns of each first alignment mark pad 833a are different from the patterns of each second alignment mark pad 833b. The patterns of each first alignment mark pad 833a are different from the patterns of each inner connection pad 832. The patterns of each second alignment mark pad 833b are different from the patterns of each inner connection pad 832. Specifically, the pattern of each first alignment mark pad 833a is cross-shaped, the pattern of each second alignment mark pad 833b is rhomboid, and the pattern of each inner connection pad 832 is circular.

[0113] The density of the plurality of first alignment marker pads 833a is greater than the density of the plurality of second alignment marker pads 833b. The density of the plurality of inner connecting pads 832 is greater than the density of the plurality of first alignment marker pads 833a, and greater than the density of the plurality of second alignment marker pads 833b.

[0114] Multiple second alignment marker pads 833b are located in the upper left and lower right corners of the figure. Multiple first alignment marker pads 833a are arranged in a square array at the position excluding the second alignment marker pads 833b. Multiple inner connecting pads 832 are arranged in a square array at the position excluding both the first alignment marker pads 833a and the second alignment marker pads 833b.

[0115] Please refer to Figure 20 . Figure 20 A top view schematic diagram illustrating an alignment substrate of an electronic device with alignment marks according to another embodiment of the present invention is shown.

[0116] In this embodiment, the alignment substrate 83' and Figure 19 The alignment substrate 83 shown is similar, except that it differs in the number and arrangement of the plurality of inner connecting pads 832, the plurality of first alignment mark pads 833a, and the plurality of second alignment mark pads 833b. Further details are omitted below.

[0117] In this embodiment, the density of the plurality of first alignment marker pads 833a is substantially equal to the density of the plurality of second alignment marker pads 833b. The density of the plurality of inner connection pads 832 is greater than the density of the plurality of first alignment marker pads 833a and greater than the density of the plurality of second alignment marker pads 833b.

[0118] The first alignment mark pads 833a are arranged in a rectangular array. The second alignment mark pads 833b are arranged in a rectangular array. The first alignment mark pads 833a and the second alignment mark pads 833b are staggered with respect to each other. Two adjacent columns of the first alignment mark pads 833a are sandwiched by one column of the second alignment mark pads 833b. Two adjacent columns of the second alignment mark pads 833b are sandwiched by one column of the first alignment mark pads 833a. The inner connection pads 832 are arranged in a square array at positions excluding the first alignment mark pads 833a and excluding the second alignment mark pads 833b.

[0119] Please refer to Figure 21 . Figure 21 A top view of an alignment substrate of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0120] In this embodiment, the alignment substrate 83" is similar to the alignment substrate 83 shown in FIG. 8, except for the number and arrangement of the inner connection pads 832, the first alignment mark pads 833a, and the second alignment mark pads 833b. The following description omits other redundant descriptions. Figure 19

[0121] In this embodiment, the density of arrangement of the first alignment mark pads 833a is substantially equal to the density of arrangement of the second alignment mark pads 833b. The density of arrangement of the inner connection pads 832 is greater than the density of arrangement of the first alignment mark pads 833a, and is greater than the density of arrangement of the second alignment mark pads 833b.

[0122] The first alignment mark pads 833a are arranged in a rectangular array. The second alignment mark pads 833b are arranged in a rectangular array. The first alignment mark pads 833a and the second alignment mark pads 833b are staggered with respect to each other. Two adjacent columns of the first alignment mark pads 833a are sandwiched by one column of the second alignment mark pads 833b. Two adjacent columns of the second alignment mark pads 833b are sandwiched by one column of the first alignment mark pads 833a. The inner connection pads 832 are arranged in a square array at positions excluding the first alignment mark pads 833a and excluding the second alignment mark pads 833b.

[0123] Please refer to Figure 22 . Figure 22 A top view of an alignment substrate of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0124] In this embodiment, the alignment substrate 83" is similar to the alignment substrate 83 shown in FIG. 8, except for the number and arrangement of the inner connection pads 832, the first alignment mark pads 833a, and the second alignment mark pads 833b. The following description omits other redundant descriptions. Figure 19 ​The alignment substrate 83 shown is similar, except for the number and arrangement of the plurality of inner connection pads 832, the plurality of first alignment mark pads 833a, and the plurality of second alignment mark pads 833b. The following omits other redundant descriptions.

[0125] In this embodiment, the plurality of first alignment mark pads 833a are arranged at a density greater than the density at which the plurality of second alignment mark pads 833b are arranged. The plurality of inner connection pads 832 are arranged at a density greater than the density at which the plurality of first alignment mark pads 833a are arranged, and greater than the density at which the plurality of second alignment mark pads 833b are arranged.

[0126] The plurality of first alignment mark pads 833a are arranged in a square array. The plurality of second alignment mark pads 833b are arranged in a diamond array. The plurality of first alignment mark pads 833a and the plurality of second alignment mark pads 833b are staggered with respect to each other. Six of the first alignment mark pads 833a are arranged to form two adjacent squares. The center of one of the squares has one of the second alignment mark pads 833b. The other square does not have one of the second alignment mark pads 833b disposed therein. The plurality of inner connection pads 832 are arranged in a square array excluding the first alignment mark pads 833a and excluding the second alignment mark pads 833b.

[0127] Please refer to Figure 23 . Figure 23 A top view of an alignment substrate of an electronic device with alignment marks according to another embodiment of the present application is shown.

[0128] In this embodiment, the alignment substrate 93 includes a core layer 930, a plurality of inner connection pads 932, a plurality of alignment mark pads 933, and a passivation layer 95. The plurality of inner connection pads 932 and the plurality of alignment mark pads 933 are disposed on the core layer 930. The passivation layer 95 covers the core layer 930, the plurality of inner connection pads 932, and the plurality of alignment mark pads 933. The passivation layer 95 is opaque and has a plurality of first openings 950a and a plurality of second openings 950b. Each first opening 950a exposes a portion of each inner connection pad 932. Each second opening 950b exposes a portion of each alignment mark pad 933. Each alignment mark pad 933 has a same pattern as each inner connection pad 932, which is circular. The pattern of each first opening 950a has a different size or shape than the pattern of each second opening 950b. Specifically, the pattern of each first opening 950a is circular, and the pattern of each second opening 950b is diamond-shaped.

[0129] In summary, the electronic device with alignment marks of an embodiment of the present application has a distribution density or number of the first conductive vias greater than that of the second conductive vias, so that most types of external electrical components can be arranged on the alignment substrate through the second conductive vias to the conductive via array substrate, and thus some of the first conductive vias are electrically floating. Furthermore, the manufacturer of the electronic device can easily arrange the external electrical components on the alignment substrate through the alignment mark pads of the alignment substrate. Therefore, most types of external electrical components can be arranged in the electronic device with alignment marks of the same specification, so that manpower and resources can be saved in the design of the structure and manufacturing process of the electronic device with alignment marks. Moreover, the alignment mark pads and the inner connection pads can be formed together, so that the alignment marks do not need to be formed by painting or other means.

Claims

1. An electronic device with alignment marks, comprising: a conductive via array substrate having a plurality of first conductive vias; an outer layer having a plurality of second conductive vias, the outer layer disposed on a side of the conductive via array substrate, the first conductive vias having a distribution density or number greater than that of the second conductive vias, such that a portion of the first conductive vias are electrically connected to the second conductive vias, and another portion of the first conductive vias are electrically floating; and an alignment substrate comprising: a core layer having a first surface and a second surface, the core layer disposed on the outer layer, the first surface facing the outer layer; a plurality of conductive traces disposed within the core layer; a plurality of inner connection pads disposed on the second surface of the core layer, a portion of the conductive traces electrically connected to a portion of the inner connection pads and a portion of the first conductive vias; and a plurality of alignment mark pads disposed on the second surface of the core layer; wherein a pattern of each of the alignment mark pads is different from a pattern of each of the inner connection pads.

2. The electronic device of claim 1, further comprising at least one electronic component disposed on the alignment substrate, the at least one electronic component comprising a plurality of marks and a plurality of conductive pads, the marks aligned to a portion of the alignment mark pads, and the conductive pads electrically connected to a portion of the inner connection pads.

3. The electronic device of claim 2, wherein a number of the alignment mark pads is greater than a number of the marks of the at least one electronic component.

4. The electronic device of claim 1, wherein a density of an arrangement of the inner connection pads is greater than a density of an arrangement of the alignment mark pads.

5. The electronic device of claim 1, wherein the alignment mark pads and the inner connection pads directly contact the second surface.

6. The electronic device of claim 1, wherein the alignment substrate further comprises a passivation layer, the passivation layer being transparent or translucent, the passivation layer covering the alignment mark pads and the core layer and having a plurality of openings exposing the inner connection pads, a distance of the alignment mark pads to the second surface being less than a distance of the inner connection pads to the second surface.

7. The electronic device of claim 6, wherein the alignment mark pads and a portion of the inner connection pads overlap in a normal direction of the second surface, a size of the pattern of each of the alignment mark pads being greater than a size of the pattern of each of the inner connection pads.

8. The electronic device of claim 7, wherein each of the alignment mark pads is electrically connected to at least one of the inner connection pads that overlaps.

9. The electronic device of claim 6, wherein the alignment mark pads and the inner connection pads do not overlap in the normal direction of the second surface.

10. The electronic device of claim 1, wherein the alignment substrate further comprises a passivation layer, the passivation layer covering the core layer and having a plurality of openings exposing the inner connection pads and the alignment mark pads. ​ 11. The electronic device of claim 10, wherein the alignment substrate further comprises a plurality of inner connection bumps and a plurality of alignment bumps, the inner connection bumps are respectively disposed on the inner connection pads, a pattern of each of the inner connection bumps projected onto the second surface is less than or equal to a pattern of each of the inner connection pads projected onto the second surface, the alignment bumps are respectively disposed on the alignment mark pads, a pattern of each of the alignment bumps projected onto the second surface is less than or equal to a pattern of each of the alignment mark pads projected onto the second surface.

12. The electronic device of claim 1, wherein the alignment substrate further comprises a passivation layer, the passivation layer is transparent or translucent, the passivation layer covers the core layer and the alignment mark pads and has a plurality of openings, the openings expose the inner connection pads, distances of the alignment mark pads to the second surface are substantially equal to distances of the inner connection pads to the second surface.

13. The electronic device of claim 12, wherein the alignment substrate further comprises a plurality of inner connection bumps, the inner connection bumps are respectively disposed on the inner connection pads, a pattern of each of the inner connection bumps projected onto the second surface is less than or equal to a pattern of each of the inner connection pads projected onto the second surface.

14. The electronic device of claim 1, wherein a size, a shape or a color of a pattern of each of the alignment mark pads is different from a size, a shape or a color of a pattern of each of the inner connection pads.

15. The electronic device of claim 1, wherein the alignment mark pads comprise a plurality of first alignment mark pads and a plurality of second alignment mark pads, a pattern of each of the first alignment mark pads is different from a pattern of each of the second alignment mark pads, a pattern of each of the first alignment mark pads is different from a pattern of each of the inner connection pads, a pattern of each of the second alignment mark pads and a pattern of each of the inner connection pads are different.

16. The electronic device of claim 1, wherein a portion of the conductive traces are electrically connected to the alignment mark pads.

17. The electronic device of claim 1, wherein at least one of the conductive traces is electrically connected to at least one of the second conductive vias.

18. The electronic device of claim 17, further comprising a switchable circuit chip, the switchable circuit chip is electrically connected to at least one of the first conductive vias, a portion of the conductive traces of the alignment substrate are electrically connected to the switchable circuit chip, the switchable circuit chip is used to control an electrical connection relationship between a portion of the inner connection pads and at least one of the first conductive vias.

19. The electronic device of claim 18, further comprising at least one electronic component, the at least one electronic component is disposed on the alignment substrate, the at least one electronic component is electrically connected to at least one of the first conductive vias via a portion of the inner connection pads, a portion of the conductive traces and the switchable circuit chip.

20. The electronic device of claim 1, further comprising a plurality of external connection pads, the external connection pads are disposed on a surface of the conductive via array substrate away from the alignment substrate and are electrically connected to the first conductive vias.

21. An electronic device with alignment marks, comprising: a conductive via array substrate having a plurality of first conductive vias; An outer layer plate having a plurality of second conductive vias, the outer layer plate disposed on a side of the conductive via array substrate, a distribution density or a number of the first conductive vias being greater than a distribution density or a number of the second conductive vias, such that a portion of the first conductive vias are electrically connected to the second conductive vias, and another portion of the first conductive vias are electrically floating; and An alignment substrate comprising: a core layer having a first surface and a second surface, the core layer disposed on the outer layer plate, the first surface facing the outer layer plate; a plurality of conductive traces disposed within the core layer; a plurality of inner connection pads disposed on the second surface of the core layer, a portion of the conductive traces electrically connected to a portion of the inner connection pads and a portion of the first conductive vias; a plurality of alignment mark pads disposed on the second surface of the core layer; and a passivation layer covering the core layer and having a plurality of first openings and a plurality of second openings, the passivation layer being opaque, each of the first openings exposing a portion of each of the inner connection pads, each of the second openings exposing a portion of each of the alignment mark pads, a pattern of a size or a shape of each of the first openings being different from a pattern of a size or a shape of each of the second openings.

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