A GaN HEMT power half-bridge circuit system

Abstract

The application relates to a GaN HEMT power half-bridge circuit system, which comprises a dead time control circuit (1), a level shift circuit and an upper side logic circuit (2), a logic and control circuit (3), a high side drive (4), a low side drive (5), a current detection circuit (6), a high side device (7), a low side device (8), a diode (D), a first capacitor (C101), an inductor (L), a second capacitor (C102) and a first resistor (R101). The GaN HEMT half-bridge circuit system of the embodiment of the application can reduce the static power consumption of the circuit, improve the performance of the circuit, and has the function of the protection circuit system for preventing the high side and low side devices from being in series; the performance of the half-bridge circuit is improved, the reliability of the circuit is improved, and the risk of equipment damage is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor device circuit, and particularly relates to a GaN HEMT power half-bridge circuit system. BACKGROUND

[0002] Gallium nitride (GaN) is a third-generation wide-bandgap semiconductor material representative, and is widely concerned by researchers in various countries. GaN has the characteristics of large band gap, high saturated electron drift speed, small dielectric constant and good chemical stability, so compared with Si-based devices, GaN-based HEMT devices have lower on-resistance, smaller parasitic capacitance, higher breakdown voltage and other excellent performances, and can meet the application requirements of larger power, smaller size and higher frequency of semiconductor devices in the next generation system.

[0003] Power electronic converters are developing towards high power density. In order to improve the power density of the converter, the switching frequency should be increased to reduce the size of passive components, and wide-bandgap devices, such as gallium nitride (GaN) transistors, are suitable for this situation. Compared with Si devices such as Si MOSFETs, GaN transistors have lower gate charge Qg, zero gate-drain recovery charge Qrr and lower on-resistance Rds(on), lower threshold voltage and lower minimum allowed gate-source voltage, so it can switch faster and has less switching and conduction loss. It is expected to replace traditional Si MOSFETs and become the implementation scheme of future high-performance power supply systems. The advantages of GaN devices are more obvious in high-voltage systems above 400v, which can realize higher switching frequency and power density, significantly improve the conversion efficiency of the system, and are particularly suitable for the miniaturization trend of power modules.

[0004] However, GaN HEMT devices are relatively weak in development, cannot use CMOS logic complementary circuits, and lack GaN power device protection circuits, resulting in the existing GaN HEMT devices constructed into power circuits having the disadvantages of serious power supply heating and low equipment reliability. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a GaN HEMT power half-bridge circuit system. The technical problems to be solved by the application are solved by the following technical scheme.

[0006] The embodiment of the application provides a GaN HEMT power half-bridge circuit system, which comprises a dead time control circuit, a level shift circuit and an upper side logic circuit, a logic and control circuit, a high side drive, a low side drive, a current detection circuit, a high side device, a low side device, a diode, a first capacitor, an inductor, a second capacitor and a first resistor, wherein,

[0007] The first input terminal of the dead time control circuit is connected with a first external signal source, the first output terminal of the dead time control circuit outputs a first target signal and is connected with the first input terminal of the level shift and up logic circuit; the first output terminal of the level shift and up logic circuit outputs a second target signal and is connected with the first input terminal of the high side driver, the second output terminal of the level shift and up logic circuit outputs a third target signal and is connected with the second input terminal of the high side driver, the output terminal of the high side driver outputs a fourth target signal and is connected with the gate of the high side device;

[0008] The second output terminal of the dead time control circuit outputs a fifth target signal and is connected with the first input terminal of the logic and control circuit; the first output terminal of the logic and control circuit outputs a sixth target signal and is connected with the first input terminal of the low side driver, the second output terminal of the logic and control circuit outputs a seventh target signal and is connected with the second input terminal of the low side driver; the output terminal of the low side driver outputs an eighth target signal and is connected with the gate of the low side device and the first input terminal of the current detection circuit;

[0009] The second input terminal of the logic and control circuit inputs a reference voltage, the third output terminal of the logic and control circuit outputs a ninth target signal and is connected with the second input terminal of the level shift and up logic circuit, the fourth output terminal of the logic and control circuit outputs a tenth target signal and is connected with the third input terminal of the level shift and up logic circuit;

[0010] The second input terminal of the dead time control circuit, the fourth input terminal of the level shift and up logic circuit, the anode of the diode are connected and input a power supply voltage, the fifth input terminal of the level shift and up logic circuit, the third input terminal of the high side driver, one end of the first capacitor is connected with the cathode of the diode; the sixth input terminal of the level shift and up logic circuit is connected with a ground terminal;

[0011] The third input terminal of the dead time control circuit, the third input terminal of the logic and control circuit, the third input terminal of the low side driver are connected with a ground terminal; the fourth input terminal of the logic and control circuit, the fourth input terminal of the low side driver are connected and input a power supply voltage;

[0012] The fourth input end of the high side drive is connected with the other end of the first capacitor, the source of the high side device, one end of the inductor, the drain of the low side device, the second input end of the current detection circuit, and a second external signal source; the other end of the inductor is connected with one end of the second capacitor and one end of the first resistor; the third input end of the current detection circuit, the other end of the second capacitor, the other end of the first resistor, and the source of the low side device are connected with a ground end; the output end of the current detection circuit outputs a current automatic detection signal and is connected with the fifth input end of the logic and control circuit.

[0013] In an embodiment of the present application, the dead time control circuit comprises a first inverter module, a first delay module, a second delay module, a second inverter module, and a third inverter module, wherein,

[0014] The input end of the first inverter module is connected with a first external signal source and serves as an input end of the dead time control circuit; the output end of the first inverter module is connected with the first input end of the first delay module; the output end of the first delay module is connected with the input end of the second inverter module and the second input end of the second delay module; the output end of the second inverter module serves as a first output end of the dead time control circuit and outputs a first target signal; the first input end of the second delay module is connected with the first external signal source and serves as an input end of the dead time control circuit; the output end of the second delay module is connected with the input end of the third inverter module and the second input end of the first delay module; the output end of the third inverter module serves as a second output end of the dead time control circuit and outputs a fifth target signal.

[0015] In an embodiment of the present application, the level shift circuit and upper side logic circuit comprise a level shift circuit and a logic circuit, wherein,

[0016] The input end of the level shift circuit is connected with the first output end of the dead time control circuit to input the first target signal and serves as a first input end of the level shift circuit and upper side logic circuit; the output end of the level shift circuit serves as a first output end of the level shift circuit and upper side logic circuit and outputs a second target signal;

[0017] The first input end of the logic circuit is connected with the third output end of the logic and control circuit to input a chip select signal and serves as a second input end of the level shift circuit and upper side logic circuit; the second input end of the logic circuit is connected with the fourth output end of the logic and control circuit to input an under voltage lockout signal and serves as a third input end of the level shift circuit and upper side logic circuit; the output end of the logic circuit serves as a second output end of the level shift circuit and upper side logic circuit and outputs a third target signal.

[0018] In one embodiment of the present application, the level shift circuit comprises a fourth inverter module, a second resistor, a first enhancement-mode GaN HEMT device and a first depletion-mode GaN HEMT device, the logic circuit comprises a NOR gate module and a fifth inverter module, wherein,

[0019] The input end of the fourth inverter module is connected to the first output end of the dead time control circuit to input a first target signal and as an input end of the level shift circuit, the output end of the fourth inverter module is connected to the gate of the first enhancement-mode GaN HEMT device, one end of the second resistor inputs a driving voltage, the other end of the second resistor is connected to the drain of the first enhancement-mode GaN HEMT device and as an output end of the level shift circuit to output a second target signal, the source of the first enhancement-mode GaN HEMT device is connected to the drain of the first depletion-mode GaN HEMT device, and the gate of the first depletion-mode GaN HEMT device is connected to the source of the first depletion-mode GaN HEMT device and a ground end;

[0020] The first input end of the NOR gate module is connected to the third output end of the logic and control circuit to input a ninth target signal and as a first input end of the logic circuit, the second input end of the NOR gate module is connected to the fourth output end of the logic and control circuit to input a tenth target signal and as a second input end of the logic circuit, the output end of the NOR gate module is connected to the input end of the fifth inverter module, and the output end of the fifth inverter module is as an output end of the logic circuit and outputs a third target signal.

[0021] In one embodiment of the present application, the logic and control circuit comprises a current protection logic circuit, a UVLO undervoltage protection circuit, a logic circuit and a buffer, wherein,

[0022] The first input end of the current protection logic circuit inputs a reference voltage and as a second input end of the logic and control circuit, the second input end of the current protection logic circuit is connected to the output end of the current detection circuit to input a current automatic detection signal and as a fifth input end of the logic and control circuit, and the output end of the current protection logic circuit outputs a ninth target signal as a third output end of the logic and control circuit;

[0023] The input end of the UVLO undervoltage protection circuit inputs a power supply voltage, and the output end of the UVLO undervoltage protection circuit outputs a tenth target signal as a fourth output end of the logic and control circuit;

[0024] The first input end of the logic circuit is connected with the output end of the current protection logic circuit to input the ninth target signal, the second input end of the logic circuit is connected with the output end of the UVLO undervoltage protection circuit to input the tenth target signal, and the output end of the logic circuit outputs the seventh target signal as the second output end of the logic and control circuit;

[0025] The input end of the buffer is connected with the second output end of the dead time control circuit to input the fifth target signal and as the first input end of the logic and control circuit, and the output end of the buffer is connected with the first input end of the low-side drive to output the sixth target signal and as the first output end of the logic and control circuit.

[0026] In an embodiment of the present application, the current protection logic circuit comprises an operational amplifier module and a sixth inverter module, the UVLO undervoltage protection circuit comprises a second enhancement-mode GaN HEMT device, a third enhancement-mode GaN HEMT device, a fourth enhancement-mode GaN HEMT device, a fifth enhancement-mode GaN HEMT device, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein,

[0027] The positive input end of the operational amplifier module inputs a reference voltage and as the first input end of the current protection logic circuit, the negative input end of the operational amplifier module is connected with the output end of the current detection circuit to input a current automatic detection signal and as the second input end of the current protection logic circuit, the output end of the operational amplifier module is connected with the input end of the sixth inverter module, and the output end of the sixth inverter module outputs the ninth target signal as the output end of the current protection logic circuit;

[0028] The drain of the second enhancement-mode GaN HEMT device, the gate of the second enhancement-mode GaN HEMT device, the drain of the third enhancement-mode GaN HEMT device, one end of the sixth resistance is connected with a power supply voltage and serves as an input terminal of the UVLO undervoltage protection circuit, the source of the second enhancement-mode GaN HEMT device is connected with the gate of the third enhancement-mode GaN HEMT device and one end of the third resistance, the source of the third enhancement-mode GaN HEMT device is connected with one end of the fourth resistance and one end of the fifth resistance, the other end of the fifth resistance is connected with the gate of the fourth enhancement-mode GaN HEMT device and one end of the seventh resistance, the other end of the seventh resistance is connected with the drain of the fifth enhancement-mode GaN HEMT device, the gate of the fifth enhancement-mode GaN HEMT device is connected with the other end of the sixth resistance and the drain of the fourth enhancement-mode GaN HEMT device and outputs a tenth target signal as an output terminal of the UVLO undervoltage protection circuit, the other end of the third resistance, the other end of the fourth resistance, the source of the fourth enhancement-mode GaN HEMT device and the source of the fifth enhancement-mode GaN HEMT device are connected with a ground terminal.

[0029] In an embodiment of the present application, the high-side drive includes a twelfth resistance, a thirteenth resistance, a fourteenth resistance, a tenth enhancement-mode GaN HEMT device, an eleventh enhancement-mode GaN HEMT device, a twelfth enhancement-mode GaN HEMT device, a thirteenth enhancement-mode GaN HEMT device, a fourteenth enhancement-mode GaN HEMT device, a fifteenth enhancement-mode GaN HEMT device, a first drive circuit module, a second drive circuit module, wherein,

[0030] one end of the twelfth resistor is connected to the first output end of the level shift circuit and upper side logic circuit to input the second target signal and as the first input end of the high side driver, the other end of the twelfth resistor is connected to one end of the thirteenth resistor, the input end of the first drive circuit module and the drain of the tenth enhancement-mode GaN HEMT device, the gate of the tenth enhancement-mode GaN HEMT device and the gate of the twelfth enhancement-mode GaN HEMT device are connected to the second output end of the level shift circuit and upper side logic circuit to input the third target signal and as the second input end of the high side driver, the output end of the first drive circuit module is connected to the input end of the second drive circuit module and the gate of the eleventh enhancement-mode GaN HEMT device, the output end of the second drive circuit module is connected to one end of the fourteenth resistor, the other end of the fourteenth resistor is connected to the drain of the twelfth enhancement-mode GaN HEMT device and the drain of the thirteenth enhancement-mode GaN HEMT device, the gate of the thirteenth enhancement-mode GaN HEMT device and as the output end of the high side driver to output the fourth target signal, the other end of the thirteenth resistor is connected to the drain of the eleventh enhancement-mode GaN HEMT device, the source of the thirteenth enhancement-mode GaN HEMT device is connected to the gate and drain of the fourteenth enhancement-mode GaN HEMT device, the source of the fourteenth enhancement-mode GaN HEMT device is connected to the gate and drain of the fifteenth enhancement-mode GaN HEMT device, the source of the fifteenth enhancement-mode GaN HEMT device, the source of the twelfth enhancement-mode GaN HEMT device, the source of the eleventh enhancement-mode GaN HEMT device and the source of the tenth enhancement-mode GaN HEMT device are connected to the second external signal source;

[0031] The low side driver includes a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a sixteenth enhancement-mode GaN HEMT device, a seventeenth enhancement-mode GaN HEMT device, an eighteenth enhancement-mode GaN HEMT device, a nineteenth enhancement-mode GaN HEMT device, a twentieth enhancement-mode GaN HEMT device, a twenty-first enhancement-mode GaN HEMT device, a third drive circuit module, a fourth drive circuit module, wherein,

[0032] One end of the fifteenth resistor is connected to a first output end of the logic and control circuit to input a sixth target signal and as a first input end of low side drive, the other end of the fifteenth resistor is connected to one end of the sixteenth resistor, an input end of the third drive circuit module and a drain of the sixteenth enhancement mode GaN HEMT device, a gate of the sixteenth enhancement mode GaN HEMT device and a gate of the eighteenth enhancement mode GaN HEMT device are connected to a second output end of the logic and control circuit to input a seventh target signal, an output end of the third drive circuit module is connected to an input end of the fourth drive circuit module and a gate of the seventeenth enhancement mode GaN HEMT device, an output end of the fourth drive circuit module is connected to one end of the seventeenth resistor, the other end of the seventeenth resistor is connected to a drain of the eighteenth enhancement mode GaN HEMT device and a drain of the nineteenth enhancement mode GaN HEMT device, a gate of the nineteenth enhancement mode GaN HEMT device and as an output end of low side drive to output an eighth target signal, the other end of the sixteenth resistor is connected to a drain of the seventeenth enhancement mode GaN HEMT device, a source of the nineteenth enhancement mode GaN HEMT device is connected to a gate and a drain of the twentieth enhancement mode GaN HEMT device, a source of the twentieth enhancement mode GaN HEMT device is connected to a gate and a drain of the twenty-first enhancement mode GaN HEMT device, a source of the twenty-first enhancement mode GaN HEMT device, a source of the eighteenth enhancement mode GaN HEMT device, a source of the seventeenth enhancement mode GaN HEMT device and a source of the sixteenth enhancement mode GaN HEMT device are connected to a ground end.

[0033] In one embodiment of the present application, the first drive circuit module, the second drive circuit module, the third drive circuit module and the fourth drive circuit module each comprises: a twenty-second enhancement mode GaN HEMT device, a second depletion mode GaN HEMT device, a twenty-third enhancement mode GaN HEMT device, a twenty-fourth enhancement mode GaN HEMT device, a twenty-fifth enhancement mode GaN HEMT device, a third capacitor, an eighteenth resistor, wherein,

[0034] The gate and the drain of the twenty-second enhancement-mode GaN HEMT device, the drain of the twenty-third enhancement-mode GaN HEMT device and one end of the eighteenth resistor are connected to a power supply voltage or a driving voltage, the source of the twenty-second enhancement-mode GaN HEMT device is connected to the drain of the second depletion-mode GaN HEMT device and one end of the third capacitor, the gate and the source of the second depletion-mode GaN HEMT device are connected to the gate of the twenty-third enhancement-mode GaN HEMT device and the drain of the twenty-fourth enhancement-mode GaN HEMT device, the gate of the twenty-fourth enhancement-mode GaN HEMT device and the gate of the twenty-fifth enhancement-mode GaN HEMT device are connected to the first output end of the level shift circuit and the upper side logic circuit or the first output end of the logic and control circuit, the source of the twenty-third enhancement-mode GaN HEMT device is connected to the other end of the eighteenth resistor and the drain of the twenty-fifth enhancement-mode GaN HEMT device, the other end of the third capacitor and the output end of the driving circuit module to output the eleventh target signal, and the source of the twenty-fourth enhancement-mode GaN HEMT device and the source of the twenty-fifth enhancement-mode GaN HEMT device are connected to a ground end or a second external signal source.

[0035] In an embodiment of the present application, the first driving circuit module, the second driving circuit module, the third driving circuit module and the fourth driving circuit module each comprises a twenty-sixth enhancement-mode GaN HEMT device, a third depletion-mode GaN HEMT device, a twenty-seventh enhancement-mode GaN HEMT device, a twenty-eighth enhancement-mode GaN HEMT device, a twenty-ninth enhancement-mode GaN HEMT device, a thirtieth enhancement-mode GaN HEMT device, a thirty-first enhancement-mode GaN HEMT device, a thirty-second enhancement-mode GaN HEMT device, a fourth capacitor, a fifth capacitor, a nineteenth resistor and a twentieth resistor, wherein,

[0036] The gate and the drain of the twenty-sixth enhancement-mode GaN HEMT device, the gate and the drain of the twenty-eighth enhancement-mode GaN HEMT device, the drain of the thirty-first enhancement-mode GaN HEMT device and one end of the twentieth resistance are connected to a power supply voltage or a driving voltage, the source of the twenty-sixth enhancement-mode GaN HEMT device is connected to the drain of the third depletion-mode GaN HEMT device and one end of the fourth capacitor, the gate and the source of the third depletion-mode GaN HEMT device are connected to the drain of the twenty-seventh enhancement-mode GaN HEMT device and the gate of the twenty-ninth enhancement-mode GaN HEMT device, the gate of the twenty-seventh enhancement-mode GaN HEMT device, the gate of the thirtieth enhancement-mode GaN HEMT device and the thirty-second enhancement-mode GaN HEMT device are connected to the first output end of the level shift circuit and the upper side logic circuit or the first output end of the logic and control circuit, the source of the twenty-eighth enhancement-mode GaN HEMT device is connected to the drain of the twenty-ninth enhancement-mode GaN HEMT device, one end of the nineteenth resistance and one end of the fifth capacitor, the source of the twenty-ninth enhancement-mode GaN HEMT device is connected to the drain of the thirtieth enhancement-mode GaN HEMT device, the gate of the thirty-first enhancement-mode GaN HEMT device, the other end of the nineteenth resistance and the other end of the fourth capacitor, the source of the thirty-first enhancement-mode GaN HEMT device is connected to the other end of the twentieth resistance and the other end of the fifth capacitor and serves as an output end of the driving circuit module to output an eleventh target signal, and the source of the twenty-seventh enhancement-mode GaN HEMT device, the source of the thirtieth enhancement-mode GaN HEMT device and the source of the thirty-second enhancement-mode GaN HEMT device are connected to a ground end or a second external signal source.

[0037] In an embodiment of the present application, the current detection circuit comprises a thirty-third enhancement-mode GaN HEMT device and a twenty-first resistance, wherein,

[0038] The gate of the low-side device and the gate of the thirty-third enhancement-mode GaN HEMT device are connected to an output end of a low-side driving to input an eighth target signal, the drain of the low-side device and the drain of the thirty-third enhancement-mode GaN HEMT device are connected to a second external signal source, the source of the thirty-third enhancement-mode GaN HEMT device is connected to one end of the twenty-first resistance and serves as an output end of the current detection circuit and outputs a current automatic detection signal, and the other end of the twenty-first resistance is connected to the source of the low-side device and connected to a ground end.

[0039] Compared with the prior art, the present application has the following beneficial effects:

[0040] 1、The GaN HEMT half-bridge circuit system of the application guarantees that the high-side device and the low-side device are always turned off first and then turned on by designing a dead-time control circuit, so that the circuit has very superior fault tolerance and improves the reliability of the circuit; by designing a level shift circuit, an upper logic circuit and a logic and control circuit, the UVLO under-voltage protection and the implementation of the logic control function in the GaN HEMT half-bridge circuit system are effectively realized, and the stability and reliability of the circuit are further strengthened; by designing a high-side drive circuit and a low-side drive circuit, the stability and reliability of the circuit are further improved without affecting the driving capability; by designing a current detection circuit, the effective protection of the circuit to the power tube is realized, and the damage of the large current to the power device caused by the direct connection of the upper and lower tubes is reduced; therefore, the GaN HEMT half-bridge circuit system improves the performance of the half-bridge circuit while improving the reliability of the circuit and reducing the risk of equipment damage.

[0041] 2、The GaN HEMT half-bridge circuit system of the application has a "self-correction" capability by designing a logic and control circuit, an upper logic circuit, a low-side drive circuit and a high-side drive circuit module and the circuit topology structure among the modules, which greatly improves the reliability and stability of the circuit, effectively prevents the circuit from working under abnormal working conditions, and further prevents major losses.

[0042] 3、The GaN HEMT half-bridge circuit system of the application designs a first drive circuit module and a second drive circuit module in the high-side drive, and designs a third drive circuit module and a fourth drive circuit module in the low-side drive, so that the drive circuit modules effectively make up for the disadvantage of high static power consumption of the drive circuit, reduce the propagation delay, and further improve the driving capability of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A structure schematic diagram of a GaN HEMT power half-bridge circuit system provided for an embodiment of the application;

[0044] Figure 2 A structure schematic diagram of a dead-time control circuit provided for an embodiment of the application;

[0045] Figure 3 A structure schematic diagram of a logic and control circuit provided for an embodiment of the application;

[0046] Figure 4 A structure schematic diagram of a logic and control circuit provided for an embodiment of the application;

[0047] Figure 5 A structure schematic diagram of an operational amplifier module provided for an embodiment of the application;

[0048] Figure 6 A high-side drive circuit structure schematic diagram provided for an embodiment of the present application;

[0049] Figure 7 A low-side drive circuit structure schematic diagram provided for an embodiment of the present application;

[0050] Figure 8 A drive circuit module structure schematic diagram provided for an embodiment of the present application;

[0051] Figure 9 Another drive circuit module structure schematic diagram provided for an embodiment of the present application;

[0052] Figure 10 A current detection circuit structure schematic diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0053] The present application will be further described below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0054] Embodiment one

[0055] Please see Figure 1 , Figure 1 A GaN HEMT power half-bridge circuit system structure schematic diagram provided for an embodiment of the present application.

[0056] The GaN HEMT power half-bridge circuit system includes a dead time control circuit 1, a level shift circuit and an upper side logic circuit 2, a logic and control circuit 3, a high-side drive 4, a low-side drive 5, a current detection circuit 6, a high-side device 7, a low-side device 8, a diode D, a first capacitor C101, an inductor L, a second capacitor C102 and a first resistor R101. Among them, the diode D is a bootstrap diode, and the first capacitor is a bootstrap capacitor.

[0057] Specifically, the first input end of the dead time control circuit 1 is connected with a first external signal source PWM_IN, the first output end of the dead time control circuit 1 outputs a first target signal PWM_HD and is connected with the first input end of the level shift circuit and the upper side logic circuit 2; the first output end of the level shift circuit and the upper side logic circuit 2 outputs a second target signal PWM_HS and is connected with the first input end of the high-side drive 4, the second output end of the level shift circuit and the upper side logic circuit 2 outputs a third target signal STOP_HS and is connected with the second input end of the high-side drive 4, and the output end of the high-side drive 4 outputs a fourth target signal HS and is connected with the gate of the high-side device 7.

[0058] The second output end of the dead-time control circuit 1 outputs a fifth target signal PWM_LD and connects a first input end of the logic and control circuit 3; the first output end of the logic and control circuit 3 outputs a sixth target signal PWM_LS and connects a first input end of the low-side drive 5, the second output end of the logic and control circuit 3 outputs a seventh target signal STOP_LS and connects a second input end of the low-side drive 5; the output end of the low-side drive 5 outputs an eighth target signal LS and connects a gate of the low-side device 8.

[0059] The second input end of the logic and control circuit 3 inputs a reference voltage VREF, the third output end of the logic and control circuit 3 outputs a ninth target signal CS and connects a second input end of the level shift and upper logic circuit 2, the fourth output end of the logic and control circuit 3 outputs a tenth target signal UVLO and connects a third input end of the level shift and upper logic circuit 2.

[0060] The second input end of the dead-time control circuit 1, the fourth input end of the level shift and upper logic circuit 2, the anode of the diode D connect and input a power supply voltage VCC, the fifth input end of the level shift and upper logic circuit 2, the third input end of the high-side drive 4, one end of the first capacitor C101 connect the cathode of the diode D; the sixth input end of the level shift and upper logic circuit 2 connects a ground end GND.

[0061] The third input end of the dead-time control circuit 1, the third input end of the logic and control circuit 3, the third input end of the low-side drive 5 connect the ground end GND; the fourth input end of the logic and control circuit 3, the fourth input end of the low-side drive 5 connect and input the power supply voltage VCC.

[0062] The fourth input end of the high-side drive 4 connects the other end of the first capacitor C101, the source of the high-side device 7, one end of the inductor L, the drain of the low-side device 8, the second input end of the current detection circuit 6 and connects a second external signal source SW; the other end of the inductor L connects one end of the second capacitor C102, one end of the first resistor R101; the second input end of the current detection circuit 6, the other end of the second capacitor C102, the other end of the first resistor R101 and the source of the low-side device 8 connect the ground end GND; the output end of the current detection circuit 6 outputs a current automatic detection signal Current_sense and connects the fifth input end of the logic and control circuit 3.

[0063] The GaN HEMT half-bridge circuit system of the embodiment controls the circuit through the design of the dead time control circuit, so that the high-side device and the low-side device are always turned off first and then turned on, the circuit has very superior fault tolerance, and the circuit reliability is improved; through the design of the level shift circuit, the upper logic circuit and the logic and control circuit, the UVLO under-voltage protection and the logic control function in the GaN HEMT half-bridge circuit system are effectively realized, and the stability and reliability of the circuit are further improved; through the design of the high-side drive circuit and the low-side drive circuit, the stability and reliability of the circuit are further improved without affecting the driving capability; through the design of the current detection circuit, the effective protection of the circuit to the power tube is realized, and the damage of the large current to the power device caused by the direct connection of the upper and lower tubes is reduced.

[0064] Please refer to Figure 2 , Figure 2 The dead time control circuit structure schematic diagram provided by the embodiment of the application.

[0065] The dead time control circuit 1 includes a first inverter module 11, a first delay module 12, a second delay module 13, a second inverter module 14 and a third inverter module 15. The input end of the first inverter module 11 is connected with a first external signal source PWM_IN and serves as the input end of the dead time control circuit 1, the output end of the first inverter module 11 is connected with the first input end of the first delay module 12, the first output end of the first delay module 12 is connected with the input end of the second inverter module 14, the output end of the second inverter module 14 serves as the first output end of the dead time control circuit 1 to output a first target signal PWM_HD; the first input end of the second delay module 13 is connected with the first external signal source PWM_IN and serves as the input end of the dead time control circuit 1, the first output end of the second delay module 13 is connected with the input end of the third inverter module 15, the output end of the third inverter module 15 serves as the second output end of the dead time control circuit 1 to output a fifth target signal PWM_LD; the second output end of the first delay module 12 is connected with the second input end of the second delay module 13; the second output end of the second delay module 13 is connected with the second input end of the first delay module 12.

[0066] Specifically, the inverter module 11, the inverter module 14 and the inverter module 15 can be composed of an RTL logic composed of a resistance and a DC enhancement type GaN HEMT device, and in another embodiment, can be composed of a DCFL logic coupled by a DC depletion type GaN HEMT device and a DC enhancement type GaN HEMT device.

[0067] Specifically, the first delay module 12 and the second inverter module 14 are composed of NAND gate modules 121, 131 and delay circuits 122, 132. The NAND gate modules 121, 131 can be composed of RTL logic composed of resistors and DC enhancement mode GaN HEMT devices, and in another embodiment, can also be composed of DCFL logic coupled by DC depletion mode GaN HEMT devices and DC enhancement mode GaN HEMT devices; the delay circuits 122, 132 can be composed of low-pass filter circuits and a plurality of even-numbered inverter modules. The circuit is a prior art, and the present embodiment will not be described again.

[0068] In the half-bridge circuit, the high-side device and the low-side device always turn on and off complementarily when receiving the gate signal. However, since the GaN HEMT half-bridge circuit can work at a frequency of 500 KHZ-1 MHZ or even higher, the high-side device and the low-side device can be affected by internal noise of the circuit, which can cause the high-side device and the low-side device to be mistakenly turned on, and further cause the DC bus voltage to pass through and damage the IGBT. Therefore, the present embodiment designs a dead time control circuit to stagger the turn-on and turn-off of the high-side device and the low-side device by a certain time, i.e., the dead time, so as to ensure that the high-side device and the low-side device are always turned off first and then turned on, so that the circuit has very superior fault tolerance and improves the reliability of the circuit.

[0069] Please refer to Figure 3 , Figure 3 A logic and control circuit structure schematic diagram is provided for the embodiment of the present application.

[0070] Specifically, the level shift circuit and upper logic circuit 2 includes a level shift circuit 21 and a logic circuit 22. The input end of the level shift circuit 21 is connected to the first output end of the dead time control circuit 1 to input the first target signal PWM_HD and serve as the first input end of the level shift circuit and upper logic circuit 2. The output end of the level shift circuit 21 serves as the first output end of the level shift circuit and upper logic circuit 2 and outputs the second target signal PWM_HS. The first input end of the logic circuit 22 is connected to the third output end of the logic and control circuit 3 to input the chip select signal CS and serve as the second input end of the level shift circuit and upper logic circuit 2. The second input end of the logic circuit 22 is connected to the fourth output end of the logic and control circuit 3 to input the under-voltage lockout signal UVLO and serve as the third input end of the level shift circuit and upper logic circuit 2. The output end of the logic circuit 22 serves as the second output end of the level shift circuit and upper logic circuit 2 and outputs the third target signal STOP_HS.

[0071] In one specific embodiment, the level shifting circuit 21 includes a fourth inverter module 211, a second resistor R301, a first enhancement-mode GaN HEMT device M301, and a first depletion-mode GaN HEMT device M302.

[0072] The input of the fourth inverter module 211 is connected to the first output of the dead-time control circuit 1 to input the first target signal PWM HD and to serve as the input of the level shift circuit 21. The output of the fourth inverter module 211 is connected to the gate of the first enhancement-type GaN HEMT device M301. One end of the second resistor R301 is connected to the drive voltage V_BOOT, and the other end of the second resistor R301 is connected to the drain of the first enhancement-type GaN HEMT device M301 and to serve as the output of the level shift circuit 21 to output the second target signal PWM_HS. The source of the first enhancement-type GaN HEMT device M301 is connected to the drain of the first depletion-type GaN HEMT device M302, and the gate of the first depletion-type GaN HEMT device M302 is connected to the source of the first depletion-type GaN HEMT device M302 and the ground terminal GND.

[0073] Specifically, the first enhancement-mode GaN HEMT device M301 needs to withstand a high voltage, so a high-voltage DC GaN HEMT device is selected. The first depletion-mode GaN HEMT device M302 has a constant gate-source voltage and can act as the current source load for the source follower formed by the first enhancement-mode GaN HEMT device M301, thereby reducing static power consumption while increasing the gain of the source follower. In another embodiment, the depletion-mode GaN HEMT device M302 can be replaced with a resistor with a larger resistance value.

[0074] In one specific embodiment, the logic circuit 22 includes a NOR gate module 221 and a fifth inverter module 222. The first input terminal of the NOR gate module 221 is connected to the third output terminal of the logic and control circuit 3 to input the ninth target signal CS and serves as the first input terminal of the logic circuit 22. The second input terminal of the NOR gate module 221 is connected to the fourth output terminal of the logic and control circuit 3 to input the tenth target signal UVLO and serves as the second input terminal of the logic circuit 22. The output terminal of the NOR gate module 221 is connected to the input terminal of the fifth inverter module 222, and the output terminal of the fifth inverter module 222 serves as the output terminal of the logic circuit 22 and outputs the third target signal STOP_HS.

[0075] Specifically, the NOR gate module 221 can be constructed from RTL logic consisting of resistors and DC enhancement-mode GaN HEMT devices. In another embodiment, it can also be constructed from DCFL logic consisting of DC depletion-mode GaN HEMT devices coupled with DC enhancement-mode GaN HEMT devices.

[0076] Reference is made to Figure 4 , Figure 4 A logic and control circuit structure schematic diagram is provided for an embodiment of the present application. The logic and control circuit 3 comprises a current protection logic circuit 31, a UVLO undervoltage protection circuit 32, a logic circuit 33 and a buffer 34.

[0077] The first input end of the current protection logic circuit 31 inputs a reference voltage VREF and serves as the second input end of the logic and control circuit 3, the second input end of the current protection logic circuit 31 is connected to the output end of the current detection circuit 6 to input a current automatic detection signal Current_sense and serves as the fifth input end of the logic and control circuit 3, the output end of the current protection logic circuit 31 outputs a ninth target signal CS and serves as the third output end of the logic and control circuit 3. The input end of the UVLO undervoltage protection circuit 32 inputs a power supply voltage VCC, the output end of the UVLO undervoltage protection circuit 32 outputs a tenth target signal UVLO and serves as the fourth output end of the logic and control circuit 3. The first input end of the logic circuit 33 is connected to the output end of the current protection logic circuit 31 to input the ninth target signal CS, the second input end of the logic circuit 33 is connected to the output end of the UVLO undervoltage protection circuit 32 to input the tenth target signal UVLO, and the output end of the logic circuit 33 outputs a seventh target signal STOP_LS and serves as the second output end of the logic and control circuit 3. The input end of the buffer 34 is connected to the second output end of the dead time control circuit 1 to input a fifth target signal PWM_LD and serves as the first input end of the logic and control circuit 3, and the output end of the buffer 34 is connected to the first input end of the low-side drive 5 to output a sixth target signal PWM_LS and serves as the first output end of the logic and control circuit 3.

[0078] In one specific embodiment, the current protection logic circuit 31 comprises an operational amplifier module 311 and a sixth inverter module 312. The positive input end of the operational amplifier module 311 inputs a reference voltage VREF and serves as the first input end of the current protection logic circuit 31, the negative input end of the operational amplifier module 311 is connected to the output end of the current detection circuit 6 to input a current automatic detection signal Current_sense and serves as the second input end of the current protection logic circuit 31, the output end of the operational amplifier module 311 is connected to the input end of the sixth inverter module 312, and the output end of the sixth inverter module 312 outputs a ninth target signal CS and serves as the output end of the current protection logic circuit 31.

[0079] In one embodiment, the reference voltage VREF can be set to 1*Vth-3*Vth, where Vth is the threshold voltage of the DC enhancement-mode GaN HEMT device, at this time when the voltage signal Current_sense is high VDD, the operational amplifier outputs low GND, and the output end of the inverter module 312 outputs the high-level target signal Output as the output end of the current protection logic circuit 31; when the voltage signal Current_sense is low GND, the operational amplifier outputs high VDD, and the output end of the inverter module 312 outputs the low-level target signal Output as the output end of the current protection logic circuit 31.

[0080] In one specific embodiment, the UVLO undervoltage protection circuit 32 includes a second enhancement-mode GaN HEMT device M401, a third enhancement-mode GaN HEMT device M402, a fourth enhancement-mode GaN HEMT device M403, a fifth enhancement-mode GaN HEMT device M404, a third resistor R401, a fourth resistor R402, a fifth resistor R403, a sixth resistor R404, and a seventh resistor R405.

[0081] In one specific embodiment, the UVLO undervoltage protection circuit 32 includes a second enhancement-mode GaN HEMT device M401, a third enhancement-mode GaN HEMT device M402, a fourth enhancement-mode GaN HEMT device M403, a fifth enhancement-mode GaN HEMT device M404, a third resistor R401, a fourth resistor R402, a fifth resistor R403, a sixth resistor R404, and a seventh resistor R405.

[0082] Specifically, the first source follower is composed of the second enhanced GaN HEMT device M401 and the third resistor R401, the second source follower is composed of the third enhanced GaN HEMT device M402 and the fourth resistor R402, and the first inverter is composed of the fourth enhanced GaN HEMT device M403 and the sixth resistor R404. When the power supply voltage VCC is less than 3*Vth, the output end of the UVLO undervoltage protection circuit 32 outputs a high level. When VCC is greater than 3*Vth, the output end of the UVLO undervoltage protection circuit 32 outputs a low level. The steady-state feedback circuit composed of the fifth enhanced GaN HEMT device M404 and the seventh resistor R405 stabilizes the output result, and enhances the stability and reliability of the circuit.

[0083] Specifically, the logic circuit 33 includes a NOR gate module 331 and a seventh inverter module 332 connected in sequence, and the circuit principle is the same as that of the logic circuit 22, which will not be repeated here.

[0084] In one specific embodiment, the buffer 34 includes an eighth inverter module 341 and a ninth inverter module 342, wherein the input end of the eighth inverter module 341 is connected to the second output end of the dead-time control circuit 1 to input the fifth target signal PWM_LD and serve as the input end of the buffer 34, the output end of the eighth inverter module 341 is connected to the input end of the ninth inverter module 342, and the output end of the ninth inverter module 342 is connected to the first input end of the low-side drive 5 to output the sixth target signal PWM_LS and serve as the output end of the buffer 34.

[0085] Please refer to Figure 5 , Figure 5 An operational amplifier module structure diagram is provided for the embodiment of the present application. The operational amplifier module 311 includes an eighth resistor R3111, a ninth resistor R3112, a tenth resistor R3113, an eleventh resistor R3114, a sixth enhanced GaN HEMT device M3111, a seventh enhanced GaN HEMT device M3112, an eighth enhanced GaN HEMT device M3113, and a ninth enhanced GaN HEMT device M3114.

[0086] The one end of the eighth resistor R3111, the one end of the ninth resistor R3112, the one end of the tenth resistor R3113, the one end of the eleventh resistor R3114 are connected with the power voltage VCC, the gate of the sixth enhancement-mode GaN HEMT device M3111 is inputted with the reference voltage VREF and is the positive input end of the operational amplifier module 311, the gate of the seventh enhancement-mode GaN HEMT device M3112 is connected with the current automatic detection signal Current_sense and is the negative input end of the operational amplifier module 311, the source of the sixth enhancement-mode GaN HEMT device M3111 and the source of the seventh enhancement-mode GaN HEMT device M3112 are connected with the load current source, the other end of the eighth resistor R3111 is connected with the drain of the sixth enhancement-mode GaN HEMT device M3111 and the gate of the ninth enhancement-mode GaN HEMT device M3114, the other end of the ninth resistor R3112 is connected with the drain of the seventh enhancement-mode GaN HEMT device M3112 and the gate of the eighth enhancement-mode GaN HEMT device M3113, the other end of the tenth resistor R3113 is connected with the drain of the eighth enhancement-mode GaN HEMT device M3113, the source of the eighth enhancement-mode GaN HEMT device M3113 and the source of the ninth enhancement-mode GaN HEMT device M3114 are connected with the load current source, the other end of the eleventh resistor R3114 is connected with the drain of the ninth enhancement-mode GaN HEMT device M3114 and is the output end of the operational amplifier module 311 to output the signal to the sixth inverter module 312.

[0087] In the embodiment, the eighth resistor R3111, the ninth resistor R3112 and the sixth enhancement-mode GaN HEMT device M3111 and the seventh enhancement-mode GaN HEMT device M3112 constitute a basic unit of the operational amplifier, the tenth resistor R3113, the eleventh resistor R3114, the eighth enhancement-mode GaN HEMT device M3113 and the ninth enhancement-mode GaN HEMT device M3114 constitute another basic unit of the operational amplifier.

[0088] Two basic units of the operational amplifier are connected in series to improve the circuit gain of the circuit module. Meanwhile, the number of the amplifier units can be appropriately increased to further improve the circuit gain and strengthen the circuit reliability under the condition of ensuring the correct circuit logic.

[0089] Please refer to Figure 6 , Figure 6A high-side drive circuit structure schematic diagram provided for an embodiment of the present application. The high-side drive 4 includes a twelfth resistor R601, a thirteenth resistor R602, a fourteenth resistor R603, a tenth enhancement-mode GaN HEMT device M601, an eleventh enhancement-mode GaN HEMT device M602, a twelfth enhancement-mode GaN HEMT device M603, a thirteenth enhancement-mode GaN HEMT device M604, a fourteenth enhancement-mode GaN HEMT device M605, a fifteenth enhancement-mode GaN HEMT device M606, a first drive circuit module 41, and a second drive circuit module 42.

[0090] Wherein one end of the twelfth resistor R601 is connected to the first output end of the level shift circuit and the upper side logic circuit 2 to input the second target signal PWM_HS and as the first input end of the high-side drive 4, the other end of the twelfth resistor R601 is connected to one end of the thirteenth resistor R602, the input end of the first drive circuit module 41 and the drain of the tenth enhancement-mode GaN HEMT device M601, the gate of the tenth enhancement-mode GaN HEMT device M601 and the gate of the twelfth enhancement-mode GaN HEMT device M603 are connected to the second output end of the level shift circuit and the upper side logic circuit 2 to input the third target signal STOP_HS and as the second input end of the high-side drive 4, the output end of the first drive circuit module 41 is connected to the input end of the second drive circuit module 42 and the gate of the eleventh enhancement-mode GaN HEMT device M602, the output end of the second drive circuit module 42 is connected to one end of the fourteenth resistor R603, the other end of the fourteenth resistor R603 is connected to the drain of the twelfth enhancement-mode GaN HEMT device M603 and the drain of the thirteenth enhancement-mode GaN HEMT device M604, the gate of the thirteenth enhancement-mode GaN HEMT device M604 and as the output end of the high-side drive 4 to output the fourth target signal HS, the other end of the thirteenth resistor R602 is connected to the drain of the eleventh enhancement-mode GaN HEMT device M602, the source of the thirteenth enhancement-mode GaN HEMT device M604 is connected to the gate and drain of the fourteenth enhancement-mode GaN HEMT device M605, the source of the fourteenth enhancement-mode GaN HEMT device M605 is connected to the gate and drain of the fifteenth enhancement-mode GaN HEMT device M606, the source of the fifteenth enhancement-mode GaN HEMT device M606, the source of the twelfth enhancement-mode GaN HEMT device M603, the source of the eleventh enhancement-mode GaN HEMT device M602 and the source of the tenth enhancement-mode GaN HEMT device M601 are connected to the second external signal source SW.

[0091] Specifically, when the third target signal STOP_HS is high, no matter what state the second target signal PWM_HS is in, the input end of the first drive circuit module 41 and the output end of the second drive circuit module 42 will be pulled low to a low signal by the first enhanced GaN HEMT device M601 and the third enhanced GaN HEMT device M603 respectively, thereby ensuring that the circuit will not work under abnormal conditions, further improving the stability and reliability of the circuit system.

[0092] Specifically, when the second target signal PWM_HS is high or low, and the third target signal STOP_HS is low, the fourth target signal HS output from the output end follows the second target signal PWM_HS being high or low. The twelfth resistor R601, the thirteenth resistor R602, and the eleventh enhanced GaN HEMT device M602 constitute a steady-state feedback circuit, which ensures the logic correctness of the input signal and the output signal of the first drive circuit module 41, prevents signal jumping, and further ensures that the correct signal is input into the rear-end circuit, ensuring the normal operation of the entire half-bridge circuit system.

[0093] When the half-bridge circuit is working, the VCC voltage jumps or the ringing signal generated by the gate parasitic inductance may break through the gate of the power tube, causing the entire half-bridge circuit system to be paralyzed, which brings great challenges to the design of the half-bridge circuit. Therefore, the system is designed with a gate potential clamping circuit composed of the thirteenth enhanced GaN HEMT device M604, the fourteenth enhanced GaN HEMT device M605, the fifteenth enhanced GaN HEMT device M606, and the fourteenth resistor R603. When the gate voltage is greater than the normal working voltage, the gate potential clamping circuit will work, stabilizing the gate voltage to about 3*Vth, and the excess voltage is transferred to both ends of the fourteenth resistor R603. This circuit further improves the stability and reliability of the circuit system.

[0094] Please refer to Figure 7 , Figure 7 A low-side drive circuit structure schematic diagram is provided for the embodiment of the application. The low-side drive 5 includes the fifteenth resistor R701, the sixteenth resistor R702, the seventeenth resistor R703, the sixteenth enhanced GaN HEMT device M701, the seventeenth enhanced GaN HEMT device M702, the eighteenth enhanced GaN HEMT device M703, the nineteenth enhanced GaN HEMT device M704, the twentieth enhanced GaN HEMT device M705, the twenty-first enhanced GaN HEMT device M706, the third drive circuit module 51, and the fourth drive circuit module 52.

[0095] Wherein, one end of the fifteenth resistor R701 is connected to the first output end of the logic and control circuit 3 to input the sixth target signal PWM_LS and as the first input end of the low-side drive 5, the other end of the fifteenth resistor R701 is connected to one end of the sixteenth resistor R702, the input end of the third drive circuit module 51 and the drain of the sixteenth enhancement-mode GaN HEMT device M701, the gate of the sixteenth enhancement-mode GaN HEMT device M701 and the gate of the eighteenth enhancement-mode GaN HEMT device M703 are connected to the second output end of the logic and control circuit 3 to input the seventh target signal STOP_LS, the output end of the third drive circuit module 51 is connected to the input end of the fourth drive circuit module 52 and the gate of the seventeenth enhancement-mode GaN HEMT device M702, the output end of the fourth drive circuit module 52 is connected to one end of the seventeenth resistor R703, the other end of the seventeenth resistor R703 is connected to the drain of the eighteenth enhancement-mode GaN HEMT device M703 and the drain of the nineteenth enhancement-mode GaN HEMT device M704, the gate of the nineteenth enhancement-mode GaN HEMT device M704 and as the output end of the low-side drive 5 to output the eighth target signal LS, the other end of the sixteenth resistor R702 is connected to the drain of the seventeenth enhancement-mode GaN HEMT device M702, the source of the nineteenth enhancement-mode GaN HEMT device M704 is connected to the gate and drain of the twentieth enhancement-mode GaN HEMT device M705, the source of the twentieth enhancement-mode GaN HEMT device M705 is connected to the gate and drain of the twenty-first enhancement-mode GaN HEMT device M706, the source of the twenty-first enhancement-mode GaN HEMT device M706, the source of the eighteenth enhancement-mode GaN HEMT device M703, the source of the seventeenth enhancement-mode GaN HEMT device M702 and the source of the sixteenth enhancement-mode GaN HEMT device M701 are connected to the ground end GND.

[0096] The working principle of the low-side drive 5 is the same as that of the high-side drive 4, which will not be repeated here.

[0097] Please refer to Figure 8 , Figure 8 A driving circuit module structure schematic diagram provided for the embodiment of the application. The first drive circuit module 41, the second drive circuit module 42, the third drive circuit module 51 and the fourth drive circuit module 52 each comprise: a twenty-second enhancement-mode GaN HEMT device M801, a second depletion-mode GaN HEMT device M802, a twenty-third enhancement-mode GaN HEMT device M803, a twenty-fourth enhancement-mode GaN HEMT device M804, a twenty-fifth enhancement-mode GaN HEMT device M805, a third capacitor C801 and an eighteenth resistor R801.

[0098] The gate and the drain of the twenty-second enhancement-mode GaN HEMT device M801, the drain of the twenty-third enhancement-mode GaN HEMT device M803 and one end of the eighteenth resistor R801 are connected to a power supply voltage VCC or a driving voltage V_BOOT, the source of the twenty-second enhancement-mode GaN HEMT device M801 is connected to the drain of the second depletion-mode GaN HEMT device M802 and one end of the third capacitor C801, the gate and the source of the second depletion-mode GaN HEMT device M802 are connected to the gate of the twenty-third enhancement-mode GaN HEMT device M803 and the drain of the twenty-fourth enhancement-mode GaN HEMT device M804, the gate of the twenty-fourth enhancement-mode GaN HEMT device M804 and the gate of the twenty-fifth enhancement-mode GaN HEMT device M805 are connected to the first output end of the level shift circuit and the upper side logic circuit 2 or the first output end of the logic and control circuit 3, the source of the twenty-third enhancement-mode GaN HEMT device M803 is connected to the other end of the eighteenth resistor R801 and the drain of the twenty-fifth enhancement-mode GaN HEMT device M805, the other end of the third capacitor C801 and serves as an output end of the driving circuit module to output the eleventh target signal OUT, and the source of the twenty-fourth enhancement-mode GaN HEMT device M804 and the source of the twenty-fifth enhancement-mode GaN HEMT device M805 are connected to a ground end GND or a second external signal source SW.

[0099] Since the performance of the GaN P-FET is much different from that of the GaN N-FET device, a CMOS complementary logic circuit similar to a silicon-based device cannot be formed at present. The conventional RTL logic circuit causes a large static power consumption of the driving circuit of the GaN IC, and the circuit system generates a large amount of heat, which brings a great challenge to the improvement of the power of the half-bridge circuit.

[0100] The driving circuit module is designed in the embodiment. When the PWM signal is at a high level, the twenty-fourth enhancement-mode GaN HEMT device M804 and the twenty-fifth enhancement-mode GaN HEMT device M805 are turned on, and the third capacitor C801 is charged. In the first path composed of the twenty-second enhancement-mode GaN HEMT device M801, the second depletion-mode GaN HEMT device M802 and the twenty-fourth enhancement-mode GaN HEMT device M804, the VGS of the second depletion-mode GaN HEMT device M802 is equal to 0, which is equivalent to a constant current source. Therefore, the static current of the path is clamped by the device, which greatly reduces the static power consumption of the first path. In the second path composed of the eighteenth resistor R801 and the twenty-fifth enhancement-mode GaN HEMT device M805, the resistance value of the eighteenth resistor R801 needs to be as large as possible, so as to reduce the static power consumption in the path.

[0101] When the PWM signal is low, at this time, the twenty-fourth enhancement-mode GaN HEMT device M804 and the twenty-fifth enhancement-mode GaN HEMT device M805 are closed, the third capacitor C801 which is fully charged charges the gate of the twenty-third enhancement-mode GaN HEMT device M803 through the second depletion-mode GaN HEMT device M802, and the eighteenth resistor R801 is short-circuited. The power supply voltage VCC forms a low-impedance loop through the twenty-third enhancement-mode GaN HEMT device M803, and the Cds of the twenty-fifth enhancement-mode GaN HEMT device M805 and the next stage circuit form a load capacitor to be quickly charged. However, as the eleventh target signal OUT signal potential rises, the source of the twenty-third enhancement-mode GaN HEMT device M803 rises, which may further cause the VGS of the twenty-third enhancement-mode GaN HEMT device M803 to gradually decrease, thereby causing the device to be closed.

[0102] Therefore, the embodiment designs a bootstrap circuit composed of the third capacitor C801 and the twenty-second enhancement-mode GaN HEMT device M801, maintains the voltage difference across the third capacitor C801, and raises the drain potential of the second depletion-mode GaN HEMT device M802 as the eleventh target signal OUT signal potential rises, thereby stabilizing the on state of the twenty-third enhancement-mode GaN HEMT device M803.

[0103] The driving circuit module effectively reduces the static power consumption of the driving circuit, reduces the propagation delay, and further improves the driving capability of the circuit.

[0104] Please refer to Figure 9 , Figure 9 Another driving circuit module structure schematic diagram provided by the embodiment of the application is provided. The first driving circuit module 41, the second driving circuit module 42, the third driving circuit module 51, and the fourth driving circuit module 52 each include: a twenty-sixth enhancement-mode GaN HEMT device M901, a third depletion-mode GaN HEMT device M902, a twenty-seventh enhancement-mode GaN HEMT device M903, a twenty-eighth enhancement-mode GaN HEMT device M904, a twenty-ninth enhancement-mode GaN HEMT device M905, a thirtieth enhancement-mode GaN HEMT device M906, a thirty-first enhancement-mode GaN HEMT device M907, a thirty-second enhancement-mode GaN HEMT device M908, a fourth capacitor C901, a fifth capacitor C902, a nineteenth resistor R901, and a twentieth resistor R902.

[0105] The gate and the drain of the twenty-sixth enhancement-mode GaN HEMT device M901, the gate and the drain of the twenty-eighth enhancement-mode GaN HEMT device M904, and the drain of the thirty-first enhancement-mode GaN HEMT device M907 and one end of the twentieth resistor R902 are connected to a power supply voltage VCC or a driving voltage V_BOOT; the source of the twenty-sixth enhancement-mode GaN HEMT device M901 is connected to the drain of the third depletion-mode GaN HEMT device M902 and one end of the fourth capacitor C901; the gate and the source of the third depletion-mode GaN HEMT device M902 are connected to the drain of the twenty-seventh enhancement-mode GaN HEMT device M903 and the gate of the twenty-ninth enhancement-mode GaN HEMT device M905; the gate of the twenty-seventh enhancement-mode GaN HEMT device M903, the gate of the thirtieth enhancement-mode GaN HEMT device M906, and the thirty-second enhancement-mode GaN HEMT device M908 are connected to the first output end of the level shift circuit and the upper side logic circuit 2 or the first output end of the logic and control circuit 3; the source of the twenty-eighth enhancement-mode GaN HEMT device M904 is connected to the drain of the twenty-ninth enhancement-mode GaN HEMT device M905, one end of the nineteenth resistor R901, and one end of the fifth capacitor C902; the source of the twenty-ninth enhancement-mode GaN HEMT device M905 is connected to the drain of the thirtieth enhancement-mode GaN HEMT device M906, the gate of the thirty-first enhancement-mode GaN HEMT device M907, the other end of the nineteenth resistor R901, and the other end of the fourth capacitor C901; the source of the thirty-first enhancement-mode GaN HEMT device M907 is connected to the other end of the twentieth resistor R902 and the other end of the fifth capacitor C902 and serves as an output end of the second driving circuit module to output an eleventh target signal OUT; and the source of the twenty-seventh enhancement-mode GaN HEMT device M903, the source of the thirtieth enhancement-mode GaN HEMT device M906, and the source of the thirty-second enhancement-mode GaN HEMT device M908 are connected to a ground end GND or a second external signal source SW.

[0106] Figure 8 The driving circuit module shown is applicable to a pre-stage driving circuit to drive a tube with a smaller size. If the size of the above circuit is directly increased to drive a power tube, a longer time for opening the M803 tube can be caused, thereby affecting the speed of accelerating the opening of the power tube.

[0107] Therefore, the embodiment designs Figure 9 The driving circuit shown is different from Figure 8 The circuit, and Figure 9The shown drive circuit adds a second path composed of the twenty-eighth enhancement-mode GaN HEMT device M904, the twenty-ninth enhancement-mode GaN HEMT device M905, the thirtieth enhancement-mode GaN HEMT device M906, the fifth capacitor C902, and the nineteenth resistor R901 as a buffer stage of the drive circuit to drive the thirty-first enhancement-mode GaN HEMT device M907 which has a larger size.

[0108] When the PWM signal is low, at this time, the principle is as described above, the fourth capacitor C901 charges the twenty-ninth enhancement-mode GaN HEMT device M905 through the third depletion-mode GaN HEMT device M902, thereby opening the twenty-ninth enhancement-mode GaN HEMT device M905, shorting the nineteenth resistor R901, accelerating the charging of the thirty-first enhancement-mode GaN HEMT device M907, and further opening the thirty-first enhancement-mode GaN HEMT device M907 to further short the second ten resistor R902. At this time, the power supply can quickly charge the next stage circuit or the load capacitor formed by the power tube.

[0109] The circuit has low static current and low propagation delay, effectively solving the problems of large static current and high propagation delay in the GaN HEMT half-bridge circuit, and is beneficial to improving the working frequency and power conversion efficiency of the GaN HEMT half-bridge circuit.

[0110] It should be noted that the first drive circuit module 41, the second drive circuit module 42, the third drive circuit module 51, and the fourth drive circuit module 52 can be selected according to actual needs Figure 8 The shown drive circuit, for example, the drive circuit modules 41, 42, 51, and 52 are all selected Figure 9 The shown drive circuit, for example, the drive circuit modules 41, 42, 51, and 52 are all selected Figure 8 The shown drive circuit, or the drive circuit modules 41, 42, 51, and 52 are all selected Figure 9 The shown drive circuit, or the drive circuit modules 41, 42, 51, and 52 are all selected Figure 8 The shown drive circuit, or the drive circuit modules 41, 42, 51, and 52 are all selected Figure 9 The shown drive circuit.

[0111] Please refer to Figure 10 , Figure 10 The current detection circuit structure schematic diagram provided for the embodiment of the application. The current detection circuit 6 includes the thirty-third enhancement-mode GaN HEMT device M1001 and the twenty-first resistor R1001.

[0112] The gate of the low-side device 8 and the gate of the thirty-third enhancement-mode GaN HEMT device M1001 are connected to the output end of the low-side drive 5 to input an eighth target signal LS, the drain of the low-side device 8 and the drain of the thirty-third enhancement-mode GaN HEMT device M1001 are connected to a second external signal source SW, the source of the thirty-third enhancement-mode GaN HEMT device M1001 is connected to one end of a twenty-first resistor R1001 and is an output end of the current detection circuit 6 and outputs a current automatic detection signal Current_sense, and the other end of the twenty-first resistor R1001 is connected to the source of the low-side device 8 and is connected to a ground end GND.

[0113] Since the GaN HEMT half-bridge circuit needs to work at a frequency of 500 KHZ-1 MHZ, at a very high switching frequency, the parasitic inductance and capacitance of the circuit are extremely easy to cause voltage and current jumps in the circuit, such as in the opening stage of the circuit, causing the generation of inrush current in the circuit, impacting the device and reducing the reliability of the circuit system. Or the ringing signal of the gate voltage of the power tube during the operation of the circuit causes the power tube to be mistakenly turned on, causing the upper and lower tubes to be directly connected. The occurrence of this situation not only causes unnecessary power loss of the circuit system, but also causes the upper and lower tubes to bear a huge current from the bus voltage, further damaging the power tube. Damage the stability of the circuit system.

[0114] Therefore, the embodiment designs Figure 10 The current detection circuit shown in the figure, when a large current passes through the power, the current automatic detection signal Current_sense output by the circuit will make the logic circuit generate a high-level CS signal, so as to turn off the upper and lower power tubes, thereby cutting off the power loop in time and protecting the circuit system.

[0115] Specifically, the replica loop composed of the thirty-third enhancement-mode GaN HEMT device M1001 and the twenty-first resistor R1001 will replicate the current of the low-side device in the ratio of A / mA. When the current in the power loop suddenly rises, the voltage drop of the twenty-first resistor R1001 will rise accordingly and be input as a current automatic detection signal Current_sense to the current protection logic circuit 31. When the current reaches a certain value, the current protection logic circuit 31 will output a high-level ninth target signal CS.

[0116] The GaN HEMT half-bridge circuit system of the present application has the self-correction ability, for example, when the working voltage of the circuit is too low, the driving circuit of the circuit may receive the wrong working signal, and the half-bridge power loop works abnormally, in the face of this situation, the UVLO undervoltage protection circuit sends a signal to the high and low side drive circuit, so that it does not accept external signals and sends a turn-off signal at the same time, thereby forcibly closing the power loop, for another example, when the upper and lower tubes in the half-bridge power loop are in series due to external interference, the current detection circuit will send a signal to the high and low side drive circuit, so that it forcibly sends a turn-off signal and does not accept external signals at the same time, thereby forcibly closing the power loop. Therefore, the GaN HEMT half-bridge circuit system greatly improves the reliability and stability of the circuit, effectively prevents the circuit from working under abnormal working conditions, and further prevents major losses.

[0117] The GaN HEMT half-bridge circuit system of the present application has the self-correction ability, for example, when the working voltage of the circuit is too low, the driving circuit of the circuit may receive the wrong working signal, and the half-bridge power loop works abnormally, in the face of this situation, the UVLO undervoltage protection circuit sends a signal to the high and low side drive circuit, so that it does not accept external signals and sends a turn-off signal at the same time, thereby forcibly closing the power loop, for another example, when the upper and lower tubes in the half-bridge power loop are in series due to external interference, the current detection circuit will send a signal to the high and low side drive circuit, so that it forcibly sends a turn-off signal and does not accept external signals at the same time, thereby forcibly closing the power loop. Therefore, the GaN HEMT half-bridge circuit system greatly improves the reliability and stability of the circuit, effectively prevents the circuit from working under abnormal working conditions, and further prevents major losses.

[0118] The GaN HEMT half-bridge circuit system of the present application has the self-correction ability, for example, when the working voltage of the circuit is too low, the driving circuit of the circuit may receive the wrong working signal, and the half-bridge power loop works abnormally, in the face of this situation, the UVLO undervoltage protection circuit sends a signal to the high and low side drive circuit, so that it does not accept external signals and sends a turn-off signal at the same time, thereby forcibly closing the power loop, for another example, when the upper and lower tubes in the half-bridge power loop are in series due to external interference, the current detection circuit will send a signal to the high and low side drive circuit, so that it forcibly sends a turn-off signal and does not accept external signals at the same time, thereby forcibly closing the power loop. Therefore, the GaN HEMT half-bridge circuit system greatly improves the reliability and stability of the circuit, effectively prevents the circuit from working under abnormal working conditions, and further prevents major losses.

[0119] In summary, the GaN HEMT half-bridge circuit system of the embodiment reduces the static power consumption of the circuit, improves the performance of the circuit, and has a protection circuit system function of preventing the high-side and low-side devices from being in series; improves the performance of the half-bridge circuit, improves the reliability of the circuit, and reduces the risk of equipment damage.

[0120] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A GaN HEMT power half-bridge circuit system, characterized in that, include: Dead-time control circuit (1), level shifting circuit and upper logic circuit (2), logic and control circuit (3), high-side drive (4), low-side drive (5), current detection circuit (6), high-side device (7), low-side device (8), diode (D), first capacitor (C101), inductor (L), second capacitor (C102) and first resistor (R101), wherein, The first input terminal of the dead time control circuit (1) is connected to the first external signal source (PWM_IN), and the first output terminal of the dead time control circuit (1) outputs the first target signal (PWM_HD) and is connected to the first input terminal of the level shift circuit and the upper logic circuit (2); the first output terminal of the level shift circuit and the upper logic circuit (2) outputs the second target signal (PWM_HS) and is connected to the first input terminal of the high-side drive (4); the second output terminal of the level shift circuit and the upper logic circuit (2) outputs the third target signal (STOP_HS) and is connected to the second input terminal of the high-side drive (4); the output terminal of the high-side drive (4) outputs the fourth target signal (HS) and is connected to the gate of the high-side device (7); The second output terminal of the dead time control circuit (1) outputs the fifth target signal (PWM_LD) and is connected to the first input terminal of the logic and control circuit (3); the first output terminal of the logic and control circuit (3) outputs the sixth target signal (PWM_LS) and is connected to the first input terminal of the low-side drive (5); the second output terminal of the logic and control circuit (3) outputs the seventh target signal (STOP_LS) and is connected to the second input terminal of the low-side drive (5); the output terminal of the low-side drive (5) outputs the eighth target signal (LS) and is connected to the gate of the low-side device (8) and the first input terminal of the current detection circuit (6); The second input terminal of the logic and control circuit (3) is input with reference voltage (VREF), the third output terminal of the logic and control circuit (3) outputs the ninth target signal (CS) and is connected to the second input terminal of the level shift circuit and the upper logic circuit (2), and the fourth output terminal of the logic and control circuit (3) outputs the tenth target signal (UVLO) and is connected to the third input terminal of the level shift circuit and the upper logic circuit (2). The second input terminal of the dead time control circuit (1), the fourth input terminal of the level shift circuit and the upper logic circuit (2), and the positive terminal of the diode (D) are connected and input power supply voltage (VCC); the fifth input terminal of the level shift circuit and the upper logic circuit (2), the third input terminal of the high-side drive (4), and one end of the first capacitor (C101) are connected to the negative terminal of the diode (D); the sixth input terminal of the level shift circuit and the upper logic circuit (2) is connected to the ground terminal (GND); The third input terminal of the dead time control circuit (1), the third input terminal of the logic and control circuit (3), and the third input terminal of the low-side drive (5) are connected to the ground terminal (GND); the fourth input terminal of the logic and control circuit (3) and the fourth input terminal of the low-side drive (5) are connected to and input the power supply voltage (VCC); The fourth input terminal of the high-side drive (4) is connected to the other end of the first capacitor (C101), the source of the high-side device (7), one end of the inductor (L), the drain of the low-side device (8), the second input terminal of the current detection circuit (6), and is connected to the second external signal source (SW); the other end of the inductor (L) is connected to one end of the second capacitor (C102) and one end of the first resistor (R101); the third input terminal of the current detection circuit (6), the other end of the second capacitor (C102), the other end of the first resistor (R101), and the source of the low-side device (8) are connected and grounded (GND); the output terminal of the current detection circuit (6) outputs an automatic current detection signal (Current_sense) and is connected to the fifth input terminal of the logic and control circuit (3).

2. The GaN HEMT power half-bridge circuit system according to claim 1, characterized in that, The dead-time control circuit (1) includes a first inverter module (11), a first delay module (12), a second delay module (13), a second inverter module (14), and a third inverter module (15), wherein, The input terminal of the first inverter module (11) is connected to the first external signal source (PWM_IN) and serves as the input terminal of the dead time control circuit (1). The output terminal of the first inverter module (11) is connected to the first input terminal of the first delay module (12). The output terminal of the first delay module (12) is connected to the input terminal of the second inverter module (14) and the second input terminal of the second delay module (13). The output terminal of the second inverter module (14) serves as the first output terminal of the dead time control circuit (1) to output the first target signal (PWM_HD). The first input terminal of the second delay module (13) is connected to the first external signal source (PWM_IN) and serves as the input terminal of the dead time control circuit (1). The output terminal of the second delay module (13) is connected to the input terminal of the third inverter module (15) and the second input terminal of the first delay module (12). The output terminal of the third inverter module (15) serves as the second output terminal of the dead time control circuit (1) to output the fifth target signal (PWM_LD).

3. The GaN HEMT power half-bridge circuit system according to claim 1, characterized in that, The level shifting circuit and the upper logic circuit (2) include a level shifting circuit (21) and a logic circuit (22), wherein, The input terminal of the level shift circuit (21) is connected to the first output terminal of the dead time control circuit (1) to input the first target signal (PWM_HD) and serve as the first input terminal of the level shift circuit and the upper logic circuit (2). The output terminal of the level shift circuit (21) serves as the first output terminal of the level shift circuit and the upper logic circuit (2) and outputs the second target signal (PWM_HS). The first input terminal of the logic circuit (22) is connected to the third output terminal of the logic and control circuit (3) to input the chip select signal (CS) and serves as the second input terminal of the level shift circuit and the upper logic circuit (2). The second input terminal of the logic circuit (22) is connected to the fourth output terminal of the logic and control circuit (3) to input the undervoltage lockout signal (UVLO) and serves as the third input terminal of the level shift circuit and the upper logic circuit (2). The output terminal of the logic circuit (22) serves as the second output terminal of the level shift circuit and the upper logic circuit (2) and outputs the third target signal (STOP_HS).

4. The GaN HEMT power half-bridge circuit system according to claim 3, characterized in that, The level shifting circuit (21) includes a fourth inverter module (211), a second resistor (R301), a first enhancement-mode GaN HEMT device (M301), and a first depletion-mode GaN HEMT device (M302). The logic circuit (22) includes a NOR gate module (221) and a fifth inverter module (222). The input terminal of the fourth inverter module (211) is connected to the first output terminal of the dead time control circuit (1) to input the first target signal (PWM_HD) and serve as the input terminal of the level shift circuit (21). The output terminal of the fourth inverter module (211) is connected to the gate of the first enhancement-mode GaN HEMT device (M301). One end of the second resistor (R301) is input with the drive voltage (V_BOOT), and the other end of the second resistor (R301) is connected to the drain of the first enhancement-mode GaN HEMT device (M301) and serves as the output terminal of the level shift circuit (21) to output the second target signal (PWM_HS). The source of the first enhancement-mode GaN HEMT device (M301) is connected to the drain of the first depletion-mode GaN HEMT device (M302), and the gate of the first depletion-mode GaN HEMT device (M302) is connected to the source of the first depletion-mode GaN HEMT device (M302) and the ground terminal (GND). The first input terminal of the NOR gate module (221) is connected to the third output terminal of the logic and control circuit (3) to input the ninth target signal (CS) and serve as the first input terminal of the logic circuit (22). The second input terminal of the NOR gate module (221) is connected to the fourth output terminal of the logic and control circuit (3) to input the tenth target signal (UVLO) and serve as the second input terminal of the logic circuit (22). The output terminal of the NOR gate module (221) is connected to the input terminal of the fifth inverter module (222). The output terminal of the fifth inverter module (222) serves as the output terminal of the logic circuit (22) and outputs the third target signal (STOP_HS).

5. The GaN HEMT power half-bridge circuit system according to claim 1, characterized in that, The logic and control circuit (3) includes a current protection logic circuit (31), a UVLO undervoltage protection circuit (32), a logic circuit (33), and a buffer (34), wherein, The first input terminal of the current protection logic circuit (31) is input to the reference voltage (VREF) and serves as the second input terminal of the logic and control circuit (3). The second input terminal of the current protection logic circuit (31) is connected to the output terminal of the current detection circuit (6) to input the current automatic detection signal (Current_sense) and serves as the fifth input terminal of the logic and control circuit (3). The output terminal of the current protection logic circuit (31) serves as the third output terminal of the logic and control circuit (3) to output the ninth target signal (CS). The input terminal of the UVLO undervoltage protection circuit (32) is supplied with power supply voltage (VCC), and the output terminal of the UVLO undervoltage protection circuit (32) is used as the fourth output terminal of the logic and control circuit (3) to output the tenth target signal (UVLO). The first input terminal of the logic circuit (33) is connected to the output terminal of the current protection logic circuit (31) to input the ninth target signal (CS), the second input terminal of the logic circuit (33) is connected to the output terminal of the UVLO undervoltage protection circuit (32) to input the tenth target signal (UVLO), and the output terminal of the logic circuit (33) serves as the second output terminal of the logic and control circuit (3) to output the seventh target signal (STOP_LS); The input terminal of the buffer (34) is connected to the second output terminal of the dead time control circuit (1) to input the fifth target signal (PWM_LD) and serves as the first input terminal of the logic and control circuit (3). The output terminal of the buffer (34) is connected to the first input terminal of the low-side drive (5) to output the sixth target signal (PWM_LS) and serves as the first output terminal of the logic and control circuit (3).

6. The GaN HEMT power half-bridge circuit system according to claim 5, characterized in that, The current protection logic circuit (31) includes an operational amplifier module (311) and a sixth inverter module (312). The UVLO undervoltage protection circuit (32) includes a second enhancement-mode GaN HEMT device (M401), a third enhancement-mode GaN HEMT device (M402), a fourth enhancement-mode GaN HEMT device (M403), a fifth enhancement-mode GaN HEMT device (M404), a third resistor (R401), a fourth resistor (R402), a fifth resistor (R403), a sixth resistor (R404), and a seventh resistor (R405). The positive input terminal of the operational amplifier module (311) is connected to the reference voltage (VREF) and serves as the first input terminal of the current protection logic circuit (31). The negative input terminal of the operational amplifier module (311) is connected to the output terminal of the current detection circuit (6) to input the current automatic detection signal (Current_sense) and serves as the second input terminal of the current protection logic circuit (31). The output terminal of the operational amplifier module (311) is connected to the input terminal of the sixth inverter module (312). The output terminal of the sixth inverter module (312) serves as the output terminal of the current protection logic circuit (31) to output the ninth target signal (CS). The drain of the second enhancement-mode GaN HEMT device (M401), the gate of the second enhancement-mode GaN HEMT device (M401), the drain of the third enhancement-mode GaN HEMT device (M402), and one end of the sixth resistor (R404) are connected to the power supply voltage (VCC) and serve as the input terminal of the UVLO undervoltage protection circuit (32). The source of the second enhancement-mode GaN HEMT device (M401) is connected to the gate of the third enhancement-mode GaN HEMT device (M402) and one end of the third resistor (R401). The source of the third enhancement-mode GaN HEMT device (M402) is connected to one end of the fourth resistor (R402) and one end of the fifth resistor (R403). The other end of the fifth resistor (R403) is connected to the gate of the fourth enhancement-mode GaN HEMT device (M403) and one end of the seventh resistor (R405). The other end of the seventh resistor (R405) is connected to the fifth enhancement-mode GaN HEMT device (M402). The drain of the HEMT device (M404), the gate of the fifth enhancement-type GaN HEMT device (M404) is connected to the other end of the sixth resistor (R404) and the drain of the fourth enhancement-type GaN HEMT device (M403) and serves as the output terminal of the UVLO undervoltage protection circuit (32) to output the tenth target signal (UVLO), the other end of the third resistor (R401), the other end of the fourth resistor (R402), the source of the fourth enhancement-type GaN HEMT device (M403) and the source of the fifth enhancement-type GaN HEMT device (M404) are connected to the ground terminal (GND).

7. The GaN HEMT power half-bridge circuit system according to claim 1, characterized in that, The high-side drive (4) includes a twelfth resistor (R601), a thirteenth resistor (R602), a fourteenth resistor (R603), a tenth enhancement-mode GaN HEMT device (M601), an eleventh enhancement-mode GaN HEMT device (M602), a twelfth enhancement-mode GaN HEMT device (M603), a thirteenth enhancement-mode GaN HEMT device (M604), a fourteenth enhancement-mode GaN HEMT device (M605), a fifteenth enhancement-mode GaN HEMT device (M606), a first drive circuit module (41), and a second drive circuit module (42), wherein, One end of the twelfth resistor (R601) is connected to the first output terminal of the level shift circuit and the upper logic circuit (2) to input the second target signal (PWM_HS) and serve as the first input terminal of the high-side drive (4). The other end of the twelfth resistor (R601) is connected to one end of the thirteenth resistor (R602), the input terminal of the first drive circuit module (41), and the drain of the tenth enhancement-type GaN HEMT device (M601). The gate of the tenth enhancement-type GaN HEMT device (M601) and the gate of the twelfth enhancement-type GaN HEMT device (M603) are connected to the second output terminal of the level shift circuit and the upper logic circuit (2) to input the third target signal (STOP_HS) and serve as the second input terminal of the high-side drive (4). The output terminal of the first drive circuit module (41) is connected to the input terminal of the second drive circuit module (42) and the eleventh enhancement-type GaN HEMT device (M603). The gate of the HEMT device (M602), the output terminal of the second driving circuit module (42) is connected to one end of the fourteenth resistor (R603), the other end of the fourteenth resistor (R603) is connected to the drain of the twelfth enhancement-type GaN HEMT device (M603) and the drain of the thirteenth enhancement-type GaN HEMT device (M604), the gate of the thirteenth enhancement-type GaNHEMT device (M604) and serves as the output terminal of the high-side drive (4) to output the fourth target signal (HS), the other end of the thirteenth resistor (R602) is connected to the drain of the eleventh enhancement-type GaN HEMT device (M602), the source of the thirteenth enhancement-type GaNHEMT device (M604) is connected to the gate and drain of the fourteenth enhancement-type GaN HEMT device (M605), the source of the fourteenth enhancement-type GaN HEMT device (M605) is connected to the gate and drain of the fifteenth enhancement-type GaN HEMT device (M606), the fifteenth enhancement-type GaN The source of the HEMT device (M606), the source of the twelfth enhancement-type GaN HEMT device (M603), the source of the eleventh enhancement-type GaN HEMT device (M602), and the source of the tenth enhancement-type GaN HEMT device (M601) are connected to a second external signal source (SW). The low-side drive (5) includes a fifteenth resistor (R701), a sixteenth resistor (R702), a seventeenth resistor (R703), a sixteenth enhancement-mode GaN HEMT device (M701), a seventeenth enhancement-mode GaN HEMT device (M702), an eighteenth enhancement-mode GaN HEMT device (M703), a nineteenth enhancement-mode GaN HEMT device (M704), a twentieth enhancement-mode GaN HEMT device (M705), a twenty-first enhancement-mode GaN HEMT device (M706), a third drive circuit module (51), and a fourth drive circuit module (52), wherein, One end of the fifteenth resistor (R701) is connected to the first output terminal of the logic and control circuit (3) to input the sixth target signal (PWM_LS) and serve as the first input terminal of the low-side drive (5). The other end of the fifteenth resistor (R701) is connected to one end of the sixteenth resistor (R702), the input terminal of the third drive circuit module (51), and the drain of the sixteenth enhancement-type GaN HEMT device (M701). The gate of the sixteenth enhancement-type GaN HEMT device (M701) and the gate of the eighteenth enhancement-type GaN HEMT device (M703) are connected to the second output terminal of the logic and control circuit (3) to input the seventh target signal (STOP_LS). The output terminal of the third drive circuit module (51) is connected to the input terminal of the fourth drive circuit module (52) and the seventeenth enhancement-type GaN HEMT device (M703). The gate of the HEMT device (M702), the output terminal of the fourth driving circuit module (52) is connected to one end of the seventeenth resistor (R703), the other end of the seventeenth resistor (R703) is connected to the drain of the eighteenth enhancement-type GaN HEMT device (M703) and the drain of the nineteenth enhancement-type GaN HEMT device (M704), the gate of the nineteenth enhancement-type GaN HEMT device (M704) and serves as the output terminal of the low-side drive (5) to output the eighth target signal (LS), the other end of the sixteenth resistor (R702) is connected to the drain of the seventeenth enhancement-type GaN HEMT device (M702), the source of the nineteenth enhancement-type GaN HEMT device (M704) is connected to the gate and drain of the twentieth enhancement-type GaN HEMT device (M705), the source of the twentieth enhancement-type GaN HEMT device (M705) is connected to the gate and drain of the twenty-first enhancement-type GaN HEMT device (M706), the twenty-first enhancement-type GaN HEMT device (M706) is connected to the gate ...2), the source of the twenty-ninth enhancement-type GaN HEMT device (M704) is connected to the gate and drain of the twenty-second enhancement-type GaN HEMT device (M705), the twenty-second enhancement-type GaN HEMT device (M706) is connected to the gate of the twenty-third enhancement-type GaN HEMT device (M706), the twenty-third enhancement-type GaN The source of the HEMT device (M706), the source of the eighteenth enhancement-type GaN HEMT device (M703), the source of the seventeenth enhancement-type GaN HEMT device (M702), and the source of the sixteenth enhancement-type GaN HEMT device (M701) are connected to the ground terminal (GND).

8. The GaN HEMT power half-bridge circuit system according to claim 7, characterized in that, The first driving circuit module (41), the second driving circuit module (42), the third driving circuit module (51), and the fourth driving circuit module (52) each include: a twenty-second enhancement-mode GaN HEMT device (M801), a second depletion-mode GaN HEMT device (M802), a twenty-third enhancement-mode GaN HEMT device (M803), a twenty-fourth enhancement-mode GaN HEMT device (M804), a twenty-fifth enhancement-mode GaN HEMT device (M805), a third capacitor (C801), and an eighteenth resistor (R801), wherein, The gate and drain of the 22nd enhancement-type GaN HEMT device (M801), the drain of the 23rd enhancement-type GaN HEMT device (M803), and one end of the 18th resistor (R801) are connected to the power supply voltage (VCC) or the drive voltage (V_BOOT). The source of the 22nd enhancement-type GaN HEMT device (M801) is connected to the drain of the 2nd depletion-type GaN HEMT device (M802) and one end of the third capacitor (C801). The gate and source of the 2nd depletion-type GaN HEMT device (M802) are connected to the gate of the 23rd enhancement-type GaN HEMT device (M803) and the drain of the 24th enhancement-type GaN HEMT device (M804). The gate of the 24th enhancement-type GaN HEMT device (M804) and the drain of the 25th enhancement-type GaN HEMT device (M804) are connected to the power supply voltage (VCC) or the drive voltage (V_BOOT). The gate of the HEMT device (M805) is connected to the first output terminal of the level shift circuit and the upper logic circuit (2) or the first output terminal of the logic and control circuit (3). The source of the 23rd enhancement-type GaN HEMT device (M803) is connected to the other end of the 18th resistor (R801) and the drain of the 25th enhancement-type GaN HEMT device (M805), the other end of the third capacitor (C801), and serves as the output terminal of the drive circuit module to output the 11th target signal (OUT). The source of the 24th enhancement-type GaN HEMT device (M804) and the source of the 25th enhancement-type GaN HEMT device (M805) are connected to the ground terminal (GND) or the second external signal source (SW).

9. The GaN HEMT power half-bridge circuit system according to claim 7, characterized in that, The first driving circuit module (41), the second driving circuit module (42), the third driving circuit module (51), and the fourth driving circuit module (52) each include: a twenty-sixth enhancement-mode GaN HEMT device (M901), a third depletion-mode GaN HEMT device (M902), a twenty-seventh enhancement-mode GaN HEMT device (M903), a twenty-eighth enhancement-mode GaN HEMT device (M904), a twenty-ninth enhancement-mode GaN HEMT device (M905), a thirtieth enhancement-mode GaN HEMT device (M906), a thirty-first enhancement-mode GaN HEMT device (M907), and a thirty-second enhancement-mode GaN HEMT device (M908), a fourth capacitor (C901), a fifth capacitor (C902), a nineteenth resistor (R901), and a twentieth resistor (R902), wherein, The gate and drain of the 26th enhancement-type GaN HEMT device (M901), the gate and drain of the 28th enhancement-type GaN HEMT device (M904), the drain of the 31st enhancement-type GaN HEMT device (M907), and one end of the 20th resistor (R902) are connected to the power supply voltage (VCC) or the drive voltage (V_BOOT). The source of the 26th enhancement-type GaN HEMT device (M901) is connected to the drain of the 3rd depletion-type GaN HEMT device (M902) and one end of the fourth capacitor (C901). The gate and source of the 3rd depletion-type GaN HEMT device (M902) are connected to the drain of the 27th enhancement-type GaN HEMT device (M903) and the gate of the 29th enhancement-type GaN HEMT device (M905). The gate of the 27th enhancement-type GaN HEMT device (M903), the gate of the 30th enhancement-type GaN HEMT device (M906), and the 32nd enhancement-type GaN HEMT device (M907) are connected to the power supply voltage (VCC) or the drive voltage (V_BOOT). The HEMT device (M908) is connected to the first output terminal of the level shift circuit and the upper logic circuit (2) or the first output terminal of the logic and control circuit (3). The source of the 28th enhancement-type GaN HEMT device (M904) is connected to the drain of the 29th enhancement-type GaN HEMT device (M905), one end of the 19th resistor (R901), and one end of the 5th capacitor (C902). The source of the 29th enhancement-type GaN HEMT device (M905) is connected to the drain of the 30th enhancement-type GaN HEMT device (M906) and the 31st enhancement-type GaN HEMT device (M904). The gate of the HEMT device (M907), the other end of the nineteenth resistor (R901), and the other end of the fourth capacitor (C901) are connected. The source of the thirty-first enhancement-type GaNHEMT device (M907) is connected to the other end of the twentieth resistor (R902) and the other end of the fifth capacitor (C902) and serves as the output terminal of the drive circuit module to output the eleventh target signal (OUT). The source of the twenty-seventh enhancement-type GaNHEMT device (M903), the source of the thirtieth enhancement-type GaN HEMT device (M906), and the source of the thirty-second enhancement-type GaN HEMT device (M908) are connected to the ground terminal (GND) or the second external signal source (SW).

10. The GaN HEMT power half-bridge circuit system according to claim 1, characterized in that, The current detection circuit (6) includes a thirty-third enhancement-mode GaN HEMT device (M1001) and a twenty-first resistor (R1001), wherein, The gate of the low-side device (8) and the gate of the thirty-third enhancement-type GaN HEMT device (M1001) are connected to the output terminal of the low-side driver (5) to input the eighth target signal (LS). The drain of the low-side device (8) and the drain of the thirty-third enhancement-type GaN HEMT device (M1001) are connected to the second external signal source (SW). The source of the thirty-third enhancement-type GaNHEMT device (M1001) is connected to one end of the twenty-first resistor (R1001) and serves as the output terminal of the current detection circuit (6) to output an automatic current detection signal (Current_sense). The other end of the twenty-first resistor (R1001) is connected to the source of the low-side device (8) and connected to the ground terminal (GND).

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