Phase interpolating device and multi-phase clock generating device

Abstract

A phase interpolator and a multiple-phase clock generator are disclosed. The phase interpolator includes a digital controller and a phase interpolator. The phase interpolator includes a capacitor and a plurality of circuit branches controlled by the digital controller to generate an nth phase clock of N phase clocks interpolated between a first input clock and a second input clock at an output node. When the digital controller controls the circuit branches to generate the nth phase clock, the digital controller controls the circuit branches to charge the capacitor with (N-n+1) x M first current sources in response to a rising edge of the first input clock and controls the circuit branches to charge the capacitor with N x M first current sources in response to a rising edge of the second input clock. N is an integer greater than 1, M is an integer greater than or equal to 1, and n is an integer from 1 to N.

Description

Technical Field

[0001] This invention relates to phase interpolation technology, and particularly to a phase interpolation device and a multi-phase clock generation device. Background Technology

[0002] Phase interpolators are widely used in multi-phase clock generation devices because they can generate different phase clocks interpolated between two input clocks. For example, assuming two input clocks have a phase time difference of T, a multi-phase clock generation device can use N phase interpolators to generate N phase clocks interpolated between the two input clocks. Ideally, the phase time difference between any two adjacent phase clocks of these N phase clocks is T / N, but in reality, this phase time difference can be affected by process variations, voltage drift, and temperature changes. Therefore, how to generate phase clocks with high linearity has become an important issue in this field. Summary of the Invention

[0003] To address the shortcomings of existing technologies, embodiments of the present invention provide a phase interpolation device, including a digital controller and a phase interpolator. The phase interpolator is coupled to the digital controller and includes multiple circuit branches. These circuit branches are coupled to an output node and controlled by the digital controller to generate, at the output node, the nth phase clock among N phase clocks interpolated between a first input clock and a second input clock, as the output clock of the phase interpolation device. N is an integer greater than 1, and n is an integer from 1 to N. Each of these circuit branches includes a first current source and a second current source connected in series between a supply voltage and a ground voltage. The output node is coupled between the first current source and the second current source, and the phase interpolator also includes a capacitor coupled between the output node and the ground voltage. The number of these circuit branches is greater than or equal to N × M, where M is an integer greater than or equal to 1. When the digital controller controls these circuit branches to generate the nth phase clock, the digital controller responds to the rising edge of the first input clock by controlling these circuit branches to charge the capacitor using (N-n+1)×M first current sources, and responds to the rising edge of the second input clock by controlling these circuit branches to charge the capacitor using N×M first current sources.

[0004] Furthermore, embodiments of the present invention provide a multi-phase clock generation device, including N clock generation circuits. These N clock generation circuits are respectively used to generate N phase clocks interpolated between a first input clock and a second input clock through N output nodes. The nth clock generation circuit among the N clock generation circuits is used to generate the nth phase clock among the N phase clocks through the nth output node among the N output nodes, and the nth clock generation circuit includes a digital controller and a phase interpolator. The phase interpolator is coupled to the digital controller and includes multiple circuit branches. These circuit branches of the nth clock generation circuit are coupled to the nth output node and controlled by the digital controller of the nth clock generation circuit to generate the nth phase clock at the nth output node. N is an integer greater than 1, and n is an integer from 1 to N. In the nth clock generation circuit, each of these circuit branches includes a first current source and a second current source connected in series between a supply voltage and a ground voltage. The nth output node is coupled between the first current source and the second current source, and the phase interpolator also includes a capacitor coupled between the nth output node and the ground voltage. In the nth clock generation circuit, the number of these circuit branches is greater than or equal to N×M, where M is an integer greater than or equal to 1. When the digital controller controls these circuit branches to generate the nth phase clock, the digital controller responds to the rising edge of the first input clock by controlling these circuit branches to charge the capacitor using (N-n+1)×M first current sources, and responds to the rising edge of the second input clock by controlling these circuit branches to charge the capacitor using N×M first current sources.

[0005] To further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the phase interpolation device according to an embodiment of the present invention.

[0007] Figure 2 This is a circuit diagram of the phase interpolator according to an embodiment of the present invention.

[0008] Figure 3 This is a schematic diagram of the four-phase clock generated by the phase interpolator in an embodiment of the present invention.

[0009] Figure 4 yes Figure 3 A schematic diagram showing how the four phase clocks are converted into pulse square waves by a buffer circuit.

[0010] Figures 5A to 5C This is a schematic diagram of the correction circuit in an embodiment of the present invention determining whether the nth phase clock has a positional offset relative to known reference data.

[0011] Figure 6 This is a schematic diagram of a multi-phase clock generation device according to an embodiment of the present invention.

[0012] Figure 7 The phase interpolator of this invention is used for Figure 6 A schematic diagram of a multi-phase clock generation device. Detailed Implementation

[0013] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and improved based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of the present invention in detail, but the content provided is not intended to limit the scope of protection of the present invention.

[0014] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein may, depending on the context, include any combination of one or more of the related listed items.

[0015] Please refer to the following: Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the phase interpolation device according to an embodiment of the present invention. Figure 2 This is a circuit diagram of the phase interpolator according to an embodiment of the present invention. Figure 1 and Figure 2 As shown, the phase interpolation device 10 includes a digital controller 101 and a phase interpolator 102. The phase interpolator 102 is coupled to the digital controller 101 and includes multiple circuit branches 200_0 to 200_K-1. The number of circuit branches 200_0 to 200_K-1 is greater than or equal to N×M, i.e., K≧(N×M). N is an integer greater than 1, and M is an integer greater than or equal to 1.

[0016] Circuit branches 200_0 to 200_K-1 are coupled to output node P and controlled by digital controller 101 to generate the nth phase clock CKI_n-1 among N phase clocks CKI_0 to CKI_N-1 interpolated between the first input clock CLK_A and the second input clock CLK_B, as the output clock of phase interpolation device 10, where n is an integer from 1 to N. In this embodiment, the phase of the first input clock CLK_A leads the phase of the second input clock CLK_B, and the two input clocks have a phase time difference of T. Therefore, the phase time difference between any two adjacent phase clocks of these N phase clocks CKI_0 to CKI_N-1 is T / N. This embodiment may also assume that the phase of the first phase clock CKI_0 is equal to the phase of the first input clock CLK_A, but this invention is not limited thereto.

[0017] Specifically, each circuit branch of the phase interpolator 102 includes a first current source and a second current source connected in series between the supply voltage VCC and the ground voltage GND, and the output node P is coupled between the first current source and the second current source. For example, Figure 2 Circuit branch 200_0 includes a first current source 202_0 and a second current source 203_0 connected in series between the supply voltage VCC and the ground voltage GND, and the output node P is coupled between the first current source 202_0 and the second current source 203_0. Similarly, circuit branch 200_K-1 includes a first current source 202_K-1 and a second current source 203_K-1 connected in series between the supply voltage VCC and the ground voltage GND, and the output node P is coupled between the first current source 202_K-1 and the second current source 203_K-1. In addition, the phase interpolator 102 also includes a capacitor C coupled between the output node P and the ground voltage GND.

[0018] Therefore, the present invention uses at least one first current source and at least one second current source to charge and discharge capacitor C sequentially through the control circuit branches 200_0 to 200_K-1 of the digital controller 101, and uses the voltage signal on the output node P as the nth phase clock CKI_n-1. More specifically, when the control circuit branches 200_0 to 200_K-1 of the digital controller 101 generate the nth phase clock CKI_n-1, the digital controller 101 responds to the rising edge of the first input clock CLK_A, and the control circuit branches 200_0 to 200_K-1 use (N-n+1)×M first current sources to charge capacitor C, and responds to the rising edge of the second input clock CLK_B, the control circuit branches 200_0 to 200_K-1 use N×M first current sources to charge capacitor C.

[0019] Furthermore, when the digital controller 101 controls the circuit branches 200_0 to 200_K-1 to generate the nth phase clock CKI_n-1, the digital controller 101 also responds to the falling edge of the first input clock CLK_A by discharging the capacitor C using (N-n+1)×M second current sources, and responds to the falling edge of the second input clock CLK_B by discharging the capacitor C using N×M second current sources. For example, assuming N and M are 4 and 1 respectively, this means that the phase interpolator 102 can generate one of the four phase clocks CKI_0 to CKI_3 interpolated between the first input clock CLK_A and the second input clock CLK_B, and it includes at least circuit branches 200_0 to 200_3.

[0020] Please refer to the following: Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the four-phase clocks generated by the phase interpolator in an embodiment of the present invention. Figure 4 yes Figure 3 A schematic diagram showing the conversion of the four-phase clock signals into pulse square waves via a buffer circuit. For ease of understanding, Figure 3 and Figure 4 These four phase clocks CKI_0 to CKI_3 are presented within the same time interval. However, those skilled in the art will understand from the foregoing that circuit branches 200_0 to 200_3 will only generate one of these four phase clocks CKI_0 to CKI_3 at a time as the output clock of the phase interpolation device 10. In this case, this embodiment can also use time points t0 and t1 to represent the rising edge time points of the first input clock CLK_A and the second input clock CLK_B, respectively, and use time points t2 and t3 to represent the falling edge time points of the first input clock CLK_A and the second input clock CLK_B, respectively.

[0021] In other words, the interval from time point t0 to t1 or the interval from time point t2 to t3 is the phase time difference between the first input clock CLK_A and the second input clock CLK_B. Therefore, when the digital controller 101 controls the circuit branches 200_0 to 200_3 to generate the first phase clock CKI_0, the digital controller 101 controls the circuit branches 200_0 to 200_3 to charge the capacitor C using four first current sources, such as first current sources 202_0 to 202_3, starting from time point t0, and continues to control the circuit branches 200_0 to 200_3 to charge the capacitor C using the four first current sources starting from time point t1.

[0022] Conversely, when the control circuit branches 200_0 to 200_3 of the digital controller 101 generate the second phase clock CKI_1, the digital controller 101, starting from time point t0, uses three first current sources, such as first current sources 202_0 to 202_2, to charge capacitor C in the control circuit branches 200_0 to 200_3, and starting from time point t1, the control circuit branches 200_0 to 200_3 use four first current sources, such as first current sources 202_0 to 202_2. 2_3 Charges capacitor C, and so on. When the digital controller 101 controls the circuit branches 200_0 to 200_3 to generate the fourth phase clock CKI_3, the digital controller 101 controls the circuit branches 200_0 to 200_3 to charge capacitor C using one first current source, such as first current source 202_0, starting from time point t0. And starting from time point t1, the control circuit branches 200_0 to 200_3 use four first current sources to charge capacitor C. It should be understood that when capacitor C is charged, the voltage signal on the output node P will gradually increase, that is, the rising edge waveform of the nth phase clock CKI_n-1 is generated, and at this time, the voltage signal is proportional to the charging current.

[0023] Therefore, between time point t0 and time point t1, the circuit branches 200_0 to 200_3 that generate the second phase clock CKI_1 use one less first current source to charge capacitor C than the circuit branches 200_0 to 200_3 that generate the first phase clock CKI_0. Similarly, the circuit branches 200_0 to 200_3 that generate the fourth phase clock CKI_3 use one less first current source to charge capacitor C than the circuit branches 200_0 to 200_3 that generate the third phase clock CKI_2. This results in the slew rates of the first, second, third, and fourth output clocks CKI_0, CKI_1, CKI_2, and CKI_3 forming an arithmetic sequence. The slew rate represents the rate of voltage change per unit time.

[0024] Furthermore, after time point t1, for circuit branches 200_0 to 200_3 that generate the second phase clock CKI_1, they will charge capacitor C using the same four first current sources as the circuit branches 200_0 to 200_3 that generate the first phase clock CKI_0. Similarly, for circuit branches 200_0 to 200_3 that generate the fourth phase clock CKI_3, they will charge capacitor C using the same four first current sources as the circuit branches 200_0 to 200_3 that generate the third phase clock CKI_2. This results in the slew rates of the first, second, third, and fourth output clocks CKI_0, CKI_1, CKI_2, and CKI_3 being in the same sequence. The details regarding the generation of the falling edge waveform will be similar to those described above, and will not be elaborated upon further here.

[0025] In summary, between time point t2 and time point t3, for circuit branches 200_0 to 200_3 that generate the second phase clock CKI_1, one less second current source is used to discharge capacitor C than for circuit branches 200_0 to 200_3 that generate the first phase clock CKI_0. Similarly, for circuit branches 200_0 to 200_3 that generate the fourth phase clock CKI_3, one less second current source is used to discharge capacitor C than for circuit branches 200_0 to 200_3 that generate the third phase clock CKI_2. This results in the slew rates of the first output clock CKI_0, the second output clock CKI_1, the third output clock CKI_2, and the fourth output clock CKI_3 forming an arithmetic sequence.

[0026] Furthermore, after time point t3, for circuit branches 200_0 to 200_3 that generate the second phase clock CKI_1, they will discharge capacitor C using four second current sources, just like the circuit branches 200_0 to 200_3 that generate the first phase clock CKI_0. Similarly, for circuit branches 200_0 to 200_3 that generate the fourth phase clock CKI_3, they will discharge capacitor C using four second current sources, just like the circuit branches 200_0 to 200_3 that generate the third phase clock CKI_2. This results in the slew rate of the first output clock CKI_0, the slew rate of the second output clock CKI_1, the slew rate of the third output clock CKI_2, and the slew rate of the fourth output clock CKI_3 being in the same sequence. Phase interpolation device 10 may further include a buffer circuit 103 coupled to phase interpolator 102 to convert the nth output clock CKI_n-1 into a corresponding pulse square wave, such as Figure 4As shown, however, the present invention does not limit the specific implementation of the buffer circuit 103. In summary, by controlling the circuit branches 200_0 to 200_3 as described above by the digital controller 101, the phase interpolator 102 can generate four phase clocks CKI_0 to CKI_3 with high linearity.

[0027] Furthermore, each circuit branch of the phase interpolator 102 may also include a first switch connected in series between the supply voltage VDD and the first current source, and a second switch connected in series between the second current source and the ground voltage GND. For example, Figure 2 The circuit branch 200_0 may also include a first switch 201_0 connected in series between the supply voltage VDD and the first current source 202_0, and a second switch 204_0 connected in series between the second current source 203_0 and the ground voltage GND. Similarly, the circuit branch 200_K-1 may also include a first switch 201_K-1 connected in series between the supply voltage VDD and the first current source 202_K-1, and a second switch 204_K-1 connected in series between the second current source 203_K-1 and the ground voltage GND, but the present invention is not limited thereto.

[0028] Therefore, the digital controller 101 generates at least one control signal CS to control circuit branches 200_0 to 200_K-1, and the at least one control signal CS may include a first control signal for controlling each first switch and a second control signal for controlling each second switch. For example, Figure 2 The at least one control signal CS may include a K-bit first control signal SW_P[K-1:0] and a K-bit second control signal SW_N[K-1:0]. The first bit SW_P[0] of the first control signal is used to control the first switch 201_0, and so on, the K-bit SW_P[N-1] of the first control signal is used to control the first switch 201_K-1, but this invention is not intended to be limiting. In addition, the first bit SW_N[0] of the second control signal is used to control the second switch 204_0, and so on, the K-bit SW_N[K-1] of the second control signal is used to control the second switch 204_K-1, but this invention is not intended to be limiting.

[0029] On the other hand, the digital controller 101 can control the circuit branches 200_0 to 200_K-1 to generate the nth phase clock CKI_n-1 among the N phase clocks CKI_0 to CKI_N-1 according to the phase selection signal P_SEL. Therefore, the phase interpolation device 10 may also include a correction circuit 104 coupled to the digital controller 101. The correction circuit 104 is used to determine whether the nth phase clock CKI_n-1 has a positional offset relative to the known reference data, and generates the phase selection signal P_SEL. That is, the correction circuit 104 can be used to select the nth phase clock CKI_n-1 as the output clock of the phase interpolation device 10.

[0030] For more details, please refer to the following: Figures 5A to 5C , Figures 5A to 5C This is a schematic diagram illustrating how the correction circuit of this invention determines whether the nth phase clock has a positional offset relative to known reference data. For example... Figure 5A As shown, if still based on Figure 4 Taking the four phase clocks CKI_0 to CKI_3 as an example, assuming that the digital controller 101 initially controls circuit branches 200_0 to 200_K-1 to generate the second phase clock CKI_1 according to the phase selection signal P_SEL, then the nth phase clock CKI_n-1 at this time is the second phase clock CKI_1. Furthermore, the correction circuit 104 can also use the first phase clock CKI_0 and the third phase clock CKI_2, which are respectively leading and lagging behind the second phase clock CKI_1, for correction.

[0031] In this embodiment, the first phase clock CKI_0, which leads the second phase clock CKI_1, can be simply referred to as the phase-leading clock CKI_pre, and the third phase clock CKI_2, which lags the second phase clock CKI_1, can be simply referred to as the phase-lagning clock CKI_post. It should be understood that all three have the same period as the reference data RD. Therefore, the correction circuit 104 can use the rising edges of these three clocks to sample the reference data RD, and it is expected that the rising edge of the second phase clock CKI_1 should be aligned with the changing edge of the reference data RD.

[0032] like Figure 5BAs shown, if the rising edge of the second phase clock CKI_1 deviates to the right from the changing edge of the reference data RD, the sampled results of the phase leading clock CKI_pre, the nth phase clock CKI_n-1, and the phase lagging clock CKI_post will be [0 1 1] or [1 0 0]. Based on this result, the correction circuit 104 can determine that the phase leading clock CKI_pre needs to be selected as the output clock of the phase interpolation device 10. Therefore, the correction circuit 104 will adjust the phase selection signal P_SEL, so that the digital controller 101 controls the circuit branches 200_0 to 200_K-1 to generate the first phase clock CKI_0 according to the adjusted phase selection signal P_SEL. That is, the nth phase clock CKI_n-1 will be changed to the first phase clock CKI_0, and the phase lagging clock CKI_post will be changed to the second phase clock CKI_1. For ease of understanding, Figure 5B The final result assumes that the rising edge of the first phase clock CKI_0 at this time will align with the changing edge of the reference data RD, but this invention is not limited to this.

[0033] In contrast, such as Figure 5C As shown, if the rising edge of the second phase clock CKI_1 deviates to the left from the changing edge of the reference data RD, the sampled results of the phase leading clock CKI_pre, the nth phase clock CKI_n-1, and the phase lagging clock CKI_post will be [0 0 1] or [1 1 0]. Based on this result, the correction circuit 104 can determine that the phase lagging clock CKI_post needs to be selected as the output clock of the phase interpolation device 10. Therefore, the correction circuit 104 will adjust the phase selection signal P_SEL, so that the digital controller 101 controls the circuit branches 200_0 to 200_K-1 to generate the third phase clock CKI_2 according to the adjusted phase selection signal P_SEL. That is, the nth phase clock CKI_n-1 will be changed to the third phase clock CKI_2, and the phase leading clock CKI_pre and the phase lagging clock CKI_post will be changed to the second phase clock CKI_1 and the fourth phase clock CKI_3, respectively. For ease of understanding, Figure 5C The final result assumes that the rising edge of the third phase clock CKI_2 will align with the changing edge of the reference data RD, but this invention is not limited to this.

[0034] According to the above steps, as long as the value of the reference data RD continues to change, the correction circuit 104 can continuously correct the output clock of the phase interpolation device 10. It should be noted that the above steps can also be modified by sampling the reference data RD using the falling edge of the nth phase clock CKI_n-1. The details are similar to those described above, and therefore will not be repeated here. Furthermore, the present invention can also utilize N phase interpolators 102 to generate N phase clocks CKI_0 to CKI_N-1 with high linearity. Therefore, please refer to [further details omitted]. Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of a multi-phase clock generation device according to an embodiment of the present invention. Figure 7 The phase interpolator of this invention is used for Figure 6 A schematic diagram of a multi-phase clock generation device.

[0035] like Figure 6 As shown, the multi-phase clock generation device 3 includes N clock generation circuits 30_0 to 30_N-1, which are used to generate N phase clocks CKI_0 to CKI_N-1 interpolated between the first input clock CLK_A and the second input clock CLK_B through N output nodes P_0 to P_N-1, respectively. In this embodiment, the nth clock generation circuit 30_n-1 is used to generate the nth phase clock CKI_n-1 through the nth output node P_n-1. For example, assuming N is still 4, the multi-phase clock generating device 3 will use four clock generating circuits 30_0 to 30_3 to generate four phase clocks CKI_0 to CKI_3 interpolated between the first input clock CLK_A and the second input clock CLK_B. The first clock generating circuit 30_0 is used to generate the first phase clock CKI_0 through the first output node P_0, and so on. The fourth clock generating circuit 30_3 is used to generate the fourth phase clock CKI_3 through the fourth output node P_3.

[0036] Based on the above disclosure, those skilled in the art will understand Figure 6 The N clock generation circuits 30_0 to 30_N-1 in the diagram are equivalent to generating N phase clocks CKI_0 to CKI_N-1 using N phase interpolators 102 respectively. Therefore, the nth clock generation circuit 30_n-1 includes a digital controller 301_n-1 and a phase interpolator 302_n-1, but for ease of representation, Figure 6Only the digital controller 301_0 and phase interpolator 302_0 of the first clock generation circuit 30_0 are shown. Similarly, the phase interpolator 302_n-1 is coupled to the digital controller 301_n-1 and includes multiple circuit branches 400_0 to 400_K-1. The circuit branches 400_0 to 400_K-1 of the phase interpolator 302_n-1 are coupled to the nth output node P_n-1 and controlled by the digital controller 301_n-1 to generate the nth phase clock CKI_n-1 on the nth output node P_n-1.

[0037] like Figure 7 As shown, each circuit branch of the phase interpolator 302_n-1 includes a first current source and a second current source connected in series between the supply voltage VCC and the ground voltage GND, and the nth output node P_n-1 is coupled between the first current source and the second current source of the phase interpolator 302_n-1. For example, circuit branch 400_0 of phase interpolator 302_n-1 includes a first current source 402_0 and a second current source 403_0 connected in series between the supply voltage VCC and the ground voltage GND, and the nth output node P_n-1 is coupled between the first current source 402_0 and the second current source 403_0 of phase interpolator 302_n-1. Similarly, circuit branch 400_K-1 of phase interpolator 302_n-1 includes a first current source 402_K-1 and a second current source 403_K-1 connected in series between the supply voltage VCC and the ground voltage GND, and the nth output node P_n-1 is coupled between the first current source 402_K-1 and the second current source 403_K-1 of phase interpolator 302_n-1. Additionally, phase interpolator 302_n-1 also includes a capacitor C_n-1 coupled between the nth output node P_n-1 and the ground voltage GND.

[0038] Since the details of the digital controller 301_0 and the phase interpolator 302_n-1 are similar to those described above, they will not be repeated here. In summary, in the nth clock generation circuit 30_n-1, the digital controller 301_n-1, in response to the rising edge of the first input clock CLK_A, controls the circuit branches 400_0 to 400_K-1 of the phase interpolator 302_n-1 to charge the capacitor C_n-1 using (N-n+1)×M first current sources, and in response to the rising edge of the second input clock CLK_B, controls the circuit branches 400_0 to 400_K-1 of the phase interpolator 302_n-1 to charge the capacitor C_n-1 using N×M first current sources. In addition, in the nth clock generation circuit 30_n-1, the digital controller 301_n-1 also responds to the falling edge of the first input clock CLK_A by controlling the circuit branches 400_0 to 400_K-1 of the phase interpolator 302_n-1 to discharge the capacitor C_n-1 using (N-n+1)×M second current sources, and responds to the falling edge of the second input clock CLK_B by controlling the circuit branches 400_0 to 400_K-1 of the phase interpolator 302_n-1 to discharge the capacitor C_n-1 using N×M second current sources.

[0039] Similarly, the nth clock generation circuit 30_n-1 may also include a buffer circuit 303_n-1 coupled to the phase interpolator 302_n-1 to convert the nth output clock CKI_n-1 into a corresponding pulse square wave. In summary, the multi-phase clock generation device 3 can use N phase interpolators 302_n-1 to generate N phase clocks CKI_0 to CKI_N-1 with high linearity. In addition, in the nth clock generation circuit 30_n-1, each circuit branch of the phase interpolator 302_n-1 may also include a first switch connected in series between the supply voltage VDD and the first current source, and a second switch connected in series between the second current source and the ground voltage GND. For example, the circuit branch 400_0 of the phase interpolator 302_n-1 may also include a first switch 401_0 connected in series between the supply voltage VDD and the first current source 402_0, and a second switch 404_0 connected in series between the second current source 403_0 and the ground voltage GND. Similarly, the circuit branch 400_K-1 of the phase interpolator 302_n-1 may also include a first switch 401_K-1 connected in series between the supply voltage VDD and the first current source 402_K-1, and a second switch 404_K-1 connected in series between the second current source 403_K-1 and the ground voltage GND, but the present invention is not limited thereto.

[0040] Therefore, in the nth clock generation circuit 30_n-1, the digital controller 301_n-1 generates at least one control signal CS to control the circuit branches 400_0 to 400_K-1 of the phase interpolator 302_n-1, and the at least one control signal CS may include a first control signal for controlling each first switch and a second control signal for controlling each second switch. For example, Figure 7 The at least one control signal CS may include a K-bit first control signal SW_P[K-1:0] and a K-bit second control signal SW_N[K-1:0].

[0041] The first bit SW_P[0] of the first control signal is used to control the first switch 401_0, and so on. The Kth bit SW_P[K-1] of the first control signal is used to control the first switch 401_K-1, but this invention does not consider it a limitation. In addition, the first bit SW_N[0] of the second control signal is used to control the second switch 404_0, and so on. The Kth bit SW_N[K-1] of the second control signal is used to control the second switch 404_K-1, but this invention does not consider it a limitation. Since the relevant details are as described above, they will not be repeated here.

[0042] In summary, the embodiments of the present invention provide a phase interpolation device and a multi-phase clock generation device, which can control multiple circuit branches of the phase interpolator to sequentially charge and discharge a capacitor using a specific number of first current sources and a specific number of second current sources to generate a phase clock with high linearity.

[0043] The above-described content is merely a preferred embodiment of the present invention and is not intended to limit the scope of the claims of the present invention. Therefore, any equivalent technical changes made based on the description and drawings of the present invention are included within the scope of the claims of the present invention.

[0044] Explanation of reference numerals in the attached figures:

[0045] 10: Phase interpolation device

[0046] 101,301_0: Digital controller

[0047] 102,302_0,302_n-1: Phase interpolator

[0048] 103,303_0: Buffer circuit

[0049] 104: Correction Circuit

[0050] CLK_A, CLK_B: Input clock

[0051] P_SEL: Phase Selection Signal

[0052] P, P_n-1: Output nodes

[0053] 200_0~200_K-1, 400_0~400_K-1: Circuit branches

[0054] VCC: Supply voltage

[0055] GND: Grounding voltage

[0056] 201_0~201_K-1,401_0~401_K-1: First switch

[0057] 202_0~202_K-1, 402_0~402_K-1: First current source

[0058] 203_0~203_K-1, 403_0~403_K-1: Second current source

[0059] 204_0~204_K-1,404_0~404_K-1: Second switch

[0060] C,C_n-1: Capacitors

[0061] SW_P[0]~SW_P[K-1]: First control signal

[0062] SW_N[0]~SW_N[K-1]: Second control signal

[0063] CKI_n-1, CKI_0~CKI_3, CKI_0~CKI_N-1: Phase clock

[0064] t0~t3: Time points

[0065] CS: Control signal

[0066] CKI_pre: Phase Leading Clock

[0067] CKI_post: Phase lags clock

[0068] RD: Reference Data

[0069] 3: Multi-phase clock generation device

[0070] 30_0~30_N-1: Clock generation circuit

Claims

1. A phase interpolation device, comprising: Digital controller; as well as A phase interpolator, coupled to the digital controller, and comprising: Multiple circuit branches are coupled to the output node and controlled by the digital controller to generate the nth phase clock among N phase clocks interpolated between the first input clock and the second input clock at the output node as the output clock of the phase interpolation device, where N is an integer greater than 1 and n is an integer from 1 to N. Each of the plurality of circuit branches includes a first current source and a second current source connected in series between the supply voltage and the ground voltage, the output node is coupled between the first current source and the second current source, and the phase interpolator further includes a capacitor coupled between the output node and the ground voltage; The number of the plurality of circuit branches is greater than or equal to N×M, where M is an integer greater than or equal to 1. When the digital controller controls the plurality of circuit branches to generate the nth phase clock, the digital controller responds to the rising edge of the first input clock by controlling the plurality of circuit branches to charge the capacitor using (N-n+1)×M first current sources, and responds to the rising edge of the second input clock by controlling the plurality of circuit branches to charge the capacitor using N×M first current sources.

2. The phase interpolation device as claimed in claim 1, wherein when the digital controller controls the plurality of circuit branches to generate the nth phase clock, the digital controller further controls the plurality of circuit branches to discharge the capacitor using (N-n+1)×M second current sources in response to the falling edge of the first input clock, and controls the plurality of circuit branches to discharge the capacitor using N×M second current sources in response to the falling edge of the second input clock.

3. The phase interpolation device as claimed in claim 2, wherein each of the plurality of circuit branches further includes a first switch connected in series between the supply voltage and the first current source, and a second switch connected in series between the second current source and the ground voltage.

4. The phase interpolation device of claim 3, wherein the digital controller generates at least one control signal to control the plurality of circuit branches, the at least one control signal including a first control signal and a second control signal, the first control signal being used to control the first switch of each of the plurality of circuit branches, and the second control signal being used to control the second switch of each of the plurality of circuit branches.

5. The phase interpolation device of claim 2, wherein the digital controller controls the plurality of circuit branches to generate the nth phase clock according to the phase selection signal, and the phase interpolation device further comprises: A correction circuit, coupled to the digital controller, is used to determine whether the nth phase clock has a positional offset relative to known reference data, and to generate the phase selection signal.

6. A multi-phase clock generating device, comprising: N clock generation circuits are used to generate N phase clocks interpolated between the first input clock and the second input clock through N output nodes. The nth clock generation circuit among the N clock generation circuits is used to generate the nth phase clock among the N phase clocks through the nth output node among the N output nodes, and the nth clock generation circuit includes: Digital controller; and A phase interpolator, coupled to the digital controller, includes: Multiple circuit branches, coupled to the nth output node and controlled by the digital controller, generate the nth phase clock on the nth output node, where N is an integer greater than 1 and n is an integer from 1 to N; In the nth clock generation circuit, each of the plurality of circuit branches includes a first current source and a second current source connected in series between the power supply voltage and the ground voltage. The nth output node is coupled between the first current source and the second current source. The phase interpolator also includes a capacitor coupled between the nth output node and the ground voltage. In the nth clock generation circuit, the number of the plurality of circuit branches is greater than or equal to N×M, where M is an integer greater than or equal to 1. The digital controller responds to the rising edge of the first input clock by controlling the plurality of circuit branches to charge the capacitor using (N-n+1)×M first current sources, and responds to the rising edge of the second input clock by controlling the plurality of circuit branches to charge the capacitor using N×M first current sources.

7. The multi-phase clock generating apparatus of claim 6, wherein in the nth clock generating circuit, the digital controller further controls the plurality of circuit branches to discharge the capacitor using (N-n+1)×M second current sources in response to the falling edge of the first input clock, and controls the plurality of circuit branches to discharge the capacitor using N×M second current sources in response to the falling edge of the second input clock.

8. The multi-phase clock generating apparatus of claim 7, wherein in the nth clock generating circuit, each of the plurality of circuit branches further includes a first switch connected in series between the power supply voltage and the first current source, and a second switch connected in series between the second current source and the ground voltage.

9. The multi-phase clock generating apparatus of claim 8, wherein in the nth clock generating circuit, the digital controller generates at least one control signal to control the plurality of circuit branches, the at least one control signal including a first control signal and a second control signal, the first control signal being used to control the first switch of each of the plurality of circuit branches, and the second control signal being used to control the second switch of each of the plurality of circuit branches.

10. The multi-phase clock generating apparatus of claim 6, wherein the phase of the first input clock leads the phase of the second input clock, and any two adjacent phase clocks of the N phase clocks have the same phase time difference.

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