Segmented digital-to-analog converter

Abstract

Embodiments of the present application relate to segmented digital-to-analog converters. A segmented DAC circuit (100) is disclosed that includes an R-2R resistor DAC (120) to convert a first sub-word (MSB) to a first analog output signal (VH, VL), an interpolating DAC (126) to shift the first analog output signal (VH, VL) based on an N-bit digital interpolating code signal (ICODE) to provide an analog output signal (VOUT), and a sigma-delta modulator (136) to modulate a modulator code (SDCODE) to provide the N-bit digital interpolating code signal (ICODE) representing values of a second sub-word (ISB) and a third sub-word (LSB).

Description

[0001] Related information of divisional application

[0002] This application is a continuation of application number "201780091154.8" filed on 21 / 06 / 2017 and titled "Segmented Digital to Analog Converter". TECHNICAL FIELD

[0003] Embodiments of the present application relate to a segmented digital to analog converter. BACKGROUND

[0004] The present application relates to a digital to analog converter circuit (DAC). DAC circuits are commonly employed (or integrated into) along with microcontroller or microprocessor circuits to convert digital values into analog signals for use in various applications. High DAC accuracy is desired in many applications such as medical devices, optical device industry control products, display drivers, etc. Higher accuracy DACs typically occupy significant circuit area, and increased bit accuracy results in a significant increase in the number of switches and resistor elements. Additionally, DAC circuits providing high bit accuracy require more calibration memory and calibration time. SUMMARY

[0005] The disclosed examples provide a segmented DAC circuit that can be used in any suitable application including, but not limited to, a successive approximation register analog-to-digital converter (SAR ADC) or any other type of DC. The segmented DAC circuit includes a resistor DAC to convert a first subword including most significant bits (MSBs) to a first analog output signal, and an interpolating DAC to offset the first analog output signal, and a modulator circuit, such as a sigma delta modulator (SDM), to modulate a modulator code to provide a digital interpolation code signal representing values of a second subword and a third subword. The interpolation code signal is provided to the interpolating DAC to offset the first analog output signal. In a particular example, the resistor DAC is a resistor-to-resistor (R-2R) DAC circuit having fewer switch and resistor elements than a conventional resistor DAC to convert the first subword. Further disclosed segmented DAC circuits include a resistor DAC to convert the first subword to the first analog output signal, a resistance ordered element matching (OEM) circuit, a resistance chopper circuit, and an interpolating DAC to offset the first analog output signal based on the second subword to provide an analog output signal. Further disclosed examples include a DAC calibration method to calibrate a DAC circuit to convert a K-bit digital input signal, where the digital input signal includes a M-bit first subword including most significant bits, an I-bit second subword, and an L-bit third subword including least significant bits, where K = M + I + L. The method includes measuring an integer M + 1 output voltages of a M-bit resistor DAC to obtain a corresponding M + 1 sets of values for the first subword, measuring 2I output voltages of an I-bit interpolating DAC to obtain a corresponding 2I sets of unique values for the second subword, and measuring 2L output voltages of an L-bit SDM to obtain a corresponding 2L sets of unique values for the third subword. The method further includes calculating K-bit output voltage values based on the measured output voltages, calculating calibration codes for the resistor DAC, the interpolating DAC, and the SDM, calculating a K-bit calibration code for the DAC circuit based on the calibration codes for the resistor DAC, the interpolating DAC, and the SDM, and storing the K-bit calibration code in a memory. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a schematic diagram of a segmented digital-to-analog converter (DAC) with a resistor-to-resistor (R-2R) most significant bit (MSB) DAC.

[0007] Figure 2 is a schematic diagram illustrating example operations of one embodiment or configuration of a segmented DAC.

[0008] Figure 3 is a schematic diagram illustrating example operations of another embodiment or configuration of a segmented DAC.

[0009] Figure 4 is a schematic diagram of an example 8-bit R-2R MSB DAC in a segmented DAC with a chopper circuit.

[0010] Figure 5 is a schematic diagram of an example 12-bit R-2R MSB DAC in a segmented DAC with a chopper circuit.

[0011] Figure 6 is a schematic diagram of an example 8-bit R-2R MSB DAC in a segmented DAC without a chopper circuit.

[0012] Figure 7 is a schematic diagram of an example 8-bit matrix MSB DAC in a segmented DAC.

[0013] Figure 8 is a schematic diagram of an example 8-bit binary-weighted MSB DAC in a segmented DAC.

[0014] Figure 9 is a schematic diagram of an example ordered element matching (OEM) circuit with seven OEM switching circuits in a MSB DAC of a segmented DAC.

[0015] Figure 10 is a schematic diagram of an example 12-bit resistor DAC with a 9-bit R-2R MSB DAC circuit and an example ordered element matching (OEM) circuit with seven OEM switching circuits.

[0016] Figure 11 is a schematic diagram of an example 8-bit resistor DAC with a 4-bit R-2R MSB DAC circuit and another example ordered element matching (OEM) circuit with fifteen OEM switching circuits in a MSB DAC of a segmented DAC.

[0017] Figure 12 is a schematic diagram of an example 8-bit resistor DAC with a 5-bit R-2R MSB DAC circuit and another example ordered element matching (OEM) circuit with seven OEM switching circuits in a MSB DAC of a segmented DAC.

[0018] Figure 13 is a schematic diagram of an example 12-bit resistor DAC with a 9-bit R-2R MSB DAC circuit and another example ordered element matching (OEM) circuit with seven OEM switching circuits in a MSB DAC of a segmented DAC.

[0019] Figure 14 is a schematic diagram of an example 4-bit interpolating DAC in a segmented DAC.

[0020] Figure 15 is a schematic diagram of another interpolating DAC or interpolating amplifier DAC in a segmented DAC.

[0021] Figure 16 is a schematic diagram of another interpolating DAC in a segmented DAC without chopper functionality.

[0022] Figure 17 is a schematic diagram of another interpolating DAC in a segmented DAC with chopper functionality.

[0023] Figure 18 is a schematic diagram of an example sigma delta modulator (SDM) and dynamic element matching (DEM) to provide 4-bit sigma delta codes to an interpolating DAC in a segmented DAC.

[0024] Figure 19 is a schematic diagram of a noise shaping model illustrating operation of a sigma delta modulator in a segmented DAC.

[0025] Figure 20 is a graph of an example chopping signal for dynamic element matching in a segmented DAC.

[0026] Figure 21 is a schematic diagram of an example calibration circuit implementation in a segmented DAC.

[0027] Figures 22 to 24 is a schematic diagram of example chopper functionality used in association with a MSB resistor DAC and / or an interpolating DAC in a segmented DAC.

[0028] Figure 25 is a flowchart of an example calibration method or process for calibrating a segmented DAC.

[0029] Figure 26 is a flowchart of another calibration method.

[0030] Figures 27 to 29 is a partial schematic diagram showing example MSB, ISB, and LSB measurements in a calibration method of Figure 25

[0031] Figure 30 is a partial schematic diagram showing example calculations of DAC output voltages in a calibration method of Figure 25

[0032] Figure 31 is a partial schematic diagram showing example calculations of DNL and INL performance of a 16-bit DAC in a calibration method of Figure 25

[0033] ​​​Figure 32 is Figure 31 a graph of the DNL performance calculated in

[0034] Figure 33 is Figure 31 a graph of the INL performance calculated in

[0035] Figure 34 is a partial schematic showing an example calculation of recorded calibration DAC codes in the calibration method of Figure 25

[0036] Figure 35 is another partial schematic showing an example calculation of recorded calibration DAC codes in the calibration method of Figure 25

[0037] Figure 36 is another partial schematic showing an example calculation of recorded calibration DAC codes in the calibration method of Figure 25

[0038] Figure 37 is another partial schematic showing an example calculation of recorded calibration DAC codes in the calibration method of Figure 25

[0039] Figure 38 is a graph of example calibration codes.

[0040] Figure 39 is a graph of example differential nonlinearity (DNL) in a segmented DAC.

[0041] Figure 40 is a graph of example integral nonlinearity (INL) in a segmented DAC.

[0042] Figure 41 is a graph of example resistor DAC DNL for an ideal resistor ladder in a segmented DAC and a mismatched resistor ladder without any resistor DAC chopping function.

[0043] Figure 42 is a graph of example resistor DAC INL for an ideal resistor ladder in a segmented DAC and a mismatched resistor ladder without any resistor DAC chopping function.

[0044] Figure 43 is a graph of example 16-bit DAC calibration codes calculated according to the method of Figure 25

[0045] Figure 44 is a graph showing example resistor DAC DNL for an ideal resistor ladder in a segmented DAC and a mismatched resistor ladder with a resistor DAC chopping function.​​​​​

[0046] Figure 45 is a graph showing an example resistor DAC INL exhibiting an ideal resistor ladder for use in a segmented DAC and a mismatched resistor ladder with resistor DAC chopping functionality. DETAILED DESCRIPTION

[0047] In the drawings, like reference numerals are used to refer to like elements throughout the several views, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the term "including" "includes" "having" "has" "with" or variants thereof are intended to be inclusive in a manner similar to the term "comprising" and thus are to be construed as meaning "including but not limited to." Also, the term "couple" or "couples" is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or with a second device, that connection can be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.

[0048] Figure 1 An example segmented DAC circuit 100 is shown that includes an input decoder 102 having an input 104 that receives a K-bit binary encoded digital input signal (CODE) for conversion to provide an analog output signal VOUT representing the value of the digital input signal CODE. The digital input signal CODE includes a M-bit first subword (MSB), an I-bit second subword (ISB), and an L-bit third subword, where M, I, and L are each greater than 1, and K = M + I + L. The first subword is referred to herein as the "MSB subword," which has M bits that include the most significant bits of the digital input signal CODE. The third subword LSB includes the least significant bits of the digital input signal CODE. The decoder 102 includes outputs 106-M that provide the M-bit first word MSB to an address (ADDR) input of a calibration memory 108. The decoder 102 also includes an output 106-I that provides the I-bit second subword ISB, and another output 106-L that provides the L-bit third subword LSB. In this example, the decoder 102 buffers and parses the digital input signal CODE into the MSB, ISB, and LSB subwords without modification. In other examples, the decoder 102 can perform other digital signal operations on the digital input signal CODE. In other implementations, the decoder 102 can be omitted. The digital input signal CODE can be received from any suitable digital signal source, such as a microcontroller (not shown).

[0049] The calibration memory 108 stores calibration data indexed according to the first subword MSB received at the first address input ADDR or according to the second subword ISB received from the decoder output 106-1 at the other address input ADDR2. In one example, the memory 108 stores a first set of K x M bits of calibration data for calibrating the first subword MSB, a second set of K x M bits of calibration data for calibrating the second subword ISB, and a third set of K x M bits of calibration data for calibrating the third subword LSB. In a particular example, the calibration memory 108 provides a calibration code CAL_CODE from the calibration data based on the digital input signal CODE. The DAC circuit 100 also includes a multiplexer 110 having an enable input 112 to receive a selection or enable signal OEM EN. The multiplexer 110 includes a first input 116 to receive the M-bit OEM signal from the OEM memory 114, and a second input to receive the M-bit first subword MSB. An output 118 of the multiplexer 110 provides the M-bit input signal to an M-bit MSB resistor DAC 120.

[0050] In one example, the resistor DAC 120 is a resistor-two resistor (R-2R) DAC including a resistor circuit and a switching circuit operating according to the M-bit input from the multiplexer output 118. In other examples, the resistor DAC 120 can be a resistor ladder circuit (e.g., the following Figure 8 ) to provide a voltage divider having a switching circuit operating according to the multiplexer output. In other implementations, the resistor DAC 120 is a resistor matrix DAC circuit (e.g., the following Figure 7 ) including a matrix of resistor elements and switches formed in a number of rows and a number of columns to provide a voltage divider operating according to the M-bit input from the multiplexer output 118. The resistor DAC 120 operates according to a reference voltage to provide a voltage divider output that is a first analog output signal. In the illustrated example, the resistor DAC 120 includes a first input 121-H and a second input 121-L to receive reference voltages VrefH and VrefL. The voltage divider circuit is formed by resistors in the resistor DAC 120 to provide the first analog output signal at a first converter output 122 at a level of or between the levels of the reference voltages VrefH and VrefL according to the M-bit input from the multiplexer output 118. In operation, when the multiplexer 110 delivers the first subword at the output 118, the first analog output signal represents the value of the first subword MSB. In Figure 1In an example, resistor DAC 120 provides a differential first analog output signal VH, VL at first output 122-H and second output 122-L. In other possible implementations, resistor DAC 120 provides a single-ended first analog output signal. In a particular example, resistor DAC 120 includes a resistive chopper circuit that operates according to a unit or multi-bit chopper switching control signal "chop" received at input 124.

[0051] DAC circuit 100 also includes an interpolating DAC 126 having an output 128 that provides an analog output signal VOUT. Interpolating DAC 126 includes an input 130 that receives an N-bit digital interpolating code signal ICODE, where N is an integer greater than one. Interpolating DAC 126 shifts the first analog output signal VH, VL based on the interpolating code signal ICODE to provide the analog output signal VOUT. In one example, interpolating DAC 126 increases or decreases the first analog output signal by an amount determined by the interpolating code signal ICODE. In a particular implementation, interpolating DAC 126 includes a chopping circuit that operates according to a chopper signal "chop" received at input 127. In the illustrated example, interpolating DAC 126 operates as a shift amplifier having a differential non-inverting input (+) connected to outputs 122-H, 122-L of resistor DAC 120, and an inverting input (-) connected to output 128 for feedback to provide the analog output signal VOUT.

[0052] The DAC circuit 100 also includes a calibration and dynamic element matching (DEM) circuit 134 with a calibration circuit 135. The circuit 134 includes an input 132 that receives a calibration code (CALCODE) from the data output (DATA) of the calibration memory 108. The calibration and DEM circuit 134 in a particular example also receives the second subword ISB from the decoder output 106-I and the third subword LSB from the decoder output 106-L. The circuit 134 in a particular example also includes a sigma delta modulator 136 (SDM). In one example, the SDM 136 is a first order modulator. In other examples, a second or higher order modulator can be used. The calibration circuit 135 provides a modulator code (SDCODE) to the SDM 136 based on the calibration code CALCODE and the second and third subwords ISB and LSB. In one implementation, the SDM 136 modulates the modulator code SDCODE from the calibration circuit 135 to provide an N-bit digital interpolation code signal ICODE that represents the values of the second and third subwords ISB and LSB, where N is less than I+L. In another example, the SDM 136 modulates the N-bit interpolation code signal based on the first and second subwords ISB and LSB. The SDM 136 in a particular example provides the N-bit digital interpolation code signal ICODE at an output 138 of the circuit 134. The SDM output represents the values of the second and third subwords ISB and LSB. A multiplexer 140 includes a control input 142 that receives a unit resolution select signal RESJSEL. In one state of the RES SEL signal, the multiplexer 140 provides the N-bit interpolation code signal ICODE from the output 138 of the circuit 134 at the input 130 of the interpolation DAC 126 for (M+I+L)-bit resolution of the DAC circuit 100. In another state of the RES SEL signal, the multiplexer 140 provides the LSB subword signal from the decoder output 106-L to the interpolation DAC input 130. The interpolation DAC 130 shifts the first analog output signals VH, VL according to the interpolation code ICODE provided by the multiplexer 140 to produce the output voltage signal VOUT.

[0053] Reference is also made to Figure 2 and 3 , Figure 2 An example 16-bit (K=16) example digital input signal 200 (CODE) is illustrated. The 16-bit example digital input signal 200 includes an 8-bit first subword MSB (in Figure 1Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 2 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 2 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 2 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 2 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 3 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 2 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as 3 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as

[0054] Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Figure 4 Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as Nyquist sampling conversion of the M=8 bit first subword at 202 and another conversion at 204 in which an I=4 bit intermediate second subword ISB undergoes Nyquist sampling conversion. Conversion 201 is equivalent to the operation of resistor DAC 120 and interpolating DAC 126 as

[0055] The circuit is configured to individually include a series of segments of tap nodes 405. The R-2R circuit 401 includes M or fewer segments, each segment having two R-2R portions individually associated with a corresponding one of the differential outputs 122. Each of the portions includes a resistor element having a resistance value of 1R connected in series with a 1R element of the other segment, and a resistor element having a resistance of 2R connected to the switching circuit at a corresponding tap node 405. The illustrated example is a differential R-2R circuit. Single-ended limiting is possible for a single output line 122, and each R-2R segment includes a single 1R element and a single 2R element. Individual resistor elements (1R and / or 2R) can be a single resistor component or can be multiple resistor components connected in any suitable series and / or parallel configuration to provide the corresponding 1R or 2R resistance. In the illustrated implementation, in each of the R-2R segments, a single tap node 405 is connected to both 2R elements. A first switching circuit 411 includes a plurality of switches S individually connected between a corresponding one of the tap nodes 405 and the voltage divider input 121. In the illustrated differential example, the switching circuit 411 includes a first switch and a second switch for each R-2R segment, with each switch connected between the segment tap node 405 and a corresponding one of the inputs 121-H, 121-L. The switches of the circuit 411 operate in complementary fashion according to a corresponding one of the first sub-words dacm<7:0> (dac, 13:8) to connect the corresponding segment tap node 405 with either the input 121-H (VrefH) or the input 121-L (VrefL).

[0056] In Figure 4In the example of FIG. 4, resistor circuit 401 includes six segments switched according to the first six MSB bits dacm<5:0> and the remaining two MSB bits dacm<7:6> are provided as inputs to thermometer decoder 404. Decoder 404 includes an output 406 that provides thermometer encoded switching control signals T<2:0> to operate an ordered element matching (OEM) switching circuit 412. The ordered element matching is implemented by a resistive OEM circuit 402 having three sets of OEM resistor elements. In one example, the resistor elements have a resistance of 2R. The 2R elements of each set are connected between the set's OEM tap node 407 and a corresponding one of the outputs 122-H, 122-L. OEM switching circuit 412 includes three sets of two OEM switches to selectively connect a corresponding one of the OEM resistor elements between the voltage divider input 121 and the first converter output 122 based on the OEM code set by the switching control signals T<2:0> from thermometer decoder 404. The OEM switches operate in a complementary fashion according to a corresponding one of the control signals T<2:0> to connect the corresponding OEM tap node 407 to either input 121-H (VrefH) or input 121-L (VrefL).

[0057] Figure 4 Resistor DAC 120 in FIG. 4 also includes a resistive chopper circuit 403 having a plurality of chopper resistors with a resistance value of 2R, and a chopper switching circuit 413. Chopper switching circuit 413 includes an input 124 to receive a chopper code "chop," and chopper switches to selectively connect a corresponding one of the chopper resistors to both voltage divider inputs 121-H and 121-L. In some embodiments, the chopper circuit can be omitted where the R-2R circuit is to be used for all MSB bits dacm <m-l:0>Provides component segmentation.

[0058] Figure 1 and 4 The DAC circuit 100 advantageously employs an R-2R MSB resistor DAC 120 to convert the first subword MSB to the first analog output signals VH, VL using significantly fewer switches than conventional resistor-stepped MSB DACs. Circuit 100 also provides an interpolation DAC buffer stage 126 that minimizes calibration memory requirements, and thus the storage capacity of calibration memory 108 can be much smaller than in conventional designs. An optional ΣΔ modulator 136 can be used to achieve additional resolution in the DAC circuit 100 without requiring an additional calibration DAC to achieve 16-bit resolution. The reduction in switching and memory capacity allows for a reduction in circuit area and power consumption. Furthermore, fewer switches improve overall DAC performance without reducing the number of bits M in the first subword. A particular embodiment includes a DEM circuit 134 to improve overall DAC INL / DNL performance.

[0059] Figure 4 The R-2R resistor DAC 120 operates according to the MSB bits dacm<5:0>. The switch of circuit 411 toggles between V=0 (logic 0) and V=Vref (logic 1), where in the illustrated differential example, Vref=VrefH-VrefL. The R-2R network causes the contribution of the MSB digital bits to the output voltage VOUT to be weighted. Depending on which bits are set to 1 and which bits are set to 0, the output voltage VOUT has a range between 0 and Vref minus the minimum step size (corresponding to bit 0 (dacm)). <0> The corresponding step values ​​between the values ​​of )). The actual value of Vref (the voltage of logic 0) will depend on the type of technology used to generate the digital signal. The R-2R DAC is a binary weighted voltage divider. The 2R branches connected in parallel with each 1R resistor in series form the binary weights, and only one bit of the first subword MSB is needed for each bit of resolution. The switch is connected to ground or a reference voltage. In addition, the equivalent impedance of the resistor ladder is generally lower than that of a conventional series DAC, and therefore the resistor DAC circuit 120 has lower noise.

[0060] Figure 5 Here is another example of a resistor-based DAC circuit, where M = 12. Figure 5 Circuit 120 in the example also uses an R-2R MSB DAC in a segmented DAC with chopper circuitry. In this example, 16-bit resolution is achieved without an SDM 136. In this example, the 12-bit resistor DAC 120 contains nine R-2R segments that are switched according to the first nine MSB bits dacm<8:0>, and the remaining three MSB bits dacm... <l1:9>provided as input to thermometer decoder 404. In this example, decoder output 406 provides thermometer encoded switching control signals T<6:0> to operate seven-segment OEM switching circuit 412. Using Figure 4 and 5 The segmented DAC circuit 100 of resistor DAC 120 also facilitates reduced calibration memory requirements and shorter factory calibration times. In a particular example, high performance for low INL and DNL can be achieved. For example, for a 16-bit case, less than + / - 1 LSB INL and DNL can be achieved over a + / - 32 LSB calibration range with + / - 1 / 4 calibration steps. Calibration memory in one 16-bit example using 12-bit MSB DAC 120 requires only 12x8-bit memory 108 for MSB calibration with chopper functionality, only 12x8-bit memory for MSB calibration without chopper functionality, and only 16x6-bit memory for LSB calibration. No additional calibration DAC is used in this example.

[0061] Figure 6 An exemplary 8-bit R-2R MSB DAC in a segmented DAC without chopper circuit is shown. This example uses 6 R-2R segments controlled by dacm<5:0> and OEM circuit 402, 412 operating according to control signals T<2:0> from thermometer decoder 404 based on dacm<7:6>. As compared to the example of Figure 4 and 5 This example provides lower power consumption as compared to the example of

[0062] Figure 7 An example 8-bit matrix MSB resistor DAC 120 usable in a segmented DAC 100 is shown. In this example, the resistor DAC 120 is a matrix DAC with resistors configured in a resistor matrix having a plurality of rows and columns, chopper functionality, and no OEM circuitry. The resistors R of a given row are connected in series with each other to define a tap node 405, and the ends of a row are connected to the beginning of the next row. The first end of the first row is connected to input 121-H (VrefH) and the final end of the last row is connected to input 121-L (VrefL). A first set of switches S is configured in the matrix to selectively connect a corresponding tap node 405 with a corresponding column line CL of the matrix along a corresponding row line RL of the matrix based on one of a first set of switching control signals 711. A row decoder 701 provides row selection signals according to the most significant set of bits dacm<7:4> of the first subword MSB. A second set of switches S is configured to selectively connect a corresponding one of the row lines RL to one of the converter outputs 122-H or 122-L based on the remaining least significant first subword bits dacm<3:0>, based on a corresponding one of a second set of switching control signals 712 from a second (column) decoder 702. Other matrix resistor DACs with any suitable number of rows and columns in different implementations can be used.

[0063] Figure 8 An example 8-bit binary-weighted MSB DAC in a segmented DAC is shown. In this case, the voltage divider circuit 804 is a resistor ladder circuit 804 with M-1 resistors R connected in series with each other to define tap nodes 805 between the resistors R. A decoder 801 provides switching control signals 802 to switches S of a switching circuit 806 to selectively connect selected ones of the tap nodes 805 to a corresponding one of the output lines 122-H or 122-L based on the first subword bits dacm<7:0>. A chopper circuit 808 is disposed at the ends of the ladder circuit 804 between the end resistors R and inputs 121-H, 121-L, with the chopper resistor circuit and chopper switches operating according to a "chop” signal from input 124. In one possible implementation, the remaining least significant bits (e.g., the remaining 4 bits for a 12-bit segmented DAC implementation or 8 remaining bits for a 16-bit implementation) are provided as inputs to the SDM 136 to deliver an interpolated code ICODE to the input 130 of the interpolated DAC 126. In this case, the interpolated DAC 126 is a binary-weighted DAC, and the SDM 136 is a binary-weighted SDM. Figure 8 In the resistor DAC 120 of FIG. 8, the decoder 801 implements the switching for the selective connection of a particular tap node 805 to either of the VH or VL output lines 122-H or 122-L, and implements any included OEM switching and chopper functionality.

[0064] Reference is also made to Figure 9 and 10 Particular examples include ordered element matching (OEM) circuits implemented in the OEM circuits 402 and 412. Figure 9 An example ordered element matching (OEM) circuit 900 with seven OEM switching circuits in the R-2R MSB resistor DAC 120 is shown. In a particular example, switching the individual 2R elements of the OEM resistor circuit 402 includes a plurality of resistor structures 902, many of which can not have the same resistance as an ideal resistor unit 904. The corresponding switches in the OEM switching circuit 412 operate based on the output signals 406 from the thermometer decoder 404. The average resistance of each set of resistor structures 902 associated with the high reference input 121-H (average of RH) is approximately equal to the average resistance of the resistor structures 902 associated with the low reference input 121-L (average of RL), and the average of the deviation from the ideal value is approximately equal (e.g., (RH - Runit_ideal) is approximately equal to (Runit_ideal - RL)). In one example, Figure 9 The example ordered element matching circuit 900 of Figure 4 may be used in conjunction with the resistor DAC structure 120 of Figure 10 In this example, the thermometer decoder 404 generates thermometer encoded control signals 406T<6:0> based on the first subword bits dacm<7:5>, and the OEM switching circuit 412 includes corresponding switches to implement ordered element matching. <l1:9>and thermometer encoding control signals 406T<7:0> are generated. With Figure 9 As in the example of Figure 10 The OEM switching circuit 412 in includes corresponding switches to implement the ordered element matching function. Figure 11 An exemplary 8-bit resistor DAC 120 with 4-bit R-2R MSB DAC circuit with fifteen OEM switching circuits is shown in the MSB DAC of a segmented DAC, along with another exemplary ordered element matching (OEM) circuit. This example provides 4-bit thermal decoding along with 4-bit binary decoding configuration. Figure 12 An exemplary 8-bit resistor DAC 120 with 5-bit R-2R MSB DAC circuit with seven OEM switching circuits is shown in the MSB DAC of a segmented DAC 100, along with another exemplary ordered element matching (OEM) circuit. This example provides 3-bit thermal decoding along with 5-bit binary decoding configuration. Figure 13 Another exemplary 12-bit resistor DAC 120 with 9-bit R-2R MSB DAC circuit with seven OEM switching circuits is shown in the MSB DAC of a segmented DAC 100, along with another exemplary ordered element matching (OEM) circuit. In this example, the OEM memory 114 receives dacm<8:6> bits and provides high OEM control signals OEMH:2:0> and low OEM control signals OEML<2:0> to the OEM logic circuit 1302 including thermometer decoder 404, respectively. The decoder 404 provides signals to the OEM circuit 412 as thermometer decoding signals T<6:0> by decoding dacm<11:9>. The OEM logic circuit 1302 provides high thermometer decoding signals TH<6:0> and low thermometer decoding signals TL<6:0> as output signals 406 to the OEM circuit 412 based on verification or calibration as shown in table 1306 in Figure 13 The OEM logic circuit 1302 provides high thermometer decoding signals TH<6:0> and low thermometer decoding signals TL<6:0> as output signals 406 to the OEM circuit 412 based on verification or calibration as shown in table 1306 in <n>+ R_TL <n>Close to ideal cell resistor (n is from 0 to 6).

[0065] Reference is also made to Figures 14 to 21 Any suitable N-bit interpolating DAC 126 can be used in the segmented DAC circuit 100, where N is an integer greater than 1. Figure 14 An example 4-bit interpolating DAC 126 is shown. The circuit 126 includes a current source driven by a positive supply voltage V+ to provide current to the sources of PMOS transistors including integer N number of matched pairs MPA1 and MPB1, MPA2 and MPB2,... MPAN-1 and MPBN-1, and MPAN and MPBN. Transistors MPA are connected in parallel between the current source 1402 and a line or circuit node 1404, and transistors MPB are connected in parallel between the current source 1402 and a second line 1406. An output stage MCX includes a second current source 1412 that provides current based on the positive voltage supply V+. Figure 14 The output stage in includes PMOS transistors MP1 and MP2, and lower NMOS transistors MN1 and MN2. MP1 and MN1 are connected in series with each other in a first circuit branch between the current source 1412 and a second voltage supply V-, and line 1404 is connected to the drains of MN1 and MP1. MP2 and MN2 are connected in series with each other in a second circuit branch between the current source 1412 and the supply voltage V-, and a node that joins the drains of MP2 and MN2 is connected to the drain of transistor MPB via line 1406. The output stage also includes a buffer amplifier 1414 that includes an input connected to line 1404, and an output 128 to provide an analog output signal VOUT. The output 128 is connected to the gate of MP2, and the gate of MP1 provides a feedback signal to the gates of transistors MPB1 through MPBN. In a particular example, a switching circuit 1408 includes an input 127 and switches that operate according to an interpolating or chop control signal chop to implement chopper functionality.

[0066] The gates of transistors MPA are connected to individual switches of switching circuit 1408. The gates of transistors MPB are connected to one another to receive an output signal from output stage 1410. The switches of circuit 1408 are opened or closed based on interpolation code signal ICODE to implement a swap based on selective connection to first converter output lines 122-H or 122-L (based on interpolation code signal ICODE) to determine whether to add the corresponding contribution of a given one of transistors MPA to the current flowing in line 1404. In this way, the interpolation code determines whether the individual gates of transistors MPA are connected to VH or VL from the differential first analog output signal from resistor DAC 120. In operation, interpolation DAC 126 interpolates output voltage VOUT between taps of resistor DAC 120 based on interpolation code signal ICODE.

[0067] Figure 15 Another interpolation DAC or interpolation amplifier DAC 126 in segmented DAC 100 is shown. Figure 15 Interpolation DAC 126 of includes an interpolation switch matrix 1500 that receives the first analog output signal (VH, VL) from resistor DAC 120. In this example, switch matrix 1500 produces a 32-bit digital output, with individual bits connected to the left side of one of 32 individual differential pair stages in differential pair circuit 1504. Individual differential pairs in circuit 1504 are biased by a corresponding one of 32 current sources in current source circuit 1502. In this case, interpolation DAC 126 has an output stage MDVI that provides output signal VOUT at output terminal 128. Figure 16 Another interpolation DAC example 126 in segmented DAC circuit 100 is shown. Figure 16 Interpolation DAC 126 of includes a single current source that provides bias current IB to interpolation DAC switching circuit 1602, which operates according to interpolation code ICODE to selectively provide binary-weighted amounts of bias current IB to one of a pair of differential pairs in differential pair circuit 1604. The positive (+) input of the first differential pair is connected to node 122-H to receive the VH signal from MSB DAC 120. The positive (+) input of the second differential pair is connected to node 122-L to receive the VL signal, and the negative (-) differential pair input is connected to node 128 to receive the output voltage signal VOUT as feedback from output stage 1606. In contrast to Figure 14 and 15 In contrast to the interpolation DAC topology of Figure 16 Interpolation DAC 126 of advantageously reduces the number of differential pair circuits to reduce associated switch leakage at the differential pair inputs.

[0068] Figure 17 Another low switch leakage interpolating DAC 126 is shown that includes a single current source to bias an interpolating DAC switching circuit 1602 that operates according to an interpolating code ICODE. Figure 17 The DAC 126 in FIG. 16A also includes a differential pair circuit 1604 having two differential pairs (as described above in connection with Figure 16 FIG. 16B), and an output stage MDCVI to provide an output voltage signal VOUT. Figure 17 The interpolating DAC 126 in FIG. 16A further includes chopper functionality in which switches in the circuit 1604 provide selective connections to swap the positive (+) and negative (-) inputs of the two differential pairs in the circuit 1604 according to a chopping input signal at input 127.

[0069] Figure 18 An example SDM circuit 136 and dynamic element matching (DEM) to provide 4-bit sigma delta codes to the interpolating DAC 126 in the segmented DAC circuit 100 is shown, and Figure 19 A noise shaping model 1900 illustrating operation of one example SDM 136 is shown. In one example, the calibrating component 135 provides a modulator code SDCODE to an input 1902 of the SDM 136. In one example, the input 1902 is an 8-bit input provided to a summer component 1904. The output of the summer component 1904 provides an input to a quantizer 1906. The output of the quantizer is connected to the SDM output and to an input 130 of the interpolating DAC 126 to provide an N-bit interpolating code ICODE. From Figure 18 the simplified schematic diagram of FIG. 16A is omitted Figure 1 the multiplexer 140 in FIG. 16A. In one example, the interpolating code ICODE is a 4-bit digital signal, but other values of N can be implemented in other examples. The quantizer output code ICODE is subtracted from the output of the summer component 1904 by a second summer component 1908 to provide an input to a delay unit 1910. The delay unit output is added to the modulator code SDCODE by the first summer component 1904. In this example, the SDM 136 delivers an N-bit interpolating code based on the N-bit second subword ISB and the third subword LSB, where N is less than I+L.

[0070] The input to the first summer component 1904 is labeled "X" and the output of the first summer component 1904 is labeled "U". Additionally, in Figure 19 In the middle, the quantizer output is labeled "Y" and the delayed input is labeled "-Q". The SDM 136 operates to modulate the received modulator code SDCODE (e.g., 8 bits in one example), with the quantizer 1906 providing the output code as input to the interpolating DAC 126. The operation of the SDM 136 is illustrated by the following equations:

[0071] U (n) = X (n) -Q (n-1) .

[0072] Q (n) = Y (n) -U (n) .

[0073] Y (n) = X (n )-Q (n-1) +Q (n) = X (n) +Q (n) -Q (n-1) .

[0074] Q (n) -Q (n-1) = (1 - Z -1 )*Q.

[0075] Y = X + (1 - Z -1 )*Q.

[0076] Figure 20 A graph 2000 is shown that includes an example signal waveform 2002 that shows a chopping signal over time in a particular implementation of the segmented DAC 100. In the illustrated example, the chopping signal is used to control the alternate selection of one of two switches S1 and S2 to perform dynamic element matching by alternately selecting one of two circuit components or elements. For example, Figure 4 The MSB resistor DAC 120 in the Figure 20 An example 50% duty cycle signal waveform 2002 is illustrated for the chopping signal. In this example, the chopping frequency is the inverse of the switching period T shown in the graph 2000. The chopping signal can also or instead be used for the chopping function in the interpolating DAC 126 (e.g., Figure 17 ), where the signal waveform 2002 can be applied to the input 127.

[0077] Figure 21 An example calibration in a segmented DAC is shown. In one example, the calibration achieves INL < + / - 1 LSB, and DNL < + / - 1 LSB and + / - 32 LSB calibration range with + / - 1 / 4 calibration step size. In one example, a 16-bit DAC LSB - Vref / 2 16 The calibration memory requires 8x9-bit memory for MSB calibration, and 16x7-bit memory for ISB calibration. For a 16-bit segmented DAC circuit 100, the calibration uses 1 / 4 LSB calibration step size within + / - 32-bit calibration range, where calibration LSB_calibration = Vref / 2 18 = LSB dac16 / 4. The calibration code range is + / - 128, and DAC ISB is thermometer decoded from dac<7:4>. An example calibration data set is shown in Table 1 below:

[0078] Table 1

[0079]

[0080] Figures 22 to 24 An example chopper functionality in a segmented DAC is illustrated. Figure 22 An interconnection is shown that applies a chopper signal to a resistor DAC 124, swapping the first analog output signal line 122 between the output of the resistor DAC 120 and the interpolating DAC 126. In Figure 22 In one example, a chopper signal is provided at input 124 to the resistor DAC 120 to switch the VH and VL signals provided to the input of the interpolating DAC 126. In Figure 23 In one example, a chopper signal is provided to the resistor DAC input 124 and the chopper input 127 of the interpolating DAC circuit 126 to switch the VH and VL signals provided to the interpolating DAC circuit. Figure 22 and 23 An example provides resistor DAC chopping. Figure 24 Another example is shown that includes a chopper amplifier circuit 2400 that provides a first signal and a second signal to the input of the interpolating DAC 126.

[0081] Reference is now made to Figures 25 to 45 , Figure 25 A DAC calibration method or process 2500 is shown. The method 2500 provides calibration for a DAC circuit that converts a K-bit digital input signal (e.g., CODE above) that includes an M-bit first subword MSB (which includes the most significant bits of the digital input signal), an I-bit second subword ISB, and an L-bit third subword LSB (which includes the least significant bits of the digital input signal). In one example, the method 2500 is implemented during manufacturing of the segmented DAC circuit 100. Moreover, the calibration method 2500 provides significant advantages in calibration memory utilization and calibration time compared to conventional calibration processes. Figure 26 A conventional calibration method 2600 is shown that includes measuring INL and DNL of a DAC system at 2610, trimming a calibration DAC at 2622, calibrating the DAC and recording the calibration code in memory at 2620, and measuring DAC INL and DNL after calibration at 2630. In comparison, the illustrated method 2500 does not require trimming of a calibration DAC and can be implemented using significantly less calibration memory than conventional techniques.

[0082] The method 2500 includes measuring DAC output voltages at 2502, including measuring output voltages of the resistor DAC to obtain a corresponding set of values for the first subword, measuring output voltages of the interpolating DAC to obtain a corresponding set of values for the second subword, and measuring output voltages of the SDM to obtain a corresponding set of third subword values. At 2510, the method includes calculating output voltage values based on the measured output voltages. At 2520, the method provides calculated calibration codes for the resistor DAC, the interpolating DAC, and the SDM, and calculates and stores a K-bit calibration code for the DAC circuit based on the calibration codes. Thereafter at 2530, the method includes calculating calibrated DAC INL and DNL. Figures 27 to 29 An example MSB, ISB, and LSB measurement in the calibration method 2500 is shown. Figure 25

[0083] The method 2500 is described in the context of the 16-bit segmented DAC circuit 100 as described above (including M = 8-bit first subword MSB, I = 4-bit second subword ISB, and L = 4-bit third subword LSB), but the method 2500 can be used in connection with calibration of other segmented DAC systems having other values for M, I, and / or L. In this example, the output voltage measurements at 2502 include measuring M+1 output voltages VH_MSB, VL_MSB of the M-bit resistor DAC 120 at 2504 to obtain a corresponding M+1 set of values for the first subword MSB. In the illustrated example, the M+1 set of values for the first subword MSB includes a first set in which all bits are set to 0 and M values in which only a single bit is set to 1. Figure 27 ​This demonstrates an example of the operation at 2504, comprising M+1 values ​​of the first subword b<15:8> and an instance set 2704 of the corresponding measured voltages VH and VL. (Example...) Figure 27 As seen, only nine values ​​of the first subword MSB need to be evaluated for the measurement at 2504. This significantly reduces measurement time compared to a conventional resistor ladder DAC in a segmented DAC system.

[0084] Method 2500 measures the 2-bit interpolation of DAC 126 at position 2506. I (=16) output voltages VOUT_ia_ISB to obtain the corresponding 2 of the second subword ISB. I The process continues with a unique set of values. Figure 28 An example of the processing at 2506 is shown, containing all 16 unique values ​​of the 4-bit second subword (dac<7:4>) and the corresponding set of instances of the measured voltage VOUT_ia_ISB. The measurement further includes measuring the L-bit ΣΔ modulator SDM 136 at 2508. L The output voltage Vout_sd is used to obtain the corresponding 2 of the third subword LSB. L A set of unique values. Figure 29 This example demonstrates the processing at position 2508, containing all 16 unique values ​​of the 4-bit third subword LSB (dac<3:0>) and the corresponding set of measured voltages Vout_sd.

[0085] Method 2500 in Figure 25 The process continues at point 2512, which involves calculating the K-bit output voltage value DAC Vout based on the measured output voltages VH_MSB, VL_MSB, VOUT_ia_ISB, and Vout_sd. Figure 30 An example of processing at 2512 is shown, including calculating the 8-bit MSB DAC output voltage using formula 3001 at 2512-1, calculating the 8-bit MSB DAC+4-bit ISB output voltage using formula 3002 at 2512-2, and calculating the 16-bit output voltage containing 8-bit MSB+4-bit ISB+4-bit output using the illustrated formula 3003.

[0086] Figure 25 Method 2500 also includes calculating the integral nonlinearity value INL and the differential nonlinearity value DNL at 2514 based on the K-bit output voltage value DAC Vout calculated at 2512. Figure 31 An example calculation 3102 of the DNL and INL performance of a 16-bit DAC is shown at 2514 in an exemplary implementation of calibration method 2500. Figure 32 Provides a graph 3200 displaying the DNL performance curve 3202, and Figure 33 A graph 3300 showing the INL performance curve 3302 calculated by the computation 3102 using Figure 31 at 2514 is provided.

[0087] Continuing in Figure 25 , in one instance, the processing at 2520 includes calculating calibration codes CAL_MSB, CAL_ISB, CAL_LSB for the resistor DAC 120, the interpolating DAC 126, and the SDM 136, respectively, at 2522, 2524, and 2526. Figure 34 An example of the processing at 2520 is illustrated, including a calculation formula 3402. This example includes calculating an 8-bit MSB calibration code code_8_bits_MSB at 2522 according to the following formula: code_8_bits_MSB = (VH - VL_ideal) / (0.25 * lsb) (for ISB = VRFF / 216). Figure 34 An example set of M+l values for the first subword MSB (dac<15:8>) is illustrated, along with the corresponding VH and VL measured values and offset value (VH - VL_ideal). In one example implementation, Figure 34 A table 3402 in

[0088] At 2524 in Figure 25 , the method 2500 includes calculating a 4-bit ISB calibration code "code_8_bits_ISB" according to the following formula: code_8_bits_ISB = (Vout_ia_ISB - Vout_ia_ISB_ideal) / (0.25 * lsb). Figure 35 An example calculation 3502 and resulting example 4-bit ISB calibration code value in one example implementation of the processing at 2524 in Figure 25

[0089] The method 2500 also includes calculating K-bit calibration codes for the DAC circuit 100 based on the calibration codes CAL_MSB, CAL_ISB, CAL_LSB for the resistor DAC 120, the interpolating DAC 126, and the SDM 136 at 2526. Figure 36 An example calculation 3602 and resulting 4-bit calculated LSB calibration code 3604 in one implementation of the processing at 2526 is shown. The K-bit calibration codes are then stored in the calibration memory 108 at 2528 in Figure 25 Figure 37 ​​The example process 2500 is further illustrated in FIG. 28, which illustrates the calculation 3702 of the example process at 2528, where the algorithm can be repeated to calculate 16-bit DAC calibration codes. The calibrated 16-bit DAC INL and DNL values can then be calculated at 2530 to complete the process 2500. Figure 25

[0090] Reference is now made to Figures 38 to 45 , Figure 38 A graph 3800 is provided, which shows example 8-bit first sub-words MSB provided from data output 132 of calibration memory 108 Figure 1 ) for a first address input ADDR provided to memory 108 and 4-bit second sub-words ISB provided to a second address input ADDR2 of memory 108. Graph 3802 illustrates the values of example error codes Error_code i in one example segmented DAC circuit 100. Figure 39 A graph 3900 is provided, which shows an example DNL curve 3902 after calibration of segmented DAC 100. Figures 40 to 45 A graph 4000 is shown with a calibrated INL curve 4002. The particular implementation provides + / - 1 LSB INL and DNL performance within + / - 1 / 4 LSB calibration steps over a certain calibration range.

[0091] Figure 41 An example linear performance curve is further illustrated, which demonstrates the effect of chopper functionality. Figure 42 A graph 4100 is provided, which shows a DNL curve 4102 for an example resistor DAC 120, as well as a curve 4104 showing performance for an ideal resistor ladder without mismatch, which the example resistor DAC does not implement any chopper functionality for a resistor ladder circuit with 1.5% mismatch in resistor DAC 120. Figure 42 A graph 4200 is included with an INL curve 4202 for a resistor DAC resistor ladder circuit with 1.5% mismatch and without implementing chopper functionality. Figure 43 A curve 4204 is also shown for an ideal resistor ladder without mismatch and without resistor DAC chopper functionality. Figure 25 A graph 4300 is provided, which shows a curve 4302 representing example 16-bit DAC calibration codes calculated according to the method of Figure 44 . With the addition of DAC chopper functionality, the linearity is improved, as shown in Figure 44 and 45 . Figure 45 ​A graph 4400 is provided showing a DNL curve 4402 for an example resistor DAC 120 having chopper functionality for a ladder circuit in resistor DAC 120 having 1.5% mismatch, and showing a curve 4404 for performance of an ideal resistor ladder without mismatch. ​ A graph 4500 is included having an INL curve 4502 for a resistor DAC resistor ladder circuit having 1.5% mismatch and having chopper functionality.

[0092] The following Table 2 illustrates various comparative advantages of the segmented DAC system over traditional calibration methods. In particular, a traditional calibration method for a 16-bit system requires more than 256x9 bits of calibration memory for MSB calibration at + / - 32 LSB range, ¼ LSB step, and 16x7 bits of memory for ISB calibration.

[0093] Table 2

[0094]

[0095] The foregoing examples merely illustrate several possible embodiments of various aspects of this application, wherein equivalents and / or modifications are possible upon reading and understanding the description and drawings. Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.< / n> < / n>

Claims

1. A circuit comprising: a decoder having a binary encoded digital input, a first bit output, and a second bit output; a calibration memory having a first input, a second input, and a calibration code output, the first input of the calibration memory coupled to the first bit output of the decoder, and the second input of the calibration memory coupled to the second bit output of the decoder; a resistor digital-to-analog converter having a first input, a second input, and an output, the first input of the resistor digital-to-analog converter coupled to the first bit output of the decoder; and a calibration circuit having a first input, a second input, and an output, the first input of the calibration circuit coupled to the output of the calibration memory, and the second input of the calibration circuit coupled to the second bit output of the decoder.

2. The circuit of claim 1, further comprising an interpolating digital-to-analog converter having a first input and a second input, the first input of the interpolating digital-to-analog converter coupled to the output of the resistor digital-to-analog converter, the second input of the interpolating digital-to-analog converter coupled to the output of the calibration circuit, wherein the decoder has an intermediate bit output.

3. The circuit of claim 1, wherein the resistor digital-to-analog converter is a resistor-two resistor digital-to-analog converter.

4. The circuit of claim 1, wherein the decoder has an intermediate significant bit output.

5. The circuit of claim 4, wherein the calibration memory has a third input and the calibration circuit has a third input, the third input of the calibration memory coupled to the intermediate significant bit output of the decoder, and the third input of the calibration circuit coupled to the intermediate significant bit output of the decoder.

6. The circuit of claim 1, wherein the resistor digital-to-analog converter further comprises: a resistive chopper circuit including a plurality of chopper resistors; and a chopper switching circuit.

7. The circuit of claim 1, wherein the circuit generates an analog output signal representing a value of a K-bit digital input signal, the digital input signal including a first subword having an integer number M of bits, a second subword having an integer number I of bits of the digital input signal, and a third subword having an integer number L of bits, the M bits including a most significant bit of the digital input signal, the L bits including a least significant bit of the digital input signal, where M, I, and L are each greater than one, and where K = M + I + L; wherein the resistor digital-to-analog converter converts the first subword to a first analog output signal representing a value of the first subword, the resistor digital-to-analog converter including: a first converter output to provide the first analog output signal, a resistive voltage divider having an input to receive a reference voltage signal, a plurality of resistors, and a plurality of tap nodes, and a second converter output to provide the second analog output signal. a first switching circuit including a plurality of switches individually connected between a corresponding one of the plurality of tap nodes and an input of the resistive voltage divider, individual ones of the switches being operated to selectively connect the corresponding one of the plurality of tap nodes with the first converter output based on a corresponding bit of the first subword; wherein the resistor digital-to-analog converter is a matrix digital-to-analog converter including the plurality of resistors configured in a resistor matrix having a plurality of rows and a plurality of columns; wherein a first set of the plurality of switches of the first switching circuit is configured in the matrix to selectively connect a corresponding one of the plurality of tap nodes with a corresponding column line of the matrix based on one of a first set of switching control signals along a corresponding row line of the matrix; wherein a second set of the plurality of switches of the first switching circuit is configured in the matrix to selectively connect a corresponding one of the row lines to the first converter output based on a corresponding one of a second set of switching control signals; wherein the resistor digital-to-analog converter further comprises: a first decoder to provide the first set of switching control signals based on a most significant bit set of the first subword, and a second decoder to provide the second set of switching control signals based on a least significant bit set of the first subword.

8. A circuit comprising: a decoder having a binary encoded digital input, a most significant bit output, and a least significant bit output; a calibration memory having a first input, a second input, and a calibration code output, the first input of the calibration memory coupled to the most significant bit output of the decoder and the second input of the calibration memory coupled to the least significant bit output of the decoder; a resistor digital-to-analog converter having a first input, a second input, and an output, the first input of the resistor digital-to-analog converter coupled to the most significant bit output of the decoder; and a calibration circuit having a first input, a second input, and an output, the first input of the calibration circuit coupled to the output of the calibration memory and the second input of the calibration circuit coupled to the least significant bit output of the decoder.

9. The circuit of claim 8, further comprising an interpolating digital-to-analog converter having a first input and a second input, the first input of the interpolating digital-to-analog converter coupled to the output of the resistor digital-to-analog converter, the second input of the interpolating digital-to-analog converter coupled to the output of the calibration circuit, wherein the decoder has an intermediate bit output.

10. The circuit of claim 8, wherein the resistor digital-to-analog converter is a resistor-two resistor digital-to-analog converter.

11. The circuit of claim 8, wherein the decoder has an intermediate significant bit output.

12. The circuit of claim 11, wherein the calibration memory has a third input and the calibration circuit has a third input, the third input of the calibration memory coupled to the intermediate significant bit output of the decoder, and the third input of the calibration circuit coupled to the intermediate significant bit output of the decoder.

13. The circuit of claim 8, wherein the resistor digital-to-analog converter further comprises: a resistive chopper circuit including a plurality of chopper resistors; and a chopper switching circuit.

14. The circuit of claim 8, wherein the circuit generates an analog output signal representing a value of a K-bit digital input signal, the digital input signal including a first subword having an integer M number of bits, a second subword having an integer I number of bits of the digital input signal, and a third subword having an integer L number of bits, the M number of bits including a most significant bit of the digital input signal, the L number of bits including a least significant bit of the digital input signal, wherein M, I, and L are each greater than 1, and wherein K = M + I + L; wherein the resistor digital-to-analog converter converts the first subword to a first analog output signal representing a value of the first subword, the resistor digital-to-analog converter including: a first converter output to provide the first analog output signal, a resistive voltage divider having an input to receive a reference voltage signal, a plurality of resistors, and a plurality of tap nodes, and a first switching circuit including a plurality of switches individually connected between a corresponding one of the plurality of tap nodes and the input of the resistive voltage divider, the switches individually operated to selectively connect the corresponding one of the plurality of tap nodes with the first converter output based on a corresponding bit of the first subword; wherein the resistor digital-to-analog converter is a matrix digital-to-analog converter, the matrix digital-to-analog converter including the plurality of resistors configured in a resistor matrix having a plurality of rows and a plurality of columns; wherein a first set of the plurality of switches of the first switching circuit is configured in the matrix to selectively connect a corresponding one of the plurality of tap nodes with a corresponding column line of the matrix based on one of a first set of switching control signals along a corresponding row line of the matrix; wherein a second set of the plurality of switches of the first switching circuit is configured in the matrix to selectively connect a corresponding one of the row lines to the first converter output based on a corresponding one of a second set of switching control signals; wherein the resistor digital-to-analog converter further comprises: a first decoder to provide the first set of switching control signals based on a most significant set of bits of the first subword, and a second decoder to provide the second set of switching control signals based on a least significant set of bits of the first subword.

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