A modulator applied to high-precision low-power analog-to-digital converter

Abstract

The application discloses a modulator applied to a high-precision low-power analog-digital converter, comprising a signal input end, a signal output end, a digital-analog converter, and sequentially connected first analog adders, first analog integrators, second analog adders, second analog integrators, third analog adders and a first comparator for processing signals; wherein the first analog integrators and the second analog integrators are both switch capacitor integrators based on dynamic amplifiers, and the switch capacitor integrators comprise a second comparator for making the output common mode level of the dynamic amplifier reach a set value. The modulator provided by the application can realize higher precision with lower power consumption on the premise of higher chip yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a modulator for use in high-precision, low-power analog-to-digital converters. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as a bridge between analog signals and digital systems, and are an indispensable analog module in electronic systems used to process natural information. Among them, the Sigma-Delta ADC, through oversampling and noise shaping techniques, significantly improves the in-band signal-to-noise ratio, gradually becoming the mainstream architecture for high-precision ADCs, and is widely used in low-rate, high-precision signal acquisition and processing scenarios (such as audio).

[0003] The Sigma-Delta modulator is the most crucial component in the Sigma-Delta analog-to-digital converter (ADC) architecture, and its performance directly impacts the overall functionality of the Sigma-Delta ADC. Existing Sigma-Delta modulators typically employ cascaded multiple operational amplifier-based switched-capacitor integrators to shape quantization noise. However, operational amplifier-based switched-capacitor integrators consume significant power. Furthermore, as the order of the Sigma-Delta modulator increases, the number of integrators also increases, leading to a further increase in system power consumption. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a modulator for a high-precision, low-power analog-to-digital converter that overcomes or at least partially solves the above problems.

[0005] The present invention provides a modulator for a high-precision, low-power analog-to-digital converter, comprising a signal input terminal, a signal output terminal, a digital-to-analog converter, and a first analog adder, a first analog integrator, a second analog adder, a third analog adder, and a first comparator connected in sequence for processing the signal.

[0006] The input terminal of the first analog adder is connected to the signal input terminal, and the output terminal of the first comparator is connected to the signal output terminal; the signal output terminal is also connected to the input terminal of the digital-to-analog converter, and the output terminal of the digital-to-analog converter is connected to the first analog adder and the second analog adder respectively;

[0007] Both the first analog integrator and the second analog integrator are switched-capacitor integrators based on dynamic amplifiers, and the switched-capacitor integrator includes a second comparator for making the output common-mode level of the dynamic amplifier reach a set value.

[0008] Optionally, the switched capacitor integrator includes an integrator input terminal, an integrator output terminal, a first sampling capacitor, a second sampling capacitor, a first integrating capacitor, a second integrating capacitor, a first switch, a second switch, a third switch, a fourth switch, and a dynamic amplifier;

[0009] The integrator input terminal includes a positive input signal terminal and a negative input signal terminal, and the integrator output terminal includes a positive output signal terminal and a negative output signal terminal;

[0010] One end of the first sampling capacitor is connected to the positive terminal of the input signal through the second switch, and the other end of the first sampling capacitor is connected to the negative input terminal of the dynamic amplifier through the third switch; one end of the first sampling capacitor is also connected to the first common-mode input voltage through the fourth switch, and the other end of the first sampling capacitor is also connected to the second common-mode input voltage through the first switch;

[0011] One end of the second sampling capacitor is connected to the negative terminal of the input signal through the second switch, and the other end of the second sampling capacitor is connected to the non-inverting input terminal of the dynamic amplifier through the third switch; one end of the second sampling capacitor is also connected to the first common-mode input voltage through the fourth switch, and the other end of the second sampling capacitor is also connected to the second common-mode input voltage through the first switch;

[0012] The positive output terminal of the dynamic amplifier is connected to the positive terminal of the output signal, and the negative output terminal of the dynamic amplifier is connected to the negative terminal of the output signal.

[0013] The first integrating capacitor is connected between the negative input terminal of the dynamic amplifier and the positive terminal of the output signal; the second integrating capacitor is connected between the positive input terminal of the dynamic amplifier and the negative terminal of the output signal.

[0014] Optionally, the dynamic amplifier includes a second comparator, a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a first current source, a second current source, a third current source, a first capacitor, a second capacitor, two reset switches, two limit switches, and three current switches.

[0015] The gates of the first and second field-effect transistors are respectively the positive and negative input terminals of the dynamic amplifier. The sources of the first and second field-effect transistors are connected and connected to one end of the third current source through the current switch; the other end of the third current source is grounded. The drains of the first and second field-effect transistors are connected to the sources of the third and fourth field-effect transistors respectively through the two limit switches. The drains of the first and second field-effect transistors are also connected to the first and second current sources respectively through the two current switches; the other ends of the first and second current sources are connected to the power supply voltage. The drains of the third and fourth field-effect transistors are respectively the negative and positive output terminals of the dynamic amplifier. The drains of the third and fourth field-effect transistors are respectively connected to the power supply voltage through the two reset switches. The gates of the third and fourth field-effect transistors are connected, and the output level at the gate connection point of the third and fourth field-effect transistors is the output common-mode level.

[0016] The first capacitor and the second capacitor are connected in series, and one end of the first capacitor is connected to the negative output terminal of the dynamic amplifier; one end of the second capacitor is connected to the positive output terminal of the dynamic amplifier; the other ends of the first capacitor and the second capacitor are both connected to the gate of the third field-effect transistor or the fourth field-effect transistor.

[0017] The positive input terminal of the second comparator is connected to the gate of the third or fourth field-effect transistor, and the negative input terminal of the second comparator is connected to the second common-mode input voltage; the output terminal of the second comparator is used to generate the clock signal for the two limit switches.

[0018] Optionally, the magnitude of the second common-mode input voltage is half of the power supply voltage.

[0019] Optionally, the capacitance of the first capacitor is equal to that of the second capacitor.

[0020] Optionally, the switched capacitor integrator further includes an external clock, which is used to generate clock signals for the first switch, the second switch, the third switch, the fourth switch, the two reset switches, and the three current switches.

[0021] Optionally, the modulator further includes a first input amplifier, a second input amplifier, and a third input amplifier;

[0022] The signal input terminal is connected to the first analog adder through the first input amplifier, the signal input terminal is connected to the second analog adder through the second input amplifier, and the signal input terminal is connected to the third analog adder through the third input amplifier.

[0023] Optionally, the modulator further includes a first feedback amplifier and a second feedback amplifier;

[0024] The input terminal of the first feedback amplifier is connected to the digital-to-analog converter, and the output terminal of the first feedback amplifier is connected to the first analog adder;

[0025] The input terminal of the second feedback amplifier is connected to the digital-to-analog converter, and the output terminal of the second feedback amplifier is connected to the second analog adder.

[0026] Optionally, the amplification factors of the first input amplifier and the first feedback amplifier are opposites of each other, and the amplification factors of the second input amplifier and the second feedback amplifier are opposites of each other.

[0027] Optionally, the modulator further includes a first output amplifier and a second output amplifier;

[0028] The input terminal of the first output amplifier is connected to the output terminal of the first analog integrator, and the output terminal of the first output amplifier is connected to the input terminal of the second analog adder.

[0029] The input terminal of the second output amplifier is connected to the output terminal of the second analog integrator, and the output terminal of the second output amplifier is connected to the third analog adder.

[0030] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0031] This invention provides a modulator for a high-precision, low-power analog-to-digital converter. By employing a switched-capacitor integrator based on a dynamic amplifier to implement the analog integrator, system power consumption can be effectively reduced. Furthermore, the switched-capacitor integrator in this invention incorporates a comparator module to ensure the common-mode output level of the dynamic amplifier reaches a set value, effectively enhancing the robustness of the dynamic amplifier and resulting in a high-precision, low-power modulator with high yield.

[0032] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0033] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0034] Figure 1 This is a circuit schematic diagram of a modulator applied to a high-precision, low-power analog-to-digital converter provided by an embodiment of the present invention;

[0035] Figure 2 This is a circuit schematic diagram of a switched capacitor integrator provided in an embodiment of the present invention;

[0036] Figure 3 This is a circuit schematic diagram of a dynamic amplifier provided in an embodiment of the present invention;

[0037] Figure 4 This is a switching timing diagram provided in an embodiment of the present invention. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings.

[0039] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this disclosure, when a layer / component is referred to as being "above" another layer / component, that layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Additionally, if a layer / component is "above" another layer / component in one orientation, then when the orientation is reversed, that layer / component may be "below" the other layer / component. In the context of this disclosure, similar or identical components may be denoted by the same or similar reference numerals.

[0041] To better understand the above technical solutions, the following will describe the above technical solutions in detail with reference to specific implementation methods. It should be understood that the embodiments of this disclosure and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0042] The Sigma-Delta modulator is a key module in the Sigma-Delta analog-to-digital converter (ADC), typically used for noise shaping of quantization noise to effectively improve the accuracy of the ADC. Traditional Sigma-Delta modulators are usually implemented by cascading multiple operational amplifier-based switched-capacitor integrators, which often result in high power consumption. While switched-capacitor integrator structures based on dynamic amplifiers can effectively reduce power consumption, the poor robustness of the dynamic amplifier limits its application in Sigma-Delta modulators. This invention provides a novel dynamic amplifier structure that effectively improves the robustness of the dynamic amplifier and applies it to a switched-capacitor integrator based on the dynamic amplifier, resulting in a high-precision, low-power Sigma-Delta modulator with high yield.

[0043] It should be noted that the modulators described in this invention are all Sigma-Delta modulators.

[0044] Figure 1 This is a circuit schematic diagram of a modulator applied to a high-precision, low-power analog-to-digital converter, provided by an embodiment of the present invention, as shown below. Figure 1 As shown, the modulator includes a signal input terminal IN, a signal output terminal OUT, a digital-to-analog converter 40, and a first analog adder 11, a first analog integrator 21, a second analog adder 12, a second analog integrator 22, a third analog adder 13, and a first comparator 50 connected in sequence for processing the signal.

[0045] The input terminal of the first analog adder 11 is connected to the signal input terminal IN, and the output terminal of the first comparator 50 is connected to the signal output terminal OUT. The signal output terminal OUT is also connected to the input terminal of the digital-to-analog converter 40, and the output terminal of the digital-to-analog converter 40 is connected to the first analog adder 11 and the second analog adder 12 respectively.

[0046] Both the first analog integrator 21 and the second analog integrator 22 are switched-capacitor integrators based on dynamic amplifiers, and the switched-capacitor integrators include a second comparator COMP for making the common-mode level of the output of the dynamic amplifier reach a set value.

[0047] Optional, such as Figure 1 As shown, the modulator also includes a first feedback amplifier 31 and a second feedback amplifier 32.

[0048] The input terminal of the first feedback amplifier 31 is connected to the digital-to-analog converter 40, and the output terminal of the first feedback amplifier 31 is connected to the first analog adder 11.

[0049] The input of the second feedback amplifier 32 is connected to the digital-to-analog converter 40, and the output of the second feedback amplifier 32 is connected to the second analog adder 12.

[0050] Optionally, the modulator also includes a first input amplifier 61, a second input amplifier 62, and a third input amplifier 63. The signal input terminal IN is connected to the first analog adder 11 through the first input amplifier 61, the signal input terminal IN is connected to the second analog adder 12 through the second input amplifier 62, and the signal input terminal IN is connected to the third analog adder 13 through the third input amplifier 63.

[0051] Optionally, the modulator also includes a first output amplifier 71 and a second output amplifier 72. The input of the first output amplifier 71 is connected to the output of the first analog integrator 21, and the output of the first output amplifier 71 is connected to the input of the second analog adder 12. The input of the second output amplifier 72 is connected to the output of the second analog integrator 22, and the output of the second output amplifier 72 is connected to the third analog adder 13.

[0052] After the signal enters the system from the signal input terminal IN, it is first amplified by three input amplifiers, and then transmitted to the first and second analog integrators and the comparator, respectively. Simultaneously, the digital signal output at the previous moment is converted into a corresponding analog signal by a digital-to-analog converter, amplified by two feedback amplifiers, and then fed back to the first and second analog integrators. In other words, the input signal and the output signal from the previous moment, after certain signal processing, are superimposed on the first and second analog adders, and then transmitted to the first and second analog integrators for integration. Specifically, the integration result of the first analog integrator is amplified by the first output amplifier and superimposed on the second analog adder. The integration result of the second analog integrator is amplified by the second output amplifier and superimposed on the third analog adder. Finally, the output signal is output from the signal output terminal OUT.

[0053] Optionally, the amplification factors of the first input amplifier 61 and the first feedback amplifier 31 are opposites of each other. The amplification factors of the second input amplifier 62 and the second feedback amplifier 32 are also opposites of each other.

[0054] From the perspective of the z-domain, the transfer function between the input and output of the signal when it passes through the analog integrator is:

[0055]

[0056] Therefore, by Figure 1 The signal transfer function (STF) of this system can be derived as follows:

[0057]

[0058] Where a1 represents the amplification factor of the first input amplifier 61, a2 represents the amplification factor of the second input amplifier 62, a3 represents the amplification factor of the third input amplifier 63, b1 represents the amplification factor of the first feedback amplifier 31, b2 represents the amplification factor of the second feedback amplifier 32, c1 represents the amplification factor of the first output amplifier 71, c2 represents the amplification factor of the second output amplifier 72, and z represents the input signal.

[0059] The system's noise transfer function (NTF) is as follows:

[0060]

[0061] By setting appropriate coefficients to make the STF close to 1 and the NTF close to 0, the high-precision, low-power Sigma-Delta modulator of this invention can produce excellent noise shaping effects.

[0062] Furthermore, assuming the input signal of the analog integrator is X1 and the quantization noise is Q, from Figure 1 We can obtain:

[0063] X1=a1·IN+b1·OUT=a1·IN+b1(STF·IN+NTF·Q)=(a1+b1STF)·IN-b1·NTF·Q

[0064] When a1 = -b1:

[0065] X1=a1(1-STF)·IN-b1·NTF·Q

[0066] Therefore, when STF is close to 1 and NTF is close to 0, we can make X1 close to 0 by setting the amplification factor a1 of the first input amplifier 61 and the amplification factor b1 of the first feedback amplifier 31 to opposite values. This effectively reduces the swing requirements of the input and output signals of the analog integrator, thereby reducing the design difficulty of the integrator. Similarly, setting the amplification factor a2 of the second input amplifier 62 and the amplification factor b2 of the second feedback amplifier 32 to opposite values ​​is also possible.

[0067] Figure 2 This is a circuit schematic diagram of a switched capacitor integrator provided in an embodiment of the present invention, such as... Figure 2 As shown, the switched capacitor integrator includes an integrator input terminal, an integrator output terminal, and a first sampling capacitor C. S1 Second sampling capacitor C S2 First integrating capacitor C I1 Second integrating capacitor C I2 First switch Φ1, second switch Φ 1d The third switch Φ2 and the fourth switch Φ 2d .

[0068] The integrator input terminals include the positive input signal terminal VIP and the negative input signal terminal VIN, and the integrator output terminals include the positive output signal terminal VOP and the negative output signal terminal VON.

[0069] First sampling capacitor C S1 One end is connected to the second switch Φ 1d The first sampling capacitor C is connected to the positive terminal VIP of the input signal. S1 The other end is connected to the negative input terminal of the dynamic amplifier D1 via the third switch Φ2. The first sampling capacitor C... S1 One end is also connected to the fourth switch Φ 2d The first sampling capacitor C is connected to the first common-mode input voltage VCM1. S1 The other end is also connected to the second common-mode input voltage VCM2 via the first switch Φ1.

[0070] Second sampling capacitor C S2 One end is connected to the second switch Φ 1d The second sampling capacitor C is connected to the negative terminal VIN of the input signal. S2 The other end is connected to the non-inverting input of the dynamic amplifier D1 via the third switch Φ2. The second sampling capacitor C... S2 One end is also connected to the fourth switch Φ 2d The second sampling capacitor C is connected to the first common-mode input voltage VCM1. S2 The other end is also connected to the second common-mode input voltage VCM2 via the first switch Φ1.

[0071] The positive output terminal of dynamic amplifier D1 is connected to the positive output signal terminal VOP, and the negative output terminal of dynamic amplifier D1 is connected to the negative output signal terminal VON.

[0072] First integrating capacitor C I1 It is connected between the negative input terminal and the positive output signal terminal VOP of the dynamic amplifier D1. The second integrating capacitor C I2 It is connected between the positive input terminal and the negative output signal terminal VON of the dynamic amplifier D1.

[0073] The working principle of the switched capacitor integrator based on a dynamic amplifier in this invention is as follows:

[0074] The entire operation of the switched capacitor integrator can be divided into a sampling phase and an integration phase, controlled by a set of two non-overlapping clocks. Control, wherein the sampling phase is controlled by Control, integral phase Control, the corresponding phase controls the corresponding switch. Lagging behind This can effectively reduce the impact of non-ideal switching factors on system linearity. Similarly, Lagging behind During sampling, the input signal is stored in the sampling capacitor C. S1 and C S2 The output signal from the previous moment is stored in the integrating capacitor C. I1 and C I2 During the integration phase, the high small-signal low-frequency gain of the dynamic amplifier D1 causes the sampling capacitor C to... S1 and C S2 The charge on the capacitor is transferred to the integrating capacitor C. I1 and C I2 Go up and complete the points function.

[0075] Figure 3 This is a circuit schematic diagram of a dynamic amplifier provided in an embodiment of the present invention, such as... Figure 3 As shown, the dynamic amplifier D1 includes a second comparator COMP, a first field-effect transistor M1, a second field-effect transistor M2, and a third field-effect transistor M... C1 The fourth field-effect transistor M C2 First current source I1, second current source I2, third current source I3, first capacitor C1, second capacitor C2, and two reset switches Φ rst Two limit switches Φ XC and three current switches Φ EN .

[0076] The gates of the first field-effect transistor M1 and the second field-effect transistor M2 are the positive and negative input terminals of the dynamic amplifier D1, respectively. The sources of the first field-effect transistor M1 and the second field-effect transistor M2 are connected and connected by a current switch Φ. EN One end of the first field-effect transistor M1 is connected to the third current source I3; the other end of the third current source I3 is grounded. The drains of the first field-effect transistor M1 and the second field-effect transistor M2 are connected to two limit switches Φ. XC Respectively with the third field-effect transistor M C1 and the fourth field-effect transistor M C2 The source connection of the first field-effect transistor M1 and the drain of the second field-effect transistor M2 are also connected through two current switches Φ. EN It is connected to the first current source I1 and the second current source I2 respectively; the other end of the first current source I1 and the second current source I2 are connected to the power supply voltage VDD. The third field-effect transistor M C1 and the fourth field-effect transistor M C2 The drains of the transistors are the negative and positive output terminals of the dynamic amplifier D1, respectively, and the third field-effect transistor M... C1 and the fourth field-effect transistor M C2 The drains are respectively connected to two reset switches Φ rst Connected to the power supply voltage VDD. Third field-effect transistor M C1 and the fourth field-effect transistor MC2 The gate is connected. The third field-effect transistor M... C1 and the fourth field-effect transistor M C2 The level output from the gate connection point is the output common-mode level X.

[0077] The first capacitor C1 and the second capacitor C2 are connected in series, with one end of the first capacitor C1 connected to the negative output terminal of the dynamic amplifier D1. One end of the second capacitor C2 is connected to the positive output terminal of the dynamic amplifier D1. The other ends of both the first capacitor C1 and the second capacitor C2 are connected to the third field-effect transistor M. C1 Or the fourth field-effect transistor M C2 The gate connection.

[0078] The non-inverting input of the second comparator COMP and the third field-effect transistor M C1 Or the fourth field-effect transistor M C2 The gate of the first comparator is connected, and the negative inverting input of the second comparator COMP is connected to the second common-mode input voltage VCM2. The output of the second comparator COMP is used to generate two limit switches Φ. XC The clock signal.

[0079] For example, the second comparator COMP can be implemented using an open-loop two-stage operational amplifier to make the output common-mode level of the dynamic amplifier reach a set value, thereby improving chip yield.

[0080] In this embodiment of the invention, four NMOS field-effect transistors (M1, M2, M...) are used. C1 and M C2 A cascode (cas-source, cas-gate) structure is used to achieve a higher DC voltage gain. In this design, a gain of approximately 50dB is achieved. However, the gain of the dynamic amplifier D1 requires a relatively long settling time. This settling time is related to the circuit's time constant. But increasing the gain of a cascode structure essentially increases the output resistance, which increases the circuit's time constant, potentially preventing the gain from setting within the defined phase time. Therefore, a first current source I1 and a second current source I2 are added. By increasing the current in the input branch, they effectively improve the circuit's settling speed. Furthermore, this structure does not affect the output branch's discharge current, nor does it affect the common-mode setup process; that is, it accelerates differential-mode setup without affecting common-mode setup. A third current source I3 is used to provide bias current to the dynamic amplifier D1, thereby determining the circuit's quiescent operating point.

[0081] The working principle of the dynamic amplifier D1 in this embodiment of the invention is as follows:

[0082] To achieve low power consumption, the dynamic amplifier D1 operates periodically according to the phase. It further subdivides the integrating phase of the switched-capacitor integrator into a reset phase and an amplification phase. During the reset phase, the reset switch Φ...rst When the circuit is closed and the other switches are open, the circuit is in a reset state, and the voltages at the positive and negative output terminals will be charged to VDD. During the amplification phase, the reset switch Φ... rst With the switch open and the other switches closed, the circuit will discharge to varying degrees on both sides according to the input voltage, and the discharge rate will be positively correlated with the input voltage. At this time, the output common-mode level X will continuously decrease, and the low-frequency small-signal gain of the circuit will begin to build up until the limit switch Φ... XC When disconnected, both common-mode and differential-mode outputs are established, and the circuit stops working. Due to the different discharge rates of the two branches, a voltage difference will appear at the circuit output, achieving the amplification function.

[0083] Optionally, the second common-mode input voltage VCM2 can be half the power supply voltage VDD, which maximizes the output signal swing of the dynamic amplifier. For the same reason, the first common-mode input voltage VCM1 can also be set to half the power supply voltage VDD.

[0084] Optionally, the capacitances of the first capacitor C1 and the second capacitor C2 are equal, thereby realizing the common-mode detection function.

[0085] The output common-mode level X can be used to power the third field-effect transistor M. C1 and the fourth field-effect transistor M C2 Provides a dynamic gate bias voltage to prevent voltage fluctuations at the output terminal during the amplification phase from affecting the third field-effect transistor M. C1 and the fourth field-effect transistor M C2 Entering the linear region affects the linearity of the system. For the same reason, the third field-effect transistor M... C1 and the fourth field-effect transistor M C2 Transistors with low threshold voltages are typically used.

[0086] The output common-mode level X is connected to the positive input of the second comparator COMP, and the negative input of the second comparator COMP is connected to the second common-mode input voltage VCM2. During amplification, the second comparator COMP continuously compares the output common-mode level X with the second common-mode input voltage VCM2. When the voltage value of the output common-mode level X is greater than the voltage value of the second common-mode input voltage VCM2, the limit switch Φ... XC The switch is on, and the circuit operates normally. When the output common-mode voltage X drops below the second common-mode input voltage VCM2, the limit switch Φ... XC When the switch is open, the output common-mode level X will stabilize near the second common-mode input voltage VCM2, thereby effectively enhancing the robustness of the dynamic amplifier and improving chip yield.

[0087] In other words, in this embodiment of the invention, the second comparator COMP can make the output common-mode level of the dynamic amplifier D1 reach a set value, which can be the voltage value of the second common-mode input voltage VCM2.

[0088] Optionally, the switched capacitor integrator also includes an external clock, which is used to generate the first switch Φ1 and the second switch Φ 1d Third switch Φ2, fourth switch Φ 2d and two reset switches Φ rst and three current switches Φ EN The clock signal.

[0089] Figure 4 This is a switching timing diagram provided in an embodiment of the present disclosure, such as... Figure 4 As shown in the embodiment of this disclosure, the current switch Φ EN The clock signal continuously operates at the reset switch Φ rst After the clock signal, the current switch Φ EN clock signal and reset switch Φ rst The total working range of the clock signal is related to the third switch Φ2 and the fourth switch Φ 2d The clock signals operate within the same timeframe. This ensures that the sampling capacitor and integrating capacitor do not experience large transient voltage drops at the output node due to charge sharing when they are switched on.

[0090] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0091] This invention provides a modulator for a high-precision, low-power analog-to-digital converter. By employing a switched-capacitor integrator based on a dynamic amplifier to implement the analog integrator, system power consumption can be effectively reduced. Furthermore, the switched-capacitor integrator in this invention incorporates a comparator module, ensuring the common-mode output level of the dynamic amplifier reaches a set value, effectively enhancing the robustness of the dynamic amplifier and resulting in a high-precision, low-power modulator with high yield.

[0092] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0093] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0094] It should be noted that the above embodiments are illustrative of the invention and not restrictive of the invention, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A modulator for use in a high-precision, low-power analog-to-digital converter, characterized in that, It includes a signal input terminal (IN), a signal output terminal (OUT), a digital-to-analog converter (40), and a first analog adder (11), a first analog integrator (21), a second analog adder (12), a second analog integrator (22), a third analog adder (13), and a first comparator (50) connected in sequence for processing the signal. The input terminal of the first analog adder (11) is connected to the signal input terminal (IN), and the output terminal of the first comparator (50) is connected to the signal output terminal (OUT); the signal output terminal (OUT) is also connected to the input terminal of the digital-to-analog converter (40), and the output terminal of the digital-to-analog converter (40) is connected to the first analog adder (11) and the second analog adder (12) respectively; The first analog integrator (21) and the second analog integrator (22) are both switched-capacitor integrators based on a dynamic amplifier (D1), and the switched-capacitor integrator includes a second comparator (COMP) for making the output common-mode level of the dynamic amplifier (D1) reach a set value. The dynamic amplifier (D1) includes a second comparator (COMP), a first field-effect transistor (M1), a second field-effect transistor (M2), and a third field-effect transistor (M3). C1 ), the fourth field-effect transistor (M) C2 ), First current source (I1), Second current source (I2), Third current source (I3), First capacitor (C1), Second capacitor (C2), Two reset switches (Φ rst Two limit switches (Φ) XC ) and three current switches (Φ EN ); The gates of the first field-effect transistor (M1) and the second field-effect transistor (M2) are respectively the positive and negative input terminals of the dynamic amplifier (D1). The sources of the first field-effect transistor (M1) and the second field-effect transistor (M2) are connected and connected through the current switch (Φ). EN The first field-effect transistor (M1) is connected to one end of the third current source (I3); the other end of the third current source (I3) is grounded; the drains of the first field-effect transistor (M1) and the second field-effect transistor (M2) are connected to the two limit switches (Φ). XC ) respectively with the third field-effect transistor (M) C1 ) and the fourth field-effect transistor (M C2 The source terminals of the first field-effect transistor (M1) and the drain terminals of the second field-effect transistor (M2) are connected through two current switches (Φ). EN The first current source (I1) and the second current source (I2) are connected to each other respectively; the other end of the first current source (I1) and the second current source (I2) are connected to the power supply voltage (VDD); the third field-effect transistor (M) is connected to the first current source (I1) and the second current source (I2) respectively. C1 ) and the fourth field-effect transistor (M C2 The drains of the three transistors are respectively the negative and positive output terminals of the dynamic amplifier (D1); and the third field-effect transistor (M) C1 ) and the fourth field-effect transistor (M C2 The drains of the two terminals are respectively connected to the two reset switches (Φ). rst The third field-effect transistor (M) is connected to the power supply voltage (VDD); C1 ) and the fourth field-effect transistor (M C2 The gate of the third field-effect transistor (M) is connected to the gate of the third field-effect transistor (M). C1 ) and the fourth field-effect transistor (M C2 The level output from the gate connection point of the gate is the output common-mode level; The first capacitor (C1) and the second capacitor (C2) are connected in series, with one end of the first capacitor (C1) connected to the negative output terminal of the dynamic amplifier (D1); one end of the second capacitor (C2) is connected to the positive output terminal of the dynamic amplifier (D1); the other ends of both the first capacitor (C1) and the second capacitor (C2) are connected to the third field-effect transistor (M). C1 ) or the fourth field-effect transistor (M C2 The gate connection of ); The non-inverting input of the second comparator (COMP) is connected to the third field-effect transistor (M). C1 ) or the fourth field-effect transistor (M C2 The gate of the second comparator (COMP) is connected to the gate of the first comparator (COMP), and the negative input of the second comparator (COMP) is connected to the second common-mode input voltage (VCM2); the output of the second comparator (COMP) is used to generate the two limit switches (Φ). XC The clock signal of ) so that the two limit switches (Φ) XC The common-mode voltage can be closed or opened to make the output common-mode level reach a set value, which is the voltage value of the second common-mode input voltage (VCM2).

2. The modulator according to claim 1, characterized in that, The switched capacitor integrator includes an integrator input terminal, an integrator output terminal, and a first sampling capacitor (C). S1 ), second sampling capacitor (C) S2 ), first integrating capacitor (C) I1 ), second integrating capacitor (C) I2 ), First switch (Φ1), Second switch (Φ 1d ), third switch (Φ2), fourth switch (Φ 2d ) and the dynamic amplifier (D1); The integrator input terminal includes a positive input signal terminal (VIP) and a negative input signal terminal (VIN), and the integrator output terminal includes a positive output signal terminal (VOP) and a negative output signal terminal (VON). The first sampling capacitor (C) S1 One end of ) is connected to the second switch (Φ) 1d The first sampling capacitor (C) is connected to the positive terminal (VIP) of the input signal. S1 The other end of the first sampling capacitor (C) is connected to the negative input terminal of the dynamic amplifier (D1) via the third switch (Φ2); S1 One end of the switch is also connected to the fourth switch (Φ). 2d The first sampling capacitor (C) is connected to the first common-mode input voltage (VCM1). S1 The other end of the circuit is also connected to the second common-mode input voltage (VCM2) via the first switch (Φ1); The second sampling capacitor (C) S2 One end of ) is connected to the second switch (Φ) 1d The second sampling capacitor (C) is connected to the negative terminal (VIN) of the input signal. S2 The other end of the second sampling capacitor (C) is connected to the non-inverting input of the dynamic amplifier (D1) via the third switch (Φ2); S2 One end of the switch is also connected to the fourth switch (Φ). 2d The second sampling capacitor (C) is connected to the first common-mode input voltage (VCM1). S2 The other end of the circuit is also connected to the second common-mode input voltage (VCM2) via the first switch (Φ1); The positive output terminal of the dynamic amplifier (D1) is connected to the positive output terminal (VOP), and the negative output terminal of the dynamic amplifier (D1) is connected to the negative output terminal (VON). The first integrating capacitor (C) I1 The second integrating capacitor (C) is connected between the negative input terminal of the dynamic amplifier (D1) and the positive output signal terminal (VOP); I2 It is connected between the positive input terminal of the dynamic amplifier (D1) and the negative terminal of the output signal (VON).

3. The modulator according to claim 1, characterized in that, The voltage of the second common-mode input voltage (VCM2) is half of the power supply voltage (VDD).

4. The modulator according to claim 1, characterized in that, The capacitance of the first capacitor (C1) is equal to that of the second capacitor (C2).

5. The modulator according to claim 2, characterized in that, The switched capacitor integrator also includes an external clock, which is used to generate the first switch (Φ1) and the second switch (Φ). 1d The third switch (Φ2), the fourth switch (Φ) 2d ), and the two reset switches (Φ rst ) and the three current switches (Φ EN The clock signal.

6. The modulator according to any one of claims 1 to 5, characterized in that, The modulator also includes a first input amplifier (61), a second input amplifier (62), and a third input amplifier (63). The signal input terminal (IN) is connected to the first analog adder (11) through the first input amplifier (61), the signal input terminal (IN) is connected to the second analog adder (12) through the second input amplifier (62), and the signal input terminal (IN) is connected to the third analog adder (13) through the third input amplifier (63).

7. The modulator according to claim 6, characterized in that, The modulator also includes a first feedback amplifier (31) and a second feedback amplifier (32); The input terminal of the first feedback amplifier (31) is connected to the digital-to-analog converter (40), and the output terminal of the first feedback amplifier (31) is connected to the first analog adder (11). The input terminal of the second feedback amplifier (32) is connected to the digital-to-analog converter (40), and the output terminal of the second feedback amplifier (32) is connected to the second analog adder (12).

8. The modulator according to claim 7, characterized in that, The amplification factors of the first input amplifier (61) and the first feedback amplifier (31) are opposites of each other, and the amplification factors of the second input amplifier (62) and the second feedback amplifier (32) are opposites of each other.

9. The modulator according to any one of claims 1 to 5, characterized in that, The modulator also includes a first output amplifier (71) and a second output amplifier (72). The input terminal of the first output amplifier (71) is connected to the output terminal of the first analog integrator (21), and the output terminal of the first output amplifier (71) is connected to the input terminal of the second analog adder (12). The input terminal of the second output amplifier (72) is connected to the output terminal of the second analog integrator (22), and the output terminal of the second output amplifier (72) is connected to the third analog adder (13).

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