Method for forming sidewall in fork structure and semiconductor device with fork structure

Abstract

A method for forming sidewalls in a fork structure, comprising: providing a substrate (201); forming an overlapping layer (202) on the substrate (201) with a first material (2021) and a second material (2022) stacked in sequence; forming a first mask layer (203) on the overlapping layer (202); forming a first trench (205) in the first mask layer (203); forming a second trench in the first trench (205) by forming a second mask layer (206) on the first mask layer (203) and within the first trench (205); etching the second mask layer (206) in an anisotropic etching manner along a direction perpendicular to the substrate (201) until the second mask layer (206) located between the sidewalls of the second trench and on the lower surface of the first trench (205) is removed to form a third trench (207) based on the second trench; using the second mask layer (206) as a protective layer, etching downward from the lower surface of the third trench (207) to form a fourth trench that penetrates the overlapping layer (202) and extends into the substrate (201); forming sidewalls (208) in the fourth trench. The method reduces the requirements for lithography accuracy and lithography capabilities during the formation of the sidewalls (208).

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for forming sidewalls in a fork structure and a semiconductor device with a fork structure. Background Art

[0002] With the continuous evolution of integrated circuit processes, new processes and new structures are constantly proposed. In 2019, IMEC proposed the forksheet structure, which is considered a potential direction for the next-generation advanced process because it can effectively reduce the distance between NMOS (N-Metal-Oxide-Semiconductor) and PMOS (P-Metal-Oxide-Semiconductor), thereby reducing the area of standard cells.

[0003] The existing forksheet structure includes: sidewalls, NMOS and PMOS located on both sides of the sidewalls. Since the width of the sidewalls is small, the distance between NMOS and PMOS is reduced. The current principle for forming sidewalls is: first, form an overlap layer, form trenches in the overlap layer through lithography, and fill the trenches to form sidewalls.

[0004] Since the sidewalls are formed by filling trenches, and the width of the trenches is determined by lithography, the width of the sidewalls is also determined by lithography. Also, because the width of the sidewalls is relatively small, the above method for forming sidewalls has high requirements for lithography accuracy and lithography capabilities. Summary of the Invention

[0005] The present application provides a method for forming sidewalls in a fork structure and a semiconductor device with a fork structure, which are used to solve the problem that the method for forming sidewalls has high requirements for lithography accuracy and lithography capabilities.

[0006] In a first aspect, a method for forming sidewalls in a fork structure according to the present application includes: providing a substrate; forming an overlap layer in which a first material and a second material are stacked in sequence on the substrate; forming a first mask layer on the overlap layer; forming a first trench in the first mask layer; forming a second trench in the first trench by forming a second mask layer on the first mask layer and in the first trench; etching the second mask layer in an anisotropic etching manner along a direction perpendicular to the substrate until the second mask layer located between the sidewalls of the second trench and on the lower surface of the first trench is removed, so as to form a third trench based on the second trench; using the second mask layer as a protection layer, etching downward from the lower surface of the third trench to form a fourth trench that penetrates the overlap layer and extends into the substrate; and forming sidewalls in the fourth trench.

[0007] Since sidewalls are formed in the fourth trench, the width of the sidewalls is determined by the width of the fourth trench. The fourth trench is formed by forming a first trench in a first mask layer, forming a second trench in the first trench by forming a second mask layer in the first trench, and anisotropically etching to remove the second mask layer located between the sidewalls of the second trench and on the lower surface of the first trench along the direction perpendicular to the substrate to obtain a third trench. Then, under the protection of the second mask layer, etching is performed downward from the lower surface of the third trench to form a fourth trench that penetrates the overlapping layer and extends into the substrate. That is, in the process of forming the fourth trench, lithography is only used in the process of forming the first trench. Since the fourth trench is formed within the first trench, the width of the first trench is greater than the width of the fourth trench, that is, the width of the first trench is relatively large. In this way, in the process of forming the first trench, the requirements for lithography accuracy and lithography ability are reduced, and then in the process of forming the sidewalls, the requirements for lithography accuracy and lithography ability are reduced.

[0008] In a possible implementation manner, the method further includes: forming a first overlapping structure and a second overlapping structure on both sides of the sidewall. Among them, the first overlapping structure, the second overlapping structure, and the sidewall are covered with a first dielectric layer and a second dielectric layer. One end of the first dielectric layer is flush with one end of the first overlapping structure and the second overlapping structure, one end of the second dielectric layer is flush with the other end of the first overlapping structure and the second overlapping structure, and the other end of the first dielectric layer is separated from the other end of the second dielectric layer by a preset distance; removing a first target material in the first overlapping structure covered by the first dielectric layer and the second dielectric layer, and removing a second target material in the second overlapping structure covered by the first dielectric layer and the second dielectric layer; forming a third dielectric layer in the area where the first target material is removed to obtain a third overlapping structure; forming a fourth dielectric layer in the area where the second target material is removed to obtain a fourth overlapping structure; forming a first doping structure at both ends of the third overlapping structure, and forming a second doping structure at both ends of the fourth overlapping structure; removing the first target material in the third overlapping structure to form a plurality of first channel layers; removing the second target material in the fourth overlapping structure to form a plurality of second channel layers; where the first target material is the material among the first material and the second material that is not used to form the first channel layer; the second target material is the material among the first material and the second material that is not used to form the second channel layer, and the doping types of the first doping structure and the second doping structure are opposite.

[0009] In a possible implementation, the method further includes: forming a first gate insulating layer on the first channel layer, and forming a second gate insulating layer on the second channel layer; forming a first gate conductive layer on the first gate insulating layer, and forming a second gate conductive layer on the second gate insulating layer.

[0010] In a possible implementation, the first gate insulating layer and the second gate insulating layer are made of the same material, and the first gate conductive layer and the second gate conductive layer are made of the same material; or the first gate conductive layer and the second gate conductive layer are made of the same material.

[0011] In a possible implementation, the method further includes: removing the sidewall located between the first dielectric layer and the second dielectric layer; forming a gate insulating layer on the first channel layer and the second channel layer; forming a gate conductive layer on the gate insulating layer.

[0012] In a possible implementation, forming the first overlapping structure and the second overlapping structure on both sides of the sidewall includes: forming a fifth overlapping structure and a sixth overlapping structure on both sides of the sidewall by removing the mask layer to be removed and the overlapping layer located below the mask layer to be removed, where the mask layer to be removed is the first mask layer located outside the sidewall of the first trench; forming a dummy gate structure covering the fifth overlapping structure, the sixth overlapping structure and the sidewall, where the length of the dummy gate structure is equal to the preset distance; forming the first dielectric layer and the second dielectric layer at both ends of the dummy gate structure; removing the region of the fifth overlapping structure that is not covered by the dummy gate structure, the first dielectric layer and the second dielectric layer to obtain the first overlapping structure; removing the region of the sixth overlapping structure that is not covered by the dummy gate structure, the first dielectric layer and the second dielectric layer to obtain the second overlapping structure.

[0013] In a possible implementation, before forming the plurality of first channel layers and the plurality of second channel layers, it further includes: removing the dummy gate structure.

[0014] In a possible implementation, the method further includes: forming a fifth dielectric layer on the substrate, and the plurality of first channel layers, the plurality of second channel layers, the first doping structure and the second doping structure are located on the fifth dielectric layer.

[0015] In a possible implementation, the first channel layer and the second channel layer are made of different materials.

[0016] In a possible implementation, the first doping structure is P-type doping, the second doping structure is N-type doping, the material of the first channel layer is silicon germanium, and the material of the second channel layer is silicon.

[0017] In a second aspect, the present application provides a semiconductor device with a fork structure, including: a substrate; sidewalls vertically disposed on the substrate; a plurality of first channel layers sequentially and spaced apart along a direction perpendicular to the substrate on one side surface of the sidewalls, the first channel layers extending along the side surface of the sidewalls; a plurality of second channel layers sequentially and spaced apart along a direction perpendicular to the substrate on the other side surface of the sidewalls, the second channel layers extending along the side surface of the sidewalls; first doping structures disposed at both ends of the plurality of first channel layers, second doping structures disposed at both ends of the plurality of second channel layers, the doping type of the first doping structures being opposite to the doping type of the second doping structures; a first dielectric layer covering one end of the first surfaces of the plurality of first channel layers and one end of the first surfaces of the plurality of second channel layers, a second dielectric layer covering the other end of the first surfaces of the plurality of first channel layers and the other end of the first surfaces of the plurality of second channel layers, wherein the first surfaces of the plurality of first channel layers are the surfaces of the plurality of first channel layers that are away from the sidewalls, and the first surfaces of the plurality of second channel layers are the surfaces of the plurality of second channel layers that are away from the sidewalls; third dielectric layers disposed at both ends of the second surfaces of the plurality of first channel layers, fourth dielectric layers disposed at both ends of the second surfaces of the plurality of second channel layers, wherein the second surfaces of the plurality of first channel layers are the surfaces of the plurality of first channel layers that are adjacent to their first surfaces and parallel to the substrate, and the second surfaces of the plurality of second channel layers are the surfaces of the plurality of second channel layers that are adjacent to their first surfaces and parallel to the substrate; a first gate insulating layer and a first gate conductive layer sequentially disposed on the first channel layers, a second gate insulating layer and a second gate conductive layer sequentially disposed on the second channel layers.

[0018] In a possible implementation manner, the semiconductor device further includes: a fifth dielectric layer located on the substrate, and the plurality of first channel layers, the plurality of second channel layers, the first doping structures, and the second doping structures are located on the fifth dielectric layer.

[0019] In a possible implementation manner, the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same; or the materials of the first gate conductive layer and the second gate conductive layer are the same.

[0020] In a possible implementation, the sidewall between the first dielectric layer and the second dielectric layer is removed; a first gate insulating layer and a first gate conductive layer are sequentially disposed on a surface of the first channel layer in contact with the removed sidewall; a second gate insulating layer and a second gate conductive layer are sequentially disposed on a surface of the second channel layer in contact with the removed sidewall; the first gate insulating layer and the second gate insulating layer are made of the same material, and the first gate conductive layer and the second gate conductive layer are made of the same material.

[0021] In a possible implementation, the first channel layer and the second channel layer are made of different materials.

[0022] In a possible implementation, the first doping structure is P-type doping, the second doping structure is N-type doping, the material of the first channel layer is silicon germanium, and the material of the second channel layer is silicon. Description of the Drawings

[0023] Figure 1 Schematic flowchart of forming a sidewall provided by an embodiment of the present application;

[0024] Figure 2 Schematic structural diagram after forming a substrate, an overlapping layer, and a first mask layer provided by an embodiment of the present application;

[0025] Figure 3 Schematic structural diagram after forming a first trench provided by an embodiment of the present application;

[0026] Figure 4 Schematic structural diagram after forming a third trench provided by an embodiment of the present application;

[0027] Figure 5 Schematic structural diagram after forming a sidewall provided by an embodiment of the present application;

[0028] Figure 6 Schematic flowchart of the first process provided by an embodiment of the present application;

[0029] Figure 7 Schematic structural diagram after forming a fifth overlapping structure and a sixth overlapping structure provided by an embodiment of the present application;

[0030] Figure 8 Schematic structural diagram after forming a gap provided by an embodiment of the present application;

[0031] Figure 9 Schematic structural diagram after forming a dummy gate structure provided by an embodiment of the present application;

[0032] Figure 10 Schematic structural diagram after forming a first overlapping structure and a second overlapping structure provided by an embodiment of the present application;

[0033] Figure 11 Schematic diagram of the structure after forming the first doping structure and the second doping structure provided by the embodiment of the present application;

[0034] Figure 12 is Figure 11 Cross-sectional view along the a-a' direction;

[0035] Figure 13 Schematic diagram of the structure after forming the first channel layer and the second channel layer provided by the embodiment of the present application;

[0036] Figure 14 Schematic diagram of the structure after forming the first gate insulating layer, the second gate insulating layer, the first gate conductive layer and the second gate conductive layer provided by the embodiment of the present application;

[0037] Figure 15 Schematic diagram of the structure after forming the electrode structure and the isolation layer provided by the embodiment of the present application;

[0038] Figure 16 Energy band diagram of the first field effect transistor and the second field effect transistor;

[0039] Figure 17 Schematic diagram of the structure after removing the sidewall between the first dielectric layer and the second dielectric layer provided by the embodiment of the present application;

[0040] Figure 18 Schematic diagram of the structure after forming the gate insulating layer and the gate conductive layer provided by the embodiment of the present application;

[0041] Figure 19 Schematic diagram of the structure after forming the fifth dielectric layer, the electrode structure and the isolation layer provided by the embodiment of the present application. Detailed implementation manners

[0042] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0043] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0044] In the embodiments of the specification, claims, and drawings of this application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0045] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: only A exists, only B exists, and both A and B exist simultaneously. Here, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0046] To solve the above technical problems, this application provides a method for forming sidewalls in a fork structure. Figure 1 As shown in the flowchart of forming sidewalls provided by the embodiments of this application, Figure 1 as shown, the method includes:

[0047] 101. Provide a substrate.

[0048] 102. Form an overlapping layer in which a first material and a second material are stacked in sequence on the substrate, and the first material is different from the second material.

[0049] 103. Form a first mask layer on the overlapping layer.

[0050] Referring to Figure 2 as shown, in a possible implementation, the material of the substrate 201 is silicon, the first material 2021 is silicon germanium, the second material 2022 is silicon, the overlapping layer 202 is formed by overlapping silicon germanium and silicon in sequence, and the first mask layer 203 is composed of an oxide layer (oxide) 2031, a polysilicon (a-Si) layer 2032, and a silicon nitride (SiN) layer 2033 stacked in sequence. It should be noted that in Figure 2In [description], a layer of developed photoresist 204 is covered on the silicon nitride (SiN) layer 2033. The manufacturing process of the developed photoresist 204 will be described below and will not be elaborated here.

[0051] In other possible implementation manners, the material of the substrate 201 can also be a semiconductor material such as germanium, and the first material 2021 and the second material 2022 can also be semiconductor materials such as germanium, semiconductor compounds (i.e., semiconductor compounds of group IV elements, semiconductor compounds of group III-V elements), etc. The number of layers included in the overlapping layer 202 can also be determined according to design requirements. The first mask layer 203 can also include more layers or fewer layers, and no special limitation is made here. The material of the first mask layer 203 can also be other materials that can be used as a mask layer in semiconductor manufacturing processes, and no special limitation is made here.

[0052] 104. Form a first trench in the first mask layer.

[0053] Reference Figure 3 As shown, in a possible implementation manner, the first trench 205 vertically penetrates through the polysilicon (a-Si) layer 2032 and the silicon nitride (SiN) layer 2033 in the first mask layer 203, that is, the first trench 205 does not completely penetrate the first mask layer 203. The process of forming the first trench 205 can be: coating photoresist on the first mask layer 203, exposing and developing the photoresist to remove the photoresist at the position on the first mask layer 203 for forming the first trench 205, and obtaining Figure 2 the developed photoresist 204 in [description], as Figure 2 shown, the area where the photoresist is removed is used to form the first trench 205; next, under the protection of the developed photoresist 204, the first mask layer 203 is etched downward in an anisotropic etching manner to form the first trench 205. The etching depth is the sum of the thicknesses of the polysilicon (a-Si) layer 2032 and the silicon nitride (SiN) layer 2033 in the first mask layer 203. It should be noted that the above process of forming the first trench 205 is only exemplary and does not limit this application.

[0054] In other possible implementation manners, the first trench 205 can also vertically and completely penetrate the first mask layer 203, and the first trench 205 can also vertically penetrate through the polysilicon (a-Si) layer 2032, the silicon nitride (SiN) layer 2033, and a part of the oxide layer 2031.

[0055] It should be noted that after the first trench 205 is formed, the photoresist 204 on the first mask layer 203 is removed. In the embodiment of the present application, the width of the first trench 205 is C, which is determined according to the width of the sidewall and the widths of the first channel layer and the second channel layer formed on both sides of the sidewall. The sidewall, the first channel layer, and the second channel layer will be described below.

[0056] 105. By forming a second mask layer on the first mask layer and in the first trench, a second trench is formed in the first trench.

[0057] The material of the second mask layer can be, for example, an oxide or silicon nitride, etc., and this is not specifically limited. The material of the second mask layer can be the same as or different from the material of the first mask layer, and this is not specifically limited here. It should be noted that in the case where the first mask layer is composed of multiple materials, the material of the second mask layer can be the same as one of the multiple materials constituting the first mask layer, or different from the multiple materials constituting the first mask layer.

[0058] The process of forming the second mask layer can be: forming the second mask layer on the surface of the structure after the first trench is formed by deposition, that is, forming the second mask layer on the first mask layer and in the first trench (i.e., on the sidewall and the lower surface of the first trench). Since there is a height difference between the lower surface of the first trench and the upper surface of the first mask layer, therefore, a second trench can be formed in the first trench by forming the second mask layer.

[0059] 106. Use an anisotropic etching method to etch the second mask layer along the direction perpendicular to the substrate until the second mask layer located between the sidewalls of the second trench and on the lower surface of the first trench is removed, so as to form a third trench based on the second trench.

[0060] During the above etching process, a part of the second mask layer on the first mask layer will also be consumed.

[0061] Refer to Figure 4 As shown, in a possible implementation, the third trench 207 uses the second mask layer 206 as its sidewall, and the lower surface of the third trench 207 is flush with the lower surface of the first trench 205, that is, the lower surface of the third trench 207 is flush with the upper surface of the oxide 2031 in the first mask layer 203. And in Figure 4 the material of the second mask layer 206 is silicon nitride.

[0062] 107. Using the second mask layer as a protective layer, etch downward from the lower surface of the third trench to form a fourth trench that penetrates the overlapping layer and extends into the substrate.

[0063] In this process, an anisotropic etching method is adopted, and with the second mask layer as the protective layer, etching is carried out downward from the lower surface of the third trench to form a fourth trench that penetrates the overlapping layer and extends into the substrate. It should be noted that the fourth trench may not completely penetrate the substrate or may completely penetrate the substrate, and no special limitation is made here.

[0064] 108. A sidewall is formed in the fourth trench.

[0065] Specifically, the fourth trench is filled to form a sidewall. The material of the sidewall can be, for example, an insulating material such as an oxide or SiN. The material of the sidewall can be the same as or different from the material of the second mask layer.

[0066] See Figure 5 As shown, in a possible implementation, the material of the sidewall 208 is the same as the material of the second mask layer 206, that is, the material of the sidewall 208 is silicon nitride. It should be noted that in Figure 5 , after the sidewall is formed, the silicon nitride on the polysilicon layer 2032 is removed.

[0067] Obviously, by controlling the thickness of the second mask layer (i.e., the thickness of the second mask layer on the sidewall of the first trench (i.e., Figure 4 B in it)), the width of the fourth trench is controlled, thereby realizing the control of the width of the sidewall, and achieving self-alignment during the formation of the sidewall, reducing the dependence on the lithography process, and lowering the requirements for lithography accuracy and lithography ability. In addition, by the above method, the size of the sidewall can be further reduced, and thus the size of the semiconductor device can be further reduced.

[0068] As can be seen from the above, since a sidewall is formed in the fourth trench, the width of the sidewall is determined by the width of the fourth trench. The formation principle of the fourth trench is to form a first trench in the first mask layer, and to form a second trench in the first trench by forming a second mask layer in the first trench, and to remove the second mask layer located between the sidewalls of the second trench and on the lower surface of the first trench along the direction perpendicular to the substrate by an anisotropic etching method to obtain a third trench, and to etch downward from the lower surface of the third trench under the protection of the second mask layer to form a fourth trench that penetrates the overlapping layer and extends into the substrate. That is, in the formation process of the fourth trench, the lithography process is only used in the formation process of the first trench. Also, since the fourth trench is formed within the first trench, the width of the first trench is greater than the width of the fourth trench, that is, the width of the first trench is relatively large. In this way, during the formation of the first trench, the requirements for lithography accuracy and lithography ability are reduced, and thus during the formation of the sidewall, the requirements for lithography accuracy and lithography ability are reduced.

[0069] After forming the sidewall, a semiconductor device with a forksheet structure can be formed by any of a variety of process flows. Below, the process flow of forming a semiconductor device with a forksheet structure will be described by taking the following two process flows as examples.

[0070] As Figure 6 shown, the process of the first process flow is as follows:

[0071] 601. Form a first overlapping structure and a second overlapping structure on both sides of the sidewall. Among them, the first overlapping structure, the second overlapping structure, and the sidewall are covered with a first dielectric layer and a second dielectric layer. One end of the first dielectric layer is flush with one end of the first overlapping structure and the second overlapping structure, one end of the second dielectric layer is flush with the other end of the first overlapping structure and the second overlapping structure, and the other end of the first dielectric layer is separated from the other end of the second dielectric layer by a preset distance. The lengths of the first overlapping structure and the second overlapping structure are both less than the length of the sidewall.

[0072] In a possible implementation, the process of forming the first overlapping structure and the second overlapping structure on both sides of the sidewall may include:

[0073] First, by removing the mask layer to be removed and the overlapping layer located below the mask layer to be removed, a fifth overlapping structure and a sixth overlapping structure located on both sides of the sidewall are formed. Among them, the mask layer to be removed is the first mask layer located outside the sidewall of the first trench. Refer to Figure 5 shown, in a possible implementation, the mask layer to be removed is the polysilicon layer 2032 and the oxide layer 2031 located outside the sidewall of the first trench in the first mask layer 203. On the basis of Figure 5 , the fifth overlapping structure and the sixth overlapping structure obtained after removing the mask layer to be removed and the overlapping layer below it are as Figure 7 shown, where the fifth overlapping structure 209 and the sixth overlapping structure 210 are located on both sides of the sidewall 208. It should be noted that during the process of forming the fifth overlapping structure 209 and the sixth overlapping structure 210, there is also a certain loss in the height of the second mask layer 206 and the sidewall 208.

[0074] In another possible implementation, in order to avoid the field effect transistors formed based on the fifth overlapping structure and the sixth overlapping structure being connected to the substrate to form parasitic devices, thereby affecting the performance of the field effect transistors, after forming the fifth overlapping structure and the sixth overlapping structure, refer to Figure 8As shown, by etching the substrate 201, a gap 211 is formed between the substrate 201 and the fifth overlapping structure 209 and the sixth overlapping structure 210, and a fifth dielectric layer is formed in the gap 211 by deposition. In this way, the substrate 201 can be separated from the fifth overlapping structure 209 and the sixth overlapping structure 210 by the fifth dielectric layer, so that the substrate 201 can be separated from the field-effect transistors formed based on the fifth overlapping structure 209 and the sixth overlapping structure 210 by the fifth dielectric layer, thereby avoiding the connection between the field-effect transistors formed based on the fifth overlapping structure 209 and the sixth overlapping structure 210 and the substrate 201 to form parasitic devices, and improving the performance of the field-effect transistors.

[0075] The material of the fifth dielectric layer can be, for example, insulating materials such as oxides and silicon nitrides, and this application does not make special limitations on this.

[0076] It should be noted that the field-effect transistors formed based on the fifth overlapping structure include multiple first channel layers and first doping structures, etc., and the field-effect transistors formed based on the sixth overlapping structure include multiple second channel layers and second doping structures, etc. As can be seen from the above, since the fifth overlapping structure and the sixth overlapping structure are located on the fifth dielectric layer, therefore, the multiple first channel layers, first doping structures, multiple second channel layers, and second doping structures are all located on the fifth dielectric layer.

[0077] It should be noted that the above method for forming the fifth dielectric layer is only exemplary and is not used to limit this application.

[0078] Then, a dummy gate structure covering the fifth overlapping structure, the sixth overlapping structure, and the sidewall is formed, wherein the length of the dummy gate structure is equal to the above preset distance. The length of the dummy gate structure is determined according to the design requirements of the device, and no special limitations are made here. Refer to Figure 9 As shown, in a possible implementation manner, the dummy gate structure 213 covers the fifth overlapping structure 209, the sixth overlapping structure 210, and the sidewall 208, and the fifth overlapping structure 209 and the sixth overlapping structure 210 are located on the fifth dielectric layer 212. The length of the dummy gate structure 213 is b.

[0079] Finally, a first dielectric layer and a second dielectric layer are formed at both ends of the dummy gate structure, and the regions of the fifth overlapping structure that are not covered by the dummy gate structure, the first dielectric layer, and the second dielectric layer are removed to obtain a first overlapping structure, and the regions of the sixth overlapping structure that are not covered by the dummy gate structure, the first dielectric layer, and the second dielectric layer are removed to obtain a second overlapping structure.

[0080] The materials of the first dielectric layer and the second dielectric layer can be insulating materials such as oxides or silicon nitrides. See Figure 10As shown, in a possible implementation, the first overlapping structure 216 and the second overlapping structure 217 are located on both sides of the sidewall 208, and the first overlapping structure 216, the second overlapping structure 217, and the sidewall 208 are covered by the dummy gate structure 213, the first dielectric layer 214, and the second dielectric layer 215. The first dielectric layer 214 and the second dielectric layer 215 are located at both ends of the dummy gate structure 213.

[0081] 602. Remove the first target material in the first overlapping structure that is covered by the first dielectric layer and the second dielectric layer, and remove the second target material in the second overlapping structure that is covered by the first dielectric layer and the second dielectric layer.

[0082] The first target material is the material among the first material and the second material that is not used to form the first channel layer; the second target material is the material among the first material and the second material that is not used to form the second channel layer. The first target material and the second target material may be the same or different, and this application does not make special limitations on this.

[0083] In a possible implementation, the first material is silicon germanium, the second material is silicon, the first target material is silicon, and the second target material is silicon germanium.

[0084] 603. Form a third dielectric layer in the area where the first target material is removed to obtain a third overlapping structure, and form a fourth dielectric layer in the area where the second target material is removed to obtain a fourth overlapping structure.

[0085] The materials of the third dielectric layer and the fourth dielectric layer can be insulating materials such as oxides or silicon nitride, etc. The materials of the third dielectric layer and the fourth dielectric layer may be the same or different.

[0086] It should be noted that the first overlapping structure from which the first target material is removed and the third dielectric layer is formed is named the third overlapping structure, and the second overlapping structure from which the second target material is removed and the fourth dielectric layer is formed is named the fourth overlapping structure.

[0087] 604. Form a first doping structure at both ends of the third overlapping structure, and form a second doping structure at both ends of the fourth overlapping structure. The doping types of the first doping structure and the second doping structure are opposite, that is, if the doping type of the first doping structure is N-type, then the doping type of the second doping structure is P-type; if the doping type of the first doping structure is P-type, then the doping type of the second doping structure is N-type.

[0088] In 604, the first doped structure can be formed at both ends of the third overlapping structure by deposition, and the second doped structure can be formed at both ends of the fourth overlapping structure. It should be noted that when forming the first doped structure and the second doped structure, deposition can be carried out first and then doping, that is, no doping is carried out during the deposition process, or a doped structure of the corresponding doping type can be deposited. The materials of the first doped structure and the second doped structure before doping can be, for example: semiconductor materials such as silicon, germanium, silicon germanium, etc.

[0089] See Figure 11 As shown, in a possible implementation, the number of the first doped structures 220 is two, and they are respectively located at both ends of the third overlapping structure. The number of the second doped structures 221 is two, and they are respectively located at both ends of the fourth overlapping structure. It should be noted that Figure 11 is a three-dimensional view. In order to clearly show the structures blocked by the first doped structure 220 and the second doped structure 221 in the figure, the first doped structure 220 and the second doped structure 221 are shown in a semi-transparent manner. Figure 12 is Figure 11 a cross-sectional view along the a-a' direction. In Figure 12 it, the first material 2021 is silicon germanium, the second material 2022 is silicon, the third overlapping structure 218 and the fourth overlapping structure 219 are located on both sides of the sidewall 208. The first target material is the second material, that is, the first target material is silicon, and the second target material is the first material, that is, the second target material is silicon germanium. The third dielectric layer 222 is located in the area where the first target material is removed, and the fourth dielectric layer 223 is located in the area where the second target material is removed.

[0090] By forming the first doped structure, the source-drain regions of the first field-effect transistor are obtained. By forming the second doped structure, the source-drain regions of the second field-effect transistor are obtained. Among them, the first field-effect transistor is a field-effect transistor formed based on the first overlapping structure (i.e., the fifth overlapping structure), and the second field-effect transistor is a field-effect transistor formed based on the second overlapping structure (i.e., the sixth overlapping structure).

[0091] 605. Remove the first target material in the third overlapping structure to form a plurality of first channel layers, and remove the second target material in the fourth overlapping structure to form a plurality of second channel layers. The first target material and the second target material have been described above, so they will not be elaborated here.

[0092] The first channel layer is the channel region of the first field-effect transistor, and the second channel layer is the channel region of the second field-effect transistor.

[0093] The materials of the first channel layer and the second channel layer may be the same or different, and no special limitation is imposed here. It should be noted that if the materials of the first channel layer and the second channel layer are different, appropriate materials can be selected for the first channel layer and the second channel layer respectively according to the types of the field effect transistors corresponding to the first channel layer and the second channel layer, so as to improve the performance of the field effect transistors.

[0094] The first channel layer and the second channel layer may be doped or undoped, and no special limitation is imposed here. It should be noted that if the first channel layer and the second channel layer are doped, the doping type of the first channel layer is opposite to that of the first doping structure, and the doping type of the second channel layer is opposite to that of the second doping structure.

[0095] It should be noted that in a possible implementation, if a dummy gate structure is covered on the third overlapping structure and the fourth overlapping structure, the dummy gate structure needs to be removed, and then, the first target material in the third overlapping structure is removed to form a plurality of first channel layers, and the second target material in the fourth overlapping structure is removed to form a plurality of second channel layers.

[0096] See Figure 13 As shown, in a possible implementation, the first material 2021 is silicon germanium, the second material 2022 is silicon, the first target material is silicon, the second target material is silicon germanium, the material of the first channel layer 224 is silicon germanium, the material of the second channel layer 225 is silicon, the doping type of the first doping structure 220 is P-type, the doping type of the second doping structure is N-type, and both the first channel layer 224 and the second channel layer 225 are undoped. As can be seen from the above, since the doping type of the first doping structure 220 is P-type and the doping type of the second doping structure is N-type, therefore, the channel type of the field effect transistor formed based on the first overlapping structure is P-type, and the channel type of the field effect transistor formed based on the second overlapping structure is N-type. Also, since the channel layer made of silicon germanium material helps to improve the performance of the P-type field effect transistor, and the channel layer made of silicon material helps to improve that of the N-type field effect transistor, therefore, silicon is selected as the material of the second channel layer 225, and silicon germanium is selected as the material of the first channel layer 224, so as to improve the performance of the field effect transistor formed based on the first overlapping structure and the field effect transistor formed based on the second overlapping structure.

[0097] It should be noted that Figure 13 is a schematic structural diagram of the first channel layer and the second channel layer formed based on the cross-sectional view along the A-A' direction. Since Figure 11 is a perspective view, therefore, the second doping structure is blocked by other structures. Figure 13 Since

[0098] 606. A first gate insulating layer is formed on the first channel layer, a second gate insulating layer is formed on the second channel layer, a first gate conductive layer is formed on the first gate insulating layer, and a second gate conductive layer is formed on the second gate insulating layer.

[0099] The materials of the first gate insulating layer and the second gate insulating layer can be, for example, silicon dioxide or high-k materials (such as ZrO 2 、HfO 2 、Al 2 O 3 etc.), and there is no special limitation here. The materials of the first gate conductive layer and the second gate conductive layer can be, for example, metal materials or heavily doped polysilicon, etc., and there is no special limitation here.

[0100] The materials of the first gate insulating layer and the second gate insulating layer can be the same or different, and the materials of the first gate conductive layer and the second gate conductive layer can be the same or different. If the materials of the first gate insulating layer and the second gate insulating layer are the same and / or the materials of the first gate conductive layer and the second gate conductive layer are the same, the manufacturing process can be simplified and the manufacturing cost can be saved.

[0101] See Figure 14 As shown, in a possible implementation, a first gate insulating layer is formed on the exposed surface of the first channel layer 224, and a second gate insulating layer is formed on the exposed surface of the second channel layer 225. The exposed surface of the first channel layer 224 is the surface of the first channel layer 224 that is not in contact with other structures, and the exposed surface of the second channel layer 225 is the surface of the second channel layer 225 that is not in contact with other structures. A first gate conductive layer is deposited on the surface of the first gate insulating layer that is away from the first channel layer, and a second gate conductive layer is deposited on the surface of the second gate insulating layer that is away from the second channel layer. It should be noted that in Figure 14 , the first gate insulating layer and the first gate conductive layer are not shown separately, that is, Figure 14 227 in is used to indicate the combination of the first gate insulating layer and the first gate conductive layer. Similarly, the second gate insulating layer and the second gate conductive layer are not shown separately, that is, Figure 14 228 in is used to indicate the combination of the second gate insulating layer and the second gate conductive layer. In addition, as Figure 14 shown, after the first gate insulating layer and the first gate conductive layer are formed, the first gate insulating layer and the first gate conductive layer are also formed on the sidewalls. In order to simplify the manufacturing process, the first gate insulating layer and the first gate conductive layer on the sidewalls do not need to be removed. The same situation also exists for the second gate insulating layer and the second gate conductive layer, which will not be elaborated here.

[0102] As can be seen from the above, the semiconductor device fabricated by the above process includes two field effect transistors, namely the first field effect transistor and the second field effect transistor, where: The first field effect transistor includes a plurality of first channel layers, a first doping structure, a first gate insulating layer, and a first gate conductive layer. The plurality of first channel layers are the channel regions of the first field effect transistor, the first gate insulating layer and the first gate conductive layer form the gate of the first field effect transistor, and the first doping structure forms the source-drain regions of the first field effect transistor. The second field effect transistor includes a plurality of second channel layers, a second doping structure, a second gate insulating layer, and a second gate conductive layer. The plurality of second channel layers are the channel regions of the second field effect transistor, the second gate insulating layer and the second gate conductive layer form the gate of the second field effect transistor, and the second doping structure forms the source-drain regions of the second field effect transistor.

[0103] On this basis, if the materials of the first gate conductive layer and the second gate conductive layer are the same, the metal contact effect of the conductive layers of the gates in the first field effect transistor and the second field effect transistor can be eliminated, that is, the metal gate contact effect is eliminated.

[0104] Since the doping types of the first doping structure and the second doping structure are opposite, the channel types of the first field effect transistor and the second field effect transistor are opposite. That is, if the doping type of the first doping structure is N-type and the doping type of the second doping structure is P-type, then the channel type of the first field effect transistor is N-type and the channel type of the second field effect transistor is P-type; that is, if the doping type of the first doping structure is P-type and the doping type of the second doping structure is N-type, then the channel type of the first field effect transistor is P-type and the channel type of the second field effect transistor is N-type.

[0105] See Figure 15 As shown, in a possible implementation, in order to facilitate applying voltages to the first gate conductive layer and the second gate conductive layer, an electrode structure 229 may also be formed on the first gate conductive layer and the second gate conductive layer after the formation of the first gate conductive layer and the second gate conductive layer. The electrode structure 229 is also used to fill the gaps between adjacent first gate conductive layers and the gaps between adjacent second gate conductive layers. The material of the electrode structure 229 includes but is not limited to metal materials such as aluminum and silver.

[0106] See Figure 15 As shown, in order to isolate the electrode structures of adjacent semiconductor devices, an isolation layer 230 may also be formed on the electrode structure 229 by deposition. The material of the isolation layer 230 may be, for example, an insulating material such as an oxide or silicon nitride, and the embodiments of the present application do not make special limitations on this.

[0107] It should be noted that in another possible implementation, the first dielectric layer and the fifth dielectric layer may also be replaced by air.

[0108] Next, the structure of the semiconductor device with the forksheet structure fabricated by the above first process flow will be described.

[0109] See Figure 15 As shown, the semiconductor device includes:

[0110] A substrate 201, a sidewall 208 vertically disposed on the substrate 201, a plurality of first channel layers 224 sequentially and spaced apart along a direction perpendicular to the substrate 201 on one side surface of the sidewall 208, and a plurality of second channel layers 225 sequentially and spaced apart along a direction perpendicular to the substrate 201 on the other side surface of the sidewall 208. Among them, the first channel layer 224 extends along the side surface of the sidewall 208, and the second channel layer 225 extends along the side surface of the sidewall 208. A first doping structure 220 is disposed at both ends of the plurality of first channel layers 224, and a second doping structure ( Figure 15 not shown in the figure) is disposed at both ends of the plurality of second channel layers 225. Among them, the doping types of the first doping structure 220 and the second doping structure are opposite. A first dielectric layer ( Figure 15 not shown in the figure) covers one end of the first surface of the plurality of first channel layers 224 and one end of the first surface of the plurality of second channel layers 225. A second dielectric layer 215 covers the other end of the first surface of the plurality of first channel layers 224 and the other end of the first surface of the plurality of second channel layers 225. Among them, the first surface of the plurality of first channel layers 224 is the surface of the plurality of first channel layers 224 that is far from the sidewall 208, and the first surface of the plurality of second channel layers 225 is the surface of the plurality of second channel layers 225 that is far from the sidewall 208. A third dielectric layer ( Figure 15 not shown in the figure) is disposed at both ends of the second surface of the plurality of first channel layers 224, and a fourth dielectric layer ( Figure 15 not shown in the figure) is disposed at both ends of the second surface of the plurality of second channel layers 225. Among them, the second surface of the plurality of first channel layers 224 is the surface of the plurality of first channel layers 224 that is adjacent to the first surface and parallel to the substrate 201, and the second surface of the plurality of second channel layers 225 is the surface of the plurality of second channel layers 225 that is adjacent to the first surface and parallel to the substrate 201; a first gate insulating layer and a first gate conductive layer are sequentially disposed on the first channel layer 224, and a second gate insulating layer and a second gate conductive layer are sequentially disposed on the second channel layer 225.

[0111] It should be noted that in Figure 15 , the first gate insulating layer and the first gate conductive layer are not separately shown, that is, Figure 15 227 in the figure is used to indicate the combination of the first gate insulating layer and the first gate conductive layer. Similarly, the second gate insulating layer and the second gate conductive layer are not separately shown, that is, Figure 15The 228 in it is used to indicate the combination of the second gate insulating layer and the second gate conductive layer.

[0112] The materials and positional relationships of the above-mentioned various parts have been described above, so they will not be elaborated here.

[0113] As can be seen from the above, the semiconductor device includes two field-effect transistors, namely the first field-effect transistor and the second field-effect transistor, and the first field-effect transistor and the second field-effect transistor are respectively located on both sides of the sidewall. Among them, multiple first channel layers serve as the channel region of the first field-effect transistor, the first doping structure serves as the source-drain region of the first field-effect transistor, the first gate insulating layer and the first gate conductive layer serve as the gate region of the first field-effect transistor, and the first dielectric layer, the second dielectric layer, and the third dielectric layer isolate the gate region and the source-drain region of the first field-effect transistor. Multiple second channel layers serve as the channel region of the second field-effect transistor, the second doping structure serves as the source-drain region of the second field-effect transistor, the second gate insulating layer and the second gate conductive layer serve as the gate region of the second field-effect transistor, and the first dielectric layer, the second dielectric layer, and the fourth dielectric layer isolate the gate region and the source-drain region of the second field-effect transistor.

[0114] The doping type of the first doping structure 220 is opposite to that of the second doping structure, that is, the channel types of the first field-effect transistor and the second field-effect transistor are opposite. That is, if the doping type of the first doping structure 220 is N-type (that is, the channel type of the first field-effect transistor is N-type), then the doping type of the second doping structure is P-type (that is, the channel type of the second field-effect transistor is P-type); if the doping type of the first doping structure 220 is P-type (that is, the channel type of the first field-effect transistor is P-type), then the doping type of the second doping structure is N-type (that is, the channel type of the second field-effect transistor is N-type).

[0115] See Figure 15 As shown, the materials of the first channel layer 224 and the second channel layer 225 are different. The first channel layer 224 and the second channel layer 225 are not in the same plane, and the upper surface of the first channel layer 224 is flush with the lower surface of the second channel layer 225.

[0116] When the materials of the first channel layer 224 and the second channel layer 225 are different, suitable materials can be selected for the first channel layer and the second channel layer respectively according to the types of the field-effect transistors corresponding to the first channel layer and the second channel layer, so as to improve the performance of the field-effect transistors and further improve the driving performance of the semiconductor device.

[0117] For example, in a feasible implementation, if the doping type of the first doping structure is P-type, that is, the channel type of the first field-effect transistor is P-type, and the doping type of the second doping structure is N-type, that is, the channel type of the second field-effect transistor is N-type. Then, since the channel layer made of silicon-germanium material helps to improve the performance of the P-type field-effect transistor, and the channel layer made of silicon material helps to improve the performance of the N-type field-effect transistor. Therefore, in order to improve the performance of the first field-effect transistor and the second field-effect transistor, the material of the first channel layer is selected as silicon-germanium, and the material of the second channel layer is selected as silicon.

[0118] It should be noted that, in another possible implementation, the materials of the first channel layer 224 and the second channel layer 225 can also be the same.

[0119] The materials of the first gate insulating layer and the second gate insulating layer can be the same or different, and the embodiments of the present application do not make special limitations on this. The materials of the first gate conductive layer and the second gate conductive layer can be the same or different, and the embodiments of the present application do not make special limitations on this.

[0120] Since the channel types of the first field-effect transistor and the second field-effect transistor are opposite, therefore, the first field-effect transistor and the second field-effect transistor have different VTs (threshold voltages). The VT of a field-effect transistor can be understood as the difference between the work function of the gate conductive layer and the Fermi level of the channel layer. In other words, if the VT of the first field-effect transistor (that is, the difference between the work function of the first gate conductive layer and the Fermi level of the first channel layer) is the first value, and the VT of the second field-effect transistor (that is, the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer) is the second value, then the first value and the second value are different. The first value is related to the channel type of the first field-effect transistor, the structure of the first field-effect transistor, and the parameters of each part of the first field-effect transistor, etc. Similarly, the second value is related to the channel type of the second field-effect transistor, the structure of the second field-effect transistor, and the parameters of each part of the second field-effect transistor, etc.

[0121] It should be noted that, if the channel type of a field-effect transistor is N-type, then the difference between the work function of the gate conductive layer and the Fermi level of the channel layer is greater than 0. If the channel type of a field-effect transistor is P-type, then the difference between the work function of the gate conductive layer and the Fermi level of the channel layer is less than 0.

[0122] The VT of a field-effect transistor (that is, the difference between the work function of the gate conductive layer and the Fermi level of the channel layer) can meet the requirements through at least one of the following four methods. Among them:

[0123] The first one is to change the Fermi level of the channel layer by adjusting the doping concentration and doping type of the channel layer.

[0124] Second, if the material of the channel layer is a semiconductor compound, the Fermi level of the channel layer is changed by adjusting the proportion of each component in the semiconductor compound.

[0125] Third, if the material of the gate insulating layer is a high-k material, the work function of the gate conductive layer is affected by selecting a suitable high-k material for the gate insulating layer and / or changing the manufacturing process of the gate insulating layer (such as annealing conditions, etc.).

[0126] Fourth, since different metal materials have different work functions, a gate conductive layer that meets the work function requirements is obtained by selecting a metal material with a corresponding work function to fabricate the gate conductive layer, and if the material of the gate conductive layer is heavily doped polysilicon, the work function of the gate conductive layer is changed by changing the doping type and concentration of the polysilicon.

[0127] As can be seen from the above, the work function of the gate conductive layer and / or the Fermi level of the channel layer are adjusted by at least one of the above four methods so that the VT of the field effect transistor meets the requirements.

[0128] Based on the above principle, when the materials of the first gate insulating layer and the second gate insulating layer are the same and the materials of the first gate conductive layer and the second gate conductive layer are the same (that is, when the work functions of the first gate conductive layer and the second gate conductive layer are the same and determined), the Fermi levels of the first channel layer and the second channel layer are adjusted by at least one of the following two methods, so that the difference between the work function of the first gate conductive layer and the Fermi level of the first channel layer is a first value, and the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer is a second value, that is, the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements, where:

[0129] Method 1: If the material of the first channel layer and / or the material of the second channel layer is a semiconductor compound, the component ratio of the semiconductor compound is adjusted.

[0130] Method 2: The doping type and doping concentration of the first channel layer and the second channel layer are adjusted.

[0131] Obviously, when the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same, that is, under the condition that the first field effect transistor and the second field effect transistor share the gate insulating layer and the gate conductive layer, the Fermi levels of the first channel layer and the second channel layer are adjusted in the above manner, so that the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements. In addition, since the first field effect transistor and the second field effect transistor share the gate conductive layer and the gate insulating layer, the metal contact effect of the gates of the first field effect transistor and the second field effect transistor, that is, the metal gate contact effect, is eliminated, improving the device performance, and at the same time simplifying the manufacturing process of the semiconductor device. In addition, the Fermi levels of the first channel layer and the second channel layer are adjusted in the above manner, so that the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements by means of the energy band difference, and further enabling the first field effect transistor and the second field effect transistor to share the gate insulating layer and the gate conductive layer.

[0132] For example, Figure 16 is the energy band diagram of the first field effect transistor and the second field effect transistor. In Figure 16 As shown, the first field effect transistor is a P-channel field effect transistor, the second field effect transistor is an N-channel field effect transistor, the material of the first channel layer is silicon germanium, the material of the second channel layer is silicon, the first gate conductive layer and the second gate conductive layer use the same material, and the first gate insulating layer and the second gate insulating layer use the same material.

[0133] On this basis, the materials of the first gate conductive layer and the second gate conductive layer can be determined first according to the Fermi level of the second channel layer (the Fermi level of silicon), so that the work function WF of the first gate conductive layer and the second gate conductive layer is greater than the Fermi level Efn of the second channel layer, and the VT of the second field effect transistor is the second value. Then, by adjusting the silicon germanium composition, the Fermi level Efp of the first channel layer is changed, so that the Fermi level Efp of the first channel layer is greater than the work function WF of the first gate conductive layer and the second gate conductive layer, and the VT of the first field effect transistor is the first value. Figure 16 In, Ecp is the conduction band of the first channel layer, Evp is the valence band of the first channel layer, Ecn is the conduction band of the second channel layer, and Evn is the valence band of the second channel layer.

[0134] Based on the above principle, when the materials of the first gate conductive layer and the second gate conductive layer are the same, at least one of the following three methods can be used to make the difference between the work function of the first gate conductive layer and the Fermi level of the first channel layer be the first value, and the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer be the second value, where:

[0135] Method 1: The materials of the first gate insulating layer and the second gate insulating layer are high-k materials, and the types of the high-k materials corresponding to the first gate insulating layer and the second gate insulating layer and / or the manufacturing processes of the first gate insulating layer and the second gate insulating layer (such as annealing temperature, time, etc.) are adjusted.

[0136] Method 2: If the material of the first channel layer and / or the material of the second channel layer is a semiconductor compound, then adjust the component ratio of the semiconductor compound.

[0137] Method 3: Adjust the doping types and doping concentrations of the first channel layer and the second channel layer.

[0138] Obviously, under the condition that the first field-effect transistor and the second field-effect transistor share the gate conductive layer (that is, under the condition that the materials of the first gate conductive layer and the second gate conductive layer are the same), by adjusting the Fermi levels of the first channel layer and the second channel layer and / or the work functions of the first gate conductive layer and the second gate conductive layer in the above manner, the VT of the first field-effect transistor and the VT of the second field-effect transistor meet the requirements. In addition, since the first field-effect transistor and the second field-effect transistor share the gate conductive layer, the metal contact effect of the gates of the first field-effect transistor and the second field-effect transistor is eliminated, the device performance is improved, and at the same time, the manufacturing process of the semiconductor device is simplified. In addition, by adjusting the Fermi levels of the first channel layer and the second channel layer and / or the work functions of the first gate conductive layer and the second gate conductive layer in the above manner, so that the VT of the first field-effect transistor and the VT of the second field-effect transistor meet the requirements by means of the energy band difference, the first field-effect transistor and the second field-effect transistor can share the gate conductive layer.

[0139] It should be noted that the above methods are only exemplary and are not used to limit the present application.

[0140] In the case where the materials of the first gate insulating layer and the second gate insulating layer are the same, at least one of the following three methods can be used to make the difference between the work function of the first gate conductive layer and the Fermi level of the first channel layer be a first value, and the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer be a second value, where:

[0141] Method 1: Adjust the doping types and doping concentrations of the first channel layer and the second channel layer.

[0142] Method 2: If the material of the first channel layer and / or the material of the second channel layer is a semiconductor compound, then adjust the component ratio of the semiconductor compound.

[0143] Method 3: Select suitable metal materials for the first gate conductive layer and the second gate conductive layer or adjust the doping types and concentrations of the first gate conductive layer and the second gate conductive layer (if the first gate conductive layer and the second gate conductive layer are heavily doped polysilicon).

[0144] Obviously, in the above manner, under the condition that the first field-effect transistor and the second field-effect transistor share the gate insulating layer, by adjusting the Fermi levels of the first channel layer and the second channel layer and / or the work functions of the first gate conductive layer and the second gate conductive layer in the above manner, the VT of the first field-effect transistor and the VT of the second field-effect transistor meet the requirements. In addition, since the first field-effect transistor and the second field-effect transistor share the gate insulating layer, the manufacturing process of the semiconductor device is simplified.

[0145] It should be noted that the above manner is only exemplary and is not used to limit the present application.

[0146] See Figure 15 As shown, in order to prevent the substrate from being connected to the first field-effect transistor and the second field-effect transistor to form parasitic devices, thereby affecting the performance of the first field-effect transistor and the second field-effect transistor, the semiconductor device further includes a fifth dielectric layer 212, and the fifth dielectric layer 212 is located between the substrate 201 and the field-effect transistors, that is, the fifth dielectric layer 212 is located on the substrate 201, and a plurality of first channel layers 224, a plurality of second channel layers 225, a first doping structure 220, and a second doping structure are located on the fifth dielectric layer 212.

[0147] In order to facilitate applying voltages to the first gate conductive layer and the second gate conductive layer, as Figure 15 shown, the semiconductor device further includes an electrode structure 229, and the electrode structure 229 is located on the first gate conductive layer and the second gate conductive layer and is used to connect the first gate conductive layer and the second gate conductive layer.

[0148] In order to isolate the electrode structures of adjacent semiconductor devices, as Figure 15 shown, the semiconductor device further includes an isolation layer 230, and the isolation layer 230 covers the electrode structure 229. It should be noted that an opening is provided on the isolation layer 230 to lead out the electrode structure 229 from the opening.

[0149] It should be noted that since the above-mentioned various parts have been described above, they will not be repeated here. And, Figure 15 This is only a structure of the semiconductor device fabricated by the first process flow and is not used to limit the present application.

[0150] The process of the second process flow is as follows:

[0151] Since the first process flow is the same as the second process flow in forming a plurality of first channel layers and a plurality of second channel layers and the processes before them, therefore, only the processes after forming a plurality of first channel layers and a plurality of second channel layers in the second process will be described below, specifically as follows:

[0152] Remove the sidewall located between the first dielectric layer and the second dielectric layer by etching. In a possible implementation, refer to the structure after removing the sidewall between the first dielectric layer and the second dielectric layer in Figure 17 as shown.

[0153] Form a gate insulating layer on the first channel layer and the second channel layer by deposition. Specifically, deposit the gate insulating layer on the exposed surfaces of the first channel layer and the second channel layer. Since the exposed surfaces of the first channel layer and the second channel layer have been described above, they will not be elaborated here. The material of the insulating layer can be, for example, silicon dioxide or high-k materials (such as ZrO 2 , HfO 2 , Al 2 O 3 etc.), and no special limitation is made here.

[0154] Form a gate conductive layer on the gate insulating layer by deposition. The material of the gate conductive layer can be, for example, metal materials and heavily doped polysilicon, etc., and no special limitation is made here.

[0155] As can be seen from the above, since the sidewall located between the first dielectric layer and the second dielectric layer is removed, therefore, the four side surfaces of the first channel layer and the second channel layer are all exposed. In this way, a gate-all-around structure can be formed, that is, the gate region composed of the gate insulating layer and the gate conductive layer covers the four side surfaces of the first channel layer and the second channel layer, improving the gate driving ability of the device.

[0156] In a possible implementation, a semiconductor device that sequentially forms a gate insulating layer and a gate conductive layer on the first channel layer and the second channel layer is as Figure 18 shown. Refer to Figure 18 It can be seen that the gate insulating layer and the gate conductive layer form a gate-all-around structure on the first channel layer 224 and the second channel layer 225. It should be noted that in Figure 18 , the gate insulating layer and the gate conductive layer are not shown separately, that is, Figure 18 231 in is used to indicate the combination of the gate insulating layer and the conductive layer.

[0157] As described above, the semiconductor device includes two field effect transistors, namely a first field effect transistor and a second field effect transistor. Among them, multiple first channel layers serve as the channel region of the first field effect, the first doping structure serves as the source-drain region of the first field effect transistor, the gate insulating layer and the gate conductive layer serve as the gate region of the first field effect transistor, and the first dielectric layer, the second dielectric layer, and the third dielectric layer isolate the gate region and the source-drain region of the first field effect transistor. Multiple second channel layers serve as the channel region of the second field effect, the second doping structure serves as the source-drain region of the second field effect transistor, the gate insulating layer and the gate conductive layer also serve as the gate region of the second field effect transistor, and the first dielectric layer, the second dielectric layer, and the fourth dielectric layer isolate the gate region and the source-drain region of the second field effect transistor.

[0158] Since the gate insulating layer and the gate conductive layer are shared by the first channel layer and the second channel layer, the process is simplified, and at the same time, the metal contact effect of the gates of the first field effect transistor and the second field effect transistor can be eliminated. In addition, since the sidewall is removed, the exposed area of the first channel layer and the second channel layer is increased, and then the coverage area of the gate insulating layer and the gate conductive layer is increased, thereby increasing the gate control ability of the device.

[0159] In the second process flow, referring to Figure 19 as shown, in a feasible implementation, a fifth dielectric layer 212, an electrode structure 229, and an isolation layer 230 can also be formed. Since the purpose and principle of forming the fifth dielectric layer 212, the electrode structure 229, and the isolation layer 230 are the same as those in the first process flow, they will not be elaborated here.

[0160] Next, the structure of the semiconductor device with a forksheet structure fabricated by the above second process flow will be described.

[0161] Referring to Figure 19 as shown, the difference between this semiconductor device and the semiconductor device fabricated by the above first manufacturing process is that:

[0162] The sidewall 208 located between the first dielectric layer and the second dielectric layer 215 is removed, and a first gate insulating layer and a first gate conductive layer are sequentially disposed on the surface of the first channel layer 224 in contact with the removed sidewall 208, and a second gate insulating layer and a second gate conductive layer are sequentially disposed on the surface of the second channel layer 225 in contact with the removed sidewall 208. Among them, the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same.

[0163] It should be noted that since the materials of the first gate insulating layer and the second gate insulating layer are the same, the first gate insulating layer and the second gate insulating layer are collectively referred to as the gate insulating layer. Since the materials of the first gate conductive layer and the second gate conductive layer are the same, the first gate conductive layer and the second gate conductive layer are collectively referred to as the gate conductive layer. Based on this, in Figure 19 the gate insulating layer and the conductive layer are not separately shown, that is, Figure 19 231 in is used to indicate the combination of the gate insulating layer and the conductive layer.

[0164] As can be seen from the above, by removing the sidewall, the four side surfaces of the first channel layer and the second channel layer are all exposed, so that a gate-all-around structure (the gate-all-around structure includes the first gate insulating layer and the first gate conductive layer) can be formed on the first channel layer, and a gate-all-around structure (the gate-all-around structure includes the second gate insulating layer and the second gate conductive layer) can be formed on the second channel layer, increasing the gate driving ability of the device. In addition, since the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same, in this way, the first field-effect transistor and the second field-effect transistor form a common-gate structure, simplifying the process flow and reducing the manufacturing cost.

[0165] Since the channel types of the first field-effect transistor and the second field-effect transistor are opposite, the first field-effect transistor and the second field-effect transistor have different VTs (threshold voltages). The VT of a field-effect transistor can be understood as the difference between the work function of the gate conductive layer and the Fermi level of the channel layer. In other words, the VT (the difference between the work function of the gate conductive layer and the Fermi level of the first channel layer) of the first field-effect transistor is the first value, and the VT (the difference between the work function of the gate conductive layer and the Fermi level of the second channel layer) of the second field-effect transistor is the second value, and the first value and the second value are different.

[0166] Since in the semiconductor device with a forksheet structure fabricated by the second process flow, the first field-effect transistor and the second field-effect transistor share the gate insulating layer and the gate conductive layer, at least one of the following two methods can be used to make the difference between the work function of the gate conductive layer (i.e., the first gate conductive layer) and the Fermi level of the first channel layer be the first value, and the difference between the work function of the gate conductive layer (i.e., the second gate conductive layer) and the Fermi level of the second channel layer be the second value, where:

[0167] Method 1: If the material of the first channel layer and / or the material of the second channel layer is a semiconductor compound, adjust the component ratio of the semiconductor compound.

[0168] Method 2: Adjust the doping type and doping concentration of the first channel layer and the second channel layer.

[0169] Obviously, under the condition that the first field-effect transistor and the second field-effect transistor share the gate insulating layer and the gate conductive layer, by adjusting the Fermi levels of the first channel layer and the second channel layer in the above manner, the VT of the first field-effect transistor and the VT of the second field-effect transistor meet the requirements. In addition, since the first field-effect transistor and the second field-effect transistor share the gate conductive layer and the gate insulating layer, the metal contact effect of the gates of the first field-effect transistor and the second field-effect transistor is eliminated, the device performance is improved, and at the same time, the manufacturing process of the semiconductor device is simplified. In addition, by adjusting the Fermi levels of the first channel layer and the second channel layer in the above manner, the VT of the first field-effect transistor and the VT of the second field-effect transistor meet the requirements by virtue of the energy band difference, so that the first field-effect transistor and the second field-effect transistor can share the gate insulating layer and the gate conductive layer.

[0170] To avoid the substrate being connected to the first field-effect transistor and the second field-effect transistor to form parasitic devices, thereby affecting the performance of the first field-effect transistor and the second field-effect transistor, as Figure 19 shown, the above semiconductor device further includes a fifth dielectric layer 212, and the fifth dielectric layer 212 is located between the substrate 201 and the field-effect transistor, that is, the fifth dielectric layer 212 is located on the substrate 201, and a plurality of first channel layers 224, a plurality of second channel layers 225, a first doping structure 220 and a second doping structure are located on the fifth dielectric layer 212.

[0171] To facilitate applying a voltage to the gate conductive layer (i.e., the first gate conductive layer and the second gate conductive layer), as shown in Figure 19 shown, the semiconductor device further includes an electrode structure 229, and the electrode structure 229 is located on the gate conductive layer. To isolate the electrode structures 229 of different semiconductor devices, the semiconductor device further includes an isolation layer 230, and the isolation layer 230 covers the electrode structure 229. It should be noted that an opening is provided in the isolation layer 230 to lead out the electrode structure 229 from the opening.

[0172] It should be noted that the above-provided drawings regarding the structure and process flow are all drawn on the basis of forming two identical fork-shaped semiconductor devices.

[0173] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A method for forming sidewalls in a fork structure, characterized in that, comprising: providing a substrate; forming an overlapping layer on the substrate with a first material and a second material stacked in sequence; forming a first mask layer on the overlapping layer; forming a first trench in the first mask layer; forming a second trench in the first trench by forming a second mask layer on the first mask layer and within the first trench; anisotropically etching the second mask layer along a direction perpendicular to the substrate until the second mask layer located between the sidewalls of the second trench and on the lower surface of the first trench is removed, so as to form a third trench based on the second trench; using the second mask layer as a protective layer, etching downward from the lower surface of the third trench to form a fourth trench that penetrates the overlapping layer and extends into the substrate; filling the fourth trench to form sidewalls in the fourth trench.

2. The method according to claim 1, characterized in that, the method further comprises: forming a first overlapping structure and a second overlapping structure on both sides of the sidewalls, wherein the first overlapping structure, the second overlapping structure, and the sidewalls are covered with a first dielectric layer and a second dielectric layer, one end of the first dielectric layer is flush with one end of the first overlapping structure and the second overlapping structure, one end of the second dielectric layer is flush with the other end of the first overlapping structure and the second overlapping structure, and the other end of the first dielectric layer is separated from the other end of the second dielectric layer by a preset distance; removing a first target material in the first overlapping structure covered by the first dielectric layer and the second dielectric layer, and removing a second target material in the second overlapping structure covered by the first dielectric layer and the second dielectric layer; forming a third dielectric layer in the area where the first target material is removed to obtain a third overlapping structure; forming a fourth dielectric layer in the area where the second target material is removed to obtain a fourth overlapping structure; forming a first doping structure at both ends of the third overlapping structure, and forming a second doping structure at both ends of the fourth overlapping structure; removing the first target material in the third overlapping structure that is not covered by the first dielectric layer and the second dielectric layer to form a plurality of first channel layers; removing the second target material in the fourth overlapping structure that is not covered by the first dielectric layer and the second dielectric layer to form a plurality of second channel layers; wherein, the first target material is the material in the first material and the second material that is not used to form the first channel layer; the second target material is the material in the first material and the second material that is not used to form the second channel layer, and the doping types of the first doping structure and the second doping structure are opposite.

3. The method according to claim 2, characterized in that, the method further comprises: forming a first gate insulating layer on the first channel layer, and forming a second gate insulating layer on the second channel layer; forming a first gate conductive layer on the first gate insulating layer, and forming a second gate conductive layer on the second gate insulating layer.

4. The method according to claim 3, It is characterized in that the materials of the first gate conductive layer and the second gate conductive layer are the same.

5. The method according to claim 2, it is characterized in that the method further includes: removing the sidewall located between the first dielectric layer and the second dielectric layer; forming a gate insulating layer on the first channel layer and the second channel layer; forming a gate conductive layer on the gate insulating layer.

6. The method according to any one of claims 2 to 5, it is characterized in that the forming of the first overlapping structure and the second overlapping structure on both sides of the sidewall includes: forming a fifth overlapping structure and a sixth overlapping structure on both sides of the sidewall by removing the mask layer to be removed and the overlapping layer located under the mask layer to be removed, wherein the mask layer to be removed is the first mask layer located outside the sidewall of the first trench; forming a dummy gate structure covering the fifth overlapping structure, the sixth overlapping structure and the sidewall, wherein the length of the dummy gate structure is equal to the preset distance; forming the first dielectric layer and the second dielectric layer at both ends of the dummy gate structure; removing the area of the fifth overlapping structure that is not covered by the dummy gate structure, the first dielectric layer and the second dielectric layer to obtain the first overlapping structure; removing the area of the sixth overlapping structure that is not covered by the dummy gate structure, the first dielectric layer and the second dielectric layer to obtain the second overlapping structure.

7. The method according to claim 6, it is characterized in that before forming the plurality of first channel layers and the plurality of second channel layers, it further includes: removing the dummy gate structure.

8. The method according to any one of claims 2 to 5, 7, it is characterized in that the method further includes: forming a fifth dielectric layer on the substrate, and the plurality of first channel layers, the plurality of second channel layers, the first doping structure and the second doping structure are located on the fifth dielectric layer.

9. The method according to any one of claims 2 to 5, 7, it is characterized in that the materials of the first channel layer and the second channel layer are different.

10. The method according to any one of claims 2 to 5, 7, it is characterized in that the first doping structure is P-type doping, the second doping structure is N-type doping, the material of the first channel layer is silicon germanium, and the material of the second channel layer is silicon.

11. A semiconductor device with a fork structure, it is characterized in that it includes: a substrate; a sidewall vertically disposed on the substrate; a plurality of first channel layers sequentially and spaced apart along a direction perpendicular to the substrate on one side surface of the sidewall, and the first channel layer extends along the side surface of the sidewall; a plurality of second channel layers sequentially and spaced apart along a direction perpendicular to the substrate on the other side surface of the sidewall, and the second channel layer extends along the side surface of the sidewall; a first doping structure disposed at both ends of the plurality of first channel layers, a second doping structure disposed at both ends of the plurality of second channel layers, and the doping type of the first doping structure is opposite to the doping type of the second doping structure; A first dielectric layer covering one end of the first surface of the plurality of first channel layers and one end of the first surface of the plurality of second channel layers, and a second dielectric layer covering the other end of the first surface of the plurality of first channel layers and the other end of the first surface of the plurality of second channel layers, wherein the first surface of the plurality of first channel layers is the surface of the plurality of first channel layers that is away from the sidewall, and the first surface of the plurality of second channel layers is the surface of the plurality of second channel layers that is away from the sidewall; A third dielectric layer provided at both ends of the second surface of the plurality of first channel layers, and a fourth dielectric layer provided at both ends of the second surface of the plurality of second channel layers, wherein the second surface of the plurality of first channel layers is the surface of the plurality of first channel layers that is adjacent to its first surface and parallel to the substrate, and the second surface of the plurality of second channel layers is the surface of the plurality of second channel layers that is adjacent to its first surface and parallel to the substrate; A first gate insulating layer and a first gate conductive layer sequentially provided on the first channel layer, and a second gate insulating layer and a second gate conductive layer sequentially provided on the second channel layer; Wherein, the sidewall is formed by filling a fourth trench; the fourth trench is formed by etching downward from the lower surface of the third trench to the substrate with the second mask layer as a protective layer, and the fourth trench penetrates the overlapping layer and extends to the substrate; the third trench is formed by anisotropically etching the second mask layer along a direction perpendicular to the substrate until the second mask layer located between the sidewalls of the second trench and on the lower surface of the first trench is removed; the second trench is formed in the first trench by forming the second mask layer on the first mask layer and in the first trench; the first trench is provided in the first mask layer; the first mask layer is provided on the overlapping layer, the overlapping layer is provided on the substrate, and the overlapping layer is formed by sequentially laminating a first material and a second material.

12. The semiconductor device according to claim 11, Characterized in that, The semiconductor device further includes: A fifth dielectric layer located on the substrate, and the plurality of first channel layers, the plurality of second channel layers, the first doping structure and the second doping structure are located on the fifth dielectric layer.

13. The semiconductor device according to claim 11 or 12, Characterized in that, Or The materials of the first gate conductive layer and the second gate conductive layer are the same.

14. The semiconductor device according to claim 11 or 12, Characterized in that, The sidewall located between the first dielectric layer and the second dielectric layer is removed; The first gate insulating layer and the first gate conductive layer are sequentially provided on the surface of the first channel layer that contacts the removed sidewall; The second gate insulating layer and the second gate conductive layer are sequentially provided on the surface of the second channel layer that contacts the removed sidewall; The materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same.

15. The semiconductor device according to claim 11 or 12, wherein, the materials of the first channel layer and the second channel layer are different.

16. The semiconductor device according to claim 11 or 12, wherein, the first doping structure is P-type doping, the second doping structure is N-type doping, the material of the first channel layer is silicon germanium, and the material of the second channel layer is silicon.

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