Parallelizing variational quantum computing and implementing a multi-reference procedure with high precision and short circuit depth

Abstract

Multi-reference parallelization to facilitate variational quantum computing to achieve high-precision systems with short circuit depth, computer-implemented methods, and computer program products. A system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a trial component that prepares a multi-reference trial state based on qubit operators by applying a unitary circuit operator to a sum of selected initial configurations.

Description

Background Technology

[0001] This subject matter discloses variable quantum computing, and more specifically, multi-reference parallelization of variable quantum computing to achieve high accuracy with short circuit depth.

[0002] Variational quantum eigenvalue solvers (VQEs) are algorithms that use parameterized circuits on a quantum computer to simulate the ground state of a molecule. A parameterized circuit is a set of quantum gates that can be implemented on a quantum computer and can be tuned by parameters such as the angle of a single-qubit rotation gate. The use of algorithms based on VQEs has great potential to solve a wide variety of problems related to quantum chemistry, many-body lattice models, lattice gauge theory models, and materials science. However, the advantage of performing variational computations on a quantum computer rather than on classical hardware is based on the greater expressibility of quantum circuits in defining variational states. This greater expressibility is based on the larger Hilbert space of quantum circuits, but is also controlled by a polynomial-increasing number of variational parameters. To surpass classical systems and computations, quantum circuits typically use a large number of gates (with deep circuit depth) to generate sufficiently entangled states to achieve greater expressibility. Summary of the Invention

[0003] The following summary is presented to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, multi-reference parallelization for variational quantum computation is provided to achieve high accuracy systems, computer-implemented methods, and / or computer program products with short circuit depths.

[0004] According to an embodiment, the system may include a processor that executes computer-executable components stored in memory. The computer-executable components include a test state component that prepares multi-reference test states based on qubit operators by applying unitary circuit operators to a sum of selected initial configurations. An advantage of such a system is that, unlike single-reference test states, selecting multiple reference test states reduces the circuit depth required for efficiently executing the VQE algorithm.

[0005] In some embodiments, the computer-executable component may further include a expectation component that computes the expectation value of the qubit operator based on a selected initial configuration. An advantage of such a system is that the performance of the VQE algorithm can be determined based on the expectation value.

[0006] According to another embodiment, a computer-implemented method may include a system operatively coupled to a processor preparing multi-reference trial states based on qubit operators by applying unitary circuit operators to the sum of selected initial configurations. An advantage of such a computer-implemented method is that, unlike single-reference trial states, by selecting multi-reference trial states, the circuit depth required for efficiently executing the VQE algorithm is reduced.

[0007] In some embodiments, the computer-implemented method described above may further include having the system calculate the expected value of the qubit operator based on the selected initial configuration. An advantage of such a computer-implemented method is that the performance of the VQE algorithm can be determined based on this expected value.

[0008] According to another embodiment, a computer program product includes a computer-readable storage medium having program instructions embodied therein, which are executable by a processor to prepare a multi-reference trial state based on a qubit operator by applying unitary circuit operators to a sum of selected initial configurations. An advantage of such a computer program product is that, in contrast to a single-reference trial state, by selecting a multi-reference trial state, the circuit depth required for efficiently executing the VQE algorithm is reduced.

[0009] In some embodiments, the program instructions can be further executed by the processor to cause the processor to calculate the expected value of the qubit operator based on the selected initial configuration. An advantage of such a computer program product is that the performance of the VQE algorithm can be determined based on this expected value. Attached Figure Description

[0010] Figure 1 A block diagram of an example non-limiting system capable of performing quantum tasks according to one or more embodiments described herein is shown.

[0011] Figure 2 A block diagram of an example non-limiting system is shown that can facilitate multi-reference parallelization of variational quantum computation to achieve high accuracy with short circuit depth.

[0012] Figure 3 A block diagram of an example non-limiting system is shown that can facilitate multi-reference parallelization of variational quantum computation to achieve high accuracy with short circuit depth.

[0013] Figure 4 A flowchart of an example non-limiting computer implementation of a method according to one or more embodiments described herein is shown, which can facilitate the parallelization of variational quantum eigenvalue solvers with high accuracy and short circuit depth.

[0014] Figure 5AA diagram illustrating a non-limiting example of a parameterized circuit according to one or more embodiments described herein, which can facilitate the parallelization of variational quantum computation with high accuracy and short circuit depth.

[0015] Figure 5B A graph comparing the performance of measuring hydrogen molecule dissociation using a multi-reference test state and a single-reference test state according to one or more embodiments described herein is shown.

[0016] Figure 6 A graph comparing the performance of Hubbard model modeling on a graphene lattice using multiple reference test states and single reference test states according to one or more embodiments described herein is shown.

[0017] Figure 7 A graph comparing the performance of Hubbard model modeling on a graphene lattice using multiple reference test states and single reference test states according to one or more embodiments described herein is shown.

[0018] Figure 8 A flowchart is shown of an example non-limiting computer implementation of a method that can facilitate multi-reference parallelization of variable quantum computation to achieve high accuracy with short circuit depth, according to one or more embodiments described herein.

[0019] Figure 9 A flowchart is shown of an example non-limiting computer implementation of a method that can facilitate multi-reference parallelization of variable quantum computation to achieve high accuracy with short circuit depth, according to one or more embodiments described herein.

[0020] Figure 10 A block diagram of an example non-limiting operating environment in which one or more embodiments described herein may be presented. Detailed Implementation

[0021] The following detailed description is merely illustrative and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any express or implied information presented in the preceding background or invention description sections or the detailed description section.

[0022] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent in various circumstances that one or more embodiments may be practiced without these specific details.

[0023] Due to hardware limitations, including cost and manufacturing issues, current quantum circuits are typically quite shallow (with a relatively small number of gates). Furthermore, the desire to reduce the length of quantum circuits also translates to fault-tolerant settings. Therefore, sequentially parameterized gate rotations become long sequences of logic gates, thus impacting the runtime of future error-correction simulations.

[0024] Given the problems described above using existing quantum variational eigenvalue solver techniques, this disclosure can be implemented to generate solutions to these problems in the form of systems, computer-implemented methods, and / or computer program products that facilitate multi-reference parallelization of variational quantum computation to achieve high accuracy with short circuit depth by: preparing multi-reference trial states based on qubit operators by applying unitary circuit operators to the sum of selected initial configurations. The advantage of such systems, computer-implemented methods, and / or computer program products is that, in contrast to single-reference trial states, by selecting multi-reference trial states, the circuit depth required for efficiently executing the VQE algorithm is reduced.

[0025] In some embodiments, this disclosure can be implemented to produce a solution to the above-described problems in the form of a system, a computer-implemented method, and / or a computer program product, which can further facilitate multi-reference parallelization of variational quantum computation to achieve high accuracy with short circuit depth by: calculating the expected value of the qubit operator based on a selected initial configuration. An advantage of such systems, computer-implemented methods, and / or computer program products is that they can be implemented to evaluate the performance of the VQE algorithm based on this expected value.

[0026] Usually, the first step is to turn. Figure 1 The one or more embodiments described herein may include one or more devices, systems, and / or apparatuses that can facilitate the performance of one or more quantum operations to facilitate the output of one or more quantum results. For example, Figure 1 A block diagram of an example non-restricted system 100 capable of performing quantum tasks is shown.

[0027] Quantum system 101 (e.g., quantum computer system, superconducting quantum computer system, etc.) may employ quantum algorithms and / or quantum circuits (including computational components and / or devices) to perform quantum operations and / or functions on input data to produce results that can be output to an entity. Quantum circuits may include quantum bits, such as multi-qubit qubits, physical circuit-level components, higher-level components, and / or functions. Quantum circuits may include physical pulses that may be structured (e.g., arranged and / or designed) to perform desired quantum functions and / or computations on data (e.g., input data and / or intermediate data derived from the input data) to produce one or more quantum results as output. Quantum results, such as quantum measurement 111, may respond to quantum job request 104 and associated input data, and may be at least partially based on the input data, quantum functions, and / or quantum computations.

[0028] In one or more embodiments, quantum system 101 may include one or more quantum components, such as quantum computing component 103, quantum processor 106, and quantum logic circuit 109, which includes one or more qubits (e.g., qubits 107A, 107B, and / or 107C), also referred to herein as qubit devices 107A, 107B, and 107C. Quantum processor 106 may be any suitable processor, such as one capable of controlling qubit coherence. Quantum processor 106 may generate one or more instructions for controlling one or more processes of quantum computing component 103.

[0029] Quantum operation component 103 can receive (e.g., download, receive, search, etc.) a quantum job request 104 requesting the execution of one or more quantum programs. Quantum operation component 103 can determine one or more quantum logic circuits, such as quantum logic circuit 109, for executing the quantum programs. Request 104 can be provided in any suitable format, such as text, binary, and / or another suitable format. In one or more embodiments, request 104 can be received by components other than those of quantum system 101, such as components of classical systems coupled to and / or communicating with quantum system 101.

[0030] Quantum operation unit 103 can perform one or more quantum processes, calculations, and / or measurements to manipulate one or more quantum circuits on one or more qubits 107A, 107B, and / or 107C. For example, quantum operation unit 103 can operate one or more qubit effectors, such as qubit oscillators, harmonic oscillators, pulse generators, etc., to induce one or more pulses to stimulate and / or manipulate the state of one or more qubits 107A, 107B, and / or 107C included in quantum system 101. That is, quantum operation unit 103, such as when combined with quantum processor 106, can perform quantum logic circuit operations on one or more qubits (e.g., qubits 107A, 107B, and / or 107C) of that circuit. Quantum operation unit 103 can output one or more quantum job results, such as one or more quantum measurements 111, in response to quantum job request 104.

[0031] It should be understood that the following description refers to the operation of a single quantum program arising from a single quantum job request. However, it will also be understood that one or more processes described herein can be scalable, such as executing one or more quantum programs and / or quantum job requests in parallel with each other.

[0032] In one or more embodiments, the non-limiting system 100 may be a hybrid system and therefore may include both one or more classical systems (such as a quantum program implementation system) and one or more quantum systems (such as quantum system 101). In one or more other embodiments, quantum system 101 may operate separately from but in combination with classical systems.

[0033] In this context, one or more communications between one or more components of the non-limiting system 100 and the classical system can be facilitated by wired and / or wireless means, including but not limited to cellular networks, wide area networks (WANs) (e.g., the Internet), and / or local area networks (LANs). Suitable wired or wireless technologies used to facilitate communications may include, but are not limited to, Wi-Fi, Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Global Microwave Access Interoperability (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3GPP Long Term Evolution (LTE), 3GPP2 Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and / or traditional telecommunications technologies. Session Initiation Protocol (SIP) RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 on low power wireless domain networks), Z-Wave, ANT, ultra-wideband (UWB) standard protocol and / or other proprietary and / or non-proprietary communication protocols.

[0034] Figure 2 and Figure 3 Block diagrams of example non-limiting systems 200 and 300 are shown, which can facilitate multi-reference parallelization of variational quantum computation to achieve high accuracy with short circuit depth. Systems 200 and 300 may each include a parallelized system 201. Figure 2 The parallelized system 201 of the system 200 depicted may include a memory 202, a processor 203, an experimental component 204, a quantum system 101, and / or a bus 218. Figure 3 The parallelization system 201 of the system 300 depicted may also include desired components 305 and / or optimization components 306.

[0035] It should be understood that the embodiments of this subject matter depicted in the various accompanying drawings are for illustrative purposes only, and therefore, the architecture of such embodiments is not limited to the systems, devices, and / or components described herein. For example, in some embodiments, system 200, system 300, and / or parallelized system 201 may also include the operating environment 1000 referenced herein and Figure 10 Various computers and / or computing-based elements are described. In several embodiments, such computers and / or computing-based elements can be combined to achieve integration. Figure 1 , Figure 2 , Figure 3 Used by one or more systems, devices, components and / or computers that implement operations as shown and described in the other accompanying drawings disclosed herein.

[0036] Memory 202 may store one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 203 (e.g., a classical processor, a quantum processor, and / or another type of processor), facilitate the execution of operations defined by the executable components and / or instructions. For example, memory 202 may store computer- and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 203, facilitate the execution of various functions described herein related to parallelization system 201, trial component 204, desired component 305, optimization component 306, quantum system 101, and / or another component associated with parallelization system 201.

[0037] Memory 202 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), and / or another type of volatile memory) and / or non-volatile memory that may employ one or more memory architectures (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and / or another type of non-volatile memory). Further examples of memory 202 are provided below with reference to system memory 1016 and... Figure 10 To describe it, such an example of memory 202 can be used to implement any embodiment disclosed in this subject matter.

[0038] Processor 203 may include one or more types of processors and / or electronic circuitry (e.g., classical processors, quantum processors, and / or other types of processors and / or electronic circuitry) that can implement one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions that can be stored on memory 202. For example, processor 203 may perform various operations that can be specified by such computer- and / or machine-readable, writable, and / or executable components and / or instructions, including but not limited to logic, control, input / output (I / O), arithmetic, etc. In some embodiments, processor 203 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system-on-a-chip (SoC), array processors, vector processors, quantum processors, and / or other types of processors. Further examples of processor 203 are described below with reference to processing unit 1014 and... Figure 10 To describe. Such an example of processor 203 can be used to implement any embodiment disclosed in this subject matter.

[0039] Parallelization system 201, memory 202, processor 203, experimental component 204, desired component 305, optimization component 306, quantum system 101, and / or another component of parallelization system 201 as described herein may be communicatively, electrically, operatively, and / or optically coupled to each other via bus 118 to perform the functions of system 200, system 300, parallelization system 201, and / or any component coupled thereto. Bus 218 may include one or more memory buses, memory controllers, peripheral buses, external buses, local buses, quantum buses, and / or another type of bus that may employ various bus architectures. Further examples of bus 218 are referenced below to system bus 1018 and... Figure 10 To describe. Such an example of bus 218 can be used to implement any embodiment disclosed in this subject matter.

[0040] Parallelization system 201 may include any type of components, machinery, facilities, devices, and / or instruments, including processors and / or devices capable of effective and / or operable communication with wired and / or wireless networks. All of these embodiments are foreseeable. For example, parallelization system 201 may include server equipment, computing devices, general-purpose computers, special-purpose computers, quantum computing devices (e.g., quantum computers), tablet computing devices, handheld devices, server-type computing machines and / or databases, laptop computers, notebook computers, desktop computers, cellular phones, smartphones, consumer appliances and / or instruments, industrial and / or commercial equipment, digital assistants, multimedia internet-enabled telephones, multimedia players, and / or other types of devices.

[0041] Parallelization system 201 can be coupled to one or more external systems, sources, and / or devices (e.g., classical and / or quantum computing devices, communication devices, and / or other types of external systems, sources, and / or devices) using wires and / or cables (e.g., communication ground, electrical ground, operational ground, optical ground, and / or via another type of coupling). For example, parallelization system 201 can be coupled to one or more external systems, sources, and / or devices (e.g., classical and / or quantum computing devices, communication devices, and / or other types of external systems, sources, and / or devices) using data cables (e.g., communication ground, electrical ground, operational ground, optical ground, and / or via another type of coupling), including but not limited to high-definition multimedia interface (HDMI) cables, recommended standard (RS) 232 cables, Ethernet cables, and / or other data cables.

[0042] In some embodiments, the parallelization system 201 may be coupled to one or more external systems, sources, and / or devices (e.g., classical and / or quantum computing devices, communication devices, and / or other types of external systems, sources, and / or devices) via a network (e.g., communicative ground, electrical ground, operational ground, optical ground, and / or via another type of coupling). For example, such a network may include wired and / or wireless networks, including but not limited to cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). The parallelized system 201 can communicate with one or more external systems, sources, and / or devices, such as computing devices, using virtually any desired wired and / or wireless technology, including but not limited to: Wi-Fi, GSM, UMTS, WiMAX, Enhanced General Packet Radio Service (Enhanced GPRS), 3GPP Long Term Evolution (LTE), 3GPP2 Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and / or traditional telecommunications technologies. Session Initiation Protocol (SIP) RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over low-power wireless domain networks), Z-Wave, ANT, ultra-wideband (UWB) standard protocol and / or other proprietary and non-proprietary communication protocols. Therefore, in some embodiments, the parallelization system 201 may include hardware (e.g., a central processing unit (CPU), transceiver, decoder, quantum hardware, quantum processor and / or other hardware), software (e.g., sets of threads, sets of processes, executing software, quantum pulse scheduling, quantum circuits, quantum gates and / or other software), or a combination of hardware and software that facilitates the transfer of information between the parallelization system 201 and external systems, sources and / or devices (e.g., computing devices, communication devices and / or another type of external system, source and / or device).

[0043] Parallelization system 201 may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 203 (e.g., a classical processor, a quantum processor, and / or another type of processor), facilitate the execution of operations defined by such components and / or instructions. Furthermore, in many embodiments, as described herein with or without reference to the various accompanying drawings disclosed herein, any component associated with parallelization system 201 may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 203, facilitate the execution of operations defined by such components and / or instructions. For example, experimental component 204, desired component 305, optimization component 306, quantum system 101, and / or any other component associated with the parallelization system 201 disclosed herein (e.g., communicatively, electronically, operatively, and / or optically coupled to and / or employed by the parallelization system 201) may include such computer and / or machine-readable, writable, and / or executable components and / or instructions. Therefore, according to many embodiments, the parallelization system 201 and / or its associated components as disclosed herein may employ processor 203 to execute such computer and / or machine-readable, writable, and / or executable components and / or instructions to facilitate the execution of one or more operations described herein with reference to the parallelization system 201 and / or any such associated components.

[0044] Parallelization system 201 can facilitate (e.g., via processor 203) the execution of operations performed by experimental component 204, desired component 305, optimization component 306, quantum system 101, and / or another component associated with parallelization system 201 disclosed herein. For example, as described in detail below, parallelization system 201 can facilitate (e.g., via processor 203) the preparation of multi-reference experimental states based on qubit operators by applying unitary circuit operators to the sum of selected initial configurations. In another example, as described in detail below, parallelization system 201 can also facilitate (e.g., via processor 203) the computation of desired values ​​of qubit operators based on selected initial configurations.

[0045] Experimental component 204 can prepare a multi-reference experimental state based on qubit operators by applying unitary circuit operators to the sum of selected initial configurations. As referenced herein, an "experimental state" is a state prepared by the quantum circuit to approximate the ground state of the molecule. For example, experimental component 204 can receive the molecule to approximate its ground state. Experimental component 204 can then signal the quantum circuit to encode the fermionic molecular Hamiltonian of the molecule into the qubit operators. In one embodiment, experimental component 204 can signal the quantum system 101 to encode the fermionic molecular Hamiltonian. In another embodiment, experimental component 204 may include quantum hardware and / or a quantum simulator to encode the fermionic molecular Hamiltonian.

[0046] As defined herein, a “multi-reference experimental state” is an experimental state comprising multiple initial configurations for a quantum circuit, as opposed to a “single-reference experimental state” comprising a single initial configuration for a quantum circuit. In embodiments, a multi-reference experimental state can be prepared by applying a unitary circuit operator to the sum of selected initial configurations. It should be understood that the multi-reference nature of the experimental state is achieved due to the sum of multiple initial configurations. In the example, the unitary circuit operator can be a parameterized quantum circuit, and the initial configuration can be a series of single determinant states and corresponding complex amplitudes. In embodiments, classical preprocessing can be used to select the initial configuration and parameter set of the parameterized circuit. For example, experimental component 204 can receive as input the initial configuration and initial parameter set of the experimental state that can subsequently be passed to quantum system 101 to generate fermionic Hamiltonians. In embodiments, this parameter set can be input by a user, or in another embodiment, experimental component 204 can select the parameter set based on a default set. In yet another embodiment, experimental component 204 can select the parameter set based on feedback from optimization component 306, which is discussed in detail below. In embodiments, the initial configuration can be selected based on the application type. For example, if the parallelized system 201 is performing a VQE application related to quantum chemistry, the initial configuration could be a set of single-excitation Slater determinants starting from a reference Hartree-Frock state. In another embodiment, the trial component 204 can select the number of initial configurations to include in the trial state. For example, given a relatively simple molecule to simulate, fewer initial configurations can be used, and a relatively low number of initial configurations can be selected. Conversely, given a relatively complex molecule to simulate, more initial configurations can be used, and a relatively high number of initial configurations can be selected. In yet another embodiment, the number of selected initial configurations can be determined based on the number of qubits in the parameterized circuit. For example, the number N of selected initial configurations... c It can be achieved through factor O(N) 2 ) to scale, where N is the number of qubits in the parameterized circuit.

[0047] In this embodiment, the test component 204 can define the multi-reference test state generated by the quantum circuit as:

[0048]

[0049] Where c i It is a complex amplitude, U(θ) is a parameterized quantum circuit with parameter θ, |ψ i > is a single-row determinant state, and N c This refers to the number of initial configurations. For example, test component 204 can receive parameterized circuits and parameters U(θ), ​​and a single-excitation Slater determinant |ψ. i >Set, complex amplitude c i The number of sets and initial configurations N c As input, as described above, the experimental component 204 can then define the experimental state by inserting the selected values ​​into the formula shown above. The experimental component 204 can then pass this definition of the multi-reference experimental state to the quantum system 101 to prepare the experimental state for the encoded molecule. In another embodiment, the experimental component 204 can pass the definition of the multi-reference experimental state to a quantum simulator, which can prepare the experimental state for the encoded molecule. It should be understood that by preparing multiple reference experimental states, the parallelized system 201 can achieve high accuracy with a shorter circuit depth than using a single-reference experimental state, because different configurations from unitary U... j and U i Instead of applying longer quantum circuits, such as U, the wave function is introduced in parallel. j and U i The sequence is as described below. Figure 6 and Figure 7 As shown.

[0050] The expectation component 305 can calculate the expectation value of the qubit operator based on the selected initial configuration. As mentioned above, the target of the variable quantum eigenvalue solver is to approximate the molecule in its ground state. Therefore, the expectation value or energy of the qubit operator can be used to evaluate the performance of the variable quantum eigenvalue solver. For example, the expectation component 305 can measure all qubits in circuit U(θ) after using circuit U(θ) to facilitate the reinitialization of the circuit using the new experimental state. This can be done by signaling the quantum system 101 to measure the qubits in circuit U(θ). Since the Hamiltonian is an operator that fully defines the quantum circuit, this measurement can be used to determine the Hamiltonian. This measurement can be used in conjunction with a cost function to determine the expectation value of the qubit operator, which is encoded with the fermionic Hamiltonian of the molecule in question. In an embodiment, the expectation component 305 can calculate the expectation value of the fermionic Hamiltonian using the following formula:

[0051]

[0052] Where H is the fermion Hamiltonian, and ψ i and ψ j This is the initial configuration, and U(θ) is a parameterized circuit with parameter θ. The formula can be operationally transformed into:

[0053]

[0054] Where |vac represents the vacuum state (all qubits in circuit U(θ) are in the zero state), and U j and U i It is the unitary form of the parameterized circuit U(θ). In the embodiment, it is desirable that component 305 can assume the unitary U. j and U i Only by creating the initial state |ψ i The short initial sub-circuits of U are different from each other. This assumption allows for a significant simplification of the circuit U(θ) because different configurations from U... j and U i Instead of applying a longer quantum circuit, the wavefunction is introduced in parallel. In one embodiment, the desired value can be calculated using classical hardware by the desired component 305. In another embodiment, the desired value can be calculated on quantum hardware or a quantum simulator by the desired component 305. For example, the desired component 305 can signal the quantum system 101 to calculate the desired value using the formula described above. In this example, an extended quantum register containing auxiliary qubits can be used to calculate the desired value, where the auxiliary qubits control the wavefunction. j and U i Activation.

[0055] The optimization component 306 can optimize the parameters of the parameterized circuit based on the expectation value of the qubit operator. In the case of the Hamiltonian of the fermion molecule, the lowest eigenstate of the Hamiltonian corresponds to the ground state of the molecule encoded in the Hamiltonian of the fermion molecule. Furthermore, the eigenstate depends on the expectation value of the qubit operator containing the Hamiltonian. Therefore, the minimized expectation value corresponds to the lowest eigenstate, and thus the ground state of the molecule. In this way, the optimization component 306 can optimize the parameters of the parameterized circuit by selecting parameters to minimize the expectation value generated by the cost function described in detail by the reference expectation component 305. To achieve this optimization, the optimization component 306 can use classical optimization techniques, such as batch gradient descent, stochastic gradient descent, mini-batch gradient descent, or any other optimization technique applicable in conjunction with the cost function. Examples of optimization algorithms that the optimization component 306 can use include Adam, RMSprop, Adagrad, or another applicable algorithm. Once the optimization component 306 has selected a new set of parameters for the parameterized circuit based on one of the above optimization methods, the optimization component 306 can signal the test component 204 to prepare a new test state using the new parameters. The expected value of the new test state can then be calculated by the expected value, which can be used by the optimization component 306 to optimize again.

[0056] It should be understood that the cycle of preparing experimental states, evaluation, and optimization can be repeated in multiple iterations. For example, in one embodiment, the cycle may run a set number of iterations. In another example, the cycle may run until a performance threshold is reached. For example, in one embodiment, the optimization unit 306 may store a record of the expected value for each iteration of the cycle. When the optimization unit 306 receives the expected value from the expectation unit 305, the optimization unit 306 may compare the expected value with the expected value from the previous iteration. If the decrease between the expected value and the previous expected value is less than or equal to the performance threshold, further optimization may not provide a significant improvement in the accuracy of the molecular ground state representation, and the optimization unit 306 may signal to the parallelization system 201 not to perform further iterations of the cycle.

[0057] It should be understood that by using the multi-reference experimental states and cost function described in detail above, the depth and complexity of the parameterized circuitry used in the variational quantum eigenvalue solver can be significantly reduced while still maintaining accuracy. Due to limitations on the depth and complexity of quantum hardware, this allows variational quantum computations to be performed on simpler quantum hardware, and also allows for more efficient execution of more complex computations. For example, as described further below, the parallelized system 201 can achieve similar results on circuitry that is four times shorter than other variational quantum computation systems.

[0058] Figure 4A flowchart of an example non-limiting computer implementation of a method 400, which facilitates the parallelization of variational quantum eigenvalue solvers with high accuracy and short circuit depth according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0059] At 410, the computer-implemented method 400 may include receiving molecules to simulate their ground state by a system (e.g., parallelization system 201 and / or experimental component 204) operatively coupled to a processor (e.g., processor 203). For example, as referenced above... Figure 2 The test component 204 can receive molecules to simulate its ground state, in this case, water molecules.

[0060] At 420, the computer-implemented method 400 may include encoding the fermionic molecular Hamiltonian of a molecule into a qubit operator by a system (e.g., parallelization system 201 and / or experimental component 204).

[0061] At 430, the computer-implemented method 400 may include preparing multi-reference experimental states by a system (e.g., parallelization system 201 and / or experimental component 204) based on qubit operators. For example, as referenced above... Figure 2 and Figure 3 The test component 204 can define the test state as a unitary circuit operator, such as a parameterized circuit, applied to the sum of selected initial configurations, such as a single determinant state. The test component 204 can then pass the definition of the test state to the quantum system 101, which can use the parameterized circuit to prepare the test state.

[0062] At 440, the computer-implemented method 400 may include the calculation of the desired value of the qubit operator by a system (e.g., parallelized system 201 and / or desired component 305) based on a selected initial configuration. For example, as referenced above. Figure 2 and Figure 3 The desired component 305 can request measurements of all qubits in the parameterization circuit from the quantum system 101 after the test state is ready. The desired component 305 can then use these measurements and a cost function to calculate the desired value. In an embodiment, the calculation of the desired value can be performed on quantum hardware by the quantum system 101 or directly by the desired component 305, using extended quantum registers and auxiliary qubits.

[0063] At 450, the computer-implemented method 400 may include a system (e.g., parallelization system 201 and / or optimization component 306) determining whether the desired value has been minimized. (See above reference...) Figure 2 and Figure 3The molecule reaches its ground state when its eigenvalues ​​are at their lowest points, which is achieved by minimizing the expected value. For example, optimization component 306 can use the expected value calculated by expected component 305 to determine whether the expected value differs from a previous expected value that is less than or equal to a threshold. In another embodiment, optimization component 306 can determine whether to continue the optimization loop based on the number of iterations performed.

[0064] At 460, the computer-implemented method 400 may include optimizing the parameters of a parameterized circuit based on the expected value of a qubit operator by a system (e.g., parallelization system 201 and / or optimization component 306). For example, as referenced above... Figure 2 and Figure 3 The optimization component 306 can pass the expected value to an optimization method, such as a stochastic gradient descent optimizer, to generate a new set of parameters for a parameterization circuit that produces a lower expected value, thereby generating an experimental state closer to the molecular ground state. The optimization component 306 can then pass this new parameter set to the experimental component 204 and signal the experimental component 204 to prepare a new experimental state using the new parameters. This process of preparing the experimental state, measuring the expected value, and optimizing the parameters can be repeated through multiple iterations.

[0065] Figure 5A Figure 500 illustrates a non-limiting example of a parameterized circuit that can facilitate the parallelization of variational quantum computation with high accuracy and short circuit depth according to one or more embodiments described herein.

[0066] Figure 500 includes two parameterized circuits, a linear circuit 510 and a full circuit 520. The linear circuit 510 has a depth of 12 controlled NOT (CNOT) quantum gates, while the full circuit 520 has a depth of 24 CNOT quantum gates. Additionally, a third quantum circuit, the full circuit d2, is shown, with a depth of 48 CNOT quantum gates.

[0067] Figure 5B A graph 530 shows a comparison between the performance of measuring the dissociation of hydrogen molecules using a multi-reference test state and a single-reference test state according to one or more embodiments described herein.

[0068] Since the energies of the dissociation of hydrogen molecules or the different bond lengths between hydrogen atoms are known, it is used as an effective test. The y-axis of Graph 530 shows the energies between hydrogen atoms, while the x-axis shows the iterations of the variable quantum eigenvalue solver. Here, the black curves presented on Graph 530 show the ideal performance based on known values. Graph 530 includes four tests: multi_lin_d1, which is a multi-reference test state prepared on linear circuit 510 and is shown as blue xs; multi_full_d1, which is a multi-reference test state prepared on full circuit 520 and is shown as orange circles; sing_full_d1, which is a single-reference test state prepared on full circuit 520 and is shown as green squares; and sing_full_d2, which is a single-reference test state prepared on full circuit d2 and is shown as red triangles. As shown in the figure, `mult_full_d1` has a higher accuracy than `sing_full_d1`, even though both `mult_full_d1` and `sing_full_d1` are prepared using the same parameterized circuitry. Furthermore, despite using half the circuit depth of `sing_full_d1` (12 CNOT gates vs. 24 CNOT gates), `mult_lin_d1` has improved accuracy compared to `sing_full_d1`, as shown in Figure 530. Moreover, as shown in Figure 530, despite using a circuit with a depth four times shorter (12 CNOT gates vs. 48 CNOT gates), `mult_lin_d1` has the same accuracy as `sing_full_d2`.

[0069] It should be understood that even in the relatively simple variational computation example described above, using a multi-reference trial state enables improved computational accuracy while simultaneously enabling a reduction in circuit depth, compared to a single-reference trial state. Furthermore, it should be understood that, due to the reduced circuit depth, a multi-reference trial state can allow problems that cannot be performed on quantum hardware due to hardware limitations (such as circuit depth) to be performed on current hardware.

[0070] Figure 6 Figure 600 shows a comparison of the performance of modeling Hubbard models on a graphene lattice using a multi-reference experimental state and a single-reference experimental state according to one or more embodiments described herein.

[0071] The Hubbard model is characterized by electrons that can hop between positions in a honeycomb lattice and experience Coulomb repulsion, defined as V, only when they occupy adjacent positions. The y-axis of Figure 600 represents the difference between the measured expected value and the exact energy of the ground state, while the x-axis represents the Coulomb repulsion of electrons in the model. Figure 600 shows three tests: `mult_full_d1` is a multi-reference test state prepared on 60 controlled X (CX) quantum gates and is shown as a blue circle; `sing_full_d1` is a single-reference test state prepared on 60 CX quantum gates and is shown as an orange square; and `sing_full_d3` is a single-reference test state prepared on 180 CX quantum gates and is shown as a green triangle. As shown in Table 600, mult_full_d1 achieves better accuracy than sing_full_d1 using the same circuit, and achieves at least the same accuracy as sing_full_d3, despite using a circuit with one-third the depth of sing_full_d3 (60 CX gates vs. 180 CX gates).

[0072] Figure 7 A graph 700 shows a comparison of the performance of modeling Hubbard models on a graphene lattice using a multi-reference experimental state and a single-reference experimental state according to one or more embodiments described herein.

[0073] In Figure 700, the y-axis represents the accuracy of the ground state as indicated by fidelity, and the x-axis represents the Coulomb repulsion of electrons in the model. Figure 700 shows three tests: `mult_full_d1` is a multi-reference test state prepared on 60 CX quantum gates and is shown as a blue circle; `sing_full_d1` is a single-reference test state prepared on 60 CX quantum gates and is shown as an orange square; and `sing_full_d3` is a single-reference test state prepared on 180 CX quantum gates and is shown as a green triangle. As shown in Figure 700, neither `sing_full_d1` nor `sing_full_d2` accurately represents the ground state of the Hubbard model because they have very low fidelity. Conversely, `mult_full_d1` achieves high fidelity and thus an accurate representation of the true ground state, despite using a shorter circuit.

[0074] Figure 8 A flowchart of an example non-limiting computer implementation of method 800 according to one or more embodiments described herein is shown, which facilitates multi-reference parallelization of variable quantum computation to achieve high accuracy with short circuit depth. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0075] At 810, the computer-implemented method 800 may include encoding fermion Hamiltonians into qubit operators by a system (e.g., parallelization system 201 and / or experimental component 204) operatively coupled to a processor (e.g., processor 203).

[0076] At 820, the computer-implemented method 800 may include preparing a multi-reference experimental state based on a qubit operator by a system (e.g., parallelized system 201 and / or experimental component 204) by applying a sum of unitary circuit operators to a selected initial configuration. For example, as referenced above... Figure 2 and Figure 3 The test component 204 can define the test state as a unitary circuit operator, such as a parameterized circuit, applied to the sum of selected initial configurations, such as a single determinant state. The test component 204 can then pass the definition of the test state to the quantum system 101, which can use the parameterized circuit to prepare the test state.

[0077] Figure 9 A flowchart of an example non-limiting computer implementation of a method 900, which facilitates multi-reference parallelization of variable quantum computation to achieve high accuracy with short circuit depth, according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0078] At 910, the computer-implemented method 900 may include encoding fermion Hamiltonians into qubit operators by a system (e.g., parallelization system 201 and / or experimental component 204) operatively coupled to a processor (e.g., processor 203).

[0079] At 920, the computer-implemented method 900 may include preparing a multi-reference experimental state based on a qubit operator by a system (e.g., parallelized system 201 and / or experimental component 204) by applying a sum of unitary circuit operators to a selected initial configuration. For example, as referenced above... Figure 2 and Figure 3 The test component 204 can define the test state as a unitary circuit operator, such as a parameterized circuit, applied to the sum of selected initial configurations, such as a single determinant state. The test component 204 can then pass the definition of the test state to the quantum system 101, which can use the parameterized circuit to prepare the test state.

[0080] At 930, the computer-implemented method 900 may include having a system (e.g., parallelized system 201 and / or desired component 305) calculate the desired value of the qubit operator based on a selected initial configuration. For example, as referenced above. Figure 2 and Figure 3The expected value can be used to calculate the energy of the qubit operator and thus determine whether the experimental state is an accurate representation of the ground state of the molecule encoded in the qubit operator.

[0081] At 940, the computer-implemented method 900 may include optimizing the parameters of a parameterized circuit based on the expected value of a qubit operator by a system (e.g., parallelization system 201 and / or optimization component 306). For example, as referenced above. Figure 2 and Figure 3 The optimization component 306 can optimize parameters by adjusting them so that the new experimental state will have a lower expected value. This optimization can be achieved using an optimization algorithm such as a stochastic gradient descent optimizer.

[0082] At 950, the computer-implemented method 900 may include selecting a new test state by a system (e.g., parallelization system 201, optimization component 306, and / or test component 204) based on optimized parameters of a parametric circuit. For example, as referenced above... Figure 2 and Figure 3 The experimental component 204 can define a new experimental state using optimized parameters of the parameterized circuit. The definition of the new experimental state can then be prepared by the quantum system 101, the expected value calculated by the expectation component 305, and the parameters further optimized by the optimization component 306. It should be understood that this cycle can be iterated multiple times to produce better results.

[0083] Parallelization system 201 can provide technical improvements to the systems, devices, components, operational steps, and / or processing steps associated with variational quantum computation and variational quantum eigenvalue solvers. For example, parallelization system 201 can prepare multi-reference trial states based on qubit operators by applying unitary circuit operators to the sum of selected initial configurations. In the above example, it should be understood that parallelization system 201 can reduce the quantum circuit depth used in variational quantum computation by using multi-reference trial states, thereby reducing resource and / or hardware usage by utilizing shorter quantum circuits.

[0084] In the examples above, it should be understood that the parallelization system 201 can provide technological improvements to the processing units associated with the parallelization system 201 and / or the quantum system 101. For example, by reducing the depth of the quantum circuits used in variable quantum computing, complex variable quantum computing tasks can be performed on shorter quantum circuits, thereby reducing the workload of the processing units (e.g., processor 203) and / or the quantum system 101. In these examples, by reducing the workload of such processing units (e.g., processor 203) and / or the quantum system 101, the parallelization system 201 can thereby facilitate improved performance, improved efficiency, and / or reduced computational costs associated with such processing units.

[0085] Furthermore, by reducing circuit depth, the parallelization system 201 can provide a technological improvement over quantum systems when approximating complex molecular systems. Since circuit depth is a limitation of quantum systems, the reduction in circuit depth and the use of multiple reference test states provided by the parallelization system 201 allow quantum systems to approximate complex molecular systems that would otherwise not be approximated using quantum systems with single reference test states. Moreover, by reducing circuit depth, and thus reducing the intensity of quantum computation, the parallelization system 201 enables the use of quantum systems with reduced circuit depth, making it possible to approximate molecular systems with cheaper and / or easier-to-manufacture quantum systems.

[0086] Parallelization system 201 can employ hardware and / or software to solve problems that are inherently highly technical, non-abstract, and cannot be performed as a set of human mental actions. In some embodiments, one or more processes described herein can be executed by one or more dedicated quantum computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, and / or another type of dedicated computer) to perform tasks defined in relation to the various technologies identified above. Parallelization system 201 and / or its components can be used to solve new problems arising from advancements in quantum computing systems, cloud computing systems, computer architectures, and / or other technologies.

[0087] It should be understood that the parallelization system 201 can utilize various combinations of electrical components, mechanical components, and circuits that cannot be replicated in the human mind or performed by a human, because the various operations that can be performed by the parallelization system 201 and / or its components as described herein are operations beyond the capabilities of the human mind. For example, the amount of data processed by the parallelization system 201 in a given time period, the speed at which such data is processed, or the type of data processed can be greater, faster, or different than the amount, speed, or type of data processed by the human mind in the same time period. In another example, one person or even thousands of people cannot execute one or more quantum programs in a time-efficient, accurate, and / or effective manner as facilitated by one or more embodiments described herein. Furthermore, neither the human mind nor humans with pen and paper can electronically execute quantum programs implemented as described in one or more embodiments herein.

[0088] According to several embodiments, the parallelization system 201 may also be fully operable for performing one or more other functions (e.g., fully powered on, fully executed, and / or another function) while simultaneously performing the various operations described herein. It should be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should be understood that the parallelization system 201 may include information that is not manually obtainable by an entity such as a human user.

[0089] For the sake of simplicity, the computer-implemented method is depicted and described as a series of actions. It will be understood and appreciated that the invention is not limited to the actions and / or the order of actions shown; for example, actions may occur in various orders and / or simultaneously, and may occur with other actions not presented and described herein. Furthermore, not all actions shown are necessary to implement the computer-implemented method according to the disclosed subject matter. Additionally, those skilled in the art will understand and appreciate that the computer-implemented method may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the computer-implemented methods disclosed below and throughout this specification can be stored on an article of manufacture to facilitate the transfer and assignment of such computer-implemented methods to a computer. The term "article of manufacture" as used herein is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0090] In order to provide context for the various aspects of the disclosed topic, Figure 10 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 10 A block diagram illustrating an example, non-limiting operating environment that may facilitate one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0091] refer to Figure 10 The suitable operating environment 1000 for implementing various aspects of this disclosure may further include a computer 1012. The computer 1012 may further include a processing unit 1014, system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to the system memory 1016, to the processing unit 1014. The processing unit 1014 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, and / or local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronic Devices (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0092] System memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. The Basic Input / Output System (BIOS), containing basic routines such as those for transferring information between components within computer 1012 during startup, is stored in non-volatile memory 1022. Computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 10 Disk storage 1024 is shown. Disk storage 1024 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Disk storage 1024 may also include a standalone storage medium or a storage medium in combination with other storage media. To facilitate connection of disk storage 1024 to system bus 1018, a removable or non-removable interface, such as interface 1026, is typically used. Figure 10 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1000 is also described. Such software may also include, for example, an operating system 1028. The operating system 1028, which can be stored on disk storage 824, is used to control and allocate the resources of computer 1012.

[0093] System application 1030 utilizes operating system 1028 to manage resources through program modules 1032 and program data 1034 stored, for example, in system memory 1016 or disk storage 1024. It should be understood that this disclosure can be implemented using various operating systems or combinations of operating systems. Users input commands or information into computer 1012 via input device 1036. Input device 1036 includes, but is not limited to, pointing devices such as mice, trackballs, pens, touchpads, keyboards, microphones, joysticks, game controllers, disc satellite antennas, scanners, TV tuners, digital cameras, digital camcorders, network cameras, etc. These and other input devices are connected to processing unit 1014 via system bus 1018 and interface port 1038. Interface port 1038 includes, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1040 uses some of the ports of the same type as input device 1036. Thus, for example, a USB port can be used to provide input to computer 1012 and output information from computer 1012 to output device 1040. Output adapter 1042 is provided to illustrate the existence of certain output devices 1040, such as monitors, speakers, and printers, as well as other output devices 1040 that require dedicated adapters. By way of example and not limitation, output adapter 1042 includes graphics cards and sound cards that provide a connection between output devices 1040 and the system bus 1018. It should be noted that other devices and / or systems that provide both input and output capabilities, such as remote computer 1044, are also included.

[0094] Computer 1012 can operate in a networked environment using logical connections to one or more remote computers (such as remote computer 1044). Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other common network node, and typically may also include many or all of the elements described relative to computer 1012. For simplicity, only memory storage device 846 is shown alongside remote computer 1044. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and then physically connected via communication connection 1050. Network interface 1048 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, and / or other wired and / or wireless communication networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks like Integrated Services Digital Network (ISDN) and its variants, packet-switched networks, and digital subscriber lines (DSL). Communication connection 1050 refers to the hardware / software used to connect network interface 1048 to system bus 1018. Although communication connection 1050 is shown as being inside computer 1012 for clarity, it can also be external to computer 1012. For illustrative purposes only, the hardware / software used to connect to network interface 1048 may also include internal and external technologies such as modems including conventional telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0095] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures on which instructions are recorded, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0096] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of the invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information of the computer-readable program instructions.

[0097] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of manufacture comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operations to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a non-consecutive order as shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0099] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure may also be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, and / or other program modules that perform a particular task and / or implement a particular abstract data type. Furthermore, those skilled in the art will understand that the computer implementation methods of the present invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked via a communication network. However, some, if not all, aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in local and remote memory storage devices. For example, in one or more embodiments, the computer-executable component may be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms "memory" and "memory cell" are used interchangeably. Furthermore, one or more embodiments described herein can execute code of a computer executable component in a distributed manner, for example, multiple processors combined or cooperating to execute code from one or more distributed memory cells. As used herein, the term "memory" can encompass a single memory or memory cell at one location or multiple memories or memory cells at one or more locations.

[0100] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities related to an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, an application running on a server and a server itself can both be components. One or more components may reside within a process and / or a thread of execution, and components may be located on a single computer and / or distributed across two or more computers. In another example, a corresponding component may be executable from various computer-readable media on which various data structures are stored. These components may communicate via local and / or remote processes, for example, based on signals having one or more data packets (e.g., data from a component via which it interacts with a local system, another component in a distributed system, and / or with other systems via a network such as the Internet). As another example, a component can be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a component can be a device that provides specific functions through electronic parts rather than mechanical parts, wherein the electronic parts can include a processor or other device to execute software or firmware that at least partially endows the electronic parts with the functions. In one aspect, the component can be emulated via a virtual machine, for example within a cloud computing system.

[0101] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to indicate any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Furthermore, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and figures should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. To avoid ambiguity, the subject matter disclosed herein is not limited to these examples. Moreover, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0102] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can employ nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "database," and substantially any other information storage component related to the operation and function of a component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may be used as external cache memory. For example, by way of illustration and not limitation, RAM may be available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0103] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components or computer-implemented methods in order to describe this disclosure; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a similar manner to how the term "comprising" is interpreted when used as a transitional word in the claims.

[0104] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system comprising: Memory, which stores executable components of a computer; A processor that executes at least one of the computer-executable components, wherein the at least one computer-executable component: Encoding the Hamiltonian of fermionic molecules into qubit operators; and A multi-reference experimental state is prepared based on the qubit operator by applying a unitary circuit operator to the sum of the selected initial configurations.

2. The system according to claim 1, wherein the multi-reference test state includes: Among them, c i It is the complex amplitude, U(θ) is the parameterized quantum circuit, and N is the complex amplitude. c It is the number of initial configurations selected. This indicates the selected initial configuration, and It is a single-row columnar configuration.

3. The system according to claim 2, wherein the at least one computer-executable component further comprises: The expected value of the qubit operator is calculated based on the selected initial configuration.

4. The system according to claim 3, wherein the expected value is defined as: in, All qubits are in a zero state, H is the Hamiltonian, and the auxiliary qubits control the unitary U. j and U i Activation.

5. The system according to claim 2, wherein It is a set of Slater determinants.

6. The system of claim 3, wherein the at least one computer-executable component further comprises: The parameters of the parameterized quantum circuit are optimized based on the expected value of the quantum bit operator; and New experimental states are selected based on the optimized parameters of the parameterized quantum circuit.

7. A computer-implemented method, comprising: The system, which is operatively coupled to the processor, encodes the Hamiltonian of the fermion molecule into a qubit operator; and The system prepares a multi-reference experimental state based on the qubit operator by applying unitary circuit operators to the sum of selected initial configurations.

8. The computer-implemented method according to claim 7, wherein the multi-reference test state includes: Among them, c i It is the complex amplitude, U(θ) is the parameterized quantum circuit, and N is the complex amplitude. c It is the number of initial configurations selected. This indicates the selected initial configuration, and It is a single-row columnar configuration.

9. The computer-implemented method according to claim 8, further comprising: The system calculates the expected value of the qubit operator based on the selected initial configuration.

10. The computer-implemented method according to claim 9, wherein the expected value is defined as: in, All qubits are in a zero state, H is the Hamiltonian, and the auxiliary qubits control the unitary U. j and U i Activation.

11. The computer-implemented method according to claim 8, wherein... It is a set of Slater determinants.

12. The computer-implemented method according to claim 9, further comprising: The system optimizes the parameters of the parameterized quantum circuit based on the expected value of the qubit operator; as well as The system selects a new experimental state based on the optimized parameters of the parameterized quantum circuit.

13. A computer program product comprising program instructions executable by a processor to cause the processor to: The processor encodes the Hamiltonian of the fermion molecule into the qubit operator; and The processor prepares a multi-reference experimental state based on the qubit operator by applying unitary circuit operators to the sum of the selected initial configurations.

14. The computer program product of claim 13, wherein the multi-reference test state includes: Among them, c i It is the complex amplitude, U(θ) is the parameterized quantum circuit, and N is the complex amplitude. c It is the number of initial configurations selected. This indicates the selected initial configuration, and It is a single-row columnar configuration.

15. The computer program product of claim 14, wherein the program instructions are further executable by the processor to cause the processor to: The processor calculates the expected value of the qubit operator based on the selected initial configuration.

16. The computer program product of claim 15, wherein the expected value is defined as: in, All qubits are in the zero state, H is the Hamiltonian, and the auxiliary qubits control the unitary U. j and U i Activation.

17. The computer program product according to claim 14, wherein It is a set of Slater determinants.

18. The computer program product of claim 15, wherein the program instructions are further executable by the processor to cause the processor to: The processor optimizes the parameters of the parameterized quantum circuit based on the expected value of the qubit operator; and The processor selects a new experimental state based on the optimized parameters of the parameterized quantum circuit.

19. A system comprising modules for performing the steps of the method according to any one of claims 7-12.

Images