Disc device

Abstract

A disk drive device is provided that improves the reliability of information recorded on the disk. According to one embodiment, a disk drive device is provided comprising a disk, a head, a preamplifier, and a controller. The head writes information to the disk based on a write current. The preamplifier supplies write current to the head. The controller enables the preamplifier to perform zero-current control. Zero-current control is control that maintains the amplitude of the write current at zero. The controller can vary the time for maintaining the amplitude of the write current at zero according to the pattern of the written data.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-203755 (filed on December 15, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a disk device. Background Technology

[0003] In a disk drive comprising a preamplifier, a writing head, and a disk, the preamplifier supplies a write current to the writing head, which then records information onto the disk based on the write current. In this case, it is desirable to improve the reliability of the information recorded on the disk. Summary of the Invention

[0004] One implementation involves providing a disk device capable of improving the reliability of information recorded on the disk.

[0005] According to one embodiment, a disk device is provided having a disk, a head, a preamplifier, and a controller. The head writes information to the disk based on a write current. The preamplifier supplies write current to the head. The controller enables the preamplifier to perform zero-current control. Zero-current control is control that maintains the amplitude of the write current at zero. The controller can vary the duration for which the amplitude of the write current is maintained at zero based on the pattern of the written data. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating the configuration of the disk device involved in the implementation method.

[0007] Figure 2 This is a diagram showing the configuration of the disk in the implementation method.

[0008] Figure 3 (a) and (b) are waveforms representing the operation of the MPRZ (Main Pole Relaxation Zone) mode in the implementation method.

[0009] Figure 4 This is a graph showing the relationship between current zero time and bit error rate (outer perimeter region) for each data mode.

[0010] Figure 5 This is a graph showing the relationship between current zero time and bit error rate for each data mode (mid-cycle region).

[0011] Figure 6 This is a graph showing the relationship between the current zero time and the bit error rate (inner peripheral region) for each data mode.

[0012] Figure 7 This is a diagram showing the configuration of the RWC and preamplifier in the implementation method.

[0013] Figure 8 (a) to (c) are waveform diagrams representing the zero-current control in the implementation method.

[0014] Figure 9 This is a diagram showing the switching information of zero current control in a modified embodiment of the implementation.

[0015] Figure 10 (a) to (f) are waveform diagrams showing the switching of zero current control in a modified embodiment.

[0016] Label Explanation

[0017] 1 disc device, 10 discs, 15 heads, 30 preamplifiers, 130 controllers. Detailed Implementation

[0018] Hereinafter, the disk device according to the embodiments will be described in detail with reference to the accompanying drawings. However, this invention is not limited to these embodiments.

[0019] (Implementation Method)

[0020] The disk device involved in the implementation includes a preamplifier, a head, and a disk. The preamplifier flows a write current to the head, and the head records information to the disk according to the write current, but efforts are made to improve the reliability of the information recorded on the disk.

[0021] For example, Figure 1 As shown, disk device 1 is connected to host 100 in a communicable manner and functions as an external storage medium for host 100. Figure 1 This diagram illustrates the configuration of disk drive 1. The host 100 is, for example, an information terminal such as a computer. The disk drive 1 is, for example, a disk-type storage medium such as an HDD (Hard Disk Drive) or an optical disk drive.

[0022] The disk drive 1 includes a head disk assembly (HDA) 2, a driver 20, a preamplifier 30, volatile memory 70, non-volatile memory 80, buffer memory 90, and a controller 130. The driver 20 can be configured as an integrated circuit (IC). The preamplifier 30 can be configured as an integrated circuit (IC). The controller 130 can be configured as a system-on-a-chip (SoC). The controller 130 is electrically connected to the driver 20, the preamplifier 30, the volatile memory 70, the non-volatile memory 80, and the buffer memory 90.

[0023] The HDA2 has a disc 10, a spindle motor (SPM) 12, a head 15, an arm 13, and a voice coil motor (VCM) 14.

[0024] like Figure 2As shown, disk 10 is a roughly disk-shaped medium used for recording information. Figure 2 This is a top view showing the configuration of disk 10. Disk 10 is rotatably supported on a frame (not shown) via a spindle. Disk 10 can be either a magnetic disk or an optical disk. The following primarily illustrates the case where disk 10 is a magnetic disk. Disk 10 has multiple concentric tracks TR defined radially in each recording surface by servo information pre-written into radial servo areas. The area between the servo areas in each recording surface of disk 10 is a data area where data can be written. Each track TR contains one or more groups of servo areas and data areas in the circumferential direction.

[0025] Multiple tracks (TRs) can be divided into multiple regions based on their radial positions. These regions can include an inner peripheral region (IR), a middle peripheral region (MR), and an outer peripheral region (OR). The inner peripheral region (IR) includes tracks (TRs) whose radial positions are located inside the radial direction. The middle peripheral region (MR) includes tracks (TRs) whose radial positions are located between the inner and outer sides of the radial direction. The outer peripheral region (OR) includes tracks (TRs) whose radial positions are located outside the radial direction.

[0026] return Figure 1 The head 15 is mounted on one end of the arm 13. The other end of the arm 13 is rotatably supported on the shaft 17. The SPM 12 can rotate the disk 10 around the spindle. The VCM 14 can rotate the arm 13 around the shaft 17. The arm 13 and VCM 14 function as actuators 3. Actuators 3 can move the head 15 radially relative to the surface of the disk 10.

[0027] The head 15 has a write head 15W and a read head 15R. The write head 15W writes information to the disk 10 according to the write current supplied from the preamplifier 30. The read head 15R reads the information written to the disk 10 and provides it to the preamplifier 30.

[0028] The controller 130 performs overall control of the disk device 1 according to firmware pre-stored in the non-volatile memory 80 or the disk 10. The firmware includes initial firmware and control firmware used in normal operation. The initial firmware, which is first executed upon startup, is stored in the non-volatile memory 80, and the control firmware used in normal operation is recorded on the disk 10. Under control according to the initial firmware, the firmware is temporarily read from the disk 10 into the buffer memory 90 and then saved in the volatile memory 70.

[0029] The controller 130 is communicatively connected to the host 100 and, during normal operation, can perform control corresponding to commands received from the host 100. The controller 130 includes a read / write channel (RWC) 60, a microprocessor (MPU) 40, and a hard disk controller (HDC) 50. The RWC 60, MPU 40, and HDC 50 are electrically connected to each other.

[0030] The driver 20 controls the driving of SPM12 and VCM14 respectively under the control of MPU40.

[0031] The preamplifier 30 includes a read amplifier 31 and a write driver 32. The read amplifier 31 amplifies the read signal read from the disk 10 via the head 15 and provides it to the RWC 60. The write driver 32 flows a write current to the head 15 corresponding to the data signal received from the RWC 60. The preamplifier 30 is electrically connected to the head 15 and the RWC 60 via wiring or the like.

[0032] MPU40 controls various parts of the disk drive 1. MPU40 receives a read command containing a read address from the host 100 via HDC50, and controls the read process for reading information from the location within the disk 10 corresponding to the read address. In controlling the read process, MPU40, based on the read address, controls the positioning of the head 15 relative to the surface of the disk 10 via VCM14, so that information is read from the disk 10 via preamplifier 30 and RWC60 when the head 15 is positioned on the target track TR.

[0033] MPU40 controls the write process, which involves receiving a write command containing a write address from host 100 via HDC50 and writing information corresponding to the write data to the location within disk 10 corresponding to the write address. In controlling the write process, MPU40, based on the write address, controls the positioning of the head 15 relative to the surface of disk 10 via VCM14, ensuring that the head 15 is positioned on the target track TR, and then writes information corresponding to the write data to disk 10 via RWC60 and preamplifier 30.

[0034] HDC50 controls data transmission. For example, HDC50 controls data transmission between host 100 and RWC60 based on instructions from MPU40. HDC50 provides MPU40 with commands received from host 100, receives responses to commands from MPU40, and sends them to host 100.

[0035] RWC60 receives a read signal from preamplifier 30, recovers the read data from the read signal according to the instruction from MPU40, and provides the read data to host 100 via HDC50. RWC60 receives write data from host 100 via HDC50, generates a data signal corresponding to the write data according to the instruction from MPU40, and provides it to preamplifier 30.

[0036] During the write process, the level of the data signal (e.g., L or H) changes according to the value of the data to be written (e.g., 0 or 1), the polarity of the write current flowing in the head 15 is reversed according to the level of the data signal, and the direction of magnetization of the disk 10, which is written as information, is reversed according to the polarity of the write current.

[0037] For example in Figure 3 During the period t0 to t2 shown in (a), the write current value is maintained at Iw = I, corresponding to the value "1" of the written data. H (>0). During the period from t2 to t3, corresponding to the value of the written data "0", the value of the write current is maintained at Iw = I L (<0). Timing t2 corresponds to the bit reversal position of the written data and the polarity reversal position of the written current.

[0038] Here, the magnetic field generated by the main pole in head 15 according to the write current has a spatial extension relative to the area capable of magnetizing disk 10 (i.e., the area capable of instantaneous writing). This spatial extension is called the MPRZ (Main Pole Relaxation Zone), and is intended to occupy an area such as... Figure 2 A portion of the circumferential length L of the head 15 as shown.

[0039] Therefore, as Figure 3 As shown in (b), the waveform of the write current in MPRZ (Main Pole Relaxation Zone) mode includes the interval (current zero time) ΔT where the write current Iw becomes zero before the polarity reversal position of the current waveform corresponding to the bit reversal position (timing t2). MPRZ The control that keeps the write current Iw at zero is called zero current control.

[0040] The purpose of zero-current control is to avoid delays in the magnetization response at the polarity reversal position of the write current. When the amplitude of the write current before the polarity reversal position is large, the magnetomotive force causing the magnetization reversal inside the head 15 is large, potentially delaying the magnetization response at the polarity reversal position. If the write current before the polarity reversal position is zero, the magnetomotive force causing the magnetization reversal inside the head 15 can be reduced, thus avoiding delays in the magnetization response at the polarity reversal position.

[0041] As a premise, zero-current control is based on the idea that even if the write current Iw is zero during the zero-current time, information can still be instantaneously recorded to disk 10. This idea assumes that even if the write current Iw is zero during the zero-current time, because the header 15 has a certain physical size, this length (footprint length) will instantaneously record information to disk 10, and its recording state will not be compromised. The unit period of the data signal corresponding to 1 bit of the written data is called 1T. When the length L of the master pole is set to be exactly equal to the footprint length, the zero-current time ΔT is... MPRZ The expected lifespan is around 2T to 3T. In the MPRZ method, the structure is often designed to make the write current Iw zero before the polarity reversal occurs above 1T. Figure 3 This is a waveform diagram representing the action of the MPRZ mode.

[0042] For example, a data pattern in which the same bit value in the original write data lasts for an nT interval (i.e., the pattern length is nT) is called an nT pattern. In MPRZ mode, a dummy data signal is generated in the original write data at a length of 4T or more, with a dummy bit inserted before the bit inversion position 2 to 3 bits, and a mask signal indicating the position of the dummy bit is generated. Furthermore, current zero control is initiated at the edge timing of the dummy data signal (e.g., falling edge timing), and the mask signal is used for shielding, thereby preventing polarity reversal of the write current at the dummy bit position. This enables the write current waveform of MPRZ mode.

[0043] In this MPRZ mode, the dummy inversion position is used for timing control when the write current Iw = 0. Therefore, in principle, the resolution becomes 1T. Furthermore, the dummy data signal and the MPRZ signal must be modulated in tandem, making it difficult to freely control the current zero time ΔT. MPRZ Make changes, current zero time ΔT MPRZ Appropriateness (e.g., optimization) is difficult.

[0044] On the other hand, the occupied area length may actually be less than 1T, contrary to expectations. This is because the magnetic field strength on the leading edge side of the first 15 is weak, limiting the area that can be recorded by sufficient overlap writing (OW) to the vicinity of the trailing edge gap. As a result, the actual occupied area length may be shorter relative to the physical size of the first 15. Therefore, for an ideal MPRZ mode, it is desirable to adjust the current zero time ΔTMPRZ with a resolution smaller than 1T.

[0045] For example, the BER (bit error rate) will be used to measure the time ΔT when the current is zero. MPRZ The results of evaluating the improvement in magnetization response under variable conditions are expressed as follows: Figures 4-6 . Figure 4 , Figure 5 , Figure 6 These refer to the peripheral region OR, mid-peripheral region MR, and inner-peripheral region IR, respectively. Figure 2 (Refer to) A graph showing the relationship between current zero time and bit error rate for each data mode.

[0046] exist Figure 4 In the evaluation results of the peripheral region OR shown, the bit error rate of the 1T mode is the smallest at the current zero time ΔT. MPRZ The bit error rate in the ΔT1.2T mode becomes the minimum current zero-time ΔT. MPRZ The bit error rate in the ΔT2.3T mode becomes the minimum current zero-time ΔT. MPRZ The bit error rate in the ΔT3.4T mode becomes the minimum current zero-time ΔT. MPRZ The bit error rate in the ΔT4.5T mode becomes the minimum current zero-time ΔT. MPRZ Let ΔT5 be the value. When representing a size relationship, it becomes Equation 1 below.

[0047] ΔT1<ΔT2<ΔT4<ΔT5<ΔT3...Equation 1

[0048] exist Figure 5 In the evaluation results of the intermediate frequency region MR shown, the bit error rate of the 1T mode is the smallest at the current zero time ΔT. MPRZ For ΔT 11 The bit error rate in 2T mode becomes the minimum current zero-time ΔT. MPRZ For ΔT 12 The bit error rate in 4T mode becomes the minimum current zero-time ΔT. MPRZ For ΔT 14 The bit error rate in 5T mode becomes the minimum current zero-time ΔT. MPRZ For ΔT 15 Furthermore, the bit error rate of the 3T mode was not detected within the evaluable range, and the current zero-time ΔT was the minimum. MPRZTherefore, the same ΔT3 as the outer region OR can also be used approximately. When representing the size relationship, it becomes Equation 2 below.

[0049] ΔT 11 <ΔT 12 <ΔT 15 <ΔT 14 <ΔT3 ···Equation 2

[0050] exist Figure 6 In the evaluation results of the inner peripheral region IR shown, the bit error rate of the 1T mode is the smallest at the current zero time ΔT. MPRZ For ΔT 21 Furthermore, within the evaluable range, the bit error rate of the 2T mode was not detected at the minimum current zero-time ΔT. MPRZ Therefore, the same ΔT as MR in the mid-perimeter region can also be used approximately. 12 Within the evaluable range, the bit error rate of the 3T mode was not detected, and the current zero-time ΔT was minimized. MPRZ Therefore, the same ΔT3 as the OR in the outer peripheral region can also be used approximately. The bit error rate of the 4T mode not detected within the evaluable range becomes the minimum current zero-time ΔT. MPRZ Therefore, the same ΔT as MR in the mid-perimeter region can also be used approximately. 14 Within the evaluable range, the bit error rate of the 5T mode was not detected, and the current zero-time ΔT was minimized. MPRZ Therefore, the same ΔT as MR in the mid-perimeter region can also be used approximately. 15 When representing size relationships, it becomes Equation 3 as follows.

[0051] ΔT 21 <ΔT 12 <ΔT 15 <ΔT 14 <ΔT3 ···Equation 3

[0052] like Figures 4-6 As shown, the improvement in bit error rate is appropriately (e.g., maximized) by the current zero-time ΔT. MPRZ It exhibits a tendency to differ according to pattern length (nT). Furthermore, in Figures 4-6 In this context, 1T represents the value of the zero-time current represented by a single-dot dashed line, and the improvement in bit error rate is appropriately (e.g., maximized) by the zero-time current ΔT. MPRZ It is roughly around 1T or tends to be smaller than 1T. In order to make the improvement effect obtained by the MPRZ method appropriate (e.g., maximize), it is desirable to be able to adjust the current zero time ΔTMPRZ individually for each data mode (e.g., 1T mode to 5T mode).

[0053] In contrast, the controller 130 of the disk device 1 enables the preamplifier 30 to perform current zero control and can change the current zero time according to the writing data mode.

[0054] The controller 130 generates an MPRZ signal for zero-current control based on the write data, and adjusts the timing of the edge of the polarity reversal position of the specified MPRZ signal according to each mode. The controller 130 generates a data signal by adding a delay amount DL1 to the write data. The controller 130 generates an MPRZ signal by adding a delay amount DL2 to the write data according to the data mode (e.g., 1T mode to 5T mode). That is, the controller 130 selects one of the candidate delay amounts corresponding to the next data mode from among multiple candidate delay amounts corresponding to multiple data modes as the delay amount DL2. All candidate delay amounts are smaller than the delay amount DL1. The controller 130 adds write data to the selected delay amount DL2 to generate the MPRZ signal. The preamplifier generates a write current based on the data signal, but starts zero-current control at the edge timing of the MPRZ signal to make the amplitude of the write current zero, and releases the zero-current control at the polarity reversal position of the data signal.

[0055] Therefore, the zero-time ΔT of the current can be individually adjusted according to each data mode (e.g., 1T mode to 5T mode). MPRZ This allows for the appropriate (e.g., maximization) of the bit error rate improvement achieved through the MPRZ method. Furthermore, the current zero-time can be controlled using the difference between two delay quantities DL1 and DL2; therefore, the current zero-time ΔT can be controlled with a resolution smaller than 1T. MPRZ Adjustments will be made.

[0056] For example, in disk device 1, RWC60 and preamplifier 30 can be configured as follows regarding write processing: Figure 7 As shown. Figure 7 This is a diagram showing the configuration of the RWC60 and preamplifier 30. Figure 7 For simplicity, diagrams of components related to reading and processing are omitted.

[0057] The RWC60 includes a write data generation circuit 61, a WPC (Write Precompensation) circuit 62, a delay circuit 63, a driver 64, a WPC circuit 65, a driver 66, and a register 67. The preamplifier 30 includes a write driver 32, a current zero control circuit 33, and a driver 34.

[0058] The write data generation circuit 61 processes the signals received from the host 100 via HDC50 to generate write data and provides the generated write data to the WPC circuit 62.

[0059] The WPC circuit 62 adds an individual delay to the edge timing of the written data according to the data mode. When the WPC circuit 62 receives the written data from the write data generation circuit 61, it analyzes the data mode (e.g., 1T mode to 5T mode). The controller 130 accesses the device memory storing multiple first setting values, obtains the first setting value WPC_XXXX corresponding to the analyzed data mode from the multiple first setting values, and sets it in register 67.

[0060] The device memory can be, for example, an area in disk 10 that stores management information, or non-volatile memory 80. The device memory stores first setting information that associates multiple data modes with a first setting value. The first setting value WPC_XXXX represents the value of the compensation amount for NLTS (Non-Linear Transition Shift). NLTS is a phenomenon where information bits recorded on disk 10 are affected by the magnetic field of the information bits immediately preceding and / or preceding them, causing the bit-flip position to drift non-linearly with respect to time. Therefore, the value of the NLTS compensation amount may vary depending on the data mode. Which data mode corresponds to which NLTS compensation amount is determined experimentally in advance and included in the first setting information. "XXXX" in "WPC_XXXX" indicates the compensation amount value that should be assigned to the data mode. The first setting value WPC_XXXX can be stored in register 67 inside RWC60, and is set from the device memory to register 67 inside RWC60 during a write operation.

[0061] For the written data, the WPC circuit 62 corrects the bit flip position with a compensation amount corresponding to the first set value WPC_XXXX. The WPC circuit 62 provides the corrected written data to the delay circuit 63, and copies the corrected written data and provides it to the WPC circuit 65.

[0062] Delay circuit 63 delays the corrected write data by a delay amount DL1, generating a data signal. The delay amount DL1 is larger than the compensation amount of a typical NLTS. Delay circuit 63 provides the data signal to driver 64. Driver 64 transmits the data signal to preamplifier 30.

[0063] WPC circuit 65 generates an MPRZ signal by delaying the bit-inverted position of the corrected write data by an amount DL2 corresponding to the second setting value WPC2_XXXX stored in register 67 inside RWC60. Controller 130 accesses the device memory storing multiple second setting values, retrieves the second setting value WPC2_XXXX corresponding to the data pattern analyzed in WPC circuit 62, and sets it in register 67.

[0064] The device memory stores second setting information relating multiple data modes to a second setting value. The second setting information can also be information relating multiple data modes and multiple regions (e.g., outer peripheral region OR, middle peripheral region MR, inner peripheral region IR) to a second setting value. The second setting value WPC2_XXXX represents the value of the delay amount used to adjust the start timing of the current zero time. Which data mode (or which combination of data mode and region) corresponds to which NLTS compensation amount is determined experimentally in advance and included in the second setting information (see reference). Figures 4-6 The “XXXX” in “WPC2_XXXX” represents the value of the delay amount that should be assigned to the data mode. The second setting value WPC2_XXXX can be stored in register 67 inside RWC60, and is set from device memory to register 67 inside RWC60 during a write operation.

[0065] WPC circuit 65 can independently add a delay amount DL2 (WPC2_XXXX) to the corrected write data, separate from the addition of the NLTS compensation amount (WPC_XXXX) performed by WPC circuit 62. The MPRZ signal indicates the start timing of the current zero time with its edge timing. Thus, WPC circuit 65 can individually adjust the current zero time in nT mode.

[0066] At this point, it is desirable for the WPC circuit 65 to ensure an adjustment width of at least 1T. Therefore, for the corrected write data with added NLTS compensation, a delay amount DL1 is added to the delay circuit 63 for overall phase adjustment with the MPRZ signal.

[0067] WPC circuit 65 provides the MPRZ signal to driver 66. Driver 66 transmits the MPRZ signal to preamplifier 30.

[0068] The driver 34 of the preamplifier 30 receives the MPRZ signal from the WPC circuit 65. The driver 34 transmits the MPRZ signal to the current zero control circuit 33. The current zero control circuit 33 controls the write driver 32 according to the MPRZ signal. The current zero control circuit 33 controls the timing of the start of current zero control of the write driver 32.

[0069] The write driver 32 receives a data signal from the driver 64 of the RWC60 and generates a write current based on the data signal. However, when specified by the current zero control circuit 33, current zero control is initiated, making the write current zero. Furthermore, the write driver 32 automatically releases the current zero control when the edge of the data signal is timed, i.e., when the polarity of the write current should be reversed.

[0070] The simplest implementation of zero-current control is the state transition of the MPRZ signal; in other words, at the polarity reversal position (L level → H level or H level → L level), the preamplifier 30 operates to make the write current Iw zero. Through the delay circuit 63, the polarity reversal position of the MPRZ signal for each nT mode is set in time before the polarity reversal position of the data signal. By adjusting the delay amount DL2 added to the MPRZ signal by the WPC circuit 65, the start timing of the zero-current time for each nT mode can be individually specified.

[0071] For example, zero current control, such as Figure 8 Proceed as shown. Figure 8 This is a waveform diagram representing zero-current control. Figure 8 (a) shows the bit sequence of the write data generated by the write data generation circuit 61, its pattern recognition results (1T mode to 6T mode), and the data signal output from the delay circuit 63. Figure 8 (b) shows the MPRZ signal output from WPC circuit 65. Figure 8 (c) shows the write current Iw generated by the write driver 32.

[0072] exist Figure 8 (a)~ Figure 8 Example (c) illustrates the case where the track TR of the outer peripheral region OR is the target track TR. The WPC circuit 65 of the RWC60 operates with the previous 3 state branches, enabling independent zero-time current control in four modes: 1T mode, 2T mode, 3T mode, and nT mode (n≥4). Furthermore, the number of independently controlled nT modes can be adjusted by adding or removing state branches of the WPC circuit 65 as needed.

[0073] Just before timer t9, based on the data signal being at a high level V H1 This becomes the write current Iw = I H The data signal becomes a signal with an added delay of DL1 to the written data corrected by the WPC circuit 62.

[0074] At this time, the MPRZ signal becomes a high level V. H2 Based on the second setting value WPC2_xx11 corresponding to the identification result that the subsequent data mode is 1T mode "1", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT1) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the falling edge timing of the MPRZ signal to the timing t9 corresponding to the 1T mode.

[0075] At time t9, the MPRZ signal transitions from a high level V. H2 Transition to low level V L2Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0076] At time t10, the data signal transitions from high level V. H1 Transition to low level V L1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT1 corresponding to the 1T mode.

[0077] Preamplifier 30 causes the write current Iw to move from 0 to level I. US change.

[0078] At this time, the MPRZ signal becomes low level V. L2 Based on the second setting value WPC2_xx11 corresponding to the identification result that the subsequent data mode is 1T mode "0", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT1) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the rising edge timing of the MPRZ signal to the timing t11 corresponding to the 1T mode.

[0079] At time t11, the MPRZ signal transitions from a low level V. L2 Transition to high level V H2 Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0080] At time t12, the data signal transitions from low level V. L1 Transition to high level V H1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT1 corresponding to the 1T mode.

[0081] Preamplifier 30 causes the write current Iw to move from 0 to level I. OS change.

[0082] At this time, the MPRZ signal becomes a high level V. H2 Based on the second setting value WPC2_x101 corresponding to the identification result that the subsequent data mode is 2T mode "11", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT2) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the falling edge timing of the MPRZ signal to the timing t14 corresponding to the 2T mode.

[0083] When timer t13 is reached, preamplifier 30 should maintain level I. OS During this period, the write current Iw is reduced from level I. OS to high level I H change.

[0084] At time t14, the MPRZ signal transitions from a high level V. H2 Transition to low level V L2 Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0085] At time t15, the data signal transitions from high level V. H1 Transition to low level V L1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT2, corresponding to the 2T mode.

[0086] Preamplifier 30 causes the write current Iw to move from 0 to level I. US change.

[0087] At this time, the MPRZ signal becomes low level V. L2 Based on the second setting value WPC2_1001 corresponding to the identification result that the subsequent data mode is 3T mode "000", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT3) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the rising edge timing of the MPRZ signal to the timing t17 corresponding to the 3T mode.

[0088] When timer t16 is reached, preamplifier 30 should maintain level I. US During this period, the write current Iw is reduced from level I. US to low level I L change.

[0089] At time t17, the MPRZ signal transitions from a low level V. L2 Transition to high level V H2 Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0090] At timer t18, the data signal transitions from low level V. L1 Transition to high level V H1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT3 corresponding to the 3T mode.

[0091] Preamplifier 30 causes the write current Iw to move from 0 to level I. OS change.

[0092] At this time, the MPRZ signal becomes a high level V. H2Based on the second setting value WPC2_0001 corresponding to the identification result that the subsequent data mode is 4T mode "1111", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT4) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the falling edge timing of the MPRZ signal to the timing t20 corresponding to the 4T mode.

[0093] When timing t19 is reached, preamplifier 30 should maintain level I. OS During this period, the write current Iw is reduced from level I. OS to high level I H change.

[0094] At time t20, the MPRZ signal transitions from a high level V. H2 Transition to low level V L2 Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0095] At time t21, the data signal transitions from high level V. H1 Transition to low level V L1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT4, corresponding to the 4T mode.

[0096] Preamplifier 30 causes the write current Iw to move from 0 to level I. US change.

[0097] At this time, the MPRZ signal becomes low level V. L2 Based on the second setting value WPC2_0001 corresponding to the identification result that the subsequent data mode is 5T mode "00000", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT4) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the rising edge timing of the MPRZ signal to the timing t23 corresponding to the 5T mode.

[0098] When timer t22 is reached, preamplifier 30 should maintain level I. US During this period, the write current Iw is reduced from level I. US to low level I L change.

[0099] At time t23, the MPRZ signal transitions from a low level V. L2 Transition to high level V H2 Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0100] At time t24, the data signal transitions from low level V.L1 Transition to high level V H1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT4, corresponding to the 5T mode.

[0101] Preamplifier 30 causes the write current Iw to move from 0 to level I. OS change.

[0102] At this time, the MPRZ signal becomes a high level V. H2 Based on the second setting value WPC2_0001 corresponding to the identification result that the subsequent data mode is 6T mode "111111", the WPC circuit 62 adds a delay amount DL2 (=DL1-ΔT4) to the written data after correction by the WPC circuit 62. As a result, the RWC60 adjusts the falling edge timing of the MPRZ signal to timing t26 corresponding to the 6T mode.

[0103] When timer t25 is reached, preamplifier 30 should maintain level I. OS During this period, the write current Iw is reduced from level I. OS to high level I H change.

[0104] At time t26, the MPRZ signal transitions from a high level V. H2 Transition to low level V L2 Correspondingly, preamplifier 30 begins current zero control, set to write current Iw = 0.

[0105] At time t27, the data signal transitions from high level V. H1 Transition to low level V L1 Correspondingly, the preamplifier 30 releases the current zero control. Thus, the current zero time is controlled to ΔT4, corresponding to the 4T mode.

[0106] As described above, in this embodiment, when the RWC60 performs zero-current control in the disk device 1, the zero-current time is changed according to the data mode, and the preamplifier 30 sets the zero-current time according to this change. Therefore, the zero-current time ΔT can be individually set according to each data mode (e.g., 1T mode to 5T mode). MPRZ Adjustments can be made to appropriately (e.g., maximize) the bit error rate improvement effect obtained through the MPRZ method. That is, the reliability of the information recorded on disk 10 can be improved.

[0107] Furthermore, in this embodiment, in disk device 1, RWC60 generates a data signal by adding a delay amount DL1 to the written data, and generates an MPRZ signal by adding a delay amount DL2 to the written data according to the data mode. Preamplifier 30 initiates zero-current control at the edge of the MPRZ signal, making the amplitude of the write current zero, and releases the zero-current control at the polarity reversal position of the data signal. Therefore, the difference between the two delay amounts DL1 and DL2 can be used to adjust the zero-current time, thus allowing adjustment of the zero-current time ΔT with a resolution smaller than 1T. MPRZ .

[0108] Furthermore, as a variation of the implementation, the disk device 1 can also be configured to switch between having and not having zero current control. For example, the zero current control circuit 33 in the preamplifier 30 can also be configured with a function such as... Figure 9 The current zero control switching information 331 is shown. Figure 9 This is a diagram showing the switching information 331 of the current zero control in a modified embodiment.

[0109] like Figure 9 As shown, the current zero control circuit 33 in the preamplifier 30 determines whether to perform current zero control based on the combination of the data signal level (L level or H level) and the state transition of the MPRZ signal (L level → H level transition or H level → L level transition).

[0110] exist Figure 9 In the case where the data signal is low level V, the current zero control circuit 33 L1 And the MPRZ signal changes to a low level V. L2 →High level V H2 In the case of, or when the data signal is at a high level V H1 And the MPRZ signal changes to a high level V. H2 →Low level V L2 In this case, selective zero-current control is performed. This is based on the following consideration: the MPRZ signal is copied according to the written data, therefore, this combination is expected in normal operation.

[0111] In other combinations, the MPRZ signal state transition can be considered as caused by unexpected timing issues such as jitter noise or adjustment errors. The current zero control circuit 33 operates when the data signal is low (V). L1 And the MPRZ signal changes to a high level V. H2 →Low level V L2 In the case of, or when the data signal is at a high level V H1 And the MPRZ signal changes to a low level V. L2 →High level V H2In this case, zero current control is not performed.

[0112] For example, Figure 4 , Figure 5 As shown, in the outer peripheral region (OR) and the middle peripheral region (MR), the bit error rate is minimized at the zero-current time ΔT in the 1T mode. MPRZ The current zero time ΔT has the lowest bit error rate compared to other data modes. MPRZ Small. Therefore, for 1T mode, the zero-time current is controlled to a relatively small value.

[0113] Even if the zero-time of the current is controlled to a relatively small value, if the phase of the data signal and the phase of the MPRZ signal are appropriate, then... Figure 10 (a)~ Figure 10 As shown in (c), the zero-current time can also be appropriately set. The edge timing t11 in the MPRZ signal corresponding to the 1T mode is located within the period t10 to t12 corresponding to the data signal of the 1T mode. Furthermore, Figure 10 (a)~ Figure 10 (c) is a waveform diagram showing the switching of zero-current control in a modified example of the implementation, and... Figure 8 (a)~ Figure 8 The timing t9 to t21 of (c) corresponds to the part.

[0114] In the MPRZ signal, at edge timing t11 corresponding to the 1T mode, the data signal is low level V. L1 The MRPZ signal transitions to a low level V. L2 →High level V H2 Therefore, according to the switching information (refer to...) Figure 9 At this point, zero-current control begins, and the write current Iw = 0. Then, at time t12, based on the low level V of the data signal... L1 →High level V H1 With this transition, the zero-current control is deactivated. Therefore, the zero-current time can be appropriately set just before the polarity reversal of the write current corresponding to the 1T mode.

[0115] On the other hand, by controlling the current to a relatively small value at zero time, due to the influence of jitter, etc., Figure 10 (d) Figure 10 As shown in (f), the phase of the data signal and the phase of the MPRZ signal may be sequential. The edge timing t11a in the MPRZ signal corresponding to the 1T mode occurs after the period t10a–t12a corresponding to the data signal in the 1T mode, i.e., within the period t12a–t15a corresponding to the data signal in the 2T mode. Furthermore, Figure 10 (d) Figure 10(f) is a waveform diagram showing the switching of zero-current control in a modified embodiment of the implementation, and... Figure 8 (a)~ Figure 8 The timing t9 to t21 of (c) corresponds to the part.

[0116] If zero current control is started at edge timing t11a, it is possible that the current Iw written becomes zero for most of the period t12a to t15a corresponding to the 2T mode, and the 2T mode "11" that should have been recorded is not recorded on disk 10.

[0117] In contrast, in a variation of the implementation, the data signal is at a high level V at the edge timing t11a corresponding to the 1T mode in the MPRZ signal. H1 The MRPZ signal transitions to a low level V. L2 →High level V H2 Therefore, according to the switching information (refer to...) Figure 9 Zero current control is not initiated. Write current Iw starts from low level I. L To level I OS This transformation avoids unintentional timing-based zero-current control.

[0118] Alternatively, in RWC60, the delay amount DL1 of the delay circuit 63 can be set to be smaller than the delay amount DL2 of the WPC circuit 65 used in 1T mode, and larger than the delay amount DL2 of the WPC circuit 65 used in other modes (modes above 2T). In this case, by using... Figure 9 The switching information 331 allows for selective non-current zero control in 1T mode, while performing current zero control in other modes (modes above 2T). This enables the appropriate (e.g., maximizing) bit error rate improvement for information written to disk 10 based on the write current, while avoiding the effects of jitter and other factors.

[0119] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A disk device comprising: a disk; a head that writes information to the disk in accordance with a write current; a preamplifier that flows the write current to the head; and a controller that is capable of causing the preamplifier to perform current zero control that maintains an amplitude of the write current at zero during a write process, and is capable of changing a time during which the amplitude of the write current is maintained at zero in accordance with a pattern of write data.

2. The disk device according to claim 1, the controller generates a first signal by adding a first delay amount to the write data, and generates a second signal by adding a second delay amount to the write data in accordance with the pattern of the write data.

3. The disk device according to claim 2, the second delay amount is smaller than the first delay amount.

4. The disk device according to claim 2, the controller selects a candidate delay amount corresponding to the pattern of the write data from among a plurality of candidate delay amounts corresponding to a plurality of patterns as the second delay amount, and generates the second signal by adding the selected second delay amount to the write data.

5. The disk device according to any one of claims 2 to 4, the preamplifier generates the write current in accordance with the first signal, and maintains an amplitude of the generated write current at zero from an edge timing of the second signal to a polarity inversion timing of the first signal.

6. The disk device according to claim 5, the preamplifier has: a first circuit that generates the write current in accordance with the first signal; and a second circuit that controls the first circuit so that the current zero control is started from an edge timing of the second signal, the first circuit releases the current zero control when it becomes a polarity inversion timing of the first signal.

7. The disk device according to claim 5, the preamplifier has: a first circuit that generates the write current in accordance with the first signal; and a second circuit that controls the first circuit so that the current zero control is started from an edge timing of the second signal in a case where a combination of a level of the first signal and a state transition of the second signal is a first combination, and controls the first circuit so that the current zero control is not performed in a case where the combination of the level of the first signal and the state transition of the second signal is a second combination, the first circuit releases the current zero control when it becomes a polarity inversion timing of the first signal in a case where the current zero control is being performed.

8. A disk device comprising: a disk; a head that writes write data to the disk in accordance with a write current; a preamplifier that is capable of supplying the write current to the head, and maintains an amplitude of the write current at zero during a predetermined period; and a controller that is capable of setting the predetermined period as a first period in a case where a pattern of the write data is a first pattern, and setting the predetermined period as a second period that is different from the first period in a case where the pattern of the write data is a second pattern that is different from the first pattern during a write process. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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