Test method and test system

Abstract

A testing method applicable to a memory device. The testing method includes the following steps: generating a first re-instruction to the memory device; storing first re-instruction address data in a register of the memory device according to the first re-instruction; reading the first re-instruction address data according to a modal register instruction; comparing the first re-instruction address data with desired address data to generate a comparison result; and generating a second re-instruction or filtering out memory devices based on the comparison result. This invention provides a testing method and system for testing memory devices, which first stores re-instruction address data in a register, thereby enabling the memory device to quickly verify multiple instructions under low-temperature conditions and high verification speeds.

Description

Technical Field

[0001] This invention relates to an electronic system and method. More specifically, this invention relates to a testing method and a testing system. Background Technology

[0002] Existing memory devices consist of multiple memory cells. These memory cells are composed of multiple capacitors. Leakage current can occur in memory devices due to manufacturing defects. Therefore, memory devices must periodically receive new instructions to protect the data stored in the multiple memory cells. However, due to the characteristics of memory cells and testing costs, memory devices are typically verified under high temperatures and low verification speeds.

[0003] Therefore, the above-mentioned technologies still have many shortcomings, and it is necessary for practitioners in this field to develop other suitable testing methods for memory devices. Summary of the Invention

[0004] One aspect of the present invention relates to a testing method applicable to a memory device. The testing method includes the following steps: generating a first renew instruction to the memory device; storing first renew address data in a register of the memory device according to the first renew instruction; reading the first renew address data according to a modal register instruction; comparing the first renew address data with desired address data to generate a comparison result; and generating a second renew instruction or filtering out memory devices based on the comparison result.

[0005] In some embodiments, the memory device includes dynamic random access memory.

[0006] In some embodiments, the first renewing instruction is different from the second renewing instruction.

[0007] In some embodiments, the step of generating a first renew instruction to a memory device includes: renewing a plurality of memory cells of one of a plurality of rows of the memory device according to the first renew instruction to generate first renew address data.

[0008] In some embodiments, the step of generating a second renew instruction or filtering out a memory device based on the comparison result includes: if the comparison result is that the first renew address data is the same as the expected address data, generating a second renew instruction to the memory device.

[0009] In some embodiments, the step of generating a second re-instruction or filtering out a memory device based on the comparison result includes: filtering out a memory device if the comparison result is that the first re-instruction address data is different from the expected address data.

[0010] In some embodiments, it is desirable for address data to be stored on a test instrument.

[0011] In some embodiments, the step of reading the first re-address data according to the modal register instruction includes: generating a modal register instruction to a memory device to output the first re-address data via an input / output control board.

[0012] Another aspect of the present invention relates to a testing system. The testing system includes a testing machine and a memory device. The testing machine is used to generate a first refresh instruction and a modal register instruction. The memory device is coupled to the testing machine. The memory device includes a register and refresh circuitry. The register is used to store first refresh address data according to the first refresh instruction. The refresh circuitry is coupled to the register and is used to read the first refresh address data according to the modal register instruction. The testing machine is used to compare the first refresh address data with desired address data to generate a comparison result. The testing machine is used to generate a second refresh instruction for the memory device or to filter out a memory device based on the comparison result.

[0013] In some embodiments, the memory device includes dynamic random access memory.

[0014] In some embodiments, the first renewing instruction is different from the second renewing instruction.

[0015] In some embodiments, the renewing circuitry is further configured to renew a plurality of memory cells of one of a plurality of rows of the memory device to generate first renewing address data.

[0016] In some embodiments, if the comparison result is that the first re-address data is the same as the expected address data, the test instrument is also used to generate a second re-address instruction to the memory device.

[0017] In some embodiments, if the comparison result shows that the first new address data is different from the expected address data, the test equipment is also used to screen out memory devices.

[0018] In some embodiments, the renew circuitry includes a renew counter. The renew counter is used to count the number of test cycles that generate the first renew instruction and the second renew instruction. Attached Figure Description

[0019] The invention will be better understood by referring to the embodiments described in the following paragraphs and the following figures:

[0020] Figure 1 A circuit block diagram of a test system illustrated according to some embodiments of the present invention; and

[0021] Figure 2 This is a flowchart illustrating the steps of a testing method according to some embodiments of the present invention. Detailed Implementation

[0022] The spirit of the present invention will be clearly explained below with illustrations and detailed description. Any person skilled in the art who understands the embodiments of the present invention can make changes and modifications based on the techniques taught in the present invention without departing from the spirit and scope of the present invention.

[0023] The terminology used in this invention is for describing specific embodiments only and is not intended to limit the invention. Singular forms such as "a," "this," "this," "the," and "the" as used in this invention also include plural forms.

[0024] The terms “comprising,” “including,” “having,” “containing,” etc., used in this invention are all open-ended terms, meaning that they include but are not limited to.

[0025] Unless otherwise specified, the terms used in this invention generally have their ordinary meaning in the context of the art, the invention, and its specific application. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.

[0026] Figure 1 This is a circuit block diagram illustrating a test system 1000 according to some embodiments of the present invention. In some embodiments, the test system 1000 includes a memory device 1100 and a test bench 1200. The memory device 1100 is coupled to the test bench 1200. The memory device 1100 includes a refresh circuit 1110 and a temporary register 1120. The refresh circuit 1110 is coupled to the temporary register 1120.

[0027] In some embodiments, the test equipment 1200 is used to generate a first renew instruction and a modal register instruction. A memory device 1100 is coupled to the test equipment 1200. A register 1120 is used to store first renew address data according to the first renew instruction. A renew circuit 1110 is used to read the first renew address data according to the modal register instruction. The test equipment 1200 is used to compare the first renew address data and desired address data to generate a comparison result. The test equipment 1200 is used to generate a second renew instruction for the memory device 1100 or to filter out the memory device 1100 based on the comparison result.

[0028] In some embodiments, the memory device 1100 includes dynamic random access memory (DRAM). In some embodiments, the memory device comprises a plurality of memory cells. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns.

[0029] In some embodiments, the renew circuit 1110 is used to renew a plurality of memory cells of one of the plurality of rows of the memory device 1100 according to a first renew instruction to generate first renew address data.

[0030] In some embodiments, the renew circuit 1110 includes a renew counter 1111. The renew counter 1111 is used to count the number of test cycles that generate the first renew instruction and the second renew instruction.

[0031] In some embodiments, in order to enable the invention Figure 1 The operation of the test system 1000 used to test the memory device 1100 is easy to understand; please refer to it as well. Figure 1 and Figure 2 . Figure 2 This is a flowchart illustrating the steps of a test method 200 for testing a memory device 1100 according to some embodiments of the present invention. In some embodiments, the test method 200 for testing a memory device includes steps 210 to 260. The steps will be described in detail in subsequent paragraphs.

[0032] In step 210, a first rewrite instruction is generated for the memory device. In some embodiments, see [link to relevant documentation]. Figure 1 and Figure 2 The test instrument 1200 generates a first renew instruction and a modal register instruction to the renew circuit 1110 of the memory device 1100.

[0033] In step 220, the first renew address data is stored in a temporary register of the memory device according to the first renew instruction. In some embodiments, please refer to... Figure 1 and Figure 2 The first renew address data is stored in the temporary register 1120 according to the first renew instruction.

[0034] In some embodiments, the refresh circuit 1110 is configured to receive a first refresh instruction. The refresh circuit 1110 is configured to refresh a plurality of memory cells of one of the plurality of rows of the memory device 1100 according to the first refresh instruction, so as to generate first refresh address data. The refresh circuit 1110 is configured to transfer the first refresh address data to a temporary register 1120 for storage.

[0035] It should be noted that the refresh circuit 1110 is used to read one row at a time according to a refresh instruction. In other words, multiple refresh instructions represent different signals. To further explain, memory refresh is the process of periodically reading information from a region of the memory device 1100 and immediately rewriting the read information to the same region without modification.

[0036] In step 230, the first new address data is read according to the modal register instruction.

[0037] In some embodiments, please refer to Figure 1 and Figure 2 The test equipment 1200 generates a modal register instruction to the refresh circuit 1110 of the memory device 1100. The refresh circuit 1110 reads the first refresh address data according to the modal register instruction. The refresh circuit 1110 outputs the first refresh address data to the test equipment 1200 via the input / output control board, without going through the refresh counter 1111.

[0038] In step 240, the first new address data and the expected address data are compared to generate a comparison result.

[0039] In some embodiments, please refer to Figure 1 and Figure 2 The test equipment 1200 compares the first new address data and the expected address data to generate a comparison result. In some embodiments, the expected address data is stored in the test equipment 1200.

[0040] It should be noted that each row of the memory device 1100 has different new address data, and the test equipment 1200 already has different expected address data corresponding to each row.

[0041] For example, memory device 1100 has 16 rows. After a memory refresh process, memory device 1100 generates 16 refresh address data corresponding to the 16 rows. Test equipment 1200 already has the 16 desired address data corresponding to the 16 rows. Test equipment 1200 compares the 16 refresh address data with the 16 desired address data to see if they are the same.

[0042] In some embodiments, the condition for performing step 250 by the test machine 1200 is if the comparison result is that the first new address data is the same as the expected address data.

[0043] In some embodiments, the condition for performing step 260 by the test machine 1200 is if the comparison result is that the first new address data is different from the expected address data.

[0044] In step 250, a second rewrite instruction is generated to the memory device based on the comparison result. In some embodiments, see [link to relevant documentation]. Figure 1 and Figure 2The test equipment 1200 generates a second re-instruction to the memory device 1100 based on the comparison result. The comparison result shows that the first re-instruction address data is the same as the expected address data. In other words, one of the multiple rows of the memory device 1100 is normal. Therefore, the test equipment 1200 generates different re-instructions to continue testing the other multiple rows of the memory device 1100.

[0045] In step 260, memory devices are selected. In some embodiments, see [link to relevant documentation]. Figure 1 and Figure 2 The memory device 1100 is selected based on the comparison results using the testing equipment 1200. The comparison result indicates that the first new address data is different from the expected address data. In other words, one of the multiple rows of the memory device 1100 is abnormal or corrupted. The memory device 1100 needs to be selected. In some embodiments, the aforementioned steps 210 to 240 can be repeated.

[0046] According to the foregoing embodiments, the present invention provides a test method 200 and a test system 1000 for testing a memory device 1100, wherein the newly added address data is first stored in a temporary register 1120, so that the memory device 1100 can quickly verify a plurality of instructions under low temperature conditions and high verification speed.

[0047] While the present invention has been disclosed above with detailed embodiments, other possible implementations are not excluded. Therefore, the scope of protection of the present invention should be determined by the claims, and not by the limitations of the foregoing embodiments.

[0048] For those skilled in the art, various modifications and refinements can be made to this invention without departing from its spirit and scope. Based on the foregoing embodiments, all modifications and refinements made to this invention are also covered within the protection scope of this invention.

[0049] [Symbol Explanation]

[0050] 1000: Test System

[0051] 1100: Memory device

[0052] 1110: Re-circuit

[0053] 1120: Temporary Register

[0054] 1111: Reset the counter

[0055] 1200: Testing equipment

[0056] 200: Method

[0057] 210-260: Steps.

Claims

1. A testing method applicable to memory devices, characterized in that, This testing method includes: A first re-instruction is generated to the memory device by a test instrument coupled to the memory device; The memory device's refresh circuit stores the first refresh address data in the memory device's temporary register according to the first refresh instruction; The renewing circuit reads the first renewing address data from the register according to the modal register instruction and sends it to the test machine. The test equipment is used to compare the first new address data with the expected address data to generate a comparison result. as well as Based on the comparison result, a second new instruction is generated for the memory device or the memory device is selected.

2. The test method according to claim 1, characterized in that, The memory device includes dynamic random access memory.

3. The test method according to claim 1, characterized in that, The first renewing instruction is different from the second renewing instruction.

4. The test method according to claim 1, characterized in that, The step of generating the first re-instruction to the memory device includes: The first re-instruction re-invents a plurality of memory cells of one of a plurality of rows of the memory device to generate the first re-instruction address data.

5. The test method according to claim 1, characterized in that, The steps of generating the second new instruction or filtering the memory device based on the comparison result include: If the comparison result is that the first re-address data is the same as the expected address data, the second re-address instruction is generated for the memory device.

6. The test method according to claim 5, characterized in that, The steps of generating the second new instruction or filtering the memory device based on the comparison result include: If the comparison result shows that the first new address data is different from the expected address data, the memory device is selected.

7. The test method according to claim 1, characterized in that, The expected address data is stored on the test machine.

8. The test method according to claim 1, characterized in that, The steps of reading the data at the first new address according to the modal register instruction include: The modal register instruction is generated and sent to the memory device so that the first new address data can be output via the input / output control board.

9. A testing system, characterized in that, Include: The test instrument is used to generate the first re-instruction and the modal register instruction; and A memory device coupled to the test equipment, wherein the memory device includes: A temporary register is used to store the first renew address data according to the first renew instruction; as well as The re-establishment circuit is coupled to the register and is used to read the first re-establishment address data according to the modal register instruction; The test equipment is used to compare the first re-address data and the expected address data to generate a comparison result. The test equipment is used to generate a second re-address instruction to the memory device or to filter out the memory device based on the comparison result.

10. The testing system according to claim 9, characterized in that, The memory device includes dynamic random access memory.

11. The testing system according to claim 9, characterized in that, The first renewing instruction is different from the second renewing instruction.

12. The testing system according to claim 9, characterized in that, The refresh circuit is also used to refresh a plurality of memory cells of one of the plurality of rows of the memory device to generate the first refresh address data.

13. The testing system according to claim 9, characterized in that, If the comparison result is that the first re-address data is the same as the expected address data, the test machine is also used to generate the second re-address instruction to the memory device.

14. The testing system according to claim 13, characterized in that, If the comparison result shows that the first new address data is different from the expected address data, the test equipment is also used to screen out the memory device.

15. The testing system according to claim 9, characterized in that, The renew circuit includes a renew counter, which is used to count the number of test cycles that generate the first renew instruction and the second renew instruction.

Images