Pulse Width Modulation Method

Abstract

A pulse width modulation method is provided for converting an input signal into a corresponding output pulse width modulation signal. The pulse width modulation method includes the following steps: generating a first linear periodic wave and a second linear periodic wave, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave, wherein the first linear periodic wave and the second linear periodic wave are triangular waves or sawtooth waves; and determining whether the level of the input signal is lower than a light load threshold. When the level of the input signal is lower than the light load threshold, the output pulse width modulation signal is generated based on a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, the output pulse width modulation signal is generated based on a comparison between the input signal and the first linear periodic wave.

Description

Technical Field

[0001] The present invention relates to a modulation method, in particular to a pulse width modulation method. Background Art

[0002] Please refer to Figure 1 , Figure 1 This is a waveform diagram of a multi-level pulse width modulation (PWM) signal in the prior art. Figure 1 As shown, waveform W1 represents an input signal, and waveform W2 represents a conventional multi-level pulse-width modulation signal, where waveform W2 is generated based on waveform W1. Conventional multi-level pulse-width modulation signals have three characteristics: the signal in each level has the same amplitude, the signal has a 50% duty cycle when idle (i.e., when the input signal level is 0), and the signal switching frequency is a fixed value. However, these three characteristics result in several disadvantages in conventional multi-level pulse-width modulation signals.

[0003] First, the multi-level pulse width modulation signal is filtered through a filter inductor and a filter capacitor before being provided to the load. Because the amplitude of conventional multi-level pulse width modulation signals is the same at each level, they cannot adaptively reduce the amplitude under light loads, resulting in a relatively large ripple current and relatively large conduction losses. On the other hand, under heavy loads (hereinafter referred to as heavy loads), the conventional multi-level pulse width modulation signal cannot adaptively increase the amplitude, resulting in a higher conduction current and higher conduction losses. Furthermore, the conventional multi-level pulse width modulation signal has a 50% duty cycle when idle, resulting in a large idle current and high power loss. Furthermore, because the switching frequency of conventional multi-level pulse width modulation signals is fixed and cannot be adaptively adjusted, the conventional multi-level pulse width modulation signal still has a large ripple current under light loads, resulting in large power loss. The aforementioned heavy load, light load, and idle state refer to states where the amplitude of the input signal or the absolute value of the AC level (especially the voltage level) is relatively high, relatively low, or zero.

[0004] In view of this, the present invention addresses the above-mentioned deficiencies in the prior art and proposes a pulse width modulation method to adaptively generate an output pulse width modulation signal, so that the power conversion efficiency of the output pulse width modulation signal can be improved under light load, heavy load and idle conditions. Summary of the Invention

[0005] The present invention provides a pulse width modulation method for converting an input signal into a corresponding output pulse width modulation signal. The method comprises: generating a first linear periodic wave and a second linear periodic wave, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave, wherein the first linear periodic wave and the second linear periodic wave are triangular waves or sawtooth waves; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output pulse width modulation signal based on a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output pulse width modulation signal based on a comparison between the input signal and the first linear periodic wave; wherein a common mode level of the second linear periodic wave and a common mode level of the input signal have a non-zero common mode offset, such that when the level of the input signal is lower than the light load threshold, the root mean square power of the output pulse width modulation signal is lower than the root mean square power of the output pulse width modulation signal when the common mode offset is zero.

[0006] In some embodiments, the PWM method further includes: comparing the input signal with the first linear cycle wave to generate a first relay PWM signal, and comparing the input signal with the second linear cycle wave to generate a second relay PWM signal; when the level of the input signal is lower than the light-load threshold, generating the output PWM signal according to the second relay PWM signal; and when the level of the input signal is higher than the light-load threshold, generating the output PWM signal according to the first relay PWM signal.

[0007] In some embodiments, the pulse width modulation method further includes: selecting the first linear cycle wave as a selected linear cycle wave when the level of the input signal is higher than the light load threshold; selecting the second linear cycle wave as the selected linear cycle wave when the level of the input signal is lower than the light load threshold; and comparing the input signal with the selected linear cycle wave to generate a selected pulse width modulation signal, and further generating the output pulse width modulation signal according to the selected pulse width modulation signal.

[0008] In some embodiments, when the value of the input signal is 0, the duty cycle of the output pulse width modulation signal is not 50%.

[0009] In some embodiments, the frequency of the second linear periodic wave is X times the frequency of the first linear periodic wave, where X is a rational number greater than or equal to 1.

[0010] In some embodiments, the aforementioned X is a non-integer greater than 1.

[0011] In some embodiments, there is a non-zero predetermined phase difference between the first linear periodic wave and the second linear periodic wave.

[0012] In some embodiments, the predetermined phase difference is the product of 2π and a rational number.

[0013] In some embodiments, the amplitude of the first linear periodic wave is Y times the amplitude of the second linear periodic wave, where Y is a non-integer greater than 1.

[0014] In some embodiments, the amplitude of the output PWM signal when the level of the input signal is higher than the light-load threshold is greater than the amplitude of the output PWM signal when the level of the input signal is lower than the light-load threshold.

[0015] In some embodiments, the pulse width modulation method is further used to control a power stage circuit to generate the output pulse width modulation signal, wherein the power stage circuit includes a plurality of switches, the plurality of switches including a first switch, a second switch, and a third switch, wherein the first switch is coupled between a light-load supply voltage and a switching node, the second switch is coupled between a heavy-load supply voltage and the switching node, and the third switch is coupled between the switching node and a ground potential, wherein the heavy-load supply voltage is higher than the light-load supply voltage; wherein when the level of the input signal is lower than the light-load threshold, the power stage circuit generates a pulse width modulation signal according to the input signal level. The input signal is compared with the second linear cycle wave to control the first switch and the third switch to periodically and complementaryly switch, thereby generating the output pulse-width modulated signal at the switching node, wherein the output pulse-width modulated signal switches between the light-load supply voltage and the ground potential. When the level of the input signal is higher than the light-load threshold, the power stage circuit controls the second switch and the third switch to periodically and complementaryly switch, thereby generating the output pulse-width modulated signal at the switching node, wherein the output pulse-width modulated signal switches between the heavy-load supply voltage and the ground potential.

[0016] In some embodiments, the amplitude of the output PWM signal when the input signal level is higher than the light load threshold is Z times the amplitude of the output PWM signal when the input signal level is lower than the light load threshold, where Z is a non-integer greater than 1.

[0017] In some embodiments, the step of determining whether the level of the input signal is lower than the light-load threshold comprises: comparing an offset linear periodic wave with the input signal to generate an offset pulse-width modulation signal, wherein the offset linear periodic wave is obtained by superimposing a non-zero common-mode offset on the first linear periodic wave, the common-mode offset being related to the light-load threshold; and periodically determining, based on an operating cycle of the offset linear periodic wave, whether both an in-phase sub-signal of the offset pulse-width modulation signal and an inverted sub-signal of the offset pulse-width modulation signal have a pulse in a previous operating cycle, thereby determining whether the level of the input signal is lower than the light-load threshold. The in-phase sub-signal and the inverted sub-signal of the input signal are complementary to each other, the in-phase sub-signal of the offset pulse-width modulation signal is obtained by comparing the offset linear periodic wave with the in-phase sub-signal of the input signal, and the inverted sub-signal of the offset pulse-width modulation signal is obtained by comparing the offset linear periodic wave with the inverted sub-signal of the input signal.

[0018] The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a waveform diagram of a multi-level pulse width modulation signal in the prior art.

[0020] Figure 2 FIG. 4 is a flow chart of a pulse width modulation method according to an embodiment of the present invention.

[0021] Figure 3A FIG. 1 is a block diagram of a Class D amplifier according to an embodiment of the present invention.

[0022] Figure 3B FIG. 1 is a circuit diagram of a pulse generating circuit in one embodiment of the present invention.

[0023] Figure 4 FIG. 1 is a flow chart of a class D amplifier operating in a pulse width modulation method according to an embodiment of the present invention.

[0024] Figure 5A FIG. 4 is a block diagram of a Class D amplifier according to another embodiment of the present invention.

[0025] Figure 5B FIG. 4 is a circuit diagram of a pulse generating circuit in another embodiment of the present invention.

[0026] Figure 6 FIG. 4 is a flow chart of a class D amplifier operating in a pulse width modulation method according to another embodiment of the present invention.

[0027] Figure 7 FIG. 1 is a signal waveform diagram of a judgment circuit in one embodiment of the present invention.

[0028] Figure 8 4 is a waveform comparison diagram of the first linear periodic wave and the second linear periodic wave in some embodiments of the present invention.

[0029] Figure 9 1 is a waveform comparison diagram of the first linear periodic wave and the second linear periodic wave in some other embodiments of the present invention.

[0030] Figure 10 FIG. 4 is a signal waveform diagram of a pulse width modulation circuit in another embodiment of the present invention.

[0031] Figure 11A FIG. 1 is a signal waveform diagram (1) of a class D amplifier in one embodiment of the present invention.

[0032] Figure 11B FIG. 2 is a signal waveform diagram of a Class D amplifier in one embodiment of the present invention.

[0033] Explanation of symbols in the figure

[0034] 100: Class D amplifier

[0035] 110A: Pulse Width Modulation Circuit

[0036] 110B: Pulse Width Modulation Circuit

[0037] 111A: Linear Periodic Wave Generator

[0038] 111B: Linear Periodic Wave Generator

[0039] 112A: Comparator

[0040] 112B: Comparator

[0041] 120: Pulse generating circuit

[0042] 121: Logic drive circuit

[0043] 122: Power stage circuit

[0044] 130: Judgment circuit

[0045] 200: Class D amplifier

[0046] 210: Pulse Width Modulation Circuit

[0047] 211A: Linear Periodic Wave Generator

[0048] 211B: Linear Periodic Wave Generator

[0049] 212: Select Circuit

[0050] 213: Comparator

[0051] 220: Pulse generating circuit

[0052] 221: Logic drive circuit

[0053] 222: Power stage circuit

[0054] 230: Judgment circuit

[0055] Cout: output capacitor

[0056] CLK1: first clock signal

[0057] CLK2: second clock signal

[0058] CLKs: clock signal

[0059] G1-G6: control signal

[0060] Lout: output inductor

[0061] LD: External load

[0062] LX: Switch Node

[0063] MS: Relay pulse width modulation circuit

[0064] MS1: First relay pulse width modulation signal

[0065] MS2: Second relay pulse width modulation signal

[0066] MSS: Select pulse width modulation signal

[0067] POI: Light load indication signal

[0068] PSOn: Inverted sub-signal of the offset pulse width modulated signal

[0069] PSOp: In-phase sub-signal of the offset pulse width modulated signal

[0070] Q1-Q6: Switch

[0071] S100-S130: Steps

[0072] S200-S240: Steps

[0073] S300-S340: Steps

[0074] t1-t2: time point

[0075] T1-T7: Operation cycle

[0076] Ts: Operation period

[0077] TR1: First linear periodic wave

[0078] TR2: Second linear periodic wave

[0079] TRO: Offset Linear Periodic Wave

[0080] TRS: Select linear periodic wave

[0081] Vcm1: first common mode level

[0082] Vcm2: Second common mode level

[0083] Vcmo: offset common mode level

[0084] Vinn: Inverted sub-signal of the input signal

[0085] Vinp: positive phase sub-signal of the input signal

[0086] Vos: common mode offset

[0087] Vthl: light load threshold

[0088] VH: Heavy load supply voltage

[0089] VIN: input signal

[0090] VL: light load supply voltage

[0091] VLX: output pulse width modulation signal

[0092] VOUT: output signal

[0093] W1-W2: Waveform DETAILED DESCRIPTION

[0094] The figures in this application are schematic, primarily intended to illustrate the coupling relationships between circuits and the relationships between signal waveforms. Circuits, signal waveforms, and frequencies are not drawn to scale. For clarity, many practical details are included in the following description, but this is not intended to limit the scope of the present invention.

[0095] Please refer to Figure 2 , Figure 2 FIG. 1 is a flow chart of a pulse width modulation method in one embodiment of the present invention. Figure 2As shown, the pulse width modulation method includes the following steps: first, generating a first linear periodic wave and a second linear periodic wave, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave, and wherein the first linear periodic wave and the second linear periodic wave are a triangle wave or a sawtooth wave (step S100). Next, determining whether the level of the input signal is lower than a light load threshold (step S110). When the input signal level is lower than the light-load threshold, an output pulse-width modulated signal is generated based on a comparison between the input signal and the second linear cycle wave (step S120). When the input signal level is higher than the light-load threshold, an output pulse-width modulated signal is generated based on a comparison between the input signal and the first linear cycle wave (step S130), wherein a non-zero common-mode offset exists between the common-mode level of the second linear cycle wave and the common-mode level of the input signal, such that when the input signal level is lower than the light-load threshold, the root mean square power of the output pulse-width modulated signal is less than the root mean square power of the output pulse-width modulated signal corresponding to a common-mode offset of zero.

[0096] It should be noted that determining whether the input signal level is lower than a light load threshold refers specifically to the absolute value of the AC level of the input signal. Furthermore, the light load mentioned in the present invention can not only mean a lower input signal level, but also mean a lower power of the input signal or output signal.

[0097] In some embodiments, a class-D amplifier can implement the pulse width modulation method. Figure 3A , Figure 3A FIG. 1 is a block diagram of a Class D amplifier 100 according to an embodiment of the present invention. Figure 3A As shown, the Class D amplifier 100 includes a plurality of pulse width modulation circuits 110A and 110B, a pulse generation circuit 120, and a determination circuit 130. The pulse generation circuit 120 is coupled to the pulse width modulation circuits 110A and 110B and the determination circuit 130. The structures and functions of the pulse width modulation circuits 110A and 110B, the pulse generation circuit 120, and the determination circuit 130 are explained in detail below.

[0098] In some embodiments, the PWM circuit 110A is configured to generate a first relay PWM signal MS1 based on an input signal VIN and a first linear cycle wave TR1, and the PWM circuit 110B is configured to generate a second relay PWM signal MS2 based on the input signal VIN and a second linear cycle wave TR2. When the value of the input signal VIN is higher than the value of the first linear cycle wave TR1 (the value of the second linear cycle wave TR2), the first relay PWM signal MS1 (the second relay PWM signal MS2) is in a first state, such as a high voltage state. When the value of the input signal VIN is lower than the value of the first linear cycle wave TR1 (the value of the second linear cycle wave TR2), the first relay PWM signal MS1 (the second relay PWM signal MS2) is in a second state, such as a low voltage state.

[0099] In some embodiments, the pulse width modulation circuit 110A includes a linear periodic wave generator 111A and a comparator 112A, while the pulse width modulation circuit 110B includes a linear periodic wave generator 111B and a comparator 112B. The linear periodic wave generator 111A is configured to generate a first linear periodic wave TR1 based on a first clock signal CLK1, while the linear periodic wave generator 111B is configured to generate a second linear periodic wave TR2 based on a second clock signal CLK2. The comparator 112A compares the input signal VIN with the first linear periodic wave TR1 to generate a first relay pulse width modulation signal MS1, while the comparator 112B compares the input signal VIN with the second linear periodic wave TR2 to generate a second relay pulse width modulation signal MS2. In some embodiments, the linear periodic wave generators 111A and 111B are triangular wave generators or sawtooth wave generators, and the first linear periodic wave TR1 and the second linear periodic wave TR2 are triangular waves or sawtooth waves. The structures and functions of the triangle wave generator, the sawtooth wave generator, and the comparators 112A and 112B are well known to those skilled in the art and are not described in detail.

[0100] In some embodiments, the pulse generating circuit 120 is configured to generate an output pulse-width-modulated signal VLX based on a light-load indication signal POI, a first relay pulse-width-modulated signal MS1, a second relay pulse-width-modulated signal MS2, a heavy-load supply voltage VH, and a light-load supply voltage VL. When the light-load indication signal POI is in a disabled state, indicating that the input signal VIN is in a heavy-load state, the pulse generating circuit 120 generates the output pulse-width-modulated signal VLX based on the first relay pulse-width-modulated signal MS1 and the heavy-load supply voltage VH. When the light-load indication signal POI is in an enabled state, indicating that the input signal VIN is in a light-load state, the pulse generating circuit 120 generates the output pulse-width-modulated signal VLX based on the second relay pulse-width-modulated signal MS2 and the light-load supply voltage VL. In some embodiments, the heavy-load supply voltage VH is higher than the light-load supply voltage VL.

[0101] In some embodiments, the determination circuit 130 is configured to determine whether the level of the input signal VIN is lower than a light-load threshold. The determination circuit 130 generates a light-load indication signal POI based on the input signal VIN and the light-load threshold. When the level of the input signal VIN is lower than the light-load threshold, the light-load indication signal POI is enabled, indicating that the input signal VIN is in a light-load state. When the level of the input signal VIN is higher than the light-load threshold, the light-load indication signal POI is disabled, indicating that the input signal VIN is in a heavy-load state.

[0102] Please refer to Figure 3B , Figure 3B FIG. 1 is a circuit diagram of the pulse generating circuit 120 in one embodiment of the present invention. Figure 3B As shown, in some embodiments, the pulse generation circuit 120 includes a logic driver circuit 121 and a power stage circuit 122, wherein the logic driver circuit 121 is coupled to the power stage circuit 122. In some embodiments, the logic driver circuit 121 is configured to generate a plurality of control signals G1-G3 based on the light-load indication signal POI, the first relay pulse-width modulation signal MS1, and the second relay pulse-width modulation signal MS2, thereby driving the operation of the power stage circuit 122. The power stage circuit 122 is configured to generate an output pulse-width modulation signal VLX based on the plurality of control signals G1-G3. In some embodiments, the power stage circuit 122 is a Y-bridge circuit, wherein the power stage circuit 122 includes a plurality of switches Q1-Q3, wherein the control signal G1 is configured to control the switch Q1, the control signal G2 is configured to control the switch Q2, and the control signal G3 is configured to control the switch Q3. In this embodiment, the switch Q2 is coupled between the light-load supply voltage VL and a switching node LX, the switch Q1 is coupled between the heavy-load supply voltage VH and the switching node LX, and the switch Q3 is coupled between the switching node LX and a ground potential.

[0103] When the light-load indication signal POI is in the disabled state, the logic driving circuit 121 generates a plurality of control signals G1-G3 according to the first relay pulse-width modulation signal MS1. At this time, the power stage circuit 122 controls the conduction states of the switches Q1-Q3 according to the control signals G1-G3, thereby generating an output pulse-width modulation signal VLX at the switching node LX. In this case, the switch Q2 is always off, and the switches Q1 and Q3 are periodically and complementary switched between the on state and the off state, so that the amplitude of the output pulse-width modulation signal is a multiple of the heavy-load supply voltage VH. When the light-load indication signal POI is in the enabled state, the logic driving circuit 121 generates a plurality of control signals G1-G3 according to the second relay pulse-width modulation signal MS2. At this time, the power stage circuit 122 controls the conduction states of the switches Q1-Q3 respectively according to the control signals G1-G3, thereby generating an output pulse-width modulation signal VLX, wherein the switch Q1 is always off, and the switches Q2 and Q3 are periodically and complementary switched between the on state and the off state, so that the amplitude of the output pulse-width modulation signal VLX is at the level of the light-load supply voltage VL.

[0104] In some embodiments, the power stage circuit 122 is further coupled to an output inductor Lout, so that the output pulse width modulation signal VLX generated by the power stage circuit 122 is filtered by the output inductor Lout and the output capacitor Cout to generate an output signal VOUT, and the output signal VOUT is further supplied to an external load LD.

[0105] Please also refer to Figure 3A and Figure 4 , Figure 4 FIG. 1 is a flow chart of a Class D amplifier 100 operating in a pulse width modulation method in one embodiment of the present invention. Figure 4As shown, first, the linear cycle wave generators 111A and 111B of the Class D amplifier 100 generate a first linear cycle wave TR1 and a second linear cycle wave TR2, respectively, where the amplitude of the first linear cycle wave TR1 is greater than the amplitude of the second linear cycle wave TR2 (step S200). Next, the comparator 112A of the Class D amplifier 100 compares the input signal VIN with the first linear cycle wave TR1 to generate a first relay pulse-width modulation signal MS1. The comparator 112B of the Class D amplifier 100 compares the input signal VIN with the second linear cycle wave TR2 to generate a second relay pulse-width modulation signal MS2 (step S210). Subsequently, the determination circuit 130 of the Class D amplifier 100 determines whether the level of the input signal VIN is below a light-load threshold (step S220). If so, the pulse generating circuit 120 of the class-D amplifier 100 generates the output PWM signal VLX according to the second relay PWM signal MS2 (step S230 ). If not, the pulse generating circuit 120 of the class-D amplifier 100 generates the output PWM signal VLX according to the first relay PWM signal MS1 (step S240 ).

[0106] Please refer to Figure 5A , Figure 5A FIG. 1 is a block diagram of a Class D amplifier 200 according to another embodiment of the present invention. Figure 5A As shown, the class-D amplifier 200 includes a pulse width modulation circuit 210, a pulse generation circuit 220, and a determination circuit 230, wherein the pulse generation circuit 220 is coupled to the pulse width modulation circuit 210 and the determination circuit 230. The structures and functions of the pulse width modulation circuit 210, the pulse generation circuit 220, and the determination circuit 230 will be explained in detail below.

[0107] In some embodiments, the pulse width modulation circuit 210 is configured to generate a selected pulse width modulation signal MSS based on an input signal VIN and a selected linear cycle wave TRS. The pulse width modulation circuit 210 selects either a first linear cycle wave TR1 or a second linear cycle wave TR2 as the selected linear cycle wave TRS based on the state of a light load indication signal POI. In some embodiments, the pulse width modulation circuit 210 includes a plurality of linear cycle wave generators 211A and 211B, a selection circuit 212, and a comparator 213. The linear cycle wave generator 211A is configured to generate the first linear cycle wave TR1 based on a first clock signal CLK1, and the linear cycle wave generator 211B is configured to generate the second linear cycle wave TR2 based on a second clock signal CLK2. The selection circuit 212 is configured to select either the first linear periodic wave TR1 or the second linear periodic wave TR2 as the selected linear periodic wave TRS based on the state of the light load indication signal POI. When the light load indication signal POI is in the disabled state (indicating a heavy load), the selection circuit 212 selects the first linear periodic wave TR1 as the selected linear periodic wave TRS. When the light load indication signal POI is in the enabled state (indicating a light load), the selection circuit 212 selects the second linear periodic wave TR2 as the selected linear periodic wave TRS. The comparator 213 compares the input signal VIN with the selected linear periodic wave TRS to generate the selected pulse-width modulation signal MSS. In some embodiments, the linear periodic wave generators 211A and 211B are triangular wave generators or sawtooth wave generators, the first linear periodic wave TR1 and the second linear periodic wave TR2 are triangular waves or sawtooth waves, and the selection circuit 212 is a multiplexer. The structure and function of the multiplexer and comparator 213 are well known to those skilled in the art and are not described in detail.

[0108] In some embodiments, the pulse generating circuit 220 is configured to generate an output pulse-width modulation signal VLX based on the light-load indication signal POI, the selected pulse-width modulation signal MSS, the heavy-load supply voltage VH, and the light-load supply voltage VL. When the light-load indication signal POI is in the disabled state, indicating that the input signal VIN is in a heavy-load state, the pulse generating circuit 220 generates the output pulse-width modulation signal VLX based on the selected pulse-width modulation signal MSS and the heavy-load supply voltage VH. When the light-load indication signal POI is in the enabled state, indicating that the input signal VIN is in a light-load state, the pulse generating circuit 220 generates the output pulse-width modulation signal VLX based on the selected pulse-width modulation signal MSS and the light-load supply voltage VL. In some embodiments, the heavy-load supply voltage VH is higher than the light-load supply voltage VL.

[0109] In some embodiments, the determination circuit 230 is configured to determine whether the level of the input signal VIN is lower than a light-load threshold. The determination circuit 230 generates a light-load indication signal POI based on the input signal VIN and the light-load threshold. When the level of the input signal VIN is lower than the light-load threshold, the light-load indication signal POI is enabled, indicating that the input signal VIN is in a light-load state. When the level of the input signal VIN is higher than the light-load threshold, the light-load indication signal POI is disabled, indicating that the input signal VIN is in a heavy-load state.

[0110] Please refer to Figure 5B , Figure 5B FIG. 2 is a circuit diagram of the pulse generating circuit 220 in another embodiment of the present invention. Figure 5B As shown, in some embodiments, the pulse generation circuit 220 includes a logic driver circuit 221 and a power stage circuit 222, wherein the logic driver circuit 221 is coupled to the power stage circuit 222. In some embodiments, the logic driver circuit 221 is configured to generate a plurality of control signals G4-G6 based on the light load indication signal POI and the selected pulse width modulation signal MSS, thereby driving the operation of the power stage circuit 222. The power stage circuit 222 is configured to generate an output pulse width modulation signal VLX based on the plurality of control signals G4-G6. In some embodiments, the power stage circuit 222 is a Y-bridge circuit, wherein the power stage circuit 222 includes a plurality of switches Q4-Q6, wherein the control signal G4 is configured to control the switch Q4, the control signal G5 is configured to control the switch Q5, and the control signal G6 is configured to control the switch Q6. In this embodiment, the switch Q5 is coupled between the light-load supply voltage VL and a switching node LX, the switch Q4 is coupled between the heavy-load supply voltage VH and the switching node LX, and the switch Q6 is coupled between the switching node LX and a ground potential.

[0111] When the light load indication signal POI is in the disabled state, the logic driving circuit 221 generates a plurality of control signals G4-G6 according to the selected pulse width modulation signal MSS. At this time, the power stage circuit 222 controls the conduction states of the switches Q4-Q6 according to the control signals G4-G6, thereby generating an output pulse width modulation signal VLX at the switching node LX. In this case, the switch Q5 is always off, and the switches Q4 and Q6 are periodically and complementary switched between the on state and the off state, so that the amplitude of the output pulse width modulation signal VLX is equal to the heavy load supply voltage VH. level; when the light-load indication signal POI is in the enabled state, the logic driving circuit 221 also generates a plurality of control signals G4-G6 according to the selected pulse-width modulation signal MSS. At this time, the power stage circuit 222 controls the conduction states of the switches Q4-Q6 respectively according to the control signals G4-G6, thereby generating an output pulse-width modulation signal VLX, wherein the switch Q4 is always off, and the switches Q5 and Q6 are periodically and complementary switched between the on state and the off state, so that the amplitude of the output pulse-width modulation signal VLX is at the level of the light-load supply voltage VL.

[0112] Please also refer to Figure 5A and Figure 6 , Figure 6 FIG. 1 is a flow chart of another embodiment of the present invention, in which the class D amplifier 200 operates in a pulse width modulation method. Figure 6 As shown, first, the linear periodic wave generators 211A and 211B of the Class D amplifier 200 generate a first linear periodic wave TR1 and a second linear periodic wave TR2, respectively, where the amplitude of the first linear periodic wave TR1 is greater than the amplitude of the second linear periodic wave TR2 (step S300). Next, the determination circuit 230 of the Class D amplifier 200 determines whether the level of the input signal VIN is below a light-load threshold (step S310). If so, the selection circuit 212 of the Class D amplifier 200 selects the second linear periodic wave TR2 as the selected linear periodic wave TRS (step S320). If not, the selection circuit 212 of the Class D amplifier 200 selects the first linear periodic wave TR1 as the selected linear periodic wave TRS (step S330). Subsequently, the comparator 213 of the Class D amplifier 200 compares the input signal VIN with the selected linear periodic wave TRS to generate the selected pulse-width modulation signal MSS. Finally, the pulse generating circuit 220 of the class-D amplifier 200 generates an output pulse-width modulation signal VLX according to the selected pulse-width modulation signal MSS (step S340 ).

[0113] Please refer to Figure 7 , Figure 7 FIG. 1 is a signal waveform diagram of the judgment circuits 130 and 230 in one embodiment of the present invention. Figure 7As shown, when the determination circuits 130 and 230 determine whether the level of the input signal is lower than a light-load threshold, the determination circuits 130 and 230 first compare an offset linear periodic wave TRO with the input signal (including a positive-phase sub-signal Vinp and an inverse-phase sub-signal Vinn, which are complementary to each other) to generate a positive-phase sub-signal PSOp of an offset pulse-width modulation signal (corresponding to the positive-phase sub-signal Vinp of the input signal) and an inverse-phase sub-signal PSOn of an offset pulse-width modulation signal (corresponding to the inverse-phase sub-signal Vinn of the input signal). The offset linear periodic wave TRO is obtained by superimposing a non-zero common-mode offset Vos on the first linear periodic wave TR1, and the common-mode offset Vos is related to the light-load threshold. In this embodiment, the common mode level of the input signal and the first linear periodic wave TR1 is the same as the first common mode level Vcm1, and the common mode level of the offset linear periodic wave TRO is the offset common mode level Vcmo, wherein the value of the offset common mode level Vcmo is higher than the value of the first common mode level Vcm1 by the common mode offset Vos.

[0114] Next, the determination circuits 130 and 230 periodically determine whether both the positive-phase sub-signal PSOp of the offset pulse width modulation signal and the negative-phase sub-signal PSOn of the offset pulse width modulation signal have a pulse in the previous operation cycle Ts according to the operation cycle Ts of the offset linear periodic wave TRO. If so, the input signal level is determined to be lower than the light load threshold and the light load indication signal POI is enabled; if not, the input signal level is determined to be higher than the light load threshold and the light load indication signal POI is disabled. Figure 7 For example, the positive phase sub-signal PSOp of the offset PWM signal and the inverse phase sub-signal PSOn of the offset PWM signal both have a pulse in the operation period T3-T5, so the light load indication signal POI is enabled in the operation period T4-T6.

[0115] Please refer to Figure 8 , Figure 8 is a waveform comparison diagram of the first linear periodic wave TR1 and the second linear periodic wave TR2 in some embodiments of the present invention, wherein the common mode level of the first linear periodic wave TR1 is the first common mode level Vcm1, which is also the common mode level of the input signal, as will be described in detail later. In this embodiment, the duty cycle of the first relay pulse width modulation signal MS1 generated when the first linear periodic wave TR1 and the input signal are zero (AC amplitude is 0) is 50%. Figure 8As shown in (a), in this embodiment, the common mode level of the second linear cycle wave TR2 is the first common mode level Vcm1, so that the duty cycle of the second relay pulse width modulation signal MS2 generated by the second linear cycle wave TR2 and the input signal is zero (AC amplitude is 0) is 50% when idle. In some embodiments, the common mode level of the second linear cycle wave TR2 is the second common mode level Vcm2, and there is a non-zero common mode offset Vos between the second common mode level Vcm2 and the common mode level of the input signal VIN. Figure 8 As shown in (b), in this embodiment, the common-mode offset Vos is a positive value, so that the duty cycle of the second relay pulse width modulation signal MS2 generated when the second linear periodic wave TR2 and the input signal are zero (AC amplitude is 0, that is, idle) is less than 50% when idle; Figure 8 As shown in (c), in this embodiment, the common-mode offset Vos is a negative value, so that the duty cycle of the second relay pulse width modulation signal MS2 generated according to the second linear periodic wave TR2 and the input signal is zero (AC amplitude is 0) is greater than 50% when idle.

[0116] Please refer to Figure 9 , Figure 9 : is a waveform comparison diagram of the first linear periodic wave TR1 and the second linear periodic wave TR2 in some other embodiments of the present invention. In some embodiments, the frequency of the second linear periodic wave TR2 is X times the frequency of the first linear periodic wave TR1, where X is a rational number greater than or equal to 1. Figure 9 As shown in (a)-(d), in some embodiments, the frequency of the second linear periodic wave TR2 is twice the frequency of the first linear periodic wave TR1. Figure 9 As shown in (e), in this embodiment, the frequency of the second linear periodic wave TR2 is 3 / 2 times the frequency of the first linear periodic wave TR1.

[0117] In some embodiments, there is a non-zero predetermined phase difference between the first linear periodic wave TR1 and the second linear periodic wave TR2. Figure 9 As shown in (b), in this embodiment, the preset phase difference between the first linear periodic wave TR1 and the second linear periodic wave TR2 is 2π*(1 / 6). Figure 9 As shown in (d), in this embodiment, the preset phase difference between the first linear periodic wave TR1 and the second linear periodic wave TR2 is 2π*k, where k is a rational number.

[0118] In some embodiments, the amplitude of the first linear periodic wave TR1 is Y times the amplitude of the second linear periodic wave TR2, where Y is a non-integer greater than 1. Figure 9As shown in (a) to (d) of FIG. 1 , in these embodiments, the amplitude of the first linear periodic wave TR1 is twice the amplitude of the second linear periodic wave TR2. Figure 9 As shown in (e), in this embodiment, the amplitude of the first linear periodic wave TR1 is 3 / 2 times the amplitude of the second linear periodic wave TR2.

[0119] Please refer to Figure 10 , Figure 10 is a signal waveform diagram of the pulse width modulation circuits 110A and 110B in one embodiment of the present invention, wherein the first linear periodic wave TR1 and the second linear periodic wave TR2 of this embodiment correspond to Figure 8 In the triangle wave signal in (c), the pulse width modulation circuit 110A generates the first relay pulse width modulation signal MS1 according to the input signal VINP and the first linear periodic wave TR1, and the pulse width modulation circuit 110B generates the second relay pulse width modulation signal MS2 according to the input signal VINP and the second linear periodic wave TR2. The duty cycle of the first relay pulse width modulation signal MS1 is 50% when idle. Figure 10 As shown, the common-mode level of the input signal VINP and the common-mode level of the first linear cycle waveform TR1 is a first common-mode level Vcm1, and the common-mode level of the second linear cycle waveform TR2 is a second common-mode level Vcm2. The first common-mode level Vcm1 differs from the second common-mode level Vcm2 by a common-mode offset Vos, and the common-mode offset Vos is related to a light-load threshold. In this embodiment, because the common-mode offset Vos is a negative value, the duty cycle of the second relay pulse-width modulation signal MS2 generated by the second linear cycle waveform TR2 is greater than 50% during the idle state (as shown in period T4).

[0120] Please refer to Figure 11A and Figure 11B , Figure 11A and Figure 11B is a signal waveform diagram of the class D amplifiers 100 and 200 in one embodiment of the present invention, wherein Figure 11B for Figure 11A Zoom in. Figure 11AAs shown, when the level of the input signal VIN is lower than the light-load threshold value Vthl, the input signal VIN is in a light-load state and the light-load indication signal POI is in the enabled state (in this embodiment, the enabled state is a high-voltage state). At this time, the amplitude of the output pulse-width modulation signal VLX is the value of the light-load supply voltage VL, that is, the output pulse-width modulation signal VLX switches between the light-load supply voltage VL and 0; when the level of the input signal VIN is higher than the light-load threshold value Vthl, the input signal VIN is in a heavy-load state and the light-load indication signal POI is in the disabled state (in this embodiment, the disabled state is a low-voltage state). At this time, the amplitude of the output pulse-width modulation signal VLX is the value of the heavy-load supply voltage VH, that is, the output pulse-width modulation signal VLX switches between the heavy-load supply voltage VH and 0. The output signal VOUT is the waveform of the output pulse-width modulation signal VLX after being filtered by the output inductor Lout and the output capacitor Cout. As shown Figure 11B As shown, in some embodiments, when the value of the input signal VIN is 0, the duty cycle of the output pulse width modulation signal VLX is not 50%. For example, in this embodiment, when the value of the input signal VIN is 0, the duty cycle of the output pulse width modulation signal VLX is 25%.

[0121] In some embodiments, the amplitude of the output pulse-width modulated signal VLX when the level of the input signal VIN is higher than the light-load threshold Vth1 is greater than the amplitude of the output pulse-width modulated signal VLX when the level of the input signal VIN is lower than the light-load threshold Vth1. In other embodiments, the amplitude of the output pulse-width modulated signal VLX (hereinafter referred to as the heavy-load pulse-width signal) when the level of the input signal VIN is higher than the light-load threshold Vth1 is Z times the amplitude of the output pulse-width modulated signal VLX (hereinafter referred to as the light-load pulse-width signal) when the level of the input signal VIN is lower than the light-load threshold Vth1, where Z is a non-integer greater than 1. Figure 11A For example, the amplitude of the heavy-load pulse width signal is the level of the heavy-load supply voltage VH, such as 12 volts; the amplitude of the light-load pulse width signal is the level of the light-load supply voltage VL, such as 1.8 volts. Therefore, the amplitude of the heavy-load pulse width signal is greater than the amplitude of the light-load pulse width signal, and the amplitude of the heavy-load pulse width signal is 20 / 3 times the amplitude of the light-load pulse width signal.

[0122] In summary, the pulse width modulation method of the present invention generates relay pulse width modulation signals with different duty cycles by adjusting characteristics such as the common-mode offset of a linear periodic wave, thereby generating an adaptive output pulse width modulation signal. This allows the output pulse width modulation signal to have a duty cycle that is different from 50% when idle, thereby generating a lower idle current and reducing power loss. Furthermore, the pulse width modulation method of the present invention can also adaptively adjust the switching frequency and amplitude of the output pulse width modulation signal, allowing the switching frequency of the output pulse width modulation signal to be adaptively adjusted under light and heavy load conditions. For example, the switching frequency can be increased or the amplitude can be decreased under light load conditions to reduce ripple current, while the switching frequency can be decreased or the amplitude can be increased under heavy load conditions, thereby reducing power loss and improving conversion efficiency.

[0123] The present invention has been described above with respect to the preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention and is not intended to limit the scope of the rights of the present invention. The various embodiments described are not limited to individual applications, but can also be applied in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A pulse width modulation method for converting an input signal into a corresponding output pulse width modulation signal, comprising: generating a first linear periodic wave and a second linear periodic wave, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave, wherein the first linear periodic wave and the second linear periodic wave are a triangle wave or a sawtooth wave; determining whether the level of the input signal is lower than a light load threshold; When the level of the input signal is lower than the light-load threshold, generating the output pulse-width modulation signal according to a comparison between the input signal and the second linear periodic wave; and When the level of the input signal is higher than the light-load threshold, the output pulse width modulation signal is generated according to the comparison between the input signal and the first linear periodic wave; in, A non-zero common-mode offset exists between the common-mode level of the second linear periodic wave and the common-mode level of the input signal, such that when the level of the input signal is lower than the light-load threshold, the root mean square power of the output pulse-width modulated signal is less than the root mean square power of the output pulse-width modulated signal corresponding to a case where the common-mode offset is zero.

2. The pulse width modulation method according to claim 1, wherein: Also includes: Comparing the input signal with the first linear periodic wave to generate a first relay pulse width modulation signal, and comparing the input signal with the second linear periodic wave to generate a second relay pulse width modulation signal; When the level of the input signal is lower than the light-load threshold, generating the output pulse-width modulation signal according to the second relay pulse-width modulation signal; and When the level of the input signal is higher than the light-load threshold, the output pulse-width modulation signal is generated according to the first relay pulse-width modulation signal.

3. The pulse width modulation method according to claim 1, wherein: Also includes: When the level of the input signal is higher than the light-load threshold, selecting the first linear periodic wave as a selected linear periodic wave; When the level of the input signal is lower than the light-load threshold, selecting the second linear periodic wave as the selected linear periodic wave; and The input signal is compared with the selected linear periodic wave to generate a selected pulse width modulation signal, and the output pulse width modulation signal is generated according to the selected pulse width modulation signal.

4. The pulse width modulation method according to claim 1, wherein: When the value of the input signal is 0, the duty cycle of the output pulse width modulation signal is not 50%.

5. The pulse width modulation method according to claim 1, wherein: The frequency of the second linear periodic wave is X times the frequency of the first linear periodic wave, where X is a rational number greater than or equal to 1.

6. The pulse width modulation method according to claim 5, wherein: The X is a non-integer greater than 1.

7. The pulse width modulation method according to claim 1, wherein: There is a non-zero predetermined phase difference between the first linear periodic wave and the second linear periodic wave.

8. The pulse width modulation method according to claim 7, wherein: The preset phase difference is the product of 2π and a rational number.

9. The pulse width modulation method according to claim 1, wherein: The amplitude of the first linear periodic wave is Y times the amplitude of the second linear periodic wave, wherein Y is a non-integer greater than 1.

10. The pulse width modulation method according to claim 1, wherein: The amplitude of the output PWM signal when the level of the input signal is higher than the light-load threshold is greater than the amplitude of the output PWM signal when the level of the input signal is lower than the light-load threshold.

11. The pulse width modulation method according to claim 10, wherein: The device is further configured to control a power stage circuit to generate the output pulse width modulation signal, wherein the power stage circuit includes a plurality of switches, the plurality of switches including a first switch, a second switch, and a third switch, wherein the first switch is coupled between a light-load supply voltage and a switching node, the second switch is coupled between a heavy-load supply voltage and the switching node, and the third switch is coupled between the switching node and a ground potential, wherein the heavy-load supply voltage is higher than the light-load supply voltage; When the level of the input signal is lower than the light-load threshold, the power stage circuit controls the first switch and the third switch to periodically and complementary switch based on a comparison between the input signal and the second linear periodic waveform to generate the output pulse-width modulation signal at the switching node, wherein the output pulse-width modulation signal switches between the light-load supply voltage and the ground potential. When the level of the input signal is higher than the light-load threshold, the power stage circuit controls the second switch and the third switch to periodically and complementary switch according to a comparison between the input signal and the first linear periodic waveform, thereby generating the output pulse-width modulation signal at the switching node, wherein the output pulse-width modulation signal switches between the heavy-load supply voltage and the ground potential.

12. The pulse width modulation method according to claim 1, wherein: The amplitude of the output PWM signal when the input signal level is higher than the light load threshold is Z times the amplitude of the output PWM signal when the input signal level is lower than the light load threshold, wherein Z is a non-integer greater than 1.

13. The pulse width modulation method according to claim 1, wherein: The step of determining whether the level of the input signal is lower than the light load threshold comprises: Comparing an offset linear periodic wave with the input signal to generate an offset pulse width modulation signal, wherein the offset linear periodic wave is obtained by superimposing a non-zero common mode offset on the first linear periodic wave, and the common mode offset is related to the light load threshold; and periodically determining, based on an operation cycle of the offset linear periodic wave, whether both the in-phase sub-signal of the offset pulse width modulation signal and the inverted sub-signal of the offset pulse width modulation signal have a pulse in a previous operation cycle, thereby determining whether the level of the input signal is lower than the light-load threshold; The in-phase sub-signal of the input signal and the inverted sub-signal of the input signal are complementary to each other. The in-phase sub-signal of the offset pulse width modulation signal is obtained by comparing the offset linear periodic wave with the in-phase sub-signal of the input signal. The inverted sub-signal of the offset pulse width modulation signal is obtained by comparing the offset linear periodic wave with the inverted sub-signal of the input signal.

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