Heat dissipation structure

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to a heat dissipation structure and a method for manufacturing the same. The structure includes a thin film resistor located within a back-end-of-line (BOL) structure, and a heat dissipation structure located below the thin film resistor. The heat dissipation structure includes a top plate having a slotted configuration and located within the BOL structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to heat dissipation structures and methods of manufacturing the same. Background Art

[0002] Thermal design is a critical consideration in semiconductor devices. Optimizing the thermal design of a device enables better performance at different power levels, topologies, and applications. Thermal design often involves using heat sinks to dissipate heat away from heat-generating components and / or structures. Summary of the Invention

[0003] In one aspect of the present disclosure, a structure includes a thin film resistor within a back-end-of-line (BEOL) structure and a heat sink structure below the thin film resistor including a top plate having a slotted configuration and within the BEOL structure.

[0004] In one aspect of the present disclosure, a structure includes: a thin film resistor located within an insulator material; a heat sink separated from the thin film resistor by the insulator material; and a plurality of heat dissipation via connections contacting the heat sink from a bottom surface, the plurality of heat dissipation via connections being located within the insulator material.

[0005] In one aspect of the present disclosure, a method includes forming a thin film resistor within a back-end-of-line (BEOL) structure and forming a heat sink structure below the thin film resistor, the heat sink structure comprising a top plate having a slotted configuration and within the BEOL structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0007] Figure 1A An exploded three-dimensional view of a heat dissipation structure according to some aspects of the present disclosure, among other features, is shown.

[0008] Figure 1B Shows, among other features, some aspects of the present disclosure Figure 1A Cross-sectional view of the heat dissipation structure.

[0009] Figure 2A An exploded three-dimensional view of a heat dissipation structure is shown, among other features, according to additional aspects of the present disclosure.

[0010] Figure 2B Shown among other features according to additional aspects of the present disclosure Figure 2A Cross-sectional view of the heat dissipation structure.

[0011] Figures 3A-3E Shown for manufacturing Figure 1A and1B Various manufacturing steps and corresponding structures of the heat dissipation structure are shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures, and more particularly, to heat dissipation structures and methods for manufacturing the same. More specifically, the present disclosure relates to heat dissipation structures for use with thin film resistors and for dissipating heat generated by the thin film resistors. Advantageously, the heat dissipation structures provide a more efficient heat sink while stabilizing the sheet resistance (Rsh) offset in the thin film resistors during high current operation (compared to conventional structures). The heat dissipation structures also eliminate the risk of short circuits by using a slotted design.

[0013] In a more specific embodiment, a heat dissipation structure is disposed beneath the thin film resistor for dissipating heat generated by the thin film resistor. In an embodiment, the thin film resistor may be a SiCr thin film resistor, although other material compositions are contemplated herein for use with the heat dissipation structure. The heat dissipation structure may include a slotted design to avoid short circuits between contacts of the thin film resistor and metal structures in the underlying heat dissipation structure. The heat dissipation structure may include one or more metal plates (e.g., layers) and a large number of via connections connected to these plates. The metal plates and via connections may be formed in a back-end-of-line (BEOL) process of an integrated circuit (IC) chip (e.g., a SiCr-based thin film resistor in a copper (Cu) or aluminum (Al) BEOL).

[0014] The heat dissipation structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, typically, methods and tools are used to form structures having micron and nanometer dimensions. Methods (i.e., techniques) for manufacturing the heat dissipation structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material patterned on top of the wafer using a photolithographic process. In particular, the manufacture of the heat dissipation structure uses three basic configuration blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) etching the film selectively to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean the etched surface of any contaminants. In addition, due to the minimal element diffusion known in the art, a rapid thermal annealing process can be used to improve material utilization and composition control when necessary.

[0015] Figure 1A shows an exploded view of a heat dissipation structure according to some aspects of the present disclosure, Figure 1B A cross-sectional view of the heat dissipation structure is shown. More specifically, Figure 1A and 1BThe illustrated structure 10 includes a stack of interlayer dielectric material 12 comprising alternating layers of insulator material 12a, 12b. In an embodiment, in a back-end-of-line structure, the insulator material comprises alternating layers of oxide material 12a and nitride material 12b.

[0016] like Figure 1A and 1B As further shown, a heat dissipation structure 15 may be provided below the thin film resistor 18. In an embodiment, the thin film resistor 18 may include, but is not limited to, SiCr, TaN, TaNO, SiCr(O), SiCr(O,N), SiCr(O,N,B), SiCrNi, NiCr, or other known materials. In addition, in an embodiment, the SiCr material may include, but is not limited to, Si3Cr5 or SiCr or Si2Cr or SiCr3, etc. In an exemplary embodiment, the thin film resistor 18 may have a thickness of approximately to In other embodiments, the thickness of thin film resistor 18 may be equal to or less than the thickness of insulator layer 12b.

[0017] Heat dissipation structure 15 includes a plurality of heat dissipation plates 14a, 14b connected together by a plurality of heat dissipation via connections 16. In an embodiment, the plurality of heat dissipation via connections 16 are in direct contact with the bottom heat dissipation plate 14a and the top heat dissipation plate 14b. In this manner, the plurality of heat dissipation plates 14a, 14b and the plurality of heat dissipation via connections 16 form a single structure, thereby acting as a heat sink to remove heat generated by thin-film resistors 18. In an embodiment, the combination of the top heat dissipation plate 14b and the heat dissipation via connections 16 can be a dual damascene or single damascene structure, as examples.

[0018] The bottom heat sink 14a and the top heat sink 14b can be solid metal plates disposed within the layers 12a, 12b of the interlayer dielectric material 12. The top heat sink 14b can be separated from the thin film resistor 18 by an insulator layer 12b (e.g., a nitride material). In addition, in an embodiment, the top heat sink 14b can be at least the same size as the thin film resistor 18, for example, equal to or larger than the footprint of the thin film resistor 18. The multiple heat sinks 14a, 14b and the multiple heat dissipation via connections 16 can be made of a heat dissipation material such as a metal material. For example, the multiple heat sinks 14a, 14b and the multiple heat dissipation via connections 16 can be Cu, W, or Al, or combinations thereof, as well as other heat dissipation materials.

[0019] Furthermore, top heat sink 14b may include slots 14c aligned with via connections 20 connected to thin-film resistor 18. In a preferred embodiment, thin-film resistor 18 may be located between slots 14c. Via connections 20 are used to bias thin-film resistor 18. To this end, via connections 20 contact thin-film resistor 18 and upper wiring structure 22.

[0020] In embodiments, the groove 14c can be rectangular, square, oval, circular, or other shapes and filled with the interlayer dielectric material 12. In other embodiments, the groove 14c can be equal to or larger than the size of the via connection 20 to ensure that the via connection 20 does not contact or electrically short to the top heat sink 14b. For example, during the etching process of forming the via in the interlayer dielectric material 12, punch-through may occur, thereby exposing the top heat sink 14b. There are cases where depositing conductive material to form the via connection 20 may cause electrical contact between the top heat sink 14b and the via connection 20, thereby causing an electrical short. However, due to the slotted configuration of the top heat sink 14b, even if punch-through occurs during the manufacturing process (e.g., the etching process), the via connection 20 will fall on the insulator material and the top heat sink 14b will remain isolated from the via connection 20, thereby preventing an electrical short.

[0021] Figure 2A An exploded view illustrating an alternative configuration of a heat dissipation structure according to some aspects of the present disclosure, Figure 2B A cross-sectional view of the heat dissipation structure is shown. More specifically, Figure 2A and 2B The illustrated structure 10a includes a heat sink structure 15a positioned below a thin film resistor 18, wherein a top heat sink 14b' extends beyond or over a via connection 20 and an upper wiring structure 22. In this manner, a via connection 20a (via) can be provided directly to the top heat sink 14b', wherein a wiring structure 22a connected to the via connection 20a is at the same or a different level as the wiring structure 22. In an embodiment, the wiring structure 22a and the via connection 20a may also provide additional metal to assist in dissipating heat from the thin film resistor 18. Additionally, the wiring structure 22a and the via connection 20a may be used to provide a back bias for the heat sink structure 15a. The remaining features are the same as those of reference 10a. Figure 1A and 1B Same as described.

[0022] Figures 3A-3E Shown for manufacturing Figures 1A-1B The same or similar manufacturing steps can be used to manufacture various manufacturing processes and corresponding structures of the structure 10. Figures 2A-2B Specifically, Figure 3AAn interlayer dielectric material 12 is shown, wherein a bottom heat sink 14a is embedded in an upper insulator layer 12a. In an embodiment, the interlayer dielectric material 12 can be formed by sequentially depositing different insulator layers 12a, 12b (e.g., oxide and nitride). The deposition process can be, for example, a chemical vapor deposition (CVD) process.

[0023] Conventional photolithography, etching, and deposition methods known to those skilled in the art can be used to form the bottom heat sink 14a in the insulator layer 12a (oxide) of the interlayer dielectric material 12. For example, a resist formed above the insulator layer 12a is exposed to energy (light) to form a pattern (opening). An etching process with selective chemical action (e.g., reactive ion etching (RIE)) is used to transfer the pattern from the patterned photoresist layer to the insulator layer 12a to form trenches in the insulator layer 12a. After the resist is removed by a conventional oxygen ashing process or other known strippers, a conductive material can be deposited by any conventional deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or electrochemical plating (ECP) process) to form the bottom heat sink 14a. Any residual conductive material on the surface of the insulator layer 12a can be removed by a conventional chemical mechanical polishing (CMP) process.

[0024] exist Figure 3B , additional insulator layers 12b, 12a, 12b, 12a may be deposited over the bottom heat sink 14a. In an embodiment, the additional insulator layers 12b, 12a, 12b, 12a may be sequentially deposited using a CVD process. Using a conventional dual damascene process (or two single damascene processes), a plurality of vias 24 may be formed in the lower insulator layers 12b, 12a to expose the upper surface of the bottom heat sink 14a. Grooves 25 may be formed over the plurality of vias 24, extending through the upper insulator layers 12b, 12a. As will be appreciated by those skilled in the art, the patterning of the trenches 25 in the insulator layers 12b, 12a will result in the formation of grooves 14c, as shown in FIG. Figure 3C shown.

[0025] exist Figure 3C In the embodiment of the present invention, conductive material can be deposited within the plurality of vias 24 and trenches 25. In this way, the conductive material will form heat dissipation via connections 16 in contact with the bottom heat dissipation plate 14a and the top heat dissipation plate 14b in contact with the heat dissipation via connections 16. A chemical mechanical planarization (CMP) process can be used to planarize the upper surface of the top heat dissipation plate 14b.

[0026] Figure 3CAlso shown is an insulator layer 12b deposited over the top heat sink 14b, followed by the formation of thin film resistor 18. Thin film resistor 18 may be formed by depositing the material for thin film resistor 18 followed by conventional patterning processes using the photolithography and etching processes already described herein.

[0027] exist Figure 3D In the embodiment of the present invention, additional insulator layers 12a, 12b, 12a can be sequentially deposited on thin film resistor 18. Like other insulator layers, additional insulator layers 12a, 12b, 12a are sequentially deposited by a CVD process. By using a conventional dual damascene process (or two single damascene processes), a plurality of vias 26 and trenches 28 can be formed in additional insulator layers 12a, 12b, 12a to expose the upper surface of thin film resistor 18.

[0028] like Figure 3E As shown, a plurality of vias 26 and trenches 28 may be filled with a conductive material to form via connections 20 and wiring structures 22. In this manner, the conductive material will form via connections 20 that contact thin film resistors 18. A chemical mechanical planarization (CMP) process may be used to planarize the upper surface of top heat sink 14b.

[0029] Thermal dissipation structures can be utilized in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, an SoC consumes significantly less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0030] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0031] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: Thin film resistors, which are located in the back-end-of-line structure; a heat dissipation structure located below the thin film resistor, comprising a top plate having a slotted configuration and located within the back-end-of-the-line structure; as well as A plurality of via connections are connected to the thin film resistor, the via connections being located above and aligned with the slots of the slotted configuration of the top plate.

2. The semiconductor structure according to claim 1, wherein The back-end-of-line (BEOL) structure includes alternating layers of insulator material, at least one of which separates the thin-film resistor from the heat dissipation structure.

3. The semiconductor structure according to claim 1, wherein The top plate includes a footprint equal to or larger than that of the thin film resistor.

4. The semiconductor structure according to claim 1, wherein The groove of the top plate is larger than the plurality of via connections.

5. The semiconductor structure according to claim 1, wherein The grooves of the top plate are filled with an insulator material. The semiconductor structure according to claim 5 , wherein: The heat dissipation structure also includes additional via connections extending from the bottom side of the top plate.

7. The semiconductor structure according to claim 6, wherein: The heat dissipation structure further includes a base plate contacting the additional via connections.

8. The semiconductor structure according to claim 1, wherein The top plate extends beyond a footprint of the thin film resistor, and another via connection extends to and contacts the top plate beyond the footprint of the thin film resistor.

9. The semiconductor structure according to claim 8, wherein The further via connection is provided on one side of the slotted configuration of the top plate, and the thin film resistor is located on the other side of the slotted configuration.

10. A semiconductor structure comprising: Thin film resistors, which are located within an insulator material; a heat sink separated from the thin film resistor by the insulator material and comprising a trench filled with the insulator material, wherein the trench is located below and aligned with a via connection to the thin film resistor; as well as A plurality of heat dissipation via connections contacts the heat dissipation plate from the bottom surface, the plurality of heat dissipation via connections being located in the insulator material.

11. The semiconductor structure according to claim 10, wherein The heat sink plate includes a footprint equal to or larger than that of the thin film resistor.

12. The semiconductor structure of claim 10, further comprising: A bottom heat sink plate is connected to the plurality of thermal via connections such that the plurality of thermal via connections, the bottom heat sink plate, and the heat sink plate comprise a single structure.

13. The semiconductor structure according to claim 10, wherein The heat sink extends beyond the footprint of the thin film resistor.

14. The semiconductor structure of claim 13, further comprising: Another via connection contacts the heat sink beyond the footprint of the thin film resistor.

15. The semiconductor structure according to claim 14, wherein The other via is connected to the heat dissipation plate at one side of the slot.

16. The semiconductor structure according to claim 15, wherein The thin film resistor is located between the grooves.

17. A method for forming a semiconductor structure, comprising: forming thin film resistors within back-end-of-line structures; forming a heat dissipation structure below the thin film resistor, the heat dissipation structure comprising a top plate having a slotted configuration and positioned within the back-end-of-the-line structure; as well as A plurality of via connections are formed to the thin film resistor, the via connections being located above and aligned with the slots of the slotted configuration of the top plate.

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