Three-dimensional stacked chip and bonding test method and test machine thereof
By setting bonding nodes and test circuits in a 3D stacked chip, and combining test control circuits and signal processors, the yield problem of hybrid bonding interconnects in 3D integrated circuits was solved, achieving more accurate anomaly location and yield improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XI AN UNIIC SEMICON CO LTD
- Filing Date
- 2021-12-15
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies make it difficult to accurately locate yield issues introduced by hybrid bonding connections in 3D integrated circuit packaging, resulting in difficulties in improving chip yield.
By setting a first bonding node and a second bonding node in a three-dimensional stacked chip, the two wafers are connected by bonding test lines, and abnormalities in the mixed bonding connections are judged by test excitation signals and result signals. Anomaly testing is achieved by combining test control circuits and signal processors.
It enables abnormal testing of hybrid bonding connections, which can more accurately locate chip abnormalities, improve chip yield, and save time and costs.
Smart Images
Figure CN116266543B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional stacked chip and its bonding test method and test equipment. Background Technology
[0002] With the continuous development of semiconductor packaging technology, ASIC (Application Specific Integrated Circuit) based on 3DIC (Three Dimensional Integrated Circuit) packaging with multi-wafer hybrid bonding is becoming increasingly widespread. Multi-wafer hybrid bonding is the core of 3DIC packaging, and the yield of the hybrid bonding interconnects directly affects the yield of the chip. Summary of the Invention
[0003] This application provides a three-dimensional stacked chip and its bonding test method and test equipment, which can realize the abnormal testing of hybrid bonding connection, and help to more accurately locate chip abnormalities.
[0004] In a first aspect, embodiments of this application provide a three-dimensional stacked chip, comprising: at least two wafers connected by hybrid bonding, wherein the two wafers in the hybrid bonding are:
[0005] A first bonding node and a second bonding node are configured;
[0006] The first bonding node and the second bonding node are connected by a bonding test line, which includes at least one hybrid bonding connection line for connecting two wafer layers.
[0007] The first bonding node receives a test excitation signal, and the second bonding node outputs a test result signal, which characterizes the abnormal situation of the mixed bonding connection in the bonding test circuit.
[0008] Furthermore, the first bonding node is connected to a test control circuit, which is in test mode based on the received control signal and receives the test excitation signal in the test mode; the control signal is an external control signal.
[0009] Furthermore, the first bonding node and the second bonding node are also connected to their respective corresponding functional circuits, and the connection between the second bonding node and the corresponding functional circuit is connected to a signal output line, which is used to output the test result signal.
[0010] The test control circuit is also in a functional mode based on the received control signal, in which the test control circuit is turned off.
[0011] Furthermore, the test control circuit includes a first selector, which includes a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein:
[0012] The first input terminal is connected to the first bonding node in the wafer via a corresponding functional circuit. The second input terminal is connected to the excitation input terminal that inputs the test excitation signal. The control terminal is connected to the mode selection terminal that inputs the control signal. The output terminal is connected to the first bonding node.
[0013] Furthermore, the number of hybrid bonding lines is odd, and the odd number of hybrid bonding lines are connected in series to form the bonding test circuit; wherein the first bonding node and the second bonding node are located on different wafers.
[0014] Furthermore, the number of hybrid bonding lines is even, and the even number of hybrid bonding lines are connected in series to form the bonding test circuit; wherein, the first bonding node and the second bonding node are located on the same wafer.
[0015] Furthermore, the bonding test circuit includes multiple hybrid bonding lines; the three-dimensional stacked chip also includes transition bonding nodes, which are respectively disposed on the two wafer layers; the multiple hybrid bonding lines are cascaded sequentially through the transition bonding nodes to form the bonding test circuit. In the bonding test circuit, a second selector is disposed between two adjacent transition bonding nodes located on the same wafer. The first input terminal of the second selector is connected to the preceding transition bonding node, the second input terminal is connected to the functional circuit corresponding to the subsequent transition bonding node, the control terminal is connected to the mode selection terminal for inputting control signals, and the output terminal is connected to the subsequent transition bonding node.
[0016] Furthermore, the first bonding node and the second bonding node are disposed on different wafers; and each of the first bonding node and the second bonding node is connected to a corresponding hybrid bonding line.
[0017] Furthermore, the wafer containing the second bonding node in the aforementioned three-dimensional stacked chip is also equipped with a parallel signal processor. The input terminals of the parallel signal processor are respectively connected to the second bonding node, and the output terminals of the parallel signal processor are connected to the corresponding test result output terminals. The parallel signal processor is used to process the M test result signals output by the second bonding node into N signals and output them to the corresponding test result output terminals, where N is less than M.
[0018] Furthermore, the parallel signal processor is an encoder or a shift register.
[0019] Furthermore, in response to both the test excitation signal and the test result signal being low or both being high, the mixed bonding connection in the bonding test circuit is in a normal connection state;
[0020] In response to one of the test excitation signal and the test result signal being at a low level and the other being at a high level, the mixed bonding connection in the bonding test circuit is in an abnormal connection state.
[0021] Secondly, embodiments of this application provide a bonding test method, the method comprising:
[0022] Receive test excitation signal;
[0023] Based on the test excitation signal, a test result signal is output. The test result signal characterizes the abnormality of the mixed bonding connection in the bonding test circuit. The mixed bonding connection is used to connect two wafer layers.
[0024] Furthermore, before receiving the test excitation signal, the procedure further includes:
[0025] In response to the received external control signal, switch to test mode.
[0026] Thirdly, embodiments of this application provide a bonding test method, the method comprising:
[0027] Input test excitation signals into the three-dimensional stacked chip;
[0028] The test result signal output by the three-dimensional stacked chip is received, and based on the test result signal, the abnormal situation of the mixed bonding connection in the bonding test line is obtained. The mixed bonding connection is used to connect two wafers in the three-dimensional stacked chip.
[0029] Furthermore, before inputting the test stimulus signal to the three-dimensional stacked chip, the process further includes:
[0030] A control signal is input to the three-dimensional stacked chip, and the control signal is used to control the three-dimensional stacked chip to switch to test mode.
[0031] Furthermore, the step of obtaining abnormal conditions of mixed bonding connections in the bonding test circuit based on the test result signal includes:
[0032] In response to the test result signal meeting the preset conditions, it is determined that the hybrid bonding connection in the bonding test circuit is in a normal connection state.
[0033] If the test result signal does not meet the preset condition, it is determined that the hybrid bonding connection in the bonding test circuit is in an abnormal connection state.
[0034] Fourthly, embodiments of this application provide a testing machine, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the steps of the bonding test method provided in the third aspect above.
[0035] The three-dimensional stacked chip and its bonding test method and test equipment provided in this application embodiment, by setting a first bonding node and a second bonding node in two hybrid-bonded wafers, the first bonding node and the second bonding node are connected by a bonding test line, which includes at least one hybrid bonding connection used to connect the two wafers. The first bonding node receives a test stimulus signal, and the second bonding node outputs a test result signal. The test result signal characterizes the abnormality of the hybrid bonding connection in the bonding test line. In this way, by injecting a test stimulus signal from outside the chip to the first bonding node, the abnormality of the hybrid bonding connection in the bonding test line can be obtained according to the test result signal output from the second bonding node. This enables the testing of abnormalities in the hybrid bonding connection, which is beneficial for more accurate location of chip abnormalities.
[0036] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description
[0037] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0038] Figure 1 A schematic diagram of an exemplary split structure of a three-dimensional stacked chip is shown in an embodiment of this specification;
[0039] Figure 2 A partial pin diagram of the three-dimensional stacked chip in an embodiment of this specification is shown;
[0040] Figure 3 A schematic diagram of an exemplary bonding test circuit in a three-dimensional stacked chip is shown in an embodiment of this specification;
[0041] Figure 4A flowchart of a bonding test method according to an embodiment of this specification is shown;
[0042] Figure 5 A flowchart of another bonding test method in an embodiment of this specification is shown;
[0043] Figure 6 A schematic diagram of the test machine in an embodiment of this specification is shown. Detailed Implementation
[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0045] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0046] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0047] Currently, when testing chips based on 3DIC packaging with CP (Chip Probe), only the yield data of the entire chip can be obtained. However, it is not possible to accurately pinpoint whether the yield problem is caused by the manufacturing of multiple wafers or by the hybrid bonding interconnects, making it difficult to find a suitable solution to the yield problem.
[0048] In view of this, embodiments of this specification provide a three-dimensional stacked chip, comprising: at least two wafers connected by hybrid bonding, wherein the two wafers are provided with: a first bonding node and a second bonding node; the first bonding node and the second bonding node are connected by a bonding test circuit, the bonding test circuit including at least one hybrid bonding connection, the hybrid bonding connection being used to connect the two wafers; the first bonding node receives a test excitation signal, the second bonding node outputs a test result signal, the test result signal characterizing the abnormality of the hybrid bonding connection in the bonding test circuit.
[0049] In this way, by injecting a test stimulus signal from outside the chip into the first bonding node, the abnormality of the hybrid bonding connection in the bonding test circuit can be obtained based on the test result signal output from the second bonding node. This enables abnormal testing of the hybrid bonding connection, which is beneficial for more accurate chip fault location. In addition, it can quickly locate abnormalities in the hybrid bonding connection, thereby saving time for improving chip yield and reducing costs.
[0050] The specific implementation schemes provided in the embodiments of this specification will be described in detail below.
[0051] Firstly, the embodiments of this specification provide a three-dimensional stacked chip, such as... Figure 1 As shown, the three-dimensional stacked chip 10 includes at least two wafers connected by hybrid bonding. It should be noted that... Figure 1 The total number of wafer layers and the number of wafer layers connected by hybrid bonding shown are for illustrative purposes only, and this embodiment does not limit these numbers.
[0052] The two-layer wafer with hybrid bonding has a first bonding node and a second bonding node. The first and second bonding nodes are connected by a bonding test circuit. The bonding test circuit includes at least one hybrid bonding connection used to connect the two wafer layers.
[0053] During testing, the first bonding node receives the test stimulus signal, which is transmitted through the bonding test circuit. The second bonding node outputs the test result signal. The test result signal indicates any abnormality in the mixed bonding connections within the bonding test circuit. For example, if both the test stimulus signal and the test result signal are low or both are high, the mixed bonding connections in the bonding test circuit are in a normal connection state. If one of the test stimulus signal or the test result signal is low and the other is high, the mixed bonding connections in the bonding test circuit are in an abnormal connection state.
[0054] In one alternative implementation, to facilitate the control chip entering test mode, such as... Figure 1 As shown, the first bonding node is connected to a test control circuit 102. The test control circuit 102 is in test mode based on the received control signal and receives the aforementioned test excitation signal in test mode to realize the aforementioned hybrid bonding connection anomaly test. The control signal is an external control signal, for example, it can be sent to the chip by a test machine.
[0055] Furthermore, the first bonding node and the second bonding node are also connected to their respective corresponding functional circuits 101. Through the hybrid bonding connection, the signal output from the functional circuit 101 in one wafer layer can be transmitted to the corresponding functional circuit 101 in the other wafer layer. The connection between the second bonding node and the corresponding functional circuit 101 is connected to a signal output line, which outputs the aforementioned test result signal. At this time, the test control circuit 102 is also in functional mode based on the received control signal. In functional mode, the test control circuit 102 is turned off. At this time, the first bonding node and the corresponding functional circuit 101 are connected and in normal working condition, and the aforementioned test excitation signal cannot be received.
[0056] For example, such as Figure 1 As shown, the three-dimensional stacked chip 10 includes a first wafer 110, a second wafer 120, and a third wafer 130 stacked sequentially. The first wafer 110 and the second wafer 120, as well as the second wafer 120 and the third wafer 130, are connected via hybrid bonding. Corresponding bonding nodes are then formed on the hybrid-bonded wafers, which are connected by hybrid bonding lines (e.g., ...). Figure 1 (As shown by the dashed line in the image). Figure 1 As shown, the corresponding bonding node pairs in the first wafer 110 and the second wafer 120 are: P1-P1′, P2-P2′, and P3-P3′; the corresponding bonding node pairs in the second wafer 120 and the third wafer 130 are: Q1-Q1′, Q2-Q2′, and Q3-Q3′. It should be noted that... Figure 1 The number of bonding node pairs shown is for illustrative purposes only. The specific number will be determined based on the number of bonding node pairs required for bonding between wafers in the actual application scenario.
[0057] In the example above, node P1 is connected to functional circuit 1 in the first wafer 110, node P2 is connected to functional circuit 2 in the first wafer 110, and node P3 is connected to functional circuit 3 in the first wafer 110; node P1′ is connected to functional circuit 1′ in the second wafer 120, node P2′ is connected to functional circuit 2′ in the second wafer 120, and node P3′ is connected to functional circuit 3′ in the second wafer 120; similarly, Q1-Q1′, Q2-Q2′, and Q3-Q3′ are also connected to their respective functional circuits, which will not be detailed here. It should be noted that... Figure 1 For illustrative purposes, the functional circuits connected by each bonding node are uniformly represented by ellipses.
[0058] Based on this, embodiments of this specification define a first bonding node and a second bonding node among these bonding nodes of the bonding wafer.
[0059] In one alternative implementation, such as Figure 1 As shown, the test control circuit 102 can be located between the first bonding node and the corresponding functional circuit 101. The test control circuit 102 controls the three-dimensional stacked chip 10 to operate in either test mode or functional mode based on the received control signal Cr. In functional mode, the first bonding node is in a conducting state with the corresponding functional circuit 101, but disconnected from the excitation input terminal, and cannot receive the test excitation signal T_in input from the excitation input terminal. In test mode, the first bonding node is in a disconnected state with the corresponding functional circuit 101, but conducting with the excitation input terminal, and can receive the test excitation signal T_in input from the excitation input terminal. At this time, the signal output line can output the test result signal T_out.
[0060] By setting up the above-mentioned test control circuit 102 and signal output line, when it is necessary to perform hybrid bonding yield test, the control signal Cr and the test excitation signal T_in are input from outside the chip, which can determine whether there are any abnormalities in the hybrid bonding connection in each bonding test line. This can conveniently and effectively realize the abnormal test of the chip's hybrid bonding connection.
[0061] In one optional implementation, the determination of the first and second bonding nodes in the two hybrid-bonded wafers can be based on the flow of functional signals in the corresponding hybrid bonding connections. That is, the first bonding node is a signal transmitting node, used to transmit the functional signals output by the corresponding functional circuit 101 to the bonded wafer, and the second bonding node is a signal receiving node, used to receive the functional signals transmitted by the bonded wafer and transmit them to the connected functional circuit 101. Of course, in other implementations, the first bonding node can also be a signal receiving node, and the second bonding node can be a signal transmitting node; or, some of the first bonding nodes can be signal transmitting nodes, and others can be signal receiving nodes. This embodiment does not limit this.
[0062] Specifically, the test control circuit 102 may include a first selector, which includes a first input terminal, a second input terminal, a control terminal, and an output terminal. The first input terminal is connected to the functional circuit 101 corresponding to the first bonding node on its respective wafer, and the second input terminal is connected to the excitation input terminal (e.g., for inputting the test excitation signal T_in) used for inputting the test excitation signal T_in. Figure 2 The pin shown (ca1) is connected, and the control terminal is connected to the mode selection terminal (e.g., for input control signal Cr) Figure 2 The pin shown (ca0) is connected, and the output terminal is connected to the first bonding node. Of course, in other embodiments of this specification, the above-described test control circuit 102 can also be implemented using other circuit structures such as logic gate circuits; this is not a limitation. It should be noted that... Figure 2 Only a portion of the pins of the 3D stacked chip 10 are shown; the rest are not.
[0063] When the control terminal of the first selector receives the first control signal from an external input, it controls the first input terminal and output terminal to conduct, that is, the first bonding node is connected to the corresponding functional circuit 101 and disconnected from the excitation input terminal pin:ca1, and the 3D stacked chip 10 operates in functional mode. When the control terminal receives the second control signal from an external input, it controls the second input terminal and output terminal to conduct, that is, the first bonding node is disconnected from the corresponding functional circuit 101 and connected to the excitation input terminal pin:ca1, so that the 3D stacked chip 10 operates in test mode. After switching to test mode, the test excitation signal T_in can be input to the second input terminal through the excitation input terminal pin:ca1, so that the test excitation signal T_in enters the bonding test line formed between the first bonding node and the corresponding second bonding node from the first bonding node. Subsequently, the signal output from the signal output line connected to the second bonding node is the test result signal T_out of the bonding test line. By detecting the test result signal T_out, it is possible to determine whether there are any abnormalities in the hybrid bonding connections contained in the bonding test line, and realize Hybrid bonding yield analysis. For details of the specific testing process, please refer to the bonding test method implementation examples below, which will not be elaborated here.
[0064] It should be noted that, in order to reduce the pin layout pressure of the three-dimensional stacked chip 10, in specific implementations, existing idle pins of the chip can be reused as excitation input terminals and test result output terminals connected to the signal output lines, respectively. Of course, in other embodiments of this specification, the excitation input pins and test output pins can also be configured independently as excitation input terminals and test result output terminals, respectively.
[0065] In practice, there are multiple ways to configure the bonding test circuit, and the specific configuration can be determined according to actual needs.
[0066] For example, a bonding test circuit can include a hybrid bonding connection. That is, for each pair of hybrid bonding nodes in two wafers with hybrid bonding, one bonding node can be designated as the first bonding node and the other as the second bonding node. In this case, the first and second bonding nodes are located on different wafers, and each first bonding node is connected to the second bonding node via a hybrid bonding connection. Figure 1 Taking the bonding node pair P1-P1′ as an example, P1 node can be considered the first bonding node, and P1′ node as the second bonding node. P1 node is connected to its corresponding functional circuit 1 via a first selector. The first input terminal of the first selector is connected to functional circuit 1, the second input terminal is connected to the excitation input terminal pin:ca1, the control terminal is connected to the mode selection terminal pin:ca0, and the output terminal is connected to P1 node. A signal output line is connected to the line between P1′ node and functional circuit 1′. This signal output line is connected to... Figure 2 The test result output pin shown is ca2. At this point, each pair of bonding nodes corresponds to one signal output line, which allows for testing of whether there are any abnormalities in the mixed bonding connections between each pair of bonding nodes, facilitating more accurate location of abnormal mixed bonding connections.
[0067] For example, the bonding test circuit may include multiple mixed bonding connections, which can be divided into the following two cases.
[0068] The first type involves an odd number of mixed bond lines in the bonding test circuit, connected in series to form the test circuit. In this case, the first and second bond nodes corresponding to the test circuit are located on different wafers. For example, as shown... Figure 1 As shown, the bonding test circuit includes three hybrid bonding lines, denoted as BL1, BL2, and BL3. BL1, BL2, and BL3 are the hybrid bonding lines between hybrid bonding nodes Q1-Q1′, Q2-Q2′, and Q3-Q3′, respectively. In this case, Q1 can be used as the first bonding node, and Q3′ as the second bonding node, located on the second wafer 120 and the third wafer 130, respectively.
[0069] The second type involves an even number of mixed bond lines in the bonding test circuit, connected in series to form the test circuit. In this case, the first and second bond nodes corresponding to the test circuit are located on the same wafer. For example, Figure 3 The bonding test circuit shown includes four hybrid bonding connections, denoted as KL1, KL2, KL3, and KL4. KL1, KL2, KL3, and KL4 are hybrid bonding connections between hybrid bonding nodes W1-W1′, W2-W2′, W3-W3′, and W4-W4′, respectively. In this case, hybrid bonding node W1 can be considered the first bonding node, and hybrid bonding node W4 can be considered the second bonding node. Both W1 and W4 are located on the second wafer 120.
[0070] At this point, the 3D stacked chip 10 also includes transition bonding nodes, which are respectively disposed on the two wafer layers. The aforementioned multiple hybrid bonding lines are cascaded sequentially through the transition bonding nodes to form a bonding test line. This allows for centralized testing of multiple hybrid bonding lines for anomalies, which helps reduce the occupation of wafer layout and routing resources. It should be noted that the specific configuration of the bonding test line can be determined according to the actual hybrid bonding yield analysis requirements. For example, the area where the hybrid bonding nodes are concentrated can be divided into a partition, or the functional signals transmitted by the bonding nodes can be partitioned. Hybrid bonding nodes used to transmit the same or corresponding functional signals, such as data signal transmission nodes, can be divided into a partition, thereby connecting multiple hybrid bonding lines in the same partition into a single bonding test line. No restrictions are imposed here.
[0071] For example, such as Figure 1 The bonding test circuit shown includes hybrid bonding connections BL1, BL2, and BL3. If node Q1 is the first bonding node and node Q3' is the second bonding node, then nodes Q1', Q2', Q2, and Q3 are the corresponding transition bonding nodes for this bonding test circuit, cascaded sequentially as follows: Q1→BL1→Q1'→Q2'→BL2→Q2→Q3→BL3→Q3'. In this case, node Q1 is connected to its corresponding functional circuit via a first selector. The first input terminal of the first selector is connected to the corresponding functional circuit, the second input terminal is connected to the excitation input terminal pin:ca1, the control terminal is connected to the mode selection terminal pin:ca0, and the output terminal is connected to node Q1. A signal output line is connected between node Q3' and the corresponding functional circuit, and this signal output line is connected to the test result output terminal pin:ca2.
[0072] In an optional implementation, to achieve cascading between two adjacent transition bonding nodes located on the same wafer, a second selector 103 can be provided between the two adjacent transition bonding nodes located on the same wafer. The first input terminal of the second selector 103 is connected to the preceding transition bonding node, the second input terminal is connected to the functional circuit corresponding to the subsequent transition bonding node, the control terminal is connected to the mode selection terminal for inputting control signals, and the output terminal is connected to the subsequent transition bonding node.
[0073] For example, in the above cascaded example Q1→BL1→Q1′→Q2′→BL2→Q2→Q3→BL3→Q3′, a second selector 103 can be set between Q1′→Q2′ and between Q2→Q3, assuming they are represented as MUX1 and MUX2 respectively.
[0074] For Q1′→Q2′, the preceding stage transition bonding node is Q1′, and the following stage transition bonding node is Q2′. The first input terminal of MUX1 is connected to Q1′, and the second input terminal is connected to the functional circuit corresponding to the Q2′ node. The control terminal is connected to the mode selection terminal pin: ca0, and the output terminal is connected to the Q2′ node. For Q2→Q3, the preceding stage transition bonding node is Q2, and the following stage transition bonding node is Q3. The first input terminal of MUX2 is connected to Q2, and the second input terminal is connected to the functional circuit corresponding to the Q3 node. The control terminal is connected to the mode selection terminal pin: ca0, and the output terminal is connected to the Q3 node. In test mode, under the action of the control signal, the control terminals of MUX1 and MUX2 switch to the first input terminal and the output terminal to conduct, thus controlling the cascading of Q1→BL1→Q1′→Q2′→BL2→Q2→Q3→BL3→Q3′.
[0075] In this way, in test mode, the test excitation signal input to node Q1 can be transmitted sequentially through BL1, Q1′, Q2′, BL2, Q2, Q3, and BL3 to node Q3′, and then through the signal output line connected to node Q3′ to the test result output pin:ca2, which is output off-chip to test whether there are any abnormalities in the hybrid bonding connections contained in the bonding test circuit, that is, whether there are any abnormalities in the hybrid bonding connections BL1, BL2, and BL3.
[0076] In practice, there are multiple ways to output the test result signal for each signal output line. For example, each signal output line can be connected to a corresponding test result output terminal, so that each test result output terminal outputs the test result signal transmitted by the signal output line.
[0077] Furthermore, to reduce the number of test result output terminals required, a parallel signal processor can also be installed in the wafer with the second bonding node. The input terminals of the parallel signal processor are connected to the second bonding node, for example, via the aforementioned signal output lines. The output terminals of the parallel signal processor are connected to the corresponding test result output terminals. The parallel signal processor processes the M test result signals output from the second bonding node into N signals, which are then output to the corresponding test result output terminals, where N is less than M.
[0078] For example, an encoded output method can be used. Specifically, the parallel signal processor can be an encoder, and the M test result signals are encoded into N signals by the encoder and output to the corresponding test result output terminals. This can reduce the number of required test result output pins while saving test result signal reading time.
[0079] For example, a serial output method can be used. Specifically, the parallel signal processor can be a shift register, with M test result signals input in parallel to the shift register, and one serial signal output to the corresponding test result output terminal. This allows multiple clock cycles to serially acquire the test result signals from multiple signal output lines from one test result output terminal, which helps to further reduce the number of pins required for the test result output terminal.
[0080] Secondly, this specification also provides a bonding test method for a three-dimensional stacked chip 10, such as... Figure 4 As shown, the method includes:
[0081] Step S401: Receive the test excitation signal;
[0082] Step S402: Output test result signal based on test excitation signal. The test result signal characterizes the abnormality of the hybrid bonding connection in the bonding test circuit. The hybrid bonding connection is used to connect two wafer layers.
[0083] For example, when performing hybrid bonding yield testing, the excitation input pin (ca1) and test result output pin (ca2) of the 3D stacked chip 10 can be connected to a testing machine. The specific number of pins represented by the test result output pin (ca2) can be determined based on the actual chip. Then, a test excitation signal is fed into the excitation input pin through the testing machine. Next, the test result signal is read from the test result output pin (ca2). Based on the test result signal, it can be further determined whether there are any abnormalities in the hybrid bonding connections in the corresponding bonding test circuit, and it can accurately locate which one or more hybrid bonding connections are abnormal.
[0084] Furthermore, considering that signal transmission requires a certain amount of time, after inputting the test excitation signal, you can wait for a preset duration before reading the test result signal from the test result output pin:ca2. The preset duration is in the microsecond range and can be determined based on multiple experiments. For example, it can be set to 1 microsecond.
[0085] In specific anomaly analysis, preset conditions can be set to determine whether there are any anomalies in the hybrid bonding connections in the bonding test circuit. If the test result signal meets the preset conditions, the corresponding hybrid bonding connection is determined to be in a normal connection state; if the test result signal does not meet the preset conditions, the corresponding hybrid bonding connection is determined to be in an abnormal connection state.
[0086] For example, preset conditions can correspond to test stimulus signal settings. There are two types of test stimulus signals: a high-level signal and a low-level signal. If the test result signal and the test stimulus signal have the same level (e.g., both are low or both are high), the test result signal is deemed to meet the preset conditions, thus indicating that the mixed bonding connection in the bonding test circuit is in a normal connection state. If the test result signal and the test stimulus signal have different levels (e.g., one is low and the other is high), the test result signal is deemed not to meet the preset conditions, thus indicating that the mixed bonding connection in the bonding test circuit is in an abnormal connection state. For example, if the input test stimulus signal is low and the output test result signal is high, the mixed bonding connection in the corresponding bonding test circuit may be shorted to the power supply terminal; conversely, it may be shorted to ground.
[0087] Understandably, if the signal read from the test result output pin:ca2 is the signal output by each second bonding node, then by detecting the read signal, it can be determined whether there is an anomaly in the mixed bonding connections within the bonding test circuit connected to that second bonding node. If the signal read from the test result output pin:ca2 is a signal processed by the aforementioned parallel signal processor, and the parallel signal processor is connected to multiple second bonding nodes, then the read signal as a whole reflects the anomaly in the bonding test circuits connected to these second bonding nodes. Therefore, by detecting this signal, it can be determined which bonding test circuit contains an anomaly in its mixed bonding connections. For example, if the parallel signal processor is an encoder, it can output 2 from k test result output pins. k If the parallel signal processor is a shift register, the test result signals of the second bonding nodes can be serially output from a single test result output terminal.
[0088] In an alternative embodiment, the 3D stacked chip 10 is further provided with a mode selection pin: ca0, used to control whether the 3D stacked chip 10 operates in functional mode or test mode. In this case, before performing step S501, the method further includes switching to test mode in response to a received external control signal. For example, a control signal can be input to the mode selection pin: ca0 of the 3D stacked chip 10 via a test instrument to control the 3D stacked chip 10 to switch to test mode, after which a test stimulus signal is received to perform anomaly testing of the mixed bonding connections.
[0089] Thirdly, this specification also provides a bonding test method, applied to a testing machine, for performing hybrid bonding tests on the aforementioned three-dimensional stacked chip 10. For example... Figure 5 As shown, the method includes:
[0090] Step S501: Input a test excitation signal into the three-dimensional stacked chip;
[0091] Step S502: Receive the test result signal output by the three-dimensional stacked chip, and based on the test result signal, obtain the abnormal situation of the hybrid bonding connection in the bonding test line. The hybrid bonding connection is used to connect two wafers in the three-dimensional stacked chip.
[0092] It should be noted that the specific implementation process of the above steps S501 and S502 can be referred to the corresponding description in the method embodiment provided in the second aspect above, and will not be repeated here.
[0093] In an optional implementation, before inputting the test stimulus signal to the 3D stacked chip 10, the method further includes: inputting a control signal to the 3D stacked chip 10, the control signal being used to control the 3D stacked chip 10 to switch to test mode. Specific implementation details can be found in the corresponding descriptions in the method embodiments provided in the second aspect above, and will not be repeated here.
[0094] In an optional implementation, the process of determining the abnormality of the mixed bonded interconnects in the bonded test circuit based on the test result signal may include: determining that the mixed bonded interconnects in the bonded test circuit are in a normal connection state in response to the test result signal meeting a preset condition; and determining that the mixed bonded interconnects in the bonded test circuit are in an abnormal connection state in response to the test result signal not meeting the preset condition. Specific implementation processes can be referred to the corresponding descriptions in the method embodiments provided in the second aspect above, and will not be repeated here.
[0095] To facilitate understanding, an exemplary test procedure for hybrid bonding testing using a test equipment is described below.
[0096] First, power on the test machine; then, pull up the potential of the mode selection pin:ca0 of the 3D stacked chip 10; control the 3D stacked chip 10 to switch from the function mode to the test mode; after waiting for 1 microsecond, drive the excitation input pin:ca1 to a low level; after waiting for another 1 microsecond, check whether all test result output pin:ca2 are low level, that is, whether they are all data state 0. If there is a high level, it is determined that there is an abnormality in the hybrid bonding connection in the corresponding bonding test circuit, the Hybridbonding test fails, and further locate the abnormal location and possible causes of the abnormality. If all levels are low, wait 1 microsecond and then drive the excitation input pin: ca1 to a high level. After another 1 microsecond, check if all test result output pins: ca2 are high, i.e., if all are data state 1. If a low level is found, it is determined that there is an abnormality in the hybrid bonding connection in the corresponding bonding test circuit, and the hybrid bonding test fails. Further locate the abnormality and the possible cause of the abnormality. If all levels are high, it is determined that the hybrid bonding connection in the corresponding bonding test circuit is normal, and the hybrid bonding test is successful. You can proceed to the next test stage.
[0097] Fourthly, based on the same inventive concept, the embodiments of this specification also provide a testing machine, such as... Figure 6 As shown, the testing equipment 60 includes a processor 620, a memory 610, and a computer program 601 stored in the memory 610 and executable on the processor 620. When the computer program is executed by the processor 620, it implements the steps of the bonding test method provided in the third aspect described above. For specific implementation details, please refer to the corresponding content of the above method embodiments.
[0098] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0099] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "a plurality of" means two or more, including two or more cases.
[0100] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.
[0101] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.
Claims
1. A three-dimensional stacked chip, characterized in that, include: At least two wafers are connected by hybrid bonding, and in the two hybrid-bonded wafers: A first bonding node and a second bonding node are configured; The first bonding node and the second bonding node are connected by a bonding test line, which includes at least one hybrid bonding connection line for connecting two wafer layers. The first bonding node receives a test excitation signal, and the second bonding node outputs a test result signal, which characterizes the abnormal situation of the mixed bonding connection in the bonding test circuit. The first bonding node and the second bonding node are disposed on different wafers; and each of the first bonding node and the second bonding node is connected to a corresponding hybrid bonding line; The wafer with the second bonding node is also provided with a parallel signal processor. The input terminal of the parallel signal processor is connected to the second bonding node, and the output terminal of the parallel signal processor is connected to the corresponding test result output terminal. The parallel signal processor is used to process the M test result signals output by the second bonding node into N signals and output them to the corresponding test result output terminal, where N is less than M. The parallel signal processor is an encoder or a shift register; When both the test excitation signal and the test result signal are at a low level or both are at a high level, the mixed bonding connection in the bonding test circuit is in a normal connection state. In response to one of the test excitation signal and the test result signal being at a low level and the other being at a high level, the mixed bonding connection in the bonding test circuit is in an abnormal connection state.
2. The three-dimensional stacked chip according to claim 1, characterized in that, The first bonding node is connected to a test control circuit, which is in test mode based on a received control signal and receives the test excitation signal in the test mode; the control signal is an external control signal.
3. The three-dimensional stacked chip according to claim 2, characterized in that, The first bonding node and the second bonding node are also connected to their respective corresponding functional circuits. The connection between the second bonding node and the corresponding functional circuit is connected to a signal output line, which is used to output the test result signal. The test control circuit is also in a functional mode based on the received control signal, in which the test control circuit is turned off.
4. The three-dimensional stacked chip according to claim 2, characterized in that, The test control circuit includes a first selector, which includes a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein: The first input terminal is connected to the first bonding node in the wafer via a corresponding functional circuit. The second input terminal is connected to the excitation input terminal that inputs the test excitation signal. The control terminal is connected to the mode selection terminal that inputs the control signal. The output terminal is connected to the first bonding node.
5. The three-dimensional stacked chip according to claim 1, characterized in that, The number of hybrid bonding lines is odd, and the odd number of hybrid bonding lines are connected in series to form the bonding test circuit; The first bonding node and the second bonding node are located on different wafers.
6. The three-dimensional stacked chip according to claim 1, characterized in that, The number of hybrid bonding lines is even, and the even number of hybrid bonding lines are connected in series to form the bonding test circuit. The first bonding node and the second bonding node are located on the same wafer.
7. The three-dimensional stacked chip according to claim 5 or 6, characterized in that, The bonding test circuit includes multiple hybrid bonding lines; the three-dimensional stacked chip also includes transition bonding nodes, which are respectively disposed on the two wafer layers; The multiple hybrid bonding lines are cascaded sequentially through the transition bonding nodes to form the bonding test circuit; In the bonding test circuit, a second selector is provided between two adjacent transition bonding nodes on the same wafer. The first input terminal of the second selector is connected to the preceding transition bonding node, the second input terminal is connected to the functional circuit corresponding to the subsequent transition bonding node, the control terminal is connected to the mode selection terminal for inputting control signals, and the output terminal is connected to the subsequent transition bonding node.
8. A bonding test method, characterized in that, The method is applied to a three-dimensional stacked chip according to any one of claims 1-7, and the method includes: Receive test excitation signal; Based on the test excitation signal, a test result signal is output. The test result signal characterizes the abnormality of the mixed bonding connection in the bonding test circuit. The mixed bonding connection is used to connect two wafer layers.
9. The method according to claim 8, characterized in that, Before receiving the test excitation signal, the method further includes: In response to the received external control signal, switch to test mode.
10. A bonding test method, characterized in that, The method is applied to a three-dimensional stacked chip according to any one of claims 1-7, and the method includes: Input test excitation signals into the three-dimensional stacked chip; The test result signal output by the three-dimensional stacked chip is received, and based on the test result signal, the abnormal situation of the mixed bonding connection in the bonding test line is obtained. The mixed bonding connection is used to connect two wafers in the three-dimensional stacked chip.
11. The method according to claim 10, characterized in that, Before inputting the test excitation signal to the three-dimensional stacked chip, the method further includes: A control signal is input to the three-dimensional stacked chip, and the control signal is used to control the three-dimensional stacked chip to switch to test mode.
12. The method according to claim 10, characterized in that, The abnormal situation of mixed bonding connections in the bonding test circuit obtained based on the test result signal includes: In response to the test result signal meeting the preset conditions, it is determined that the hybrid bonding connection in the bonding test circuit is in a normal connection state. If the test result signal does not meet the preset condition, it is determined that the hybrid bonding connection in the bonding test circuit is in an abnormal connection state.
13. A testing machine, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the bonding test method as described in any one of claims 10-12.