Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of achieving improvement in electrical characteristics. A semiconductor device of an embodiment has a substrate, a first external connection pad, a first coil, a first stack, and a second stack. The first external connection pad is provided separately from the substrate in a thickness direction of the substrate, i.e., a first direction. The first coil is electrically connected to the first external connection pad. The first stack is provided between the first external connection pad and the substrate and between the first coil and the substrate. The first stack includes a first insulator, a first wiring, and a first pad. The second stack is provided between the first stack and the substrate. The second stack includes a second insulator, a second wiring, a second pad, and a second coil. The first pad is joined to the second pad. In the first direction, at least part of the first coil overlaps with the second coil.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-204117 (filed on December 16, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] A semiconductor device with an inductive element is known. Summary of the Invention

[0005] The present invention provides a semiconductor device capable of improving electrical characteristics.

[0006] A semiconductor device according to an embodiment includes a substrate, a first external connection pad, a first coil, a first laminate, and a second laminate. The first external connection pad is disposed separately from the substrate in the thickness direction of the substrate, i.e., a first direction. The first coil is disposed separately from the substrate in the first direction. The first coil is electrically connected to the first external connection pad. The first laminate is disposed between the first external connection pad and the substrate, and between the first coil and the substrate. The first laminate includes a first insulator, a first wiring disposed in the first insulator, and a first pad electrically connected to the first wiring. The second laminate is disposed between the first laminate and the substrate. The second laminate includes a second insulator, a second wiring disposed in the second insulator, a second pad electrically connected to the second wiring, and a second coil. The first insulator is in contact with the second insulator. The first pad is bonded to the second pad. In the first direction, at least a portion of the first coil overlaps with the second coil. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of a memory system having the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram showing an example of the circuit configuration of the line decoder included in the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a block diagram illustrating an example of the configuration of a sense amplifier module included in the semiconductor device according to the first embodiment.

[0010] Figure 4This is a circuit diagram showing an example of the circuit configuration of the sense amplifier module included in the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a circuit diagram illustrating an example of the circuit configuration of a transceiver module and a memory controller included in the semiconductor device according to the first embodiment.

[0012] Figure 6 This is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a cross-sectional view showing the vicinity of the storage pillars of the storage cell array in the first embodiment.

[0014] Figure 8 This is a diagram showing the positional relationship between the first coil and the second coil according to the first embodiment.

[0015] Figure 9 This is a block diagram illustrating a configuration example of a memory system equipped with the semiconductor device according to the second embodiment.

[0016] Figure 10 This is a circuit diagram illustrating an example of the circuit configuration of a transceiver module and a memory controller included in the semiconductor device according to the second embodiment.

[0017] Figure 11 This is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment.

[0018] Figure 12 This is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment.

[0019] Figure 13 This is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment.

[0020] Figure 14 This is a diagram showing the positional relationship of the first coil, the second coil, and the third coil according to the fourth embodiment.

[0021] Figure 15 This is a top view showing the positional relationship of the first coil in the first embodiment of the implementation.

[0022] Figure 16 This is a top view showing the positional relationship of the first coil in the second embodiment of the implementation.

[0023] Figure 17 This is a top view showing the positional relationship of the first coil in the third embodiment of the implementation. Detailed Implementation

[0024] The semiconductor device according to the embodiments will now be described with reference to the accompanying drawings. In the following description, components having the same or similar functions will be labeled with the same reference numerals. Furthermore, repeated descriptions of these components will sometimes be omitted. "Connection" is not limited to physical connections, but also includes electrical connections. That is, "connection" is not limited to direct contact, but also includes cases where other components are present. "Orthogonal" and "same" also include cases of "substantially orthogonal" and "substantially same," respectively.

[0025] (First Implementation)

[0026] <1. Overall Structure of a Semiconductor Device>

[0027] Figure 1 This is a block diagram illustrating an example configuration of a memory system having the semiconductor device 1 according to the first embodiment. The semiconductor device 1, for example, uses a NAND flash memory. The semiconductor device 1 is controlled by a memory controller 2. Communication between the semiconductor device 1 and the memory controller 2, for example, supports the NAND interface standard.

[0028] like Figure 1 As shown, for example, semiconductor device 1 includes a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder 15, a sense amplifier module 16, and a transceiver module 17.

[0029] The memory cell array 10 contains multiple blocks BLK1 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells capable of non-volatile data storage, used for example as a data erasure unit. Multiple bit lines and multiple word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0030] Command register 11 holds commands CMD received by semiconductor device 1 from memory controller 2 via transceiver module 17. Commands CMD include, for example, commands that cause sequencer 13 to perform read operations, write operations, erase operations, etc.

[0031] Address register 12 holds address information ADD received by semiconductor device 1 from memory controller 2 via transceiver module 17. Address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used to select block BLK, word line, and bit line, respectively.

[0032] The sequencer 13 controls the operation of the entire semiconductor device 1. For example, the sequencer 13 controls the driver module 14, the line decoder 15, and the sense amplifier module 16, etc., based on the command CMD held in the command register 11, to perform read operations, write operations, erase operations, etc.

[0033] The driver module 14 generates voltages used in read, write, and erase operations. Furthermore, the driver module 14 applies the generated voltages to the signal lines corresponding to the selected word lines, for example, based on the page address PAd held in the address register 12.

[0034] The row decoder 15 selects a block within the corresponding memory cell array 10 based on the block address BAd held in the address register 12. The row decoder 15, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block.

[0035] During the write operation, the sense amplifier module 16 applies a desired voltage to each bit line based on the write data DAT received from the memory controller 2 via the transceiver module 17. Conversely, during the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage or current flowing through the bit line, and transmits the determination result as read data DAT to the memory controller 2 via the transceiver module 17.

[0036] The transceiver module 17 sends signals from the memory controller 2 to the command register 11, address register 12, etc. in the semiconductor device 1, and sends signals output from the sensing amplifier module 16 to the memory controller 2.

[0037] The semiconductor device 1 and memory controller 2 described above can also be combined to form a semiconductor device. Examples of such semiconductor devices include SSDs (solid-state drives).

[0038] (Line decoder)

[0039] Next, use Figure 2 The configuration of the line decoder 15 of the semiconductor device 1 according to the first embodiment will be explained.

[0040] like Figure 2 As shown, the line decoder 15 includes multiple block decoders 181 (181a, 181b, ...) and multiple transmit switch groups 182 (182a, 182b, ...). The transmit switch group 182 includes transistors TT0 to TT12, UDT0 to UDT3, and UST.

[0041] One block decoder 181 and one transmit switch group 182 are assigned to one block BLK. Figure 2 In the example, block decoder 181a and transmit switch group 182a are assigned to block BLK0, and block decoder 181b and transmit switch group 182b are assigned to block BLK1. In the following description, the block BLK that will be the object of writing, reading, and erasing is referred to as the selected block BLK.

[0042] During data writing, reading, and erasing, the block decoder 181 decodes the block address signal received from the address register 12. If the decoding result indicates that the block BLK corresponding to the block decoder 181 is the selected block BLK, the block decoder 181 outputs a "H" level signal BLKSEL and a "L" level signal RDECADn. Conversely, if the corresponding block BLK is not the selected block BLK, the block decoder 181 outputs a "L" level signal BLKSEL and a "H" level signal RDECADn. The signal BLKSEL is a voltage that turns on transistors TT0-TT12 at "H" level and turns them off at "L" level. The signal RDECADn is a voltage that turns on transistors UDT0-UDT3 and UST at "H" level and turns them off at "L" level.

[0043] Transistors TT0 to TT7 are used to transmit voltage to word lines WL0 to WL7 of the selection block BLK, respectively. The first terminal of each transistor TT0 to TT7 is connected to the word lines WL0 to WL7 of the corresponding block BLK, the second terminal is connected to the signal lines CG0 to CG7, and the gate is connected to the signal line BLKSEL.

[0044] Transistors TT8-TT11 and UDT0-UDT3 are used to transmit voltage to the select gate lines SGD0-SGD3 of the select block BLK, respectively. The first terminal of each transistor TT8-TT11 is connected to the select gate line SGD0-SGD3 of the corresponding block BLK, and the second terminal is connected to the signal line SGDL0-SGDL3. Their gates are all connected to the signal line BLKSEL. Similarly, the first terminal of each transistor UDT0-UDT3 is connected to the select gate line SGD0-SGD3 of the corresponding block BLK, and the second terminal can be grounded to the ground voltage VSS. Their gates are all connected to the signal line RDECADn.

[0045] Transistors TT12 and UST are used to deliver voltage to the select gate line SGS of the select block BLK. The first terminal of transistor TT12 is connected to the select gate line SGS of the corresponding block BLK, the second terminal is connected to the signal line SGSL, and its gate is connected to the signal line BLKSEL. Similarly, the first terminal of transistor UST is connected to the select gate line SGS of the corresponding block BLK, the second terminal can be grounded to the ground voltage VSS, and its gate is connected to the signal line RDECADn.

[0046] Therefore, for example, in the transmission switch group 182 corresponding to the selection block BLK, transistors TT0 to TT12 are in the on state, while transistors UGT0 to UGT3 and UST are in the off state. Consequently, word lines WL0 to WL7 are connected to signal lines CG0 to CG7, selection gate lines SGD0 to SGD3 are connected to signal lines SGDL0 to SGDL3, and selection gate line SGS is connected to signal line SGSL.

[0047] On the other hand, in the transmission switch group 182 corresponding to the unselected block BLK, transistors TT0 to TT12 are in the off state, while transistors UGT0 to UGT3 and UST are in the on state. As a result, the word line WL is separated from the signal line CG, the select gate lines SGD0 to SGD3 are separated from the signal lines SGDL0 to SGDL3 respectively, and the select gate line SGS is separated from the signal line SGSL.

[0048] Driver module 14 supplies voltage to signal lines CG, SGDL, and SGSL according to the address received from address register 12. Signal lines CG, SGDL, and SGSL transmit various voltages supplied from driver module 14 to each of the transfer switch groups 182a, 182b, ... That is, the voltage supplied from driver module 14 is transmitted to word line WL, select gate line SGD, and SGS in select block BLK via transistors TT0 to TT12 in transfer switch group 182 corresponding to select block BLK.

[0049] The above describes the line decoder 15 in the semiconductor device 1 according to the first embodiment. However, the line decoder 15 is not limited to the circuit configuration described above, as long as it can transmit the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block.

[0050] (Sensing Amplifier Module)

[0051] Figure 3 This is an example of the circuit configuration of the sense amplifier module 16 in the semiconductor device 1 according to the first embodiment. For example... Figure 3As shown, the sense amplifier module 16 includes, for example, sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes, for example, a sense amplifier section SA, a bus LBUS, and latch circuits SDL, ADL, BDL, and XDL.

[0052] For example, during a read operation, the sensing amplifier section SA determines whether the read data is "0" or "1" based on the voltage or current flowing through the associated bit line BL. In other words, the sensing amplifier section SA detects the data read on the associated bit line BL and determines the data to be stored in the selected memory cell. The latch circuits SDL, ADL, BDL, and XDL temporarily store the read data, write data, etc., respectively.

[0053] The sensing amplifier unit SA and latch circuits SDL, ADL, BDL, and XDL are connected to the LBUS bus, enabling them to send and receive data. The latch circuit XDL is connected to an input / output circuit (not shown) and is used for data input / output between the sensing amplifier unit SAU and the input / output circuit. Additionally, the latch circuit XDL can also be used as a buffer memory for the semiconductor device 1. For example, even when the latch circuits SDL, ADL, and BDL are in use, the semiconductor device 1 can be in a ready state when the latch circuit XDL is idle.

[0054] Figure 4 An example of the circuit configuration of the sense amplifier unit SAU in the semiconductor device 1 according to the first embodiment is shown. For example... Figure 4 As shown, for example, the sensing amplifier section SA includes transistors 20-27 and capacitor 28.

[0055] Transistor 20 is a P-type MOS transistor. Transistors 21-23 and 25-27 are N-type MOS transistors. Transistor 24 is an N-type MOS transistor with a higher voltage withstand capability than transistors 21-23 and 25-27. Hereinafter, transistors 21-23 and 25-27 will be referred to as low-voltage transistors, and transistor 24 will be referred to as a high-voltage transistor.

[0056] The source of transistor 20 can be connected to a power supply line. The drain of transistor 20 is connected to node ND1. The gate of transistor 20 is connected, for example, to node INV within the latch circuit SDL. The drain of transistor 21 is connected to node ND1. The source of transistor 21 is connected to node ND2. The gate of transistor 21 is fed with the control signal BLX. The drain of transistor 22 is connected to node ND1. The source of transistor 22 is connected to node SEN. The gate of transistor 22 is fed with the control signal HLL.

[0057] The drain of transistor 23 is connected to node SEN. The source of transistor 23 is connected to node ND2. The gate of transistor 23 is connected to the input control signal XXL. The drain of transistor 24 is connected to node ND2. The gate of transistor 24 is connected to the input control signal BLC. The source of transistor 24 is connected to bit line BL. The drain of transistor 25 is connected to node ND2. The source of transistor 25 is connected to node SRC. The gate of transistor 25 is connected, for example, to node INV within the latch circuit SDL.

[0058] The source of transistor 26 can be grounded. The gate of transistor 26 is connected to node SEN. The drain of transistor 27 is connected to the bus LBUS. The source of transistor 27 is connected to the drain of transistor 26. The gate of transistor 27 is fed with the control signal STB. One electrode of capacitor 28 is connected to node SEN. The other electrode of capacitor 28 is fed with the clock signal CLK.

[0059] In the circuit configuration of the sense amplifier unit SAU described above, a power supply voltage, such as VDD, can be applied to the power supply line connected to the source of transistor 20. A ground voltage, such as VSS, can be applied to node SRC. Each of the control signals BLX, HLL, XXL, BLC, STB, BLS, and clock CLK is generated, for example, by sequencer 13. The sense amplifier section SA determines the data read on bit line BL based, for example, the timing when the control signal STB becomes ON.

[0060] Furthermore, the sense amplifier module 16 included in the semiconductor device 1 according to the first embodiment is not limited to the circuit configuration described above. For example, the number of latch circuits included in each sense amplifier unit SAU can be appropriately changed according to the number of pages stored in one unit CU. The sense amplifier section SA can be configured with other circuits as long as it can determine the data read on the bit line BL.

[0061] (Send and receive module)

[0062] Figure 5 This is an example of a circuit configuration consisting of a transceiver module 17 and a portion of a memory controller in the semiconductor device 1 according to the first embodiment. The transceiver module 17, for example, has a transmitting circuit 61 and a receiving circuit 62.

[0063] The transmitting circuit 61, for example, has a first coil 30. The first coil 30 is connected to an inverter 31 disposed outside the semiconductor device 1. Additionally, a power supply voltage VDD can be supplied to the first coil 30. The inverter 31 is connected to an AND gate 32 disposed outside the semiconductor device 1. In this embodiment, the inverter 31 and the AND gate 32 are located within the memory controller 2. The AND gate 32 is, for example, fed by input signals Txdata and Tx-enable. The inverter 31, for example, uses a CMOS inverter.

[0064] The receiving circuit 62 includes, for example, a second coil 33, resistors 35A and 35B, and transistors 36A to 36I. The receiving circuit 62 uses, for example, a hysteresis comparator circuit. Transistors 36A to 36D are P-type MOS transistors. Transistors 36E to 36I are N-type MOS transistors.

[0065] Resistor 35A is connected to nodes NDA and NDB. Resistor 35B is connected to nodes NDB and NDC. Voltage VB can be supplied to node NDB. The source of transistor 36A is connected to the power supply line. The drain of transistor 36A is connected to the drain of transistor 36E. The gate of transistor 36A is connected to node NDD. The source of transistor 36B is connected to the power supply line. The drain of transistor 36B is connected to node NDE. The gate of transistor 36B is connected to node NDF.

[0066] The source of transistor 36C is connected to the power supply line. The drain of transistor 36C is connected to node NDF. The gate of transistor 36C is connected to node NDE. The source of transistor 36D is connected to the power supply line. The drain of transistor 36D is connected to the drain of transistor 36H. The gate of transistor 36D is connected to node NDG.

[0067] The drain of transistor 36E is connected to the drain of transistor 36A. The source of transistor 36E is connected to node NDH. The gate of transistor 36E is connected to node NDD. The drain of transistor 36F is connected to node NDE. A ground voltage VSS can be applied to the source of transistor 36F. The gate of transistor 36F is activated by the input signal Reset.

[0068] The drain of transistor 36G is connected to node NDF. A ground voltage VSS can be applied to the source of transistor 36G. A ground voltage VSS can be applied to the gate of transistor 36G. The drain of transistor 36H is connected to the drain of transistor 36D. The source of transistor 36H is connected to node NDH. The gate of transistor 36H is connected to node NDG.

[0069] The drain of transistor 36I is connected to node NDH. A ground voltage VSS can be applied to the source of transistor 36I. The gate of transistor 36I is enabled by the input signal Rx.

[0070] The following describes the process of transmitting a signal from the transmitting circuit 61 to the receiving circuit 62. The transmitting circuit 61 is controlled by the signal Tx-enable. For example, when the signal Tx-enable is High, the transmitting circuit 61 starts and transmits a current I. T The current flows through the first coil 30 within the transmitting circuit 61. Therefore, when the input signal Txdata changes, due to the inductive coupling between the first coil 30 in the transmitting circuit 61 and the second coil 33 in the receiving circuit 62, a pulse-type receiving voltage V is generated across the second coil. R The receiving circuit 62, for example, has a hysteresis width V that distinguishes between data and noise. H The receiving circuit 62 is controlled by the signal Rx-enable. For example, when the signal Rx-enable is "H", the receiving circuit 62 is activated. When the received voltage V... R The amplitude is greater than the hysteresis width V H When the amplitude is reached, the receiving circuit 62 reverses the received signal Rxdata, restoring the input signal Txdata. To ensure consistent hysteresis polarity, a Reset signal is input each time the signal is activated by the Rx-enable signal. Here, an example of sending an input signal from the transmitting circuit 61 to the receiving circuit 62 has been described, but it is also possible to send an output signal from the receiving circuit 62 to the transmitting circuit 61. Furthermore, signals sent from the transmitting circuit 61 to the receiving circuit 62 can include data signals, control signals, data strobe signals, etc.

[0071] The transceiver module 17 in the semiconductor device 1 according to the first embodiment has been described above. However, the transceiver module 17 is not limited to the circuit configuration described above, as long as it can transmit signals from the first coil 30 to the second coil.

[0072] (Structure of a semiconductor device)

[0073] Hereinafter, an example of the structure of the semiconductor device 1 according to the first embodiment will be described. Figure 6 This is a cross-sectional view showing the configuration of semiconductor device 1. In semiconductor device 1, for example, a three-dimensional memory is used where a circuit chip 200 and an array chip 300 are bonded at a bonding surface S. The circuit chip 200 includes control circuitry (logic circuitry) that controls the operation of the array chip 300. The construction of semiconductor device 1 will now be described in detail.

[0074] First, the X direction, Y direction, +Z direction, and -Z direction are defined. The X and Y directions are along the first substrate 100 (described later) (refer to...). Figure 6The direction of surface 100a of the first substrate 100. The Y direction is the direction that intersects (e.g., is orthogonal) the X direction. The +Z and -Z directions are the directions that intersect (e.g., are orthogonal) the X and Y directions, respectively, and are the thickness directions of the first substrate 100. The +Z direction is from the first substrate 100 toward the laminate 110 (refer to...). Figure 6 The direction of gravity is -Z. The -Z direction is the opposite of the +Z direction. Without distinguishing between +Z and -Z, it is simply referred to as the "Z direction." In the following explanations, the "+Z direction" may sometimes be called "up" and the "-Z direction" may be called "down." However, these expressions are for convenience and do not limit the direction of gravity. The Z direction is an example of the "first direction."

[0075] Semiconductor device 1, for example, includes a first substrate 100, a first external connection pad 71, a second external connection pad 72, a first coil 30, wiring 150, a laminate 110, a laminate 120, and an insulating layer 140. The first substrate 100, the laminate 120, the laminate 110, and the insulating layer 140 are stacked sequentially from bottom to top. In a first embodiment, the first external connection pad 71, the second external connection pad 72, the first coil 30, and the wiring 150 are disposed on a first surface 1101, which is the upper surface of the laminate 110.

[0076] The first external connection pad 71 is disposed separately from the first substrate 100 in the thickness direction (Z direction). The first external connection pad 71 can be an input pad, an output pad, or a pad that serves as both input and output. The second external connection pad 72 is disposed separately from the first substrate 100 in the Z direction. The second external connection pad 72 is a pad different from the first external connection pad 71. The first external connection pad 71 and the second external connection pad 72 are not connected. Power can be supplied to the second external connection pad 72 from an external power source, or a reference voltage (e.g., ground voltage) can be applied to the second external connection pad 72.

[0077] The first coil 30 is disposed separately from the first substrate 100 in the Z direction. The first coil 30 is connected to the first external connection pad 71. Wiring 150 is electrically connected to the source line 60. The first external connection pad 71, the second external connection pad 72, the first coil 30, and the wiring 150 are formed using a conductive material such as copper (Cu), tungsten (W), or aluminum (Al). The first coil 30 will be described later. The first external connection pad 71 and the second external connection pad 72 are provided with external connection terminals (e.g., solder balls), which are electrically connected to the external parts of the semiconductor device 1. Signals that can be input to the first coil 30 via the first external connection pad 71 are at least one of a data signal, a control signal, and a data strobe signal.

[0078] Data signals include, for example, signals indicating write object data stored by the memory cell array, read object data read from the memory cell array, signals of various commands, and signals indicating the address of the write destination or read destination of the data.

[0079] Control signals include, for example, chip enable signals, write enable signals, read enable signals, write protect signals, and ready / busy signals. A chip enable signal is a signal that allows the selection of a semiconductor device 1 from among multiple semiconductor devices 1 for access. A write enable signal is a signal that allows data (e.g., command CMD or address ADD) to be transferred to semiconductor device 1. A read enable signal is a signal that allows data to be read from semiconductor device 1. A write protect signal is a signal that is activated when writing and erasing are disabled. A ready / busy signal is a signal that distinguishes whether semiconductor device 1 is in a ready state or a busy state.

[0080] A data strobe signal is a data strobe signal used for latching or outputting data signals.

[0081] The first substrate 100 is a substrate included in the circuit chip 200. The first substrate 100 is, for example, a semiconductor substrate made of silicon or the like. The first substrate 100 has a surface 100a for stacking the laminate 120. The source region and drain region of the transistor included in the laminate 120 are provided on the first substrate 100.

[0082] A stack 110 is disposed on top of a stack 120. The stack 110 is disposed between the first external connection pad 71, the second external connection pad 72, the first coil 30, and the first substrate 100. In this embodiment, the stack 110 constitutes an array chip 300. The stack 110 includes a memory cell array 10, a plurality of contact plugs 42, a plurality of wirings 43, a plurality of pads 44, an insulator 45, a first power pad 48, and a first power wiring 49. The stack 110 is an example of a "first stack".

[0083] The memory cell array 10 is disposed below the source line 60. The memory cell array 10 has multiple conductive layers 41 and multiple memory pillars P. The multiple conductive layers 41 and multiple memory pillars P are respectively connected to contact plugs 42. In addition, the multiple memory pillars P are connected to the source line 60.

[0084] Multiple conductive layers 41 are formed, for example, using tungsten (W) or polycrystalline silicon (Poly-Si) doped with impurities. Intercalating between the multiple conductive layers 41 is an interlayer insulating film 45b (see reference 45b) included in an insulator 45. Figure 7The conductive layers 41 are stacked in the Z direction. The conductive layers 41 on the stack body 120 side (-Z direction side), which in this embodiment are four conductive layers 41 on the stack body 120 side, function as drain-side selected gate lines (SGD). The conductive layer 41 on the source line 60 side (+Z direction side), which in this embodiment is one conductive layer 41 on the source line 60 side, function as source-side selected gate lines (SGS). The remaining conductive layers 41 located between the drain-side selected gate line (SGD) and the source-side selected gate line (SGS) function as multiple word lines (WL).

[0085] Multiple memory pillars P extend in the Z direction, connecting the drain-side select gate line SGD, multiple word lines WL, and the source-side select gate line SGS. Memory cells MC are formed at the intersections of the multiple word lines WL and the multiple memory pillars P. Thus, the multiple memory cells MC are arranged in a three-dimensional configuration with spacing in the X, Y, and Z directions. The memory cells MC will be described in detail later.

[0086] Contact plugs 42, wiring 43, and pads 44 electrically connect the memory cell array 10 to the laminate 120. Contact plugs 42, wiring 43, and pads 44 are formed using conductive materials such as copper, tungsten, or aluminum. Contact plugs 42 extend in the Z direction and are wiring that electrically connects different layers within the laminate 110. Wiring 43 is wiring that extends in the X or Y direction.

[0087] Pad 44 is a connection electrode provided in the laminate 110. When the laminate 110 and laminate 120 are stacked, the pad 44 of the laminate 110 is disposed on top of the pad 54 of the laminate 120 and is bonded to the pad 54 of the laminate 120. Pad 44 is an example of a "first pad". Among the plurality of traces 43, the trace 47 connected to the pad 44 is an example of a "first trace".

[0088] An insulator 45 is disposed between a plurality of contact plugs 42, a plurality of wirings 43, and a plurality of pads 44, electrically insulating these components from each other. That is, the plurality of contact plugs 42, the plurality of wirings 43, and the plurality of pads 44 are disposed within the insulator 45. The insulator 45 is formed, for example, using silicon oxide or silicon nitride. The insulator 45 is an example of a "first insulator".

[0089] The source line 60 is, for example, a two-layer film comprising a lower portion using tungsten (W) and an upper portion using silicon (Si). The source line 60 is disposed in the region where the memory cell array 10 is located, but not in the region where the first coil 30 and the first power supply wiring are located. Potential can be supplied to various portions of the source line 60 from the laminate 120. The source line 60 is connected to the wiring 150.

[0090] A first power supply trace 49 extending in the Z direction within the insulator 45 connects the second external connection pad 72 to the first power supply pad 48. The first power supply pad 48 is bonded to the second power supply pad 58. Therefore, power supply voltage, reference voltage, etc., can be applied to the laminate 120 via the second external connection pad 72.

[0091] The laminate 120 is located between the first substrate 100 and the laminate 110 in the Z direction. The laminate 120 is disposed on the first substrate 100. In this embodiment, the circuit chip 200 is formed by the first substrate 100 and the laminate 120. The laminate 120 includes a second coil 33, a plurality of transistors 51, a plurality of contact plugs 52, a plurality of wirings 53, a plurality of pads 54, a second power pad 58, and an insulator 55. The second coil 33 is connected to the wirings 53. The laminate 120 is an example of a "second laminate".

[0092] Transistor 51 is disposed on the first substrate 100. Transistor 51 is connected to contact plug 52. Transistor 51 is electrically connected to memory cell array 10 and second external connection pad 72 via contact plugs 42 and 52, wiring 43 and 53, pads 44 and 54, first power pad 48 and second power pad 58. Transistor 51 controls memory cell array 10, for example. Figure 6 In the middle, transistor TT7 of the line decoder 15 is connected to one of the plurality of pads 54. Similarly, transistor 24 of the sense amplifier module 16 is connected to one of the plurality of pads 54.

[0093] Contact plugs 52, wiring 53, and pads 54 electrically connect multiple transistors 51 to the laminate 110. The second coil 33, contact plugs 52, wiring 53, and pads 54 are formed using conductive materials such as copper, tungsten, or aluminum. Contact plugs 52 extend in the Z-direction and are wiring that electrically connects different layers within the laminate 120. Wiring 53 is wiring that extends in the X or Y direction.

[0094] Pad 54 is a connection electrode provided in the laminate 120. When the laminate 110 and laminate 120 are stacked, pad 54 of laminate 120 is bonded to pad 44 of laminate 110. Pad 54 is an example of a "second pad". Wiring 57, which is connected to pad 54 among the plurality of wirings 53, is an example of a "second wiring".

[0095] An insulator 55 is disposed between a plurality of contact plugs 52, a plurality of wirings 53, and a plurality of pads 54, electrically insulating these components from each other. That is, the plurality of contact plugs 52, the plurality of wirings 53, and the plurality of pads 54 are disposed within the insulator 55. The insulator 55 is formed, for example, using silicon oxide (SiO2) or silicon nitride (SiN). When the laminates 110 and 120 are stacked, the insulator 55 of the laminate 120 is in contact with the insulator 45 of the laminate 110. The insulator 55 is an example of a "second insulator".

[0096] An insulating layer 140 is disposed above the first coil 30 and the wiring 150. The insulating layer 140 is a passivation film protecting the laminate 110. The insulating layer 140 is, for example, a silicon oxide film.

[0097] Figure 7 This is a cross-sectional view showing the vicinity of memory pillar P in memory cell array 10. (See diagram below.) Figure 7 As shown, multiple word lines WL are stacked in the Z direction, with an interlayer insulating film 45b sandwiched between them. The multiple word lines WL extend in the X direction. The memory cell array 10 has a memory hole MH for a memory pillar P. The memory pillar P extends in the Z direction inside the memory hole MH, penetrating the multiple word lines WL.

[0098] When viewed from the Z direction, the memory column P is, for example, circular or elliptical. From the inside, the memory column P has a core insulator 63, a semiconductor body 64, and a memory film 65 in sequence.

[0099] The core insulator 63 is a columnar body extending in the Z direction. The core insulator 63 comprises, for example, silicon oxide. The core insulator 63 is located inside the semiconductor body 64.

[0100] The semiconductor body 64 extends in the Z direction and functions as a channel. The semiconductor body 64 is connected to the source line 60. The semiconductor body 64 covers the outer peripheral surface of the core insulator 63. The semiconductor body 64 may contain silicon, for example. The silicon may be, for example, polycrystalline silicon obtained by crystallizing amorphous silicon.

[0101] The memory film 65 extends in the Z direction. The memory film 65 covers the outer peripheral surface of the semiconductor body 64. The memory film 65 is located between the inner surface of the memory hole MH and the outer surface of the semiconductor body 64. The memory film 65 includes, for example, a tunnel insulating film 66 and a charge storage film 67.

[0102] A tunnel insulating film 66 is located between the charge storage film 67 and the semiconductor substrate 64. The tunnel insulating film 66 may comprise, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 66 acts as a potential barrier between the semiconductor substrate 64 and the charge storage film 67.

[0103] A charge storage film 67 is disposed between each word line WL and between each interlayer insulating film 45b and tunnel insulating film 66. The charge storage film 67 may contain, for example, silicon nitride. The intersection of the charge storage film 67 and the word line WL functions as a memory cell MC. The memory cell MC retains data based on the presence or absence of charge or the amount of charge stored in the intersection of the charge storage film 67 and the word line WL (charge storage section). The charge storage section is located between the word line WL and the semiconductor body 64 and is surrounded by an insulating material.

[0104] A barrier insulating film 68 and a barrier film 69 can be provided between the word line WL and the interlayer insulating film 45b, and between the word line WL and the memory film 65. The barrier insulating film 68 is an insulating film that suppresses reverse tunneling. Reverse tunneling is the phenomenon of charge returning from the word line WL to the memory film 65. The barrier insulating film 68 can be, for example, a silicon oxide film, a metal oxide film, or a laminated film composed of multiple insulating films. An example of a metal oxide is aluminum oxide. The barrier film 69 can be, for example, a titanium nitride film or a laminated film of titanium nitride and titanium.

[0105] A cover insulating film 70 may be provided between the interlayer insulating film 45b and the charge storage film 67. The cover insulating film 70 may contain, for example, silicon oxide. The cover insulating film 70 protects the charge storage film 67 from etching during processing. The cover insulating film 70 may also be absent, or a portion may be retained between the conductive layer 41 and the charge storage film 67 to serve as a barrier insulating film.

[0106] <Composition of the first and second coils>

[0107] Figure 8 This diagram illustrates the positional relationship between the first coil 30 and the second coil 33. At least a portion of the first coil 30 overlaps with the second coil 33 in the Z direction. The first coil 30 is capable of inductive coupling with the second coil 33. The positional relationship between the first coil 30 and the second coil 33 is not particularly limited as long as they are capable of inductive coupling. The shape of the first coil 30 is, for example, a quadrilateral frame or a ring. The shape of the second coil 33 is, for example, a quadrilateral frame or a ring. Preferably, the first coil 30 and the second coil 33 have the same shape. In the first embodiment, the second coil 33 is closer to the first substrate 100 side in the Z direction than the bonding surface S of the pads 44 and 54.

[0108] The length D1 of the first coil 30 in the X direction is not particularly limited. Similarly, the length D3 of the first coil 30 in the Y direction is not particularly limited. Preferably, the length D3 of the first coil 30 in the Y direction is equal to the length D1 in the X direction. Preferably, the length D1 of the first coil 30 in the X direction is longer than the distance H1 between the first coil 30 and the second coil 33 in the Z direction. Preferably, the length D3 of the first coil 30 in the Y direction is longer than the distance H1 between the first coil 30 and the second coil 33 in the Z direction.

[0109] The length D2 of the second coil 33 in the X direction is not particularly limited. Similarly, the length D4 of the second coil 33 in the Y direction is not particularly limited. Preferably, the length D4 of the second coil 33 in the Y direction is equal to the length D2 in the X direction. Preferably, the length D2 of the second coil 33 in the X direction is longer than the distance H1 between the first coil 30 and the second coil 33 in the Z direction. Preferably, the length D4 of the second coil 33 in the Y direction is longer than the distance H1 between the first coil 30 and the second coil 33 in the Z direction.

[0110] The first embodiment has been described above. The semiconductor device 1 can be manufactured using known methods. In the semiconductor device 1 according to the first embodiment, signal transmission is achieved by using inductive coupling between the first coil 30 and the second coil 33, thus achieving power saving. In addition, since the wiring used in the transmission of data signals, etc., can be omitted, the design constraints of the configuration of external connection pads are reduced. As a result, the size of the semiconductor device 1 can be reduced.

[0111] (Second Implementation)

[0112] Next, refer to Figure 9 The semiconductor device 1B according to the second embodiment of the present invention will be described. In addition, in this second embodiment, the same reference numerals are used for the same components as in the first embodiment, and their descriptions are omitted; only the differences are described.

[0113] Figure 9 This is a block diagram illustrating an example configuration of a memory system equipped with the semiconductor device 1B according to the second embodiment. The semiconductor device 1B, for example, uses a NAND flash memory. The semiconductor device 1B is controlled by a memory controller 2. Communication between the semiconductor device 1B and the memory controller 2, for example, supports the NAND interface standard.

[0114] like Figure 9 As shown, for example, semiconductor device 1B includes a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder 15, a sense amplifier module 16, and a transceiver module 17B.

[0115] The transceiver module 17B sends signals from the memory controller 2 to the command register 11, address register 12, etc. in the semiconductor device 1B, and sends signals from the sense amplifier module 16 to the memory controller 2.

[0116] (Send and receive module)

[0117] Figure 10 This is an example of a transceiver module 17B and a portion of the circuitry of a memory controller in the semiconductor device 1B according to the second embodiment. The transceiver module 17B, for example, has a transmitting circuit 61B and a receiving circuit 62.

[0118] The transmitting circuit 61B includes, for example, a first coil 30, an inverter 31, and an AND gate 32. The first coil 30 is connected to the inverter 31 of the transceiver module 17B. The first coil 30 is supplied with a power supply voltage VDD. The inverter 31 is connected to the AND gate 32. The AND gate 32 receives input signals Txdata and Tx-enable from the memory controller 2, for example.

[0119] (Structure of a semiconductor device)

[0120] Hereinafter, an example of the structure of the semiconductor device 1B according to the second embodiment will be described. Figure 11 This is a cross-sectional view showing the configuration of semiconductor device 1B. Semiconductor device 1B is, for example, a three-dimensional memory in which a circuit chip 200 and an array chip 300 are bonded at a bonding surface S. The circuit chip 200 includes control circuitry (logic circuitry) that controls the operation of the array chip 300. The construction of semiconductor device 1B will now be described in detail.

[0121] Semiconductor device 1B includes, for example, a first substrate 100, a first external connection pad 71, a second external connection pad 72, a first coil 30, a laminate 110, a laminate 120, a second substrate 160, and a laminate 165.

[0122] The second substrate 160 is disposed above the laminate 110. The second substrate 160 is disposed separately from the first substrate 100 in the Z direction. The second substrate 160 is disposed on the first surface 1101 of the laminate 110. The second substrate 160 is, for example, a semiconductor substrate such as silicon. The source region and drain region of the transistor 152 included in the laminate 165 are provided on the second substrate 160.

[0123] The laminate 165 is disposed on surface 160a of the second substrate 160. The laminate 165 has a plurality of wirings 150B, a plurality of contact plugs 151, a plurality of transistors 152, a plurality of wirings 153, an insulating layer 141, an insulating layer 142, a first external connection pad 71, a second external connection pad 72, and a first coil 30.

[0124] The first external connection pad 71 is disposed separately from the first substrate 100 in the thickness direction, i.e., the Z direction. The second external connection pad 72 is disposed separately from the first substrate 100 in the Z direction. The first coil 30 is disposed separately from the first substrate 100 in the Z direction. The first coil 30 is connected to the first external connection pad 71. The wiring 150B is electrically connected to the source line 60 of the laminate 110. In the second embodiment, the first external connection pad 71, the second external connection pad 72, the first coil 30, and the plurality of wirings 150B are disposed on the first surface 141a of the insulating layer 141. The first external connection pad 71, the second external connection pad 72, the first coil 30, the contact plug 151, and the wirings 150B are formed using a conductive material such as copper, tungsten, or aluminum. The first external connection pad 71 and the second external connection pad 72 are provided with external connection terminals (e.g., solder balls), which are not shown, and are electrically connected to the external semiconductor device 1B via these external connection terminals. The signal that can be input to the first coil via the first external connection pad 71 is at least one of a data signal, a control signal, and a data strobe signal.

[0125] Transistor 152 is disposed on the second substrate 160. Transistor 152 is connected to contact plug 151. Transistor 152 is electrically connected to the first coil 30 and the first external connection pad 71 via contact plug 151 and wiring 150B. The plurality of transistors 152 are transistors constituting inverter 31 and AND gate 32. Inverter 31 is disposed separately from the first substrate 100 in the Z direction. Furthermore, inverter 31 is electrically connected between the first external connection pad 71 and the first coil 30.

[0126] An insulating layer 141 is disposed between a plurality of contact plugs 151 and a plurality of wirings 153, electrically insulating these components from each other. The insulating layer 141 is formed, for example, using silicon oxide or silicon nitride.

[0127] An insulating layer 142 is disposed above the first coil 30 and the wiring 150B. The insulating layer 142 is a passivation film that protects the first coil 30 and the wiring 150B. The insulating layer 142 is, for example, a silicon oxide film.

[0128] The second embodiment has been described above. The semiconductor device 1B can be manufactured using known methods. In the semiconductor device 1B according to the second embodiment, signal transmission is achieved by using inductive coupling between the first coil 30 and the second coil 33, thus achieving power saving. Furthermore, since wiring used in the transmission of data signals, etc., can be omitted, the design constraints on the configuration of external connection pads are reduced. Therefore, the size of the semiconductor device 1B can be reduced. In the semiconductor device 1B, since an inverter and an AND gate are provided on the second substrate, a portion of the circuitry on the memory controller 2 side can be omitted.

[0129] (Third Implementation)

[0130] Next, refer to Figure 12 The semiconductor device 1C according to the third embodiment of the present invention will be described. Furthermore, in this second embodiment, the same reference numerals are used for the components that are the same as those in the first embodiment, and their descriptions are omitted; only the differences are described.

[0131] (Structure of a semiconductor device)

[0132] Hereinafter, an example of the structure of the semiconductor device 1C according to the third embodiment will be described. Figure 12 This is a cross-sectional view showing the configuration of semiconductor device 1C. In semiconductor device 1C, for example, circuit chip 200 is bonded to array chip 300A at bonding surface S1A. Array chip 300B is bonded to array chip 300A at bonding surface S1B. Circuit chip 200 includes control circuitry (logic circuitry) that controls the operation of array chips 300A and 300B. The structure of semiconductor device 1C will now be described in detail.

[0133] The first external connection pad 71 is disposed separately from the first substrate 100 in the thickness direction, i.e., the Z direction. The second external connection pad 72 is disposed separately from the first substrate 100 in the Z direction. The second external connection pad 72 is a pad different from the first external connection pad 71. Power can be supplied to the second external connection pad 72 from an external power source, or a reference voltage (e.g., ground voltage) can be applied to the second external connection pad 72.

[0134] The first coil 30 is disposed separately from the first substrate 100 in the Z direction. The first coil 30 is also connected to the first external connection pad 71. Wiring 150 is electrically connected to source lines 60A and 60B. In the third embodiment, the first external connection pad 71, the second external connection pad 72, the first coil 30, and the wiring 150 are disposed on the first surface 110B1 of the laminate 110B. The first external connection pad 71, the second external connection pad 72, the first coil 30, and the wiring 150 are formed of a conductive material such as copper, tungsten, or aluminum. The first coil 30 will be described later. The first external connection pad 71 and the second external connection pad 72 are provided with external connection terminals (e.g., solder balls), which are electrically connected to the external components of the semiconductor device 1.

[0135] The stack 110A constitutes the array chip 300A. The stack 110A is disposed on top of the stack 120. The stack 110A is disposed between the first substrate 100 and the stack 110B. The stack 110A includes a memory cell array 10A, multiple contact plugs 42A, multiple wirings 43A, multiple pads 44A and 46A, an insulator 45A, a first power pad 48A, and a first power wiring 49A. The stack 110A is an example of a "first stack". The pad 44A is an example of a "first pad". The pad 44B is an example of a "fourth pad". The insulator 45A is an example of a "first insulator". The wiring 47A connected to the pad 44 in the wiring 43A is an example of a "first wiring".

[0136] The stack 110B constitutes the array chip 300B. The stack 110B is disposed on top of the stack 110A. The stack 110B is disposed between the first external connection pad 71, the second external connection pad 72, the first coil 30, and the stack 110A. The stack 110B includes a memory cell array 10B, multiple contact plugs 42B, multiple wirings 43B, multiple pads 44B, an insulator 45B, a first power pad 48B, and a first power wiring 49B. The stack 110B is an example of a "third stack". The pads 44B are an example of "third pads". The insulator 45B is an example of "third insulators". The wiring 47B connected to the pads 44 in the wirings 43B is an example of "third wiring".

[0137] Pad 46A is a connection electrode provided in the laminate 110A. When the laminates 110A and 110B are stacked, pad 46A of the laminate 110A is bonded to pad 44B of the laminate 110B. Additionally, insulator 45A is in contact with insulator 45B.

[0138] The third embodiment has been described above. The semiconductor device 1C can be manufactured using known methods. In the semiconductor device 1C according to the third embodiment, signal transmission is achieved by using inductive coupling between the first coil 30 and the second coil 33, thus achieving power saving. Furthermore, since wiring used in the transmission of data signals, etc., can be omitted, the design constraints on the configuration of external connection pads are reduced. Therefore, the size of the semiconductor device 1C can be reduced. The semiconductor device 1C has multiple array chips. Therefore, the storage capacity can be larger than that of the semiconductor device 1.

[0139] In the third embodiment, an example of two array chips is described, but the number of array chips is not limited to two. The number of array chips in a semiconductor device can also be two or more.

[0140] (Fourth Implementation)

[0141] Next, refer to Figure 13 The semiconductor device 1D according to the fourth embodiment of the present invention will be described. In addition, in this fourth embodiment, the same reference numerals are used for the same components as in the first and third embodiments, and their descriptions are omitted; only the differences are described.

[0142] (Structure of a semiconductor device)

[0143] Hereinafter, an example of the structure of the semiconductor device 1D according to the fourth embodiment will be described. Figure 13 This is a cross-sectional view showing the configuration of a semiconductor device 1D. In the semiconductor device 1D, for example, a circuit chip 200 is bonded to an array chip 300A at a bonding surface S1A. An array chip 300B is bonded to an array chip 300A at a bonding surface S1B. Similarly, array chips 300C to 300F are bonded to each other. The circuit chip 200 includes a control circuit (logic circuit) that controls the operation of array chips 300A, 300B, 300C, 300D, 300E, and 300F. The construction of the semiconductor device 1D will now be described in detail. The semiconductor device 1D has a first coil 30, a second coil 33, and a third coil 34. The third coil 34 has a laminate 110C.

[0144] The first external connection pad 71 is disposed separately from the first substrate 100 in the thickness direction, i.e., the Z direction. The second external connection pad 72 is disposed separately from the first substrate 100 in the Z direction. The second external connection pad 72 is a pad different from the first external connection pad 71. Power can be supplied to the second external connection pad 72 from an external power source, or a reference voltage (e.g., ground voltage) can be applied to the second external connection pad 72. The first coil 30 is disposed separately from the first substrate 100 in the Z direction. In addition, the first coil 30 is connected to the first external connection pad 71. The wiring 150 is electrically connected to the source line 60. In the fourth embodiment, the first external connection pad 71, the second external connection pad 72, the first coil 30, and the wiring 150 are disposed on the first surface 110F1 of the laminate 110F.

[0145] <The structure of the first, second, and third coils>

[0146] Figure 14 It is a diagram showing the positional relationship of the first coil 30, the second coil 33 and the third coil 34.

[0147] In the Z direction, at least a portion of the first coil 30 overlaps with the third coil 34. The first coil 30 is capable of inductive coupling with the third coil 34. As long as the first coil 30 and the third coil 34 are capable of inductive coupling, the positional relationship between the first coil 30 and the third coil 34 is not particularly limited.

[0148] In the Z direction, at least a portion of the third coil 34 overlaps with the second coil 33. The third coil 34 is capable of inductive coupling with the second coil 33. As long as the third coil 34 and the second coil 33 are capable of inductive coupling, the positional relationship between the third coil 34 and the second coil 33 is not particularly limited.

[0149] The first coil 30 is, for example, in the shape of a quadrilateral frame or a ring. The second coil 33 is, for example, in the shape of a quadrilateral frame or a ring. The third coil 34 is, for example, in the shape of a quadrilateral frame or a ring. Preferably, the shape of the first coil 30 is the same as the shape of the third coil 34. Preferably, the shape of the third coil 34 is the same as the shape of the second coil 33.

[0150] The length D1 of the first coil 30 in the X direction is not particularly limited. Similarly, the length D3 of the first coil 30 in the Y direction is not particularly limited. Preferably, the length D3 of the first coil 30 in the Y direction is equal to the length D1 in the X direction. Preferably, the length D1 of the first coil 30 in the X direction is longer than the distance H2 between the first coil 30 and the third coil 34 in the Z direction. Preferably, the length D3 of the first coil 30 in the Y direction is longer than the distance H2 between the first coil 30 and the third coil 34 in the Z direction.

[0151] The length D2 of the second coil 33 in the X direction is not particularly limited. Similarly, the length D4 of the second coil 33 in the Y direction is not particularly limited. Preferably, the length D4 of the second coil 33 in the Y direction is equal to the length D2 in the X direction. Preferably, the length D2 of the second coil 33 in the X direction is longer than the distance H3 between the third coil 34 and the second coil 33 in the Z direction. Preferably, the length D4 of the second coil 33 in the Y direction is longer than the distance H3 between the third coil 34 and the second coil 33 in the Z direction.

[0152] The length D5 of the third coil 34 in the X direction is not particularly limited. Similarly, the length D6 of the third coil 34 in the Y direction is not particularly limited. Preferably, the length D6 of the third coil 34 in the Y direction is equal to the length D5 in the X direction. Preferably, the length D5 of the third coil 34 in the X direction is longer than the distance H2 between the first coil 30 and the third coil 34 in the Z direction. Preferably, the length D6 of the third coil 34 in the Y direction is longer than the distance H2 between the first coil 30 and the third coil 34 in the Z direction. Preferably, the length D5 of the third coil 34 in the X direction is longer than the distance H3 between the third coil 34 and the second coil 33 in the Z direction. Preferably, the length D6 of the third coil 34 in the Y direction is longer than the distance H3 between the third coil 34 and the second coil 33 in the Z direction.

[0153] The fourth embodiment has been described above. The semiconductor device 1D can be manufactured using known methods. In the semiconductor device 1D according to the fourth embodiment, power saving is achieved by using inductive coupling between the first coil 30 and the third coil 34, and between the third coil 34 and the second coil 33, for signal transmission. Furthermore, since wiring used in the transmission of data signals can be omitted, design constraints on the configuration of external connection pads are reduced. Therefore, the size of the semiconductor device 1D can be reduced. The semiconductor device 1D has multiple array chips. Therefore, the storage capacity can be larger than that of the semiconductor device 1. Additionally, the semiconductor device 1D has a third coil 34. Therefore, even with multiple array chips, signal transmission between the first coil 30 and the second coil 33 is possible.

[0154] In the fourth embodiment, an example of one third coil 34 is described, but it is also possible to have two or more third coils 34.

[0155] <Example>

[0156] The following describes several embodiments relating to the configuration of the first coil 30. The configuration of the first coil 30 will be used as an example in the description. The second coil 33 is configured at a position where it can be inductively coupled to the first coil 30. However, the configuration of the first coil 30 and the second coil 33 is not limited to the embodiments described below.

[0157] (First Embodiment)

[0158] Figure 15 This is a top view showing an example of the configuration of the first coil 30. The sense amplifier region RSA is the area in the circuit chip 200 where the sense amplifier module 16 is located. The line decoder region RD is the area in the circuit chip 200 where the line decoder 15 is located. The peripheral circuit region PERI is the area in the circuit chip 200 where the sequencer 13, etc., is located. The memory region MA is the area in the stack 110 where the memory cell array 10 is located. The memory region MA includes the sense amplifier region RSA.

[0159] In the semiconductor device 1E, a plurality of first coils 30 and a plurality of first external connection pads 71 ​​are provided in the peripheral circuit region PERI.

[0160] The semiconductor device 1E is capable of transmitting signals between the first coil 30 and the second coil 33 using inductive coupling.

[0161] (Second Embodiment)

[0162] Figure 16 This is a top view showing an example of the configuration of the first coil 30. In the semiconductor device 1F, a plurality of first external connection pads 71 ​​are provided in the peripheral circuit region PERI. Additionally, the first coil 30 is provided in the storage region MA. The storage region MA includes the sense amplifier region RSA.

[0163] Similar to semiconductor device 1E, semiconductor device 1F is capable of transmitting signals between the first coil 30 and the second coil 33 using inductive coupling.

[0164] (Third Embodiment)

[0165] Figure 17 This is a top view showing an example of the configuration of the first coil 30. In the semiconductor device 1G, a plurality of first external connection pads 71 ​​and a plurality of first coils 30 are provided in the peripheral circuit region PERI. Additionally, a plurality of first external connection pads 71 ​​and a plurality of first coils 30 are provided in the storage region MA. The storage region MA includes the sense amplifier region RSA and the peripheral circuit region PERI.

[0166] Similar to semiconductor device 1E, semiconductor device 1G can transmit signals between the first coil 30 and the second coil 33 using inductive coupling. Furthermore, semiconductor device 1G is smaller in size than semiconductor devices 1E and 1F.

[0167] According to at least one embodiment described above, a semiconductor device includes a first substrate, a first external connection pad, a first coil, a first laminate, and a second laminate. The first external connection pad is disposed separately from the first substrate in the thickness direction, i.e., a first direction. The first coil is disposed separately from the first substrate in the first direction. The first coil is electrically connected to the first external connection pad. The first laminate is disposed between the first external connection pad and the first substrate, and between the first coil and the first substrate. The first laminate includes a first insulator, a first wiring disposed in the first insulator, and a first pad electrically connected to the first wiring. The second laminate is disposed between the first laminate and the first substrate. The second laminate includes a second insulator, a second wiring disposed in the second insulator, a second pad electrically connected to the second wiring, and a second coil. The first insulator is in contact with the second insulator. The first pad is bonded to the second pad. In the first direction, at least a portion of the first coil overlaps with the second coil. With this configuration, improved electrical characteristics can be achieved.

[0168] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to the invention as described in the claims.

[0169] [Explanation of the labels]

[0170] 1 Semiconductor device, 2 Memory controller, 10 Memory cell array, 11 Command register, 12 Address register, 13 Sequencer, 14 Driver module, 15 Line decoder, 16 Sensing amplifier module, 17 Transceiver module, 30 First coil, 33 Second coil, 71 First external connection pad, 72 Second external connection pad, 100 First substrate, 110, 120, 165 Laminates.

Claims

1. A semiconductor device comprising: substrate; The first external connection pad is disposed separately from the substrate in the thickness direction of the substrate, i.e., in the first direction. A first coil is disposed separately from the substrate in the first direction and is electrically connected to the first external connection pad; A first laminate is disposed between the first external connection pad and the substrate and between the first coil and the substrate. The first laminate includes a first insulator, a first wiring disposed in the first insulator, and a first pad electrically connected to the first wiring. as well as A second laminate is disposed between the first laminate and the substrate. The second laminate includes a second insulator, a second wiring disposed in the second insulator, a second pad electrically connected to the second wiring, and a second coil. The first insulator is in contact with the second insulator. The first pad is bonded to the second pad. In the first direction, at least a portion of the first coil overlaps with the second coil.

2. The semiconductor device according to claim 1, wherein, In the first direction, the second coil is closer to the substrate than the interface between the first pad and the second pad.

3. The semiconductor device according to claim 1, wherein, It also includes a third laminate disposed between the first external connection pad and the first laminate, and between the first coil and the first laminate. The third laminate includes a third insulator, a third wiring disposed in the third insulator, and a third pad electrically connected to the third wiring. The first laminate further includes a fourth pad, which is electrically connected to the first wiring and is bonded to the third pad. The first insulator is in contact with the third insulator.

4. The semiconductor device according to claim 1, wherein, It also includes a third coil, which is disposed between the first coil and the second coil in the first direction. In the first direction, at least a portion of the first coil overlaps with the third coil. In the first direction, at least a portion of the third coil overlaps with the second coil.

5. The semiconductor device according to claim 1, wherein, It also includes an inverter, which is disposed separately from the substrate in the first direction and electrically connected between the first external connection pad and the first coil.

6. The semiconductor device according to claim 1, wherein, It has a second external connection pad, which is disposed separately from the substrate in the first direction, and can be powered by an external power source or have a reference voltage applied to it. The first laminate further includes a first power trace and a first power pad, the first power trace being electrically connected to the second external connection pad and extending along the first direction within the first insulator, and the first power pad being electrically connected to the first power trace. The second stack further includes a second power pad that is coupled to the first power pad.

7. The semiconductor device according to claim 1, wherein, The signal that can be input to the first coil is at least one of a data signal, a control signal, and a data strobe signal.

8. The semiconductor device according to claim 1, wherein, The second pad is electrically connected to the line decoder.

9. The semiconductor device according to claim 1, wherein, The second pad is electrically connected to the sensing amplifier module.

10. The semiconductor device according to claim 1, wherein, The shape of the first coil is the same as that of the second coil.

11. The semiconductor device according to claim 1, wherein, The first length of the first coil in the second direction is greater than the distance between the first coil and the second coil in the first direction. The second length of the second coil in the second direction is greater than the distance. The second direction is the direction that intersects with the first direction.

12. The semiconductor device according to claim 1, wherein, It also includes a storage cell array in the first region, a sensor amplifier module in the second region, a line decoder in the third region, and a sequencer in the fourth region. The first region includes the second region. The third region is located next to the second direction side of the first region. The fourth region is located next to the third region on the third-direction side of the first region and the third region. The second direction is the direction that intersects with the first direction. The third direction is the direction that intersects with the first direction and the second direction.

13. The semiconductor device according to claim 12, wherein, The first external connection pad and the first coil are disposed in the fourth region.

14. The semiconductor device according to claim 12, wherein, The first external connection pad is located in the fourth region. The first coil is disposed in the first region.

15. The semiconductor device according to claim 1, wherein, It also includes a storage cell array in the first region, a sensor amplifier module in the second region, a line decoder in the third region, and a sequencer in the fourth region. The first region includes the second region and the fourth region. The third region is located next to the second direction side of the first region. The second direction is the direction that intersects with the first direction. The first external connection pad and the first coil are disposed in the fourth region.

16. A semiconductor device comprising: substrate; The first external connection pad is disposed separately from the substrate in the thickness direction of the substrate, i.e., in the first direction. A first coil is disposed separately from the substrate in the first direction and is electrically connected to the first external connection pad; A first laminate is disposed between the first external connection pad and the substrate and between the first coil and the substrate. The first laminate includes a first insulator, a first wiring disposed in the first insulator, and a first pad electrically connected to the first wiring. as well as A second laminate is disposed between the first laminate and the substrate. The second laminate includes a second insulator, a second wiring disposed in the second insulator, a second pad electrically connected to the second wiring, and a second coil. The first insulator is in contact with the second insulator. The first pad is bonded to the second pad. The first coil can be inductively coupled to the second coil.

17. The semiconductor device according to claim 16, wherein, In the first direction, the second coil is closer to the substrate than the interface between the first pad and the second pad.

18. The semiconductor device according to claim 16, wherein, It also includes a third laminate disposed between the first external connection pad and the first laminate, and between the first coil and the first laminate. The third laminate includes a third insulator, a third wiring disposed in the third insulator, and a third pad electrically connected to the third wiring. The first laminate further includes a fourth pad, which is electrically connected to the first wiring and is bonded to the third pad. The first insulator is in contact with the third insulator.

19. The semiconductor device according to claim 16, wherein, It also includes a third coil, which is disposed between the first coil and the second coil in the first direction. The third coil is capable of inductive coupling with the first coil and the second coil.

20. A semiconductor device comprising: Array chip, which includes an array of memory cells; and A circuit chip, disposed on the array chip in a first direction, includes control circuitry capable of controlling the memory cell array. The array chip includes: The first surface that contacts the circuit chip; A second surface on the side opposite to the first surface; A first external connection pad is disposed on the second surface side; A first coil disposed on the second surface side; First insulator; The first wiring disposed inside the first insulator; and The first pad electrically connected to the first wiring, The circuit chip includes: A second insulator that is in contact with the first insulator; A second wiring disposed inside the second insulator; The second pad is electrically connected to the second wiring and contacts the first pad; as well as The second coil, at least a portion of which overlaps with the first coil in the first direction.

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