Amplifier circuit with low parasitic pole effect and buffer circuit therein

Abstract

An amplifier circuit with low parasitic pole effects and a buffer circuit therein. The amplifier circuit with low parasitic pole effects includes: a preamplifier, an output transistor, and a buffer circuit. The buffer circuit generates a drive signal based on a preamplified signal generated by the preamplifier to control the output transistor. The buffer circuit includes: a buffer input transistor for generating a drive signal at a non-inverting output terminal, the input impedance of the buffer input transistor's control terminal being less than the input impedance of the output transistor's control terminal; a low output impedance circuit having an output impedance less than the inverting output impedance of the buffer input transistor's inverting output terminal; an amplifier transistor for generating an amplified signal at its inverting output terminal; and an amplifier stage circuit for amplifying the amplified signal by an amplification factor such that the equivalent output impedance of the non-inverting output terminal of the buffer input transistor is less than or equal to the product of the intrinsic output impedance and the inverse of the amplification factor.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit with low parasitic pole effect. The present invention also relates to a buffer circuit for reducing the parasitic pole effect. Background Art

[0002] See also Figure 1 , Figure 1 The low-dropout regulator (LDO) of the prior art is shown. Figure 1 As shown, in a low-dropout linear regulator 1000, amplifier 11 generates an amplified signal SA based on an input signal and a feedback loop to regulate the output voltage Vout. Amplified signal SA is used to drive transistor M1. When a load RL requires a large output current I1, transistor M1 must be sufficiently large to generate a sufficiently large drain current, thereby generating a sufficient current I1 to supply the load RL. However, a disadvantage of this prior art is that, in order to achieve high accuracy in the output voltage Vout, the gain of amplifier 11 is relatively high, resulting in a relatively large output resistance (the gain is proportional to the product of the conductance of amplifier 11 and the output resistance). Furthermore, because transistor M1 is physically large, the gate capacitance (input capacitance) of transistor M1 is also relatively large. When the low-dropout linear regulator 1000 is a multi-pole system, due to the larger output resistance of the amplifier 11 and the higher input capacitance of the transistor M1, a relatively high pole effect (i.e., a lower pole frequency) is generated at the node Nm1, thereby causing problems such as poor stability of the low-dropout linear regulator 1000, difficulty in compensation, and poor transient response of the system.

[0003] Compared to the aforementioned prior art, the amplifier circuit with low parasitic pole effect of the present invention, through the design of the buffer circuit therein, not only effectively reduces the parasitic pole effect, but also has the advantages of high bandwidth and high power supply rejection ratio (PSRR), and can further achieve the requirement of high system stability. Summary of the Invention

[0004] From one perspective, the present invention provides an amplifier circuit with low parasitic pole effects, comprising: a pre-amplifier for generating a pre-amplified signal based on an input signal; an output transistor for generating an output signal based on a drive signal applied to a control terminal of the output transistor; and a buffer circuit for generating the drive signal based on the pre-amplified signal. The buffer circuit comprises: a buffer input transistor configured as a follower coupler, wherein a control terminal of the buffer input transistor is controlled by the pre-amplified signal to generate the drive signal at an in-phase output terminal of the buffer input transistor and to generate an inverted control signal at an inverted output terminal of the buffer input transistor. The input impedance of the control terminal of the buffer input transistor is smaller than that of the control terminal of the output transistor. an input impedance of the buffer input transistor; a first low output impedance circuit coupled to an inverting output terminal of the buffer input transistor, wherein the output impedance of the first low output impedance circuit is less than an inverting output impedance of the inverting output terminal of the buffer input transistor; a first amplifier transistor controlled by the inverting control signal to generate a first amplified signal at an inverting output terminal of the first amplifier transistor; an amplifier stage circuit for amplifying the first amplified signal to generate a second amplified signal, wherein an amplification factor is defined between the second amplified signal and the inverting control signal, wherein the second amplified signal is coupled to the driving signal such that an equivalent output impedance of the non-inverting output terminal of the buffer input transistor is less than or equal to a product of an intrinsic output impedance of the non-inverting output terminal of the buffer input transistor and a reciprocal of the amplification factor.

[0005] In a preferred embodiment, a gate capacitance of the buffer input transistor is smaller than a gate capacitance of the output transistor.

[0006] In a preferred embodiment, the gate capacitance of the buffer input transistor is less than 1 percent of the gate capacitance of the output transistor.

[0007] In a preferred embodiment, the first low output impedance circuit is a transistor in a diode coupling form.

[0008] In a preferred embodiment, the first amplifying transistor is a metal-oxide-semiconductor (MOS) transistor or a bipolar junction transistor (BJT).

[0009] In a preferred embodiment, the buffer circuit further includes a second amplifier transistor, wherein the second amplifier transistor and the first amplifier transistor are transistors of the same conductivity type or complementary conductivity type, wherein the first amplifier transistor and the second amplifier transistor are coupled to form a homotype Darlington pair or a heterotype Darlington pair.

[0010] In a preferred embodiment, the amplifier stage circuit has an even number of inverting amplifier transistors connected in series.

[0011] In a preferred embodiment, the buffer circuit further includes a second low output impedance circuit coupled to the inverting output terminal of the first amplifier transistor, wherein the output impedance of the second low output impedance circuit is less than an intrinsic output impedance of the inverting output terminal of the first amplifier transistor.

[0012] In a preferred embodiment, the second low output impedance circuit is a transistor in a diode coupling form.

[0013] In a preferred embodiment, the buffer circuit further includes a first current source circuit and a second current source circuit for biasing the buffer input transistor, wherein the first current source circuit adjusts the current level of the first current source circuit according to the transient change of the output signal to accelerate the transient response of the buffer circuit.

[0014] In a preferred embodiment, when the first current source circuit adjusts the current level of the first current source circuit to increase according to the transient change of the output signal, the output impedance of the first low output impedance circuit is further reduced, thereby accelerating the transient response and improving the transient stability of the amplifier circuit with low parasitic pole effect.

[0015] From another perspective, the present invention also provides a buffer circuit for reducing parasitic pole effects in an amplifier circuit, the buffer circuit generating a drive signal based on a pre-amplified signal generated by a pre-amplifier of the amplifier circuit, wherein the drive signal is used to control a control terminal of an output transistor of the amplifier circuit to generate an output signal. The buffer circuit includes: a buffer input transistor configured as a follower coupler, wherein a control terminal of the buffer input transistor is controlled by the pre-amplified signal to generate the drive signal at an in-phase output terminal of the buffer input transistor and an inverted control signal at an inverted output terminal of the buffer input transistor, wherein the input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor; A first low output impedance circuit is coupled to an inverting output terminal of the buffer input transistor, wherein the output impedance of the first low output impedance circuit is less than an intrinsic output impedance of the inverting output terminal of the buffer input transistor; a first amplifier transistor is controlled by the inverting control signal to generate a first amplified signal at an inverting output terminal of the first amplifier transistor; and an amplifier stage circuit is configured to amplify the first amplified signal to generate a second amplified signal, wherein an amplification factor is defined between the second amplified signal and the inverting control signal, and wherein the second amplified signal is coupled to the driving signal such that an equivalent output impedance of the non-inverting output terminal of the buffer input transistor is less than or equal to a product of an intrinsic output impedance of the non-inverting output terminal of the buffer input transistor and a reciprocal of the amplification factor.

[0016] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A low dropout linear regulator of the prior art is shown.

[0018] Figure 2 A block diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention.

[0019] Figure 3A A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention.

[0020] Figure 3B and Figure 3C Schematic diagrams showing two embodiments of the first amplifying transistor in the amplifier circuit with low parasitic pole effect of the present invention.

[0021] Figure 4A A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention.

[0022] Figure 4B and Figure 4C Schematic diagrams showing two coupling embodiments of the first amplifying transistor and the second amplifying transistor in the amplifier circuit with low parasitic pole effect of the present invention.

[0023] Figure 5 A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention.

[0024] Figure 6 A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention.

[0025] Explanation of symbols in the figure

[0026] 11: Amplifier

[0027] 13: First amplifier transistor

[0028] 14: Second amplifier transistor

[0029] 102: Preamplifier

[0030] 1000: Low Dropout Linear Regulator

[0031] 24: The first low output impedance circuit

[0032] 25: The first low output impedance circuit

[0033] 202: Buffer circuit

[0034] 203: Buffer circuit

[0035] 204: Buffer circuit

[0036] 205: Buffer circuit

[0037] 206: Buffer circuit

[0038] 2002, 2003, 2004, 2005, 2006: Amplifier circuit

[0039] 34, 35, 36: Amplifier circuit

[0040] 305: Output motion detector

[0041] 46: Second Low Output Impedance Circuit

[0042] I1: High current

[0043] IL: Load

[0044] M1: transistor

[0045] Mb1: First current source circuit

[0046] Mb2: Second current source circuit

[0047] Mb3: third current source circuit

[0048] MN1, MN3, MN4: transistors

[0049] MN2: MOS transistor

[0050] Mp: output transistor

[0051] Mp2: Buffer input transistor

[0052] N1: non-inverting output terminal

[0053] N2: Inverting output terminal

[0054] N3: Inverting output terminal

[0055] Nm1: node

[0056] Q1, Q1': BJT transistors

[0057] RL: Load

[0058] SA: Amplify Signal

[0059] Va1: first amplified signal

[0060] Va2: Second amplified signal

[0061] Vb1, Vb2: control signals

[0062] Vdynb: control signal

[0063] VEA: Preamplifier signal

[0064] Vfb: feedback signal

[0065] VG: driving signal

[0066] VG3: driving signal

[0067] VG4: driving signal

[0068] VG5: driving signal

[0069] VG6: driving signal

[0070] Vn2: Inverting control signal

[0071] Vo: output signal

[0072] Vout: output voltage

[0073] Vref: reference signal DETAILED DESCRIPTION

[0074] The drawings in the present invention are schematic diagrams, mainly intended to illustrate the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0075] See also Figure 2 , Figure 2 A block diagram (amplifier circuit 2002) illustrates an embodiment of an amplifier circuit with low parasitic pole effects according to the present invention. In one embodiment, amplifier circuit 2002 includes a preamplifier 102, an output transistor Mp, and a buffer circuit 202. In one embodiment, preamplifier 102 generates a preamplified signal VEA based on an input signal, wherein the input signals are a feedback signal Vfb and a reference signal Vref. Preamplifier 102 generates preamplified signal VEA based on the difference between feedback signal Vfb and reference signal Vref. Buffer circuit 202 generates a drive signal VG based on preamplified signal VEA. Output transistor Mp generates output signal Vo based on drive signal VG applied to a control terminal of output transistor Mp. Output transistor Mp is physically larger to accommodate the high current required by load IL, and therefore has a relatively large input capacitance. The buffer circuit 202 has a lower input capacitance than the input capacitance of the output transistor Mp and a lower output impedance than the output impedance of the pre-amplifier 102. Therefore, the configuration of the buffer circuit 202 allows the amplifier circuit 2002 to form a relatively low pole effect between the output terminal of the pre-amplifier 102 and the input terminal of the buffer circuit 202, due to the equivalent impedance at the output terminal of the pre-amplifier 102 and the relatively low input capacitance of the buffer circuit 202. Furthermore, the larger input capacitance at the control terminal of the output transistor Mp and the relatively low output resistance of the buffer circuit 202 form a relatively low pole effect between the control terminal of the output transistor Mp and the output terminal of the buffer circuit 202. The parasitic pole effect is positively correlated with the product of capacitance and resistance and negatively correlated with bandwidth. Therefore, the configuration of the buffer circuit 202 can significantly reduce the parasitic pole effect of the amplifier circuit 2002, increase bandwidth, and enhance system stability.

[0076] See also Figure 3A , Figure 3A A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention (amplifier circuit 2003 ) is shown. Figure 3A The amplifier circuit 2003 is similar to Figure 2 Amplifier circuit 2002, Figure 3A The buffer circuit 203 is Figure 2A more specific embodiment of the buffer circuit 202 is shown. In one embodiment, the buffer circuit 203 is configured to generate a drive signal VG3 based on the pre-amplified signal VEA. The buffer circuit 203 includes a buffer input transistor Mp2, a first amplifier transistor I3, a first current source circuit Mb1, and a third current source circuit Mb3. In one embodiment, the first current source circuit Mb1 and the third current source circuit Mb3 are configured to bias the buffer input transistor Mp2 based on the control signal Vdynb and the control signal Vb1, respectively.

[0077] In one embodiment, the buffer input transistor Mp2 is configured as a non-inverting follower. Figure 3A In one embodiment, the buffer input transistor Mp2 is a metal-oxide-semiconductor (MOS) transistor configured as a source-follower. In this embodiment, the control terminal of the buffer input transistor Mp2 is controlled by the pre-amplifier signal VEA to generate a drive signal VG3 at the non-inverting output terminal N1 of the buffer input transistor Mp2 and an inverted control signal Vn2 at the inverting output terminal N2 of the buffer input transistor Mp2. Note that the inverting and inverting phases correspond to changes in the control terminal. In one embodiment, the actual size of the buffer input transistor Mp2 is configured to be smaller than the actual size of the output transistor Mp, such that the gate capacitance of the buffer input transistor Mp2 is smaller than the gate capacitance of the output transistor Mp. Consequently, the input impedance of the control terminal of the buffer input transistor Mp2 is smaller than the input impedance of the control terminal of the output transistor Mp. In one embodiment, the gate capacitance of the buffer input transistor Mp2 is significantly smaller than the gate capacitance of the output transistor Mp. For example, the gate capacitance of the buffer input transistor Mp2 is less than one percent of the gate capacitance of the output transistor Mp.

[0078] Please continue reading Figure 3A In one embodiment, the first amplifier transistor 13 is controlled by the inverting control signal Vn2 to generate a first amplified signal Va1 at the inverting output terminal N3 of the first amplifier transistor 13. The first amplified signal Va1 is inversely proportional to the input signal. In this embodiment, because the non-inverting output terminal N1 of the buffer input transistor Mp2 has a relatively low output resistance, and the cascade amplification of the first amplifier transistor 13 and the buffer input transistor Mp2 further reduces the output resistance at the inverting output terminal N3 of the first amplifier transistor 13. In summary, because the buffer input transistor Mp2 has a relatively low gate capacitance and the inverting output terminal N3 of the first amplifier transistor 13 has a relatively low output resistance, the buffer circuit 203 can reduce the parasitic pole effect between the output terminal of the pre-amplifier 102 and the control terminal of the output transistor Mp.

[0079] Please also see Figure 3B and Figure 3C, Figure 3B and Figure 3C Two schematic diagrams showing two embodiments of the first amplifying transistor in the amplifier circuit with low parasitic pole effect of the present invention. In one embodiment, Figure 3A The first amplifying transistor 13 can be configured as Figure 3B The BJT transistor Q1 shown is a bipolar junction transistor (BJT), or a transistor configured as Figure 3C The MOS transistor MN2 shown is a Metal-Oxide-Semiconductor (MOS) transistor. Specifically, when Figure 3A The first amplifying transistor 13 is configured as Figure 3B When the BJT transistor Q1 is connected, the equivalent impedance R VG3 As shown below:

[0080] R VG3 ≈1 / [gm Mp2 (1+β)] Formula 1

[0081] In formula 1, gm Mp2 R is roughly the transconductance gain of the buffer input transistor Mp2, and β is roughly the current gain of the BJT transistor Q1. The equivalent impedance R of the control terminal of the output transistor Mp is shown in Equation 1. VG3 , which is less than the input impedance of the control terminal of the output transistor Mp when not regulated by the buffer circuit 203.

[0082] On the other hand, when Figure 3A The first amplifying transistor 13 is configured as Figure 3C When the MOS transistor MN2 is connected, the equivalent impedance R VG3 As shown below:

[0083] R VG3 ≈1 / (gm Mp2* gm MN2* ro) Formula 2

[0084] In formula 2, gm MN2* ro is roughly the amplification gain of the MOS transistor MN2. The equivalent impedance R of the control terminal of the output transistor Mp is shown in Equation 2. VG3 , which is less than the input impedance of the control terminal of the output transistor Mp when not regulated by the buffer circuit 203.

[0085] See also Figure 4A , Figure 4A A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention (amplifier circuit 2004 ) is shown. Figure 4A The amplifier circuit 2004 is similar to Figure 3A In one embodiment, the buffer circuit 204 is configured to generate a drive signal VG4 based on the pre-amplified signal VEA. Compared to the buffer circuit 2003, the buffer circuit 204 further includes a first low output impedance circuit 24, an amplifier stage circuit 34, and a second current source circuit Mb2. In one embodiment, the second current source circuit Mb2 is configured to bias the buffer input transistor Mp2 based on the control signal Vb2. In one embodiment, the first low output impedance circuit 24 is coupled to the inverting output terminal N2 of the buffer input transistor Mp2. The output impedance of the first low output impedance circuit 24 is lower than the inverting output impedance of the inverting output terminal N2 of the buffer input transistor Mp2, thereby reducing the parasitic pole effect of the inverting output terminal N2 of the buffer input transistor Mp2 and improving system stability.

[0086] In one embodiment, the amplifier stage circuit 34 is configured to amplify the first amplified signal Va1 to generate the second amplified signal Va2. The voltage of the first amplified signal Va1 and the voltage of the second amplified signal Va2 are in phase, wherein an amplification factor is provided between the second amplified signal Va2 and the inverting control signal Vn2. The second amplified signal Va2 is coupled to the drive signal VG such that the equivalent output impedance of the non-inverting output terminal N1 of the buffer input transistor Mp2 is less than or equal to the product of the intrinsic output impedance of the non-inverting output terminal N1 of the buffer input transistor Mp2 and the inverse of the amplification factor.

[0087] Please also see Figures 4A to 4C , Figure 4B and Figure 4C Schematic diagrams showing two coupling embodiments of the first amplifying transistor and the second amplifying transistor in the amplifier circuit with low parasitic pole effect of the present invention. In one embodiment, the buffer circuit 204 in the amplifier circuit 2004 further includes a second amplifying transistor 14. Figure 4B and Figure 4C As shown, the second amplifying transistor 14 can be configured as a BJT transistor Q1'. In one embodiment, the BJT transistor Q1' and the BJT transistor Q1 are Figure 4B The same conductivity type transistors are shown and are coupled as a same type Darlington pair; in another embodiment, the BJT transistor Q1' and the BJT transistor Q1 are Figure 4C The complementary conductivity type transistors are shown and are coupled as a heterodyne Darlington pair. Figure 4B and Figure 4C In the embodiment, the BJT transistor Q1' is used to increase the current gain of the BJT transistor.

[0088] See also Figure 5 , Figure 5 A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention (amplifier circuit 2005 ) is shown. Figure 5The amplifier circuit 2005 is similar to Figure 4A Compared to amplifier circuit 2004, in one embodiment, amplifier circuit 2005 further includes an output motion detector 305. In one embodiment, buffer circuit 205 is configured to generate drive signal VG5 based on pre-amplified signal VEA. The first low output impedance circuit 25 in buffer circuit 205 is configured as a diode-coupled transistor MN1. The amplifier stage circuit 35 in buffer circuit 205 includes an even number of inverting amplifier transistors connected in series. Figure 5 In the embodiment, an even number of serially connected inverting amplifier transistors includes transistor MN3 and transistor MN4. In this embodiment, because the diode-coupled transistor MN1 has a low equivalent impedance, the parasitic pole effect on the inverting output terminal N2 of the buffer input transistor Mp2 is significantly reduced, thereby improving system stability.

[0089] like Figure 5 As shown, in one embodiment, the output dynamic detector 305 is configured to generate a control signal Vdynb based on the transient change of the output signal Vo. The first current source circuit Mb1 adjusts the current level of the first current source circuit Mb1 based on the control signal Vdynb to accelerate the transient response of the buffer circuit 205. In one embodiment, when the current level of the first current source circuit Mb1 is increased based on the control signal Vdynb, the drain current of the transistor MN1 increases, thereby increasing the transconductance gain of the transistor MN1. As a result, the output impedance of the first low output impedance circuit 25 is further reduced, thereby accelerating the transient response and improving the transient stability of the amplifier circuit with a low parasitic pole effect. Figure 5 In the embodiment, the equivalent impedance R of the control terminal of the output transistor Mp is VG5 As shown below:

[0090] R VG5 ≈1 / (gm Mp2* gm Q1* ro * gm MN3* ro) Formula 3

[0091] In formula 3, gm Q1* ro is roughly the amplification gain of the BJT transistor Q1, gm MN3* ro is roughly the amplification gain of transistor MN3. Compared with formula 1 or formula 2 (such as Figure 3A The equivalent impedance R of the control terminal of the output transistor Mp shown in Formula 3 is VG5 It is known that the equivalent impedance R of the control terminal of the output transistor Mp can be significantly reduced by the cascade amplification of the amplifier circuit 35. VG5It is greatly reduced, thereby greatly reducing its parasitic pole effect and improving bandwidth.

[0092] See also Figure 6 , Figure 6 A schematic diagram showing an embodiment of an amplifier circuit with low parasitic pole effect according to the present invention (amplifier circuit 2006 ) is shown. Figure 6 The amplifier circuit 2006 is similar to Figure 5 Amplifier circuit 2005. Compared to amplifier circuit 2005, in one embodiment, buffer circuit 206 is configured to generate drive signal VG6 based on pre-amplified signal VEA. In one embodiment, within buffer circuit 206, amplifier stage circuit 36 ​​further includes a second low output impedance circuit 46 coupled to the inverting output terminal of MOS transistor MN2. The output impedance of second low output impedance circuit 46 is lower than the intrinsic output impedance of the inverting output terminal of MOS transistor MN2 (first amplifier transistor 13), thereby reducing parasitic pole effects on first amplified signal Va1. In one embodiment, second low output impedance circuit 46 is a diode-coupled transistor MN5. Figure 6 In the embodiment, the equivalent impedance R of the control terminal of the output transistor Mp is VG6 As shown below:

[0093] R VG6 ≈1 / (gm Mp2* gm MN3* ro)

[0094] The present invention has been described above with respect to the preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention and is not intended to limit the scope of the rights of the present invention. The various embodiments described are not limited to individual applications, but can also be applied in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. An amplifier circuit with low parasitic pole effect, comprising: a pre-amplifier for generating a pre-amplified signal according to an input signal; an output transistor for generating an output signal according to a driving signal applied to a control terminal of the output transistor; as well as a buffer circuit for generating the driving signal according to the pre-amplified signal, the buffer circuit comprising: a buffer input transistor configured as a co-inverter coupler, wherein a control terminal of the buffer input transistor is controlled by the pre-amplified signal to generate the drive signal at an in-phase output terminal of the buffer input transistor and generate an inverted control signal at an inverted output terminal of the buffer input transistor, and an input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor; a first low output impedance circuit coupled to an inverting output terminal of the buffer input transistor, wherein an output impedance of the first low output impedance circuit is smaller than an inverting output impedance of the inverting output terminal of the buffer input transistor; a first amplifying transistor, controlled by the inverting control signal to generate a first amplified signal at an inverting output terminal of the first amplifying transistor; as well as An amplifier stage circuit is configured to amplify the first amplified signal to generate a second amplified signal, wherein an amplification factor is defined between the second amplified signal and the inverted control signal, and wherein the second amplified signal is coupled to the drive signal such that an equivalent output impedance of the non-inverting output terminal of the buffer input transistor is less than or equal to a product of an intrinsic output impedance of the non-inverting output terminal of the buffer input transistor and a reciprocal of the amplification factor.

2. The amplifier circuit with low parasitic pole effect according to claim 1, wherein: A gate capacitance of the buffer input transistor is smaller than a gate capacitance of the output transistor.

3. The amplifier circuit with low parasitic pole effect as claimed in claim 2, wherein: The gate capacitance of the buffer input transistor is less than 1 percent of the gate capacitance of the output transistor.

4. The amplifier circuit with low parasitic pole effect according to claim 1, wherein: The first low output impedance circuit is a transistor in a diode coupling form.

5. The amplifier circuit with low parasitic pole effect as claimed in claim 1, wherein: The first amplifying transistor is a metal oxide semiconductor transistor or a bipolar junction transistor.

6. The amplifier circuit with low parasitic pole effect as claimed in claim 1, wherein: The buffer circuit further includes a second amplifier transistor, wherein the second amplifier transistor and the first amplifier transistor are transistors of the same conductivity type or complementary conductivity type, wherein the first amplifier transistor and the second amplifier transistor are coupled to form a homotype Darlington pair or a heterotype Darlington pair.

7. The amplifier circuit with low parasitic pole effect as claimed in claim 1, wherein: The amplifier stage circuit has an even number of inverting amplifier transistors connected in series.

8. The amplifier circuit with low parasitic pole effect as claimed in claim 1, wherein: The buffer circuit further includes a second low output impedance circuit coupled to the inverting output terminal of the first amplifying transistor, wherein an output impedance of the second low output impedance circuit is less than an intrinsic output impedance of the inverting output terminal of the first amplifying transistor.

9. The amplifier circuit with low parasitic pole effect as claimed in claim 8, wherein: The second low output impedance circuit is a transistor in a diode coupling form.

10. The amplifier circuit with low parasitic pole effect according to claim 1, wherein: The buffer circuit further includes a first current source circuit and a second current source circuit for biasing the buffer input transistor, wherein the first current source circuit adjusts the current level of the first current source circuit according to the transient change of the output signal to accelerate the transient response of the buffer circuit.

11. The amplifier circuit with low parasitic pole effect according to claim 10, wherein: When the first current source circuit adjusts the current level of the first current source circuit to increase according to the transient change of the output signal, the output impedance of the first low output impedance circuit is further reduced, thereby accelerating the transient response and improving the transient stability of the amplifier circuit with low parasitic pole effect.

12. A buffer circuit for reducing parasitic pole effects of an amplifier circuit, configured to generate a drive signal based on a pre-amplified signal generated by a pre-amplifier of the amplifier circuit, wherein the drive signal is used to control a control terminal of an output transistor of the amplifier circuit to generate an output signal, wherein the buffer circuit comprises: a buffer input transistor configured as a co-inverter coupler, wherein a control terminal of the buffer input transistor is controlled by the pre-amplified signal to generate the drive signal at an in-phase output terminal of the buffer input transistor and generate an inverted control signal at an inverted output terminal of the buffer input transistor, and an input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor; a first low output impedance circuit coupled to an inverting output terminal of the buffer input transistor, wherein an output impedance of the first low output impedance circuit is less than an intrinsic output impedance of the inverting output terminal of the buffer input transistor; a first amplifying transistor, controlled by the inverting control signal to generate a first amplified signal at an inverting output terminal of the first amplifying transistor; and An amplifier stage circuit is configured to amplify the first amplified signal to generate a second amplified signal, wherein an amplification factor is defined between the second amplified signal and the inverted control signal, and wherein the second amplified signal is coupled to the drive signal such that an equivalent output impedance of the non-inverting output terminal of the buffer input transistor is less than or equal to a product of an intrinsic output impedance of the non-inverting output terminal of the buffer input transistor and a reciprocal of the amplification factor.

13. The buffer circuit according to claim 12, wherein: A gate capacitance of the buffer input transistor is smaller than a gate capacitance of the output transistor.

14. The buffer circuit according to claim 12, wherein: The first low output impedance circuit is a transistor in a diode coupling form.

15. The buffer circuit according to claim 12, wherein: The first amplifying transistor is a metal oxide semiconductor transistor or a bipolar junction transistor.

16. The buffer circuit according to claim 12, wherein: The device further comprises a second amplifying transistor, wherein the second amplifying transistor and the first amplifying transistor are transistors of the same conductivity type or transistors of complementary conductivity type, wherein the first amplifying transistor and the second amplifying transistor are coupled to form a homotype Darlington pair or a heterotype Darlington pair.

17. The buffer circuit according to claim 12, wherein: The amplifier stage circuit has an even number of inverting amplifier transistors connected in series.

18. The buffer circuit according to claim 12, wherein: The device further comprises a second low output impedance circuit coupled to the inverting output terminal of the first amplifying transistor, wherein the output impedance of the second low output impedance circuit is smaller than an intrinsic output impedance of the inverting output terminal of the first amplifying transistor.

19. The buffer circuit according to claim 12, wherein: The device further comprises a first current source circuit and a second current source circuit for biasing the buffer input transistor, wherein the first current source circuit adjusts the current level of the first current source circuit according to the transient change of the output signal to accelerate the transient response of the buffer circuit.

Images