Digital slope analog-to-digital converter and signal conversion method

Abstract

This application relates to a digital slope analog-to-digital converter and a signal conversion method. The digital slope analog-to-digital converter includes a charge-injection digital-to-analog converter circuit, a comparator circuit, a detection circuit, and a control logic circuit system. The charge-injection digital-to-analog converter circuit includes multiple capacitors and samples multiple input signals through these capacitors, generating multiple signals. The comparator circuit compares these multiple signals to generate multiple decision signals. The detection circuit generates an index signal based on the multiple decision signals. The control logic circuit system generates an enable signal based on the index signal and generates a digital output when the comparator circuit detects a crossover point of the multiple signals. The charge-injection digital-to-analog converter circuit gradually adjusts the charge stored in at least one of the multiple capacitors according to the enable signal until the comparator circuit detects the crossover point.

Description

Technical Field

[0001] This application relates to analog-to-digital converters, and in particular to digital slope analog-to-digital converters and signal conversion methods using charge-injection digital-to-analog converter circuits. Background Technology

[0002] Digital slope analog-to-digital converters (DPPs) generate digital codes using ramp-like (or step-like) voltage changes. In existing DPPs, a capacitor array circuit with multiple capacitors is used to gradually adjust the signal level to generate the aforementioned ramp-like voltage change. However, due to potential mismatches between the capacitors, the linearity of the DPP is poor. Furthermore, a sufficient number of capacitors is required to generate this ramp-like voltage change, significantly increasing circuit area and device cost. Summary of the Invention

[0003] In some embodiments, a digital-slope analog-to-digital converter (DADC) includes a charge-injection DADC circuit, a comparator circuit, a detection circuit, and a control logic circuit system. The charge-injection DADC circuit includes a first capacitor and a second capacitor, and is used to sample a first input signal and a second input signal via the first capacitor and the second capacitor, respectively, and generate a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal and the second signal to generate a plurality of decision signals. The detection circuit generates an index signal based on the plurality of decision signals. The control logic circuit system generates an enable signal based on the index signal and generates a digital output when the comparator circuit detects an intersection point between the first signal and the second signal. The charge-injection DADC circuit further adjusts the charge stored in at least one of the first capacitor and the second capacitor according to the enable signal until the comparator circuit detects the intersection point.

[0004] In some embodiments, the signal conversion method includes the following operations: sampling a first input signal and a second input signal via a first capacitor and a second capacitor respectively, and generating a first signal via the first capacitor and a second signal via the second capacitor; comparing the first signal and the second signal to generate a plurality of decision signals; generating an enable signal based on the plurality of decision signals, and gradually adjusting the charge stored in at least one of the first capacitor and the second capacitor according to the enable signal by a charge-injection digital-to-analog converter circuit until an intersection point of the first signal and the second signal is detected; and generating a digital output when the intersection point is detected.

[0005] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0006] [ Figure 1 [A schematic diagram of a digital slope analog-to-digital converter is shown according to some embodiments of this application;]

[0007] [ Figure 2A [Drawn according to some embodiments of this application] Figure 1 A schematic diagram of the charge injection circuit in the diagram;

[0008] [ Figure 2B [Drawn according to some embodiments of this application] Figure 1 Waveform diagrams of multiple signals in the diagram;

[0009] [ Figure 3A [Drawn according to some embodiments of this application] Figure 1 A flowchart illustrating how the control logic circuit system generates digital outputs.

[0010] [ Figure 3B [Drawn according to some embodiments of this application] Figure 1 Partial circuit diagram of the control logic circuit system; and

[0011] [ Figure 4 This is a flowchart illustrating a signal conversion method according to some embodiments of this application. Detailed Implementation

[0012] All terms used herein have their ordinary meanings. The definitions of the terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0013] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit system” can be a single system formed by at least one circuit, and the term “circuit” can be a device that connects at least one transistor and / or at least one active or passive component in a certain manner to process signals.

[0014] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the intent of this application. For ease of understanding, similar elements in the various figures will be designated with the same reference numerals.

[0015] Figure 1 A schematic diagram of a digital slope analog-to-digital converter 100 is shown according to some embodiments of this application. The digital slope analog-to-digital converter 100 includes switches SW1 and SW2, a comparator circuit 120, a charge injection digital-to-analog converter circuit 140, a detection circuit 160, and a control logic circuit system 180.

[0016] Under the control of the control logic circuit system 180, switches SW1 and SW2 are turned on during sampling to transmit input signals VIP and VIN to the charge-injection digital-to-analog converter circuit 140. Under the control of the control logic circuit system 180, switches SW1 and SW2 are not turned on during analog-to-digital conversion.

[0017] The charge-injection digital-to-analog converter circuit 140 includes capacitors C1 and C2, and a charge injection circuit 141. The charge-injection digital-to-analog converter circuit 140 samples the input signal VIP via capacitor C1 and generates a signal VP via capacitor C1. Similarly, the charge-injection digital-to-analog converter circuit 140 samples the input signal VIN via capacitor C2 and generates a signal VN via capacitor C2. During analog-to-digital conversion, comparator circuit 120 compares signals VP and VN to generate decision signals VON and VOP. In response to decision signals VON and VOP, detection circuit 160 generates an index signal VF, which can be used to indicate whether a transition has occurred in decision signals VON and VOP. For example, detection circuit 160 may be (but is not limited to) a gate circuit with an inverting input. This inverting input receives decision signal VOP, and the other input receives decision signal VON. When the decision signal VON is logic 1 and the decision signal VOP is logic 0, the detection circuit 160 can generate an index signal VF with a logic value of 1. When the decision signal VON is logic 0 and the decision signal VOP is logic 1, the detection circuit 160 can generate an index signal VF with a logic value of 0.

[0018] The control logic circuit system 180 generates an enable signal EN based on the index signal VF, and generates a digital output DOUT when the comparator circuit 120 detects the crossing point between signals VP and VN. During the analog-to-digital conversion, the charge-injection digital-to-analog converter circuit 140 gradually adjusts the charge stored in at least one of capacitors C1 and C2 according to the enable signal EN, adjusting at least one corresponding signal between VP and VN until the comparator circuit 120 detects the crossing point between VP and VN. For example, the charge injection circuit 141 gradually adjusts at least one corresponding capacitor between C1 and C2 according to the enable signal EN until the decision signals VON and VOP generated by the comparator circuit 120 change state (i.e., the index signal VF changes state). The operation of the comparator circuit 120 and the charge-injection digital-to-analog converter circuit 140 will be described later. Figure 2A as well as Figure 2B illustrate.

[0019] In some embodiments, the control logic circuit system 180 may also control the timing of switches SW1 and SW2, comparator circuit 120, and charge-injection digital-to-analog converter circuit 140. In some embodiments, the control logic circuit system 180 may include a clock generator circuit (not shown), a counter circuit (not shown), and an encoder circuit (not shown) to perform the aforementioned operations. The operation of the control logic circuit system 180 will be described later. Figure 3A illustrate.

[0020] Figure 2A Drawings based on some embodiments of this application Figure 1 A schematic diagram of the charge injection circuit 141 is shown. The charge injection circuit 141 can be used to gradually adjust the enable signal EN, the decision signal VOP, and the decision signal VON according to the decision signal VON. Figure 1 The charge stored in at least one of capacitors C1 and C2. In this example, the charge injection circuit 141 includes a control circuit 220, a switching circuit 240, and a current source circuit 260.

[0021] Control circuit 220 generates switching signal E1 based on decision signal VON, decision signal VOP, and enable signal EN. Switching circuit 240 is selectively connected to capacitor C1 or capacitor C2 according to switching signal E1. In some embodiments, switching circuit 240 may include multiple switches that are turned on according to multiple control bits (not shown) of switching signal E1 to connect current source circuit 260 to capacitor C1 or capacitor C2. In this way, current source circuit 260 can discharge capacitor C1 or capacitor C2 via switching circuit 240. Equivalently, during the period when switching circuit 240 is turned on (e.g., for...), Figure 2BDuring the time period t, capacitor C1 (or capacitor C2) will inject charge into the current source circuit 260 to gradually adjust (e.g., to reduce) the level of signal VP (or signal VN).

[0022] In some embodiments, the control circuit 220 may be implemented by several logic gate circuits and register circuits to generate multiple control bits in the switching signal E1. The register circuit can be used to store decision signals VON and VOP corresponding to the first comparison result generated by the comparator circuit 120 during the analog-to-digital conversion. Based on the decision signals VON and VOP corresponding to the first comparison result, the switching circuit 240 can decide to connect the current source circuit 260 to capacitor C1 or capacitor C2. For example, the comparator circuit 120 is reset before starting the comparison, such that the decision signals VOP and VON have the same reset level (e.g., a low level corresponding to logic value 0 or a high level corresponding to logic value 1). If, in the first comparison after the sampling period, the comparator circuit 120 confirms that the level of signal VP is higher than the level of signal VN, the comparator circuit 120 will output a decision signal VON with a first logic value (e.g., logic value 1) and a decision signal VOP with a second logic value (e.g., logic value 0) (equivalent to the first comparison result). In response to the decision signals VON and VOP, the switching circuit 240 can connect the current source circuit 240 to capacitor C1 according to the switching signal E1 to gradually discharge capacitor C1. In other words, the charge injection circuit 141 can discharge one of capacitors C1 and C2 with the higher level according to the decision signals VON and VOP corresponding to the first comparison result to detect the crossover point of signals VP and VN. Furthermore, the charge injection circuit 141 can determine the conduction period of the switching circuit 240 (i.e., the time for the current source circuit 260 to discharge capacitor C1 or capacitor C2) according to the enable signal EN. Figure 2B The time length t).

[0023] Figure 2B Drawings based on some embodiments of this application Figure 1 The waveforms of signals VP and VN are shown in the diagram. During period T1 (i.e., the sampling period), switches SW1 and SW2 are turned on. Under this condition, capacitor C1 samples the input signal VIP, causing the level of signal VP (i.e., the level of capacitor C1) to become high, and capacitor C2 samples the input signal VIN, causing the level of signal VN (i.e., the level of capacitor C2) to become low.

[0024] During period T2, the analog-to-digital conversion begins, therefore switches SW1 and SW2 are not turned on. Comparator circuit 120 compares signal VP with signal VN, and confirms that signal VP is higher than signal VN, outputting a decision signal VON with a logic value of 1 and a decision signal VOP with a logic value of 0. In other words, in this example, the level of the indicator signal VP after the first comparison after sampling the input signals VIP and VIN is higher than the level of signal VN. Under this condition, detection circuit 120 will output an indicator signal VF with a logic value of 1, and charge-injection digital-to-analog converter circuit 140 can gradually discharge capacitor C1 according to decision signals VOP and VON.

[0025] During period T3, the charge-injection digital-to-analog converter circuit 140 discharges capacitor C1 to reduce the level of signal VP. Comparator circuit 120 compares signal VP with signal VN again, and confirms that signal VP is still higher than signal VN, and outputs decision signal VON with logic value 1 and decision signal VOP with logic value 0. Then, detection circuit 160 outputs indicator signal VF with logic value 1 again. This process continues, with the charge-injection digital-to-analog converter circuit 140 gradually reducing the level of signal VP over subsequent periods (each period corresponding to time length t) until the level of signal VP is lower than the level of signal VN. For example, in the last period T4, the charge-injection digital-to-analog converter circuit 140 discharges capacitor C1 to reduce the level of signal VP. Comparator circuit 120 compares signal VP with signal VN again, and confirms that signal VP is lower than signal VN, and outputs decision signal VON with logic value 0 and decision signal VOP with logic value 1. Under these conditions, the detection circuit 160 generates an indicator signal VF with a logic value of 0 to indicate that the comparator circuit 120 has detected the intersection point of signals VP and VN. The control logic circuit system 180 can generate corresponding digital outputs DOUT based on the multiple indicator signals VF generated in the above process and end the analog-to-digital conversion.

[0026] Figure 3A Drawings based on some embodiments of this application Figure 1 The flowchart shows the process by which the control logic circuit system 180 generates the digital output DOUT. Figure 3B Drawings based on some embodiments of this application Figure 1 The diagram shows a portion of the control logic circuit system 180. For an explanation of how the control logic circuit system 180 generates the digital output DOUT, please refer to [the diagram / reference needed]. Figure 3A and Figure 3B To simplify the explanation, Figure 3BOnly the circuitry portion of the control logic circuitry system 180 primarily related to generating the digital output DOUT is shown. In some embodiments, the control logic circuitry system 180 includes a counter circuit 305 and an encoder circuit 315, which can be used to perform... Figure 3A Multiple operations are performed to produce the digital output DOUT.

[0027] In operation S310, counting is performed based on the indicator signal to generate a count value. In operation S320, it is checked whether the comparator circuit has detected a crossover point. If a crossover point is detected, operation S330 is executed. If no crossover point is detected, the process returns to operation S310. In operation S330, the count value is encoded to generate a digital output.

[0028] For example, the counter circuit 305 can be configured to operate during sampling (e.g., for...). Figure 2B The period T1 is reset, and counting is triggered by the indicator signal VF after the sampling period to generate the count value CT. Figure 2B For example, during period T2, the indicator signal VF has a logic value of 1. In response to this indicator signal VF, the counter circuit 305 can increment the count value CT by one unit (e.g., the count value CT increases from 0 to +1). During period T3, the indicator signal VF still has a logic value of 1. In response to this indicator signal VF, the counter circuit 305 can increment the count value CT by another unit (e.g., the count value CT increases from +1 to +2). And so on, until the last period T4, when the indicator signal VF changes state to have a logic value of 0. In response to this indicator signal VF, the counter circuit 305 stops incrementing the count value CT and outputs the current count value to the encoder circuit 315. The encoder circuit 315 can encode the count value CT to generate a digital output DOUT. In other words, by operating S310 to S330, the control logic circuit system 180 can count according to the indicator signal VF until the comparator circuit 120 detects the crossover point to generate a count value CT, and encodes the count value CT to generate the digital output DOUT.

[0029] The above-described operation for generating digital output DOUT and the configuration of the control logic circuit system 180 are for illustrative purposes only, and are not intended to limit the scope of this application. Various operations capable of generating digital output DOUT and their corresponding circuit configurations are all within the scope of this application.

[0030] In some related technologies, digital slope analog-to-digital converters (DPPs) use capacitor arrays with multiple capacitors to generate a ramp-like voltage change. In these technologies, mismatches between the multiple capacitors can reduce the linearity of the DPP using the capacitor array. Furthermore, the capacitor array requires multiple capacitors to gradually adjust the level, significantly increasing the circuit area. In the aforementioned embodiments, the number of current source circuits (e.g., current source circuit 260) used to adjust capacitors C1 and C2 in the charge-injection DPP circuit 140 is one. This avoids mismatches in the charge-injection DPP circuit 140 and effectively reduces the circuit area. Additionally, since the charge-injection DPP circuit 140 operates by sequentially injecting charge at different times, this operating characteristic meets the operational requirements of the digital slope analog-to-digital converter 100 to gradually adjust the signal level to detect crossover points.

[0031] In the foregoing embodiments, one of capacitors C1 and C2 is adjusted to detect a crossover point, but this application is not limited thereto. In other embodiments, both capacitors C1 and C2 can be adjusted to detect a crossover point. For example, the charge-injection digital-to-analog converter circuit 140 may further include an additional charge injection circuit for charging the other of capacitors C1 and C2 (i.e., injecting charge into the other of capacitors C1 and C2). Figure 2B For example, since the initial comparison result indicates that the level of signal VN is low, this additional charge injection circuit can gradually charge capacitor C2 to gradually increase the level of signal VN. This allows for faster detection of the crossover point between signals VP and VN. In other words, in some embodiments, the charge injection digital-to-analog converter circuit 140 may include multiple charge injection circuits 141, one of which can be used to discharge one of capacitors C1 and C2 (e.g., the capacitor with the higher potential), and another charge injection circuit 141 can be used to charge one of capacitors C1 and C2 (e.g., the capacitor with the lower potential).

[0032] Alternatively, in other embodiments, the charge-injection digital-to-analog converter circuit 140 may utilize the same charge injection circuit (e.g., charge injection circuit 141) to alternately discharge one of capacitors C1 and C2 and charge the other of capacitors C1 and C2. Figure 2B For example, during period T2, the current source circuit 260 can discharge capacitor C1 via the switching circuit 240. During period T3, the current source circuit 260 can discharge via an additional switch in the switching circuit 240 (not in...). Figure 2A(As shown) capacitor C2 is charged. Similarly, the crossover point between signal VP and signal VN can be detected. Therefore, in different embodiments, the charge-injection digital-to-analog converter circuit 140 can gradually adjust the charge stored in at least one of capacitors C1 and C2 to adjust at least one corresponding signal VN and signal VP until the comparator circuit 120 detects the crossover point.

[0033] The above-described configuration of the charge-injection digital-to-analog converter circuit 140 is for illustrative purposes only and is not intended to limit the scope of this application. Various circuit configurations that allow for gradual adjustment of the level of at least one of capacitors C1 and C2 are all within the scope of this application.

[0034] Figure 4 This is a flowchart illustrating a signal conversion method 400 according to some embodiments of this application. In operation S410, a first input signal (e.g., input signal VIP) and a second input signal (e.g., input signal VIN) are sampled via a first capacitor (e.g., capacitor C1) and a second capacitor (e.g., capacitor C2), respectively. A first signal (e.g., signal VP) is generated via the first capacitor, and a second signal (e.g., signal VN) is generated via the second capacitor. In operation S420, the first signal and the second signal are compared to generate multiple decision signals (e.g., decision signal VON and decision signal VOP). In operation S430, an enable signal (e.g., enable signal EN) is generated based on the multiple decision signals. The charge stored in at least one of the first and second capacitors is gradually adjusted according to the enable signal by a charge-injection digital-to-analog converter circuit (e.g., charge-injection digital-to-analog converter circuit 140) until a crossover point between the first and second signals is detected. In operation S440, a digital output is generated when the crossover point is detected.

[0035] The above operations can be understood by referring to the foregoing embodiments, and therefore will not be repeated here. The above-described operations of the signal conversion method 400 are merely examples and are not limited to being executed in the order shown in this example. Without departing from the operation mode and scope of the embodiments of this application, the various operations in the signal conversion method 400 may be appropriately added, replaced, omitted, or executed in a different order (for example, they may be executed simultaneously or partially simultaneously).

[0036] In summary, the digital-slope analog-to-digital converter and signal conversion method provided in some embodiments of this application can utilize a charge injection circuit to gradually adjust the signal level to generate a ramp-like voltage change. This reduces the effects of mismatch and decreases the number of circuits used, thereby reducing the overall circuit area.

[0037] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

[0038] [Symbol Explanation]

[0039] 100: Digital Slope Analog-to-Digital Converter

[0040] 120: Comparator Circuit

[0041] 140: Charge-injection digital-to-analog converter circuit

[0042] 141: Charge Injection Circuit

[0043] 160: Detection circuit

[0044] 180: Control logic circuit system

[0045] 220: Control circuit

[0046] 240: Switching circuit

[0047] 260: Current source circuit

[0048] 305: Counter Circuit

[0049] 315: Encoder Circuit

[0050] 400: Signal Conversion Methods

[0051] C1, C2: Capacitors

[0052] CT: Count value

[0053] DOUT: Digital Output

[0054] E1: Switching signal

[0055] EN: Enable signal

[0056] S310, S320, S330, S410, S420, S430, S440: Operation

[0057] SW1, SW2: Switches

[0058] T1~T4: Period

[0059] VF: Indicator Signal

[0060] VIN, VIP: Input signal

[0061] VN,VP: Signals

[0062] VON, VOP: Decision Signals

[0063] t: Duration of time.

Claims

1. A digital slope-based analog-to-digital converter, comprising: A charge-injection digital-to-analog converter circuit includes a first capacitor, a second capacitor, and a charge-injection circuit. The charge-injection digital-to-analog converter circuit is used to sample a first input signal and a second input signal through the first capacitor and the second capacitor, respectively, and generate a first signal through the first capacitor and a second signal through the second capacitor. A comparator circuit is used to compare the first signal with the second signal to generate multiple decision signals; A detection circuit for generating an index signal based on the plurality of decision signals; as well as A control logic circuit system is configured to generate an enable signal based on the index signal, and to generate a digital output when the comparator circuit detects an intersection point between the first signal and the second signal. The charge injection circuit is used to gradually adjust the charge stored in at least one of the first capacitor and the second capacitor according to the enable signal and the plurality of decision signals until the comparator circuit detects the crossover point. The charge injection circuit includes: A control circuit for generating a switching signal based on the enable signal and the plurality of decision signals; A switching circuit for selectively connecting to the first capacitor or the second capacitor according to the switching signal; and A current source circuit is used to discharge the first capacitor or the second capacitor via the switching circuit.

2. The digital slope analog-to-digital converter of claim 1, wherein the charge-injection digital-to-analog converter circuit is configured to determine, based on the plurality of decision signals corresponding to an initial comparison result of the first signal and the second signal, the charge stored in the first capacitor and the second capacitor.

3. The digital slope analog-to-digital converter according to claim 1, wherein if the first comparison result after the first input signal and the second input signal are sampled indicates that the level of the first signal is higher than the level of the second signal, the charge injection digital-to-analog converter circuit gradually discharges the first capacitor according to the plurality of decision signals.

4. The digital slope analog-to-digital converter of claim 1, wherein the control logic circuit system is configured to count according to the index signal until the comparator circuit detects the crossover point to generate a count value, and encode the count value to generate the digital output.

5. The digital slope analog-to-digital converter according to claim 1, wherein the number of current source circuits for adjusting the first capacitor or the second capacitor in the charge injection digital-to-analog converter circuit is 1.

6. The digital slope analog-to-digital converter according to claim 1, wherein the charge-injection digital-to-analog converter circuit further comprises: Multiple charge injection circuits are used to discharge one of the first capacitor and the second capacitor and charge the other of the first capacitor and the second capacitor according to the enable signal and the multiple decision signals.

7. A signal conversion method, comprising: A first input signal and a second input signal are sampled via a first capacitor and a second capacitor, respectively, and a first signal is generated via the first capacitor and a second signal is generated via the second capacitor. The first signal is compared with the second signal to generate multiple decision signals; An enable signal is generated based on the plurality of decision signals, and a charge-injection digital-to-analog converter circuit gradually adjusts the charge stored in at least one of the first capacitor and the second capacitor according to the enable signal and the plurality of decision signals until an intersection point of the first signal and the second signal is detected. as well as A digital output is generated when the crossover point is detected. Gradually adjusting the stored charge includes: A switching signal is generated based on the enable signal and the plurality of decision signals; The switching signal is used to selectively connect to the first capacitor or the second capacitor; and The first capacitor or the second capacitor is discharged via a switching circuit.

8. The signal conversion method according to claim 7, wherein gradually adjusting the charge stored in at least one of the first capacitor and the second capacitor by means of the charge-injection digital-to-analog converter circuit according to the enable signal comprises: The charge stored in at least one of the first capacitor and the second capacitor is adjusted based on the plurality of decision signals corresponding to an initial comparison result between the first signal and the second signal.

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