Electrical Discharge Machining Pulse Power Supply and Machining Method Based on Three-Level Cuk Circuit

Abstract

The present invention provides an electrical discharge machining (EDM) pulse power supply and machining method based on a three-level Cuk circuit, comprising: a three-level Cuk main power circuit, a DC voltage source, an FPGA control circuit, and a drive circuit. The three-level Cuk main power circuit is used to connect the EDM gap to achieve discharge machining. The DC voltage source outputs an adjustable DC voltage to power the three-level Cuk main power circuit. The FPGA control circuit generates a PWM signal that enters the drive circuit. The drive circuit processes the PWM signal to generate a drive signal to control the on / off state of the switching transistors in the three-level Cuk main power circuit. This invention effectively increases the switching frequency of the system, significantly reduces voltage and current ripple, and lowers the selection requirements for switching transistors, filter inductors, and output filter capacitors. Simultaneously, it can meet the requirements of high and low voltage composite output for EDM pulse power supplies, efficiently and reliably fulfilling the requirements for EDM pulse power supplies.

Description

Technical Field

[0001] This invention relates to the field of pulse power supplies for electrical discharge machining (EDM), and particularly to an EDM pulse power supply and machining method based on a three-level Cuk circuit. Background Technology

[0002] The problem of insufficient independent manufacturing capabilities for key core components in my country is becoming increasingly apparent, making the demand for high-precision, high-efficiency, and high-quality machining technologies increasingly urgent. Traditional contact machining cannot or is difficult to meet the machining requirements of high-melting-point, high-brittleness, high-hardness, high-strength, and special materials and complex structures. Electrical discharge machining (EDM) has advantages such as high precision, high efficiency, and high quality in machining special materials and complex structures, and has therefore been widely used. The principle of EDM is to provide controllable electrical energy between the electrode wire and the workpiece through a pulsed power supply, forming a continuous pulsed spark discharge channel to erode the material. EDM can be divided into three stages: breakdown delay, discharge machining, and deionization. In the breakdown delay stage, the pulsed power supply needs to provide a large open-circuit voltage to the gap; in the discharge machining stage, the voltage across the gap is a quasi-sustaining voltage of about 20V; in the deionization stage, the pulsed power supply stops working, and no energy is output to the gap. EDM removes material by controlling the conversion of electrical energy into heat and kinetic energy; therefore, the change in discharge energy is the key to determining machining efficiency and quality. Since the voltage remains essentially constant during the discharge phase interval, discharge energy control primarily depends on the regulation of the discharge current. Existing EDM pulse power supplies exhibit significant current ripple, which negatively impacts EDM performance. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides an electrical discharge machining pulse power supply and machining method based on a three-level Cuk circuit. It can output a high-voltage breakdown gap during the breakdown delay stage, output a low quasi-sustaining voltage during the discharge machining stage, and enable the discharge current to meet the requirements of low ripple and high current electrical discharge machining.

[0004] The electrical discharge machining pulse power supply based on a three-level Cuk circuit provided by this invention includes: a three-level Cuk main power circuit, a DC voltage source, an FPGA control circuit, and a drive circuit. The three-level Cuk main power circuit is used to connect to the electrical discharge machining gap to realize discharge machining. The DC voltage source is used to output an adjustable DC voltage to power the three-level Cuk main power circuit. The FPGA control circuit is used to generate a PWM signal to enter the drive circuit. The drive circuit is used to process the PWM signal to generate a drive signal to control the on and off of the switching transistor of the three-level Cuk main power circuit.

[0005] Furthermore, the main component of the three-level Cuk main power circuit is a DC voltage source (V). in), First inductor (L1), First switching transistor (Q1), Second switching transistor (Q2), First capacitor (C1), Second capacitor (C2), First diode (D1), Second diode (D2), Second inductor (L2), Third diode (D3), Third voltage regulator capacitor (C o ), load gap (V) o The DC voltage source (V) in The positive terminal of the first inductor (L1) is connected to the left end of the first inductor (L1), the right end of the first inductor (L1) is connected to the anode of the first capacitor (C1), the cathode of the first capacitor (C1) is connected to the left end of the second inductor (L2), the right end of the second inductor (L2) is connected to the cathode of the third diode (D3), and the anode of the third diode (D3) is connected to the load gap (V). o The negative terminal of the load gap (V) is connected to the negative terminal. o The positive terminal of capacitor C1 is connected to the anode of capacitor C2, and the cathode of capacitor C2 is connected to the DC voltage source (V). in The negative terminal of the first switching transistor (Q1) is connected to the junction of the first inductor (L1) and the first capacitor (C1). The source of the first switching transistor (Q1) is connected to the drain of the second switching transistor (Q2). The source of the second switching transistor (Q2) is connected to the junction of the second capacitor (C2) and the DC voltage source (V). in The first diode (D1) is connected to the connection point of the first capacitor (C1) and the second inductor (L2). The cathode of the first diode (D1) is connected to the connection point of the first switch (Q1) and the second switch (Q2). The anode of the second diode (D2) is connected to the cathode of the first diode (D1). The cathode of the second diode (D2) is connected to the connection point of the load gap (V). o The third voltage regulator capacitor (C) is connected to the connection point of the second capacitor (C2) and the third voltage regulator capacitor (C) o The cathode of the third diode (D3) and the load gap (V) o The connection point is connected to the third voltage regulator capacitor (C). o The anode and load gap (V) o It is connected to the connection point of the second capacitor (C2).

[0006] Furthermore, the switching transistor is a metal-oxide-semiconductor field-effect transistor made of silicon carbide, or a metal-oxide-semiconductor field-effect transistor made of silicon and gallium nitride.

[0007] The pulse power supply method for electrical discharge machining based on a three-level Cuk circuit includes the following steps in a single cycle of electrical discharge machining:

[0008] Step S1: During the breakdown delay stage, the gap is not broken down, and the three-level Cuk circuit is in boost mode. Boost mode can be divided into four stages. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the on / off state of the first switch (Q1) and the second switch (Q2). In the first stage, the first switch (Q1) is turned on and the second switch (Q2) is turned off. At this time, the DC voltage source (V... in The first inductor (L1) and the second capacitor (C2) form a circuit to charge the second capacitor (C2). The first capacitor (C1), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the second capacitor (C2). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a higher forward voltage; in the second stage, the first switch (Q1) and the second switch (Q2) are turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The circuit consists of a first inductor (L1), a second capacitor (C2), a second inductor (L2), a third diode (D3), and a third voltage-regulating capacitor (C). o ), load gap (V) o A power circuit is formed, with the first capacitor (C1) and the second capacitor (C2) simultaneously supplying power to the load gap (V). o The system provides a higher forward voltage; in the third stage, the first switch (Q1) is turned off and the second switch (Q2) is turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The first inductor (L1) and the first capacitor (C1) form a circuit to charge the first capacitor (C1). The second capacitor (C2), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the first capacitor (C1). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a higher forward voltage; in the fourth stage, the first switch (Q1) and the second switch (Q2) are turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The circuit consists of a first inductor (L1), a second capacitor (C2), a second inductor (L2), a third diode (D3), and a third voltage-regulating capacitor (C). o ), load gap (V) o A power circuit is formed, with the first capacitor (C1) and the second capacitor (C2) simultaneously supplying power to the load gap (V). o Provide a higher forward voltage; repeat the above four stages and wait for the gap to break down;

[0009] Step S2: After the gap is broken down, the discharge machining stage begins. The three-level Cuk circuit is in buck mode, which can be divided into four stages. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the switching of the first switch (Q1) and the second switch (Q2). In the first stage, the first switch (Q1) is turned on and the second switch (Q2) is turned off. At this time, the DC voltage source (V... in The first inductor (L1) and the second capacitor (C2) form a circuit to charge the second capacitor (C2). The first capacitor (C1), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the second capacitor (C2). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The first switch (Q1) and the second switch (Q2) are turned off, providing a lower forward voltage. In the second stage, the DC voltage source (V) is then switched off. in The first inductor (L1), the first capacitor (C1), and the second capacitor (C2) form a circuit to charge the first capacitor (C1) and the second capacitor (C2). The third voltage regulator capacitor (C) o ), second inductor (L2), third diode (D3), load gap (V) o ) forms the power circuit, and the third voltage regulator capacitor (C) o ), the second inductor (L2) to the load gap (V o The system provides a lower forward voltage; in the third stage, the first switch (Q1) is turned off and the second switch (Q2) is turned on, at which time the DC voltage source (V) provides a lower forward voltage. in The first inductor (L1) and the first capacitor (C1) form a circuit to charge the first capacitor (C1). The second capacitor (C2), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the first capacitor (C1). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a lower forward voltage; in the fourth stage, the first switch (Q1) and the second switch (Q2) are turned off, at which time the DC voltage source (V) provides a lower forward voltage. in The first inductor (L1), the first capacitor (C1), and the second capacitor (C2) form a circuit to charge the first capacitor (C1) and the second capacitor (C2). The third voltage regulator capacitor (C) o ), second inductor (L2), third diode (D3), load gap (V) o ) forms the power circuit, and the third voltage regulator capacitor (C) o ), the second inductor (L2) to the load gap (V o Provide a lower forward voltage; repeat the above four stages to provide discharge energy to the gap;

[0010] Step S3: After the discharge machining stage ends, the deionization stage begins. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the first switch (Q1) and the second switch (Q2) to be normally off to perform deionization and make the voltage across the gap zero.

[0011] Step S4: Repeat steps S1 to S4 above to enter the next processing cycle.

[0012] Compared with the prior art, the present invention, employing the above technical solution, has the following beneficial effects:

[0013] 1. The present invention proposes an EDM pulse power supply and processing method based on a three-level Cuk circuit, which effectively increases the switching frequency of the system, greatly reduces voltage and current ripple, reduces the selection requirements for switching transistors, filter inductors and output filter capacitors, and improves the power density and reliability of the pulse power supply.

[0014] 2. The electrical discharge machining pulse power supply and machining method based on a three-level Cuk circuit proposed in this invention can meet the requirements of high and low voltage composite output of electrical discharge machining pulse power supply. It outputs high voltage for breakdown gap during breakdown delay stage and low voltage for discharge machining during discharge machining stage. The topology is simpler and efficiently and reliably meets the requirements of electrical discharge machining pulse power supply.

[0015] 3. The electrical discharge machining pulse power supply and machining method based on a three-level Cuk circuit proposed in this invention have lower voltages across the first capacitor (C1) and the second capacitor (C2), which reduces the selection requirements for the first capacitor (C1) and the second capacitor (C2) and improves the power density and reliability of the pulse power supply.

[0016] 4. The electrical discharge machining pulse power supply and machining method based on a three-level Cuk circuit proposed in this invention, the control circuit part of which adopts FPGA programming, can provide a variety of electrical parameters to meet the needs of different machining scenarios. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This invention provides a pulse power supply framework for an electrical discharge machining (EDM) circuit based on a three-level Cuk circuit.

[0019] Figure 2 This invention presents a three-level Cuk circuit for electrical discharge machining pulse power supply topology.

[0020] Figures 3 to 10 The circuit topology and equivalent circuit diagram of the three-level Cuk circuit for electrical discharge machining pulse power supply in each working state proposed in this invention are shown below.

[0021] Figure 11 This is a schematic diagram of the driver chip used in this invention.

[0022] Figures 12 to 14 This is a schematic diagram of the discharge waveform of the three-level Cuk circuit proposed in this invention for electrical discharge machining using a pulse power supply. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] like Figure 1 As shown, this invention is an electrical discharge machining pulse power supply based on a three-level Cuk circuit, including a three-level Cuk main power circuit, a DC source, an FPGA control circuit, and a drive circuit. The three-level Cuk main power circuit is used to connect to the electrical discharge machining gap to achieve discharge machining. The DC voltage source is used to output an adjustable DC voltage to power the three-level Cuk main power circuit. The FPGA control circuit is used to generate a PWM signal to enter the drive circuit. The drive circuit is used to process the PWM signal to generate a drive signal to control the on and off of the switching transistor of the three-level Cuk main power circuit.

[0025] As a specific example, the switching transistor in the circuit topology can be a silicon metal-oxide-semiconductor field-effect transistor (MOSFET), or a silicon carbide or gallium nitride MOSFET. Since this circuit topology primarily serves as a pulse power supply for electrical discharge machining (EDM), considering the average discharge current is 4A and the maximum value does not exceed 10A, the maximum voltage across its terminals is V. in With a maximum input voltage of approximately 100V, and considering margin and reliability, Infineon's IPP60R099CPA MOSFET is selected for some applications, with a maximum drain-source voltage V. DS 650V, drain current I D The maximum on-resistance is 31A (25℃) / 19A (100℃). DS(on)With a resistance of 99mΩ, it can be applied to the electrical discharge machining pulse power supply based on a three-level Cuk circuit as described in the invention.

[0026] As a specific example, for FPGA control circuits, FPGA (Field Programmable Gate Array) is mainly used for control. Since the corresponding control circuit structure is integrated inside, the drive signal of the corresponding switching transistor can be automatically obtained through program calculation. At the same time, program control can be used to meet the needs of different processing stages. In this invention, the Cyclone IV series chip EP4CE6F17C8 from Altera is selected.

[0027] An example of the operating state of a three-level Cuk circuit when the first switch (Q1) is turned on and the second switch (Q2) is turned off is as follows: Figure 3 As shown, the equivalent circuit diagram is as follows: Figure 4 As shown; the operating state of a three-level Cuk circuit when the first switch (Q1) is turned on and the second switch (Q2) is turned on is as follows. Figure 5 As shown, the equivalent circuit diagram is as follows: Figure 6 As shown; the operating state of a three-level Cuk circuit when the first switch (Q1) is off and the second switch (Q2) is on is as follows. Figure 7 As shown, the equivalent circuit diagram is as follows: Figure 8 As shown; the operating state of a three-level Cuk circuit when the first switch (Q1) is turned off and the second switch (Q2) is turned off is as follows. Figure 9 As shown, the equivalent circuit diagram is as follows: Figure 10 As shown;

[0028] As a specific example, the driving circuit can be selected from a driver chip with dual high- and low-side driving and isolation characteristics. This invention selects the Texas Instruments UCC21521 driver chip, such as... Figure 11 As shown, the chip has a small propagation delay and pulse width distortion. The chip's driver can be configured as two low-side drivers, two high-side drivers, or one single-zone driver. It is an isolated dual-channel gate driver chip that can be used for switching transistors with frequencies up to 5MHz. It can meet the requirements of high efficiency, high power density, and robustness in the pulse power supply of this invention.

[0029] As shown in the figure Figures 12 to 14 As shown, a single cycle of the electrical discharge machining includes the following steps:

[0030] Step S1: During the breakdown delay phase, the gap is not broken down, such as... Figure 12 As shown in t0~t1, the three-level Cuk circuit is in boost mode. Boost mode can be divided into four stages t0~t4, as follows: Figure 13As shown. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the switching of the first switch (Q1) and the second switch (Q2). During the first stage t0~t1, the first switch (Q1) is turned on and the second switch (Q2) is turned off. At this time, the DC voltage source (V in The first inductor (L1) and the second capacitor (C2) form a circuit to charge the second capacitor (C2). The first capacitor (C1), the second inductor (L2), and the third voltage regulator capacitor (C) form a circuit to charge the second capacitor (C2). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a higher forward voltage; during the second stage t1 to t2, the first switch (Q1) and the second switch (Q2) are turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The first inductor (L1) forms a circuit, and the first capacitor (C1), the second capacitor (C2), the second inductor (L2), and the third voltage-regulating capacitor (C) form a circuit. o ), load gap (V) o A power circuit is formed, with the first capacitor (C1) and the second capacitor (C2) simultaneously supplying power to the load gap (V). o The system provides a higher forward voltage; during the third stage t2 to t3, the first switch (Q1) is turned off and the second switch (Q2) is turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The first inductor (L1) and the first capacitor (C1) form a circuit to charge the first capacitor (C1). The second capacitor (C2), the second inductor (L2), and the third voltage regulator capacitor (C1) form a circuit to charge the first capacitor (C1). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a higher forward voltage; during the fourth stage t3 to t4, the first switch (Q1) and the second switch (Q2) are turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The first inductor (L1) forms a circuit, and the first capacitor (C1), the second capacitor (C2), the second inductor (L2), and the third voltage-regulating capacitor (C) form a circuit. o ), load gap (V) o A power circuit is formed, with the first capacitor (C1) and the second capacitor (C2) simultaneously supplying power to the load gap (V). o Provide a higher forward voltage; repeat the above four stages and wait for the gap to break down;

[0031] Step S2: After the gap is broken down, the electrical discharge machining stage begins, such as... Figure 12 As shown in t1~t2, the three-level Cuk circuit is in buck mode. Buck mode can be divided into four stages t0~t4, as follows: Figure 14As shown. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the switching of the first switch (Q1) and the second switch (Q2). During the first stage t0~t1, the first switch (Q1) is turned on and the second switch (Q2) is turned off. At this time, the DC voltage source (V in The first inductor (L1) and the second capacitor (C2) form a circuit to charge the second capacitor (C2). The first capacitor (C1), the second inductor (L2), and the third voltage regulator capacitor (C) form a circuit to charge the second capacitor (C2). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The DC voltage source (V) provides a lower forward voltage; during the second stage t1 to t2, the first switch (Q1) and the second switch (Q2) are turned off, and the DC voltage source (V) provides a lower forward voltage. in The first inductor (L1), the first capacitor (C1), and the second capacitor (C2) form a circuit to charge the first capacitor (C1) and the second capacitor (C2). The third voltage regulator capacitor (C) o ), second inductor (L2), load gap (V) o ) forms the power circuit, and the third voltage regulator capacitor (C) o ), the second inductor (L2) to the load gap (V o The system provides a lower forward voltage; during the third stage t2 to t3, the first switch (Q1) is turned off and the second switch (Q2) is turned on, at which time the DC voltage source (V) provides a lower forward voltage. in The first inductor (L1) and the first capacitor (C1) form a circuit to charge the first capacitor (C1). The second capacitor (C2), the second inductor (L2), and the third voltage regulator capacitor (C1) form a circuit to charge the first capacitor (C1). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The DC voltage source (V) provides a lower forward voltage; during the fourth stage t3 to t4, the first switch (Q1) and the second switch (Q2) are turned off, at which time the DC voltage source (V) in The first inductor (L1), the first capacitor (C1), and the second capacitor (C2) form a circuit to charge the first capacitor (C1) and the second capacitor (C2). The third voltage regulator capacitor (C) o ), second inductor (L2), load gap (V) o ) forms the power circuit, and the third voltage regulator capacitor (C) o ), the second inductor (L2) to the load gap (V o Provide a lower forward voltage; repeat the above four stages to provide discharge energy to the gap;

[0032] Step S3: After the electrical discharge machining stage ends, the deionization stage begins, such as... Figure 12As shown in t2~t3, the FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the first switch (Q1) and the second switch (Q2) to be normally off, thereby deionizing and making the voltage across the gap zero.

[0033] Step S4: Repeat steps S1 to S3 above to enter the next processing cycle.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electrical discharge machining pulse power supply based on a three-level Cuk circuit, characterized in that, The system includes a three-level Cuk main power circuit, a DC voltage source, an FPGA control circuit, and a drive circuit. The three-level Cuk main power circuit is used to connect to the EDM gap to achieve electrical discharge machining. The DC voltage source outputs an adjustable DC voltage to power the three-level Cuk main power circuit. The FPGA control circuit generates a PWM signal that enters the drive circuit. The drive circuit processes the PWM signal to generate a drive signal to control the switching transistors of the three-level Cuk main power circuit. The main component of the three-level Cuk main power circuit is: a DC voltage source (V... in ), First inductor (L1), First switching transistor (Q1), Second switching transistor (Q2), First capacitor (C1), Second capacitor (C2), First diode (D1), Second diode (D2), Second inductor (L2), Third diode (D3), Third voltage regulator capacitor (C o ), load gap (V) o The DC voltage source (V) in The positive terminal of the first inductor (L1) is connected to the left end of the first inductor (L1), the right end of the first inductor (L1) is connected to the anode of the first capacitor (C1), the cathode of the first capacitor (C1) is connected to the left end of the second inductor (L2), the right end of the second inductor (L2) is connected to the cathode of the third diode (D3), and the anode of the third diode (D3) is connected to the load gap (V). o The negative terminal of the load gap (V) is connected to the negative terminal. o The positive terminal of capacitor C1 is connected to the anode of capacitor C2, and the cathode of capacitor C2 is connected to the DC voltage source (V). in The negative terminal of the first switching transistor (Q1) is connected to the junction of the first inductor (L1) and the first capacitor (C1). The source of the first switching transistor (Q1) is connected to the drain of the second switching transistor (Q2). The source of the second switching transistor (Q2) is connected to the junction of the second capacitor (C2) and the DC voltage source (V). in The first diode (D1) is connected to the connection point of the first capacitor (C1) and the second inductor (L2). The cathode of the first diode (D1) is connected to the connection point of the first switch (Q1) and the second switch (Q2). The anode of the second diode (D2) is connected to the cathode of the first diode (D1). The cathode of the second diode (D2) is connected to the connection point of the load gap (V). o The third voltage regulator capacitor (C) is connected to the connection point of the second capacitor (C2) and the third voltage regulator capacitor (C) o The cathode of the third diode (D3) and the load gap (V) o The connection point is connected to the third voltage regulator capacitor (C). o The anode and load gap (V) o It is connected to the connection point of the second capacitor (C2).

2. The electrical discharge machining pulse power supply based on a three-level Cuk circuit according to claim 1, characterized in that, The switching transistor is a metal-oxide-semiconductor field-effect transistor made of silicon carbide, or a metal-oxide-semiconductor field-effect transistor made of silicon and gallium nitride.

3. The electrical discharge machining pulse power supply based on a three-level Cuk circuit according to claim 2, characterized in that, The semiconductor field-effect transistor is a metal-oxide material made of silicon carbide or a metal-oxide material made of silicon and gallium nitride.

4. A pulse power supply method for electrical discharge machining based on a three-level Cuk circuit, applicable to the pulse power supply for electrical discharge machining based on a three-level Cuk circuit as described in claims 1-3, characterized in that, A single cycle of electrical discharge machining includes the following steps: Step S1: During the breakdown delay stage, the gap is not broken down, and the three-level Cuk circuit is in boost mode. Boost mode consists of four stages. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the on / off state of the first switch (Q1) and the second switch (Q2). In the first stage, the first switch (Q1) is turned on and the second switch (Q2) is turned off. At this time, the DC voltage source (V... in The first inductor (L1) and the second capacitor (C2) form a circuit to charge the second capacitor (C2). The first capacitor (C1), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the second capacitor (C2). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a higher forward voltage; in the second stage, the first switch (Q1) and the second switch (Q2) are turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The circuit consists of a first inductor (L1), a second capacitor (C2), a second inductor (L2), a third diode (D3), and a third voltage-regulating capacitor (C). o ), load gap (V) o A power circuit is formed, with the first capacitor (C1) and the second capacitor (C2) simultaneously supplying power to the load gap (V). o The system provides a higher forward voltage; in the third stage, the first switch (Q1) is turned off and the second switch (Q2) is turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The first inductor (L1) and the first capacitor (C1) form a circuit to charge the first capacitor (C1). The second capacitor (C2), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the first capacitor (C1). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a higher forward voltage; in the fourth stage, the first switch (Q1) and the second switch (Q2) are turned on, at which time the DC voltage source (V) provides a higher forward voltage. in The circuit consists of a first inductor (L1), a second capacitor (C2), a second inductor (L2), a third diode (D3), and a third voltage-regulating capacitor (C). o ), load gap (V) o A power circuit is formed, with the first capacitor (C1) and the second capacitor (C2) simultaneously supplying power to the load gap (V). o Provide a higher forward voltage; repeat the above four stages and wait for the gap to break down; Step S2: After the gap is broken down, the discharge machining stage begins. The three-level Cuk circuit is in buck mode, which is divided into four stages. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the on / off state of the first switch (Q1) and the second switch (Q2). In the first stage, the first switch (Q1) is turned on and the second switch (Q2) is turned off. At this time, the DC voltage source (V in The first inductor (L1) and the second capacitor (C2) form a circuit to charge the second capacitor (C2). The first capacitor (C1), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the second capacitor (C2). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The first switch (Q1) and the second switch (Q2) are turned off, providing a lower forward voltage. In the second stage, the DC voltage source (V) is then switched off. in The first inductor (L1), the first capacitor (C1), and the second capacitor (C2) form a circuit to charge the first capacitor (C1) and the second capacitor (C2). The third voltage regulator capacitor (C) o ), second inductor (L2), third diode (D3), load gap (V) o ) forms the power circuit, and the third voltage regulator capacitor (C) o ), the second inductor (L2) to the load gap (V o The system provides a lower forward voltage; in the third stage, the first switch (Q1) is turned off and the second switch (Q2) is turned on, at which time the DC voltage source (V) provides a lower forward voltage. in The first inductor (L1) and the first capacitor (C1) form a circuit to charge the first capacitor (C1). The second capacitor (C2), the second inductor (L2), the third diode (D3), and the third voltage regulator capacitor (C) form a circuit to charge the first capacitor (C1). o ), load gap (V) o ) forms a power circuit, supplying power to the load gap (V o The system provides a lower forward voltage; in the fourth stage, the first switch (Q1) and the second switch (Q2) are turned off, at which time the DC voltage source (V) provides a lower forward voltage. in The first inductor (L1), the first capacitor (C1), and the second capacitor (C2) form a circuit to charge the first capacitor (C1) and the second capacitor (C2). The third voltage regulator capacitor (C) o ), second inductor (L2), third diode (D3), load gap (V) o ) forms the power circuit, and the third voltage regulator capacitor (C) o ), the second inductor (L2) to the load gap (V o Provide a lower forward voltage; repeat the above four stages to provide discharge energy to the gap; Step S3: After the discharge machining stage ends, the deionization stage begins. The FPGA control circuit generates a PWM signal, which, after passing through the drive circuit, controls the first switch (Q1) and the second switch (Q2) to be normally off to deionize and make the voltage across the gap zero. Step S4: Repeat steps S1 to S3 above to enter the next processing cycle.

Images