A connection device for chip testing

Abstract

This invention provides a connection device for chip testing, comprising: a chip and a connection component located above the chip. The device utilizes multiple conductive holes on the chip, with the connection component positioned above the corresponding conductive holes. When testing the chip, pressure is applied to the side of the connection component away from the chip, causing signal probes within the connection component to contact the chip surface and electrically connect with the multiple conductive holes. This allows high-speed signals from the chip to be routed to the side of the chip away from the packaging substrate and directly introduced into the connection component for testing, reducing performance interference caused by process and material properties.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal testing technology for chips, and more particularly to a connection device for chip testing. Background Technology

[0002] High-speed signal testing of chips should avoid signal performance deviations caused by factors other than the chip itself. A common technique is to use conductive bumps on the chip to guide the signal to the package substrate electrically connected to the chip, then guide the signal to the PCB (Printed Circuit Board) through a socket or solder balls, and finally connect it to an oscilloscope or VNA (Vector Network Analyzer) for testing via a connector.

[0003] Because the signal needs to pass through conductive bumps, packaging substrates, sockets and PCBs, as well as connectors and cables, to finally connect to the oscilloscope and VNA, the high-speed signal transmission path of the chip is too long, resulting in a lot of reflection and loss problems. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a connection device for chip testing, so as to reduce the interference and loss problems introduced by high-speed signal testing of chips.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] According to one aspect of the present invention, a connection device for chip testing is provided, comprising:

[0007] The chip has opposing first and second surfaces, and includes a plurality of conductive via units, each of the conductive via units including a plurality of conductive holes penetrating the first and second surfaces in the thickness direction. A plurality of first conductive bumps are provided on the second surface of the chip, and the chip is electrically connected to a packaging substrate through the plurality of first conductive bumps.

[0008] A connection component is located above the first surface of the chip. The connection component includes multiple test signal line groups corresponding to the multiple conductive hole units. Each test signal line group includes a signal probe, an elastic element, and multiple cables arranged in a stacked manner. The signal probe, the elastic element, and the multiple cables are electrically connected to each other.

[0009] When testing the chip, pressure is applied to the side surface of the connection assembly facing away from the chip, and the elastic element is compressed, causing the signal probe to extend from the side surface of the connection assembly close to the chip and abut against the first surface of the chip to electrically connect with the plurality of conductive holes in the chip.

[0010] Furthermore, the plurality of conductive holes are arranged coaxially.

[0011] Furthermore, at least one redistribution layer is disposed on the first surface of the chip, and the at least one redistribution layer is electrically connected to the corresponding plurality of conductive vias.

[0012] Furthermore, the signal probe is T-shaped overall, and the signal probe also includes a conductive part perpendicular to the main extension direction of the signal probe on the side near the elastic member. This conductive part is used for electrical connection with the elastic member.

[0013] Furthermore, in the main extension direction of the signal probe, each test signal line group also includes a grounding probe arranged around the signal probe; wherein, in the direction perpendicular to the main extension direction of the signal probe, there is a preset distance between the grounding probe and the signal probe.

[0014] Furthermore, in the radial direction from which the signal probe points to the ground probe, a first dielectric layer is filled between the ground probe and the signal probe, such that the first dielectric layer covers a portion of the signal probe in the main extension direction of the signal probe.

[0015] Furthermore, in the main extension direction of the signal probe, the end of the first dielectric layer near the elastic element is in direct contact with the elastic element.

[0016] Furthermore, in the main extension direction of the signal probe, there is a gap of a predetermined size between the end of the first dielectric layer away from the elastic element and the side surface of the connection assembly near the chip.

[0017] Furthermore, the multiple cables are arranged in a one-to-one correspondence with the multiple conductive holes, and the multiple cables are arranged coaxially.

[0018] Furthermore, each of the test signal line groups also includes a second dielectric layer covering the plurality of cables; in the main extension direction of the plurality of cables, the end of the second dielectric layer away from the elastic element is flush with the side surface of the connection component facing away from the chip, and the end of the second dielectric layer near the elastic element is in direct contact with the elastic element.

[0019] Furthermore, each of the test signal line groups also includes a third dielectric layer covering the elastic element; wherein the third dielectric layer is air.

[0020] Furthermore, it also includes a protective cover, in which the connecting component is embedded.

[0021] The present invention provides a connection device for chip testing, comprising: a chip and a connection component located above the chip. The device utilizes multiple conductive holes on the chip and a connection component positioned above the corresponding conductive holes. When testing the chip, pressure is applied to the side of the connection component away from the chip, causing signal probes within the connection component to contact the chip surface and electrically connect with the multiple conductive holes. This allows high-speed signals from the chip to be routed to the side of the chip away from the packaging substrate and directly introduced into the connection component for testing, reducing performance interference caused by process and material properties. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other implementation methods can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic cross-sectional view of a connection device for chip testing provided according to an embodiment of the present invention.

[0024] Figure 2 It is based on Figure 1 The diagram shows a partially enlarged structural schematic of the connection device used for chip testing.

[0025] Figure 3 It is based on Figure 1 The diagram shows the arrangement of multiple conductive holes within each conductive hole unit in the chip.

[0026] Figure 4 This is another cross-sectional structural schematic diagram of a connection device for chip testing provided according to an embodiment of the present invention. Detailed Implementation

[0027] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] To make the objectives, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] This invention provides a connection device for chip testing, which reduces interference introduced by high-speed signal testing of chips.

[0031] Figure 1 This is a schematic cross-sectional view of a connection device for chip testing provided according to an embodiment of the present invention. Figure 2 It is based on Figure 1 The diagram shows a partially enlarged structural schematic of the connection device used for chip testing.

[0032] like Figure 1 and Figure 2 As shown, the connection device for chip testing provided in this embodiment of the invention includes: a chip 102 and a connection component 500 located above the chip 102.

[0033] The chip 102 has a first surface 102a and a second surface 102b opposite to each other. The chip 102 includes a plurality of conductive hole units 110. Each conductive hole unit 110 includes a plurality of conductive holes 111 that penetrate the first surface 102a and the second surface 102b in the thickness direction. A plurality of first conductive bumps 103 are provided on the second surface 102b of the chip 102. The chip 102 is electrically connected to the packaging substrate 101 through the plurality of first conductive bumps 103.

[0034] The connection component 500 is located above the first surface 102a of the chip 102. The connection component 500 includes a plurality of test signal line groups 200 corresponding to the plurality of conductive hole units 110. Each test signal line group 200 includes a signal probe 201, an elastic element 206 and a plurality of cables 208 arranged in a stacked manner. The signal probe 201, the elastic element 206 and the plurality of cables 208 are electrically connected to each other.

[0035] When testing the chip 102, pressure is applied to the side surface of the connection component 500 away from the chip 102, and the elastic member 206 is compressed, so that the signal probe 201 extends out of the side surface of the connection component 500 close to the chip 102 and abuts against the first surface 102a of the chip 102 to electrically connect with the plurality of conductive holes 111 in the chip 102.

[0036] Specifically, in this embodiment of the invention, the chip 102 includes a plurality of conductive holes 111 penetrating its first surface 102a and second surface 102b. The plurality of conductive holes 111 are implemented using through silicon via (TSV) technology. The plurality of conductive holes 111 are filled with conductive material, which may be conductive materials such as copper, tungsten, or polycrystalline silicon.

[0037] In this embodiment of the invention, functional layers are formed on the second surface of the chip 102. The plurality of conductive vias 111 are electrically connected to the corresponding first pins / electrodes of the functional layers of the chip 102, thereby electrically connecting the corresponding first pins / electrodes of the functional layers to the connection component 500 to achieve high-speed signal testing. The function of the first conductive bump 103 is to electrically connect the corresponding second pins / electrodes of the functional layers of the chip 102 to the packaging substrate 101, realizing other functions of the chip 102, such as power supply, low-frequency signal testing, and control signal transmission. Exemplarily, the first conductive bump 103 is, for example, a solder pad (metal bump) or a solder ball.

[0038] It should be noted that, in commonly used technologies, TSV technology was invented to increase chip density and improve the computing power per unit area. However, in this embodiment of the invention, it is desirable to use TSV technology to lead high-speed signals from the chip to the side of the chip away from the packaging substrate and directly into the connector and cable for testing. This avoids the need for high-speed signals to pass through long wires via the packaging substrate, socket, and PCB board before connecting to the connector, reducing losses caused by long wires and minimizing performance interference caused by process and material properties.

[0039] The technical solution provided by the embodiments of the present invention aims to utilize multiple conductive holes on a chip and to place a connection component above the corresponding positions of the conductive holes on the chip. When testing the chip, pressure is applied to the side of the connection component away from the chip, causing the signal probe inside the connection component to contact the surface of the chip and electrically connect with the multiple conductive holes in the chip. This allows the high-speed signal on the chip to be led out to the side of the chip away from the packaging substrate and directly introduced into the connection component for testing, reducing performance interference problems caused by process and material properties.

[0040] Figure 3 It is based on Figure 1 The diagram shows the arrangement of multiple conductive holes within each conductive hole unit in the chip.

[0041] like Figure 3 As shown, the plurality of conductive holes 111 are arranged coaxially. This is because the coaxial arrangement of the plurality of conductive holes 111 results in low signal loss and good impedance matching.

[0042] Furthermore, in order to improve the power distribution network performance of chip 102, at least one redistribution layer (not shown) is provided on the first surface 102a of chip 102, and the at least one redistribution layer (not shown) is electrically connected to the corresponding plurality of conductive holes 111.

[0043] In some embodiments, the signal probe 201 is a probe for detecting high-speed signals. The signal probe 201 is T-shaped. The signal probe 201 also includes a conductive part 2011 on the side near the elastic member 206, which is perpendicular to the main extension direction of the signal probe 201. The conductive part 2011 is used to electrically connect with the elastic member 206.

[0044] Furthermore, in the main extension direction of the signal probe 201, each test signal line group 200 also includes a ground probe 202 arranged around the signal probe 201; wherein, in the direction perpendicular to the main extension direction of the signal probe 201, the ground probe 202 and the signal probe 201 have a predetermined spacing. For example, the ground probe 202 is annular and coaxially arranged with the signal probe 201.

[0045] Furthermore, in the radial direction from the signal probe 201 to the ground probe 202, a first dielectric layer 2051 is filled between the ground probe 202 and the signal probe 201, so that the first dielectric layer 2051 covers part of the signal probe 201 in the main extension direction of the signal probe 201.

[0046] Furthermore, in the main extension direction of the signal probe 201, one end of the first dielectric layer 2051 near the elastic member 206 is in direct contact with the elastic member 206.

[0047] Furthermore, in the main extension direction of the signal probe 201, there is a gap of a predetermined size between the end of the first dielectric layer 2051 away from the elastic member 206 and the side surface of the connection assembly 500 near the chip 102. This gap is typically filled with air to reduce parasitic capacitance.

[0048] Furthermore, the dielectric constant of the first dielectric layer 2051 is lower than a preset value. That is, the first dielectric layer 2051 is made of a material with a low dielectric constant. Generally, the lower the dielectric constant of a dielectric layer, the stronger its ability to store charge.

[0049] In some embodiments, since the multiple cables 208 correspond one-to-one with the multiple conductive holes 111, the multiple cables 208 are also arranged coaxially. Similarly, the coaxial arrangement can reduce signal loss and improve impedance matching.

[0050] Furthermore, each of the test signal line groups 200 also includes a second dielectric layer 2052 covering the plurality of cables 208; that is, the plurality of cables 208 are embedded in the second dielectric layer 2052.

[0051] Furthermore, the dielectric constant of the second dielectric layer 2052 is lower than a preset value. That is, the second dielectric layer 2052 is made of a material with a low dielectric constant. Generally, the lower the dielectric constant of a dielectric layer, the stronger its ability to store charge. Optionally, the second dielectric layer 2052 and the first dielectric layer 2051 are made of the same material with a low dielectric constant.

[0052] In the main extension direction of the multiple cables 208, the end of the second dielectric layer 2052 away from the elastic member 206 is flush with the side surface of the connection assembly 500 opposite to the chip 102, and the end of the second dielectric layer 2052 near the elastic member 206 is in direct contact with the elastic member 206.

[0053] In some embodiments, each of the test signal line groups 200 further includes a third dielectric layer 207 covering the elastic element 206; wherein the third dielectric layer 207 is air to reduce parasitic capacitance.

[0054] Figure 4 This is another cross-sectional structural schematic diagram of a connection device for chip testing provided according to an embodiment of the present invention.

[0055] like Figure 4 As shown, the connection device for chip testing provided in this embodiment of the invention further includes a protective cover 104 for fixing the connection component 500. Exemplarily, the connection component 500 is embedded in the protective cover 104. Specifically, the protective cover with the connection component 500 embedded can be placed above the chip 102 to be tested, so as to test the high-speed signal of the chip 102.

[0056] As can be seen from the above, the connection device for chip testing provided in this embodiment of the invention includes: a chip and a connection component located above the chip. It aims to utilize multiple conductive holes provided on the chip and to provide a connection component above the positions of the multiple conductive holes on the chip. When testing the chip, pressure is applied to the side of the connection component away from the chip, causing the signal probes inside the connection component to contact the surface of the chip and make electrical connections with the multiple conductive holes in the chip. This allows the high-speed signals on the chip to be led out to the side of the chip away from the packaging substrate and directly introduced into the connection component for testing, reducing performance interference problems caused by process and material properties.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A connection device for chip testing, characterized in that, include: The chip has opposing first and second surfaces, and includes a plurality of conductive via units, each of the conductive via units including a plurality of conductive holes penetrating the first and second surfaces in the thickness direction. A plurality of first conductive bumps are provided on the second surface of the chip, and the chip is electrically connected to a packaging substrate through the plurality of first conductive bumps. The conductive holes are implemented using through-silicon vias; A connection component is located above the first surface of the chip. The connection component includes multiple test signal line groups corresponding to the multiple conductive via units. Each test signal line group includes a signal probe, an elastic element, and multiple cables arranged in a stacked manner. The signal probe, the elastic element, and the multiple cables are electrically connected to each other. The multiple conductive vias are electrically connected to a first pin or a first electrode on the second surface, so that the first pin or the first electrode is electrically connected to the connection component. When testing the chip, pressure is applied to the side surface of the connection assembly facing away from the chip, and the elastic element is compressed, causing the signal probe to extend from the side surface of the connection assembly close to the chip and abut against the first surface of the chip to electrically connect with the plurality of conductive holes in the chip.

2. The connection device for chip testing as described in claim 1, characterized in that, The multiple conductive holes are arranged coaxially.

3. The connection device for chip testing as described in claim 2, characterized in that, At least one redistribution layer is disposed on the first surface of the chip, and the at least one redistribution layer is electrically connected to the corresponding plurality of conductive vias.

4. The connection device for chip testing as described in claim 1, characterized in that, The signal probe is T-shaped, and on the side near the elastic member, there is a conductive part perpendicular to the main extension direction of the signal probe, which is used to electrically connect with the elastic member.

5. The connection device for chip testing as described in claim 4, characterized in that, In the main extension direction of the signal probe, each of the test signal line groups also includes a grounding probe arranged around the signal probe; Wherein, in the main extension direction perpendicular to the signal probe, there is a preset distance between the ground probe and the signal probe.

6. The connection device for chip testing as described in claim 5, characterized in that... In the radial direction from the signal probe to the ground probe, a first dielectric layer is filled between the ground probe and the signal probe, such that the first dielectric layer covers a portion of the signal probe in the main extension direction of the signal probe.

7. The connection device for chip testing as described in claim 6, characterized in that, In the main extension direction of the signal probe, the end of the first dielectric layer near the elastic element is in direct contact with the elastic element.

8. The connection device for chip testing as described in claim 7, characterized in that, In the main extension direction of the signal probe, there is a gap of a predetermined size between the end of the first dielectric layer away from the elastic member and the side surface of the connection assembly near the chip.

9. The connection device for chip testing as described in claim 1, characterized in that, The multiple cables are arranged in a one-to-one correspondence with the multiple conductive holes, and the multiple cables are arranged coaxially.

10. The connection device for chip testing as described in claim 1 or 9, characterized in that, Each of the test signal line groups also includes a second dielectric layer covering the plurality of cables; In the main extension direction of the multiple cables, the end of the second dielectric layer away from the elastic element is flush with the side surface of the connection assembly opposite to the chip, and the end of the second dielectric layer near the elastic element is in direct contact with the elastic element.

11. The connection device for chip testing as described in claim 1, characterized in that, Each of the test signal line groups further includes a third dielectric layer covering the elastic element; The third dielectric layer is air.

12. The connection device for chip testing as described in claim 1, characterized in that, It also includes a protective cover, in which the connecting component is embedded.

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