Voltage sampling device, method and system

Abstract

A voltage acquisition device, method and system, the device comprising a first sampling switch coupled between a first voltage bus and a sampling capacitor; a first clock generator configured to generate a first gate drive signal to feed a gate of the first sampling switch, the first clock generator comprising a first capacitively coupled clock shifter, a first reset circuit and a second reset circuit; a second sampling switch coupled between a second voltage bus and the sampling capacitor; and a second clock generator configured to generate a second gate drive signal to feed a gate of the second sampling switch, the second clock generator comprising a second capacitively coupled clock shifter, a third reset circuit and a fourth reset circuit.

Description

Technical Field

[0001] The present invention relates to an apparatus, method and system for measuring high-voltage side voltage, and in a particular embodiment, to an apparatus for accurately measuring the voltage of the upper battery of a plurality of batteries connected in series. Background Technology

[0002] With further technological advancements, various applications, such as electric vehicles, require power from multiple batteries connected in series. In electric vehicles, accurately monitoring the individual voltage of these batteries is crucial. Accurate monitoring of individual voltages facilitates effective control over the charging and discharging of the multiple batteries.

[0003] In some applications (e.g., multi-cell fuel gauge applications), the voltage of the battery under test (e.g., 5-10V for a two-cell battery system or 35-40V for an eight-cell battery system) is significantly higher than the supply voltage of the voltage measurement circuit (e.g., 3V). To protect the voltage measurement circuit from damage by the high voltage of the battery system, a voltage divider is used to ensure that the voltage fed into the voltage measurement circuit is lower than the supply voltage. For example, in an eight-cell battery system, the voltage range across the two electrodes of the top cell is 35V to 40V. The supply voltage of the voltage measurement circuit is approximately 3V. A voltage divider with a 20:1 ratio is used to convert the voltage under test from the high voltage range (e.g., 35V to 40V) to the low voltage range (e.g., 1.75V to 2V).

[0004] Voltage dividers result in additional power consumption. Furthermore, they can occupy a significant amount of silicon area. Additionally, they reduce the signal-to-noise ratio. More importantly, due to resistor mismatch, they introduce unwanted gain errors and / or offsets.

[0005] Another known method for measuring high-voltage signals is based on a voltage-to-current converter. The voltage-to-current converter is configured to convert the high-voltage side voltage into a current flowing through a small resistor. The voltage across the small resistor generates a voltage within the power supply range of the voltage measurement circuit.

[0006] The drawback of this solution is that the voltage-to-current converter requires a high-power supply (e.g., 40V) to handle the high-voltage input signal. This high-power supply can be implemented as a charge pump circuit. However, this solution may lead to the same problems as the voltage divider described above.

[0007] The existing high-voltage measurement methods described above have many drawbacks. A simple and accurate method for sampling the high-voltage side voltage in battery power systems is desired. This disclosure addresses this need. Summary of the Invention

[0008] These and other problems are generally solved or circumvented by preferred embodiments of the present disclosure, and generally achieve technical advantages, which provide means for accurately measuring the voltage of an upper battery in a battery power system having multiple batteries connected in series.

[0009] According to one embodiment, an apparatus is provided comprising: a first sampling switch coupled between a first voltage bus and a sampling capacitor; a first clock generator configured to generate a first gate drive signal fed into the gate of the first sampling switch, the first clock generator including a first capacitively coupled clock shifter, a first reset circuit, and a second reset circuit; a second sampling switch coupled between a second voltage bus and the sampling capacitor; and a second clock generator configured to generate a second gate drive signal fed into the gate of the second sampling switch, the second clock generator including a second capacitively coupled clock shifter, a third reset circuit, and a fourth reset circuit.

[0010] According to another embodiment, a method is provided, comprising: shifting the potential of a first clock signal to a first voltage range via a first capacitively coupled clock shifter, the first voltage range having an upper limit equal to a voltage on a first voltage bus; resetting the first capacitively coupled clock shifter such that its output voltage is equal to the voltage on the first voltage bus when the first clock signal stops via a first reset circuit and a second reset circuit; shifting the potential of a second clock signal to a second voltage range via a second capacitively coupled clock shifter, the second voltage range having a lower limit equal to a voltage on a second voltage bus; and resetting the second capacitively coupled clock shifter such that its output voltage is equal to the voltage on the second voltage bus when the second clock signal stops via a third reset circuit and a fourth reset circuit.

[0011] According to another embodiment, a system is provided, comprising: a plurality of batteries connected in series; a sampling circuit having two input terminals respectively coupled to the positive and negative terminals of one of the plurality of batteries, wherein the sampling circuit includes: a first sampling switch coupled between a first voltage bus and a sampling capacitor; a first clock generator configured to generate a first gate drive signal fed into the gate of the first sampling switch, the first clock generator including a first capacitively coupled clock shifter, a first reset circuit and a second reset circuit, the first capacitively coupled clock shifter being configured to shift the potential of the first clock signal to obtain the first gate drive signal; a second sampling switch coupled between a second voltage bus and the sampling capacitor; and a second clock generator configured to generate a second gate drive signal fed into the gate of the second sampling switch, the second clock generator including a second capacitively coupled clock shifter, a third reset circuit and a fourth reset circuit, the second capacitively coupled clock shifter being configured to shift the potential of the second clock signal to obtain the second gate drive signal; a common-mode reference voltage coupled to the output terminal of the sampling circuit via a first control switch; and a charging processing circuit coupled to the output terminal of the sampling circuit via a second control switch.

[0012] The features and technical advantages of this disclosure have been outlined quite extensively above to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure, which form the subject matter of the claims, will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure as set forth in the appended claims. Attached Figure Description

[0013] To gain a more complete understanding of this disclosure and its advantages, the following description is given in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 A block diagram of a high-voltage side voltage sampling system according to various embodiments of the present disclosure is shown;

[0015] Figure 2 Various embodiments according to this disclosure are shown. Figure 1 The diagram shows a high-voltage side voltage sampling system.

[0016] Figure 3 A schematic diagram of a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown;

[0017] Figure 4 A schematic diagram of a second capacitively coupled clock shifter according to various embodiments of the present disclosure is shown;

[0018] Figure 5 A first implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown;

[0019] Figure 6 Various embodiments of the present disclosure are shown. Figure 5 The various signals associated with the first capacitively coupled clock shifter are shown.

[0020] Figure 7 A first implementation of the reset circuit for a second capacitively coupled clock shifter according to various embodiments of the present disclosure is shown;

[0021] Figure 8 Various embodiments of the present disclosure are shown. Figure 7 The various signals associated with the second capacitively coupled clock shifter are shown;

[0022] Figure 9 A second implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown;

[0023] Figure 10 A third implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown;

[0024] Figure 11 A fourth implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown; and

[0025] Figure 12 Various embodiments of the present disclosure illustrate the generation of [something] for [something] Figure 1 The flowchart shows the method for the gate drive signal of the voltage sampling system.

[0026] Unless otherwise stated, corresponding numbers and symbols in the various figures generally refer to corresponding parts. These figures are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0027] The following discusses in detail the making and use of the present preferred embodiments. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0028] This disclosure will describe a preferred embodiment in a specific context, namely, an apparatus for accurately measuring the voltage of the upper battery in a battery power system having multiple batteries connected in series. However, this disclosure can also be applied to measuring various parameters in electronic systems. Various embodiments will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 A block diagram of a high-voltage side voltage sampling system according to various embodiments of the present disclosure is shown. Multiple batteries are connected in series between the voltage bus VB and ground. For simplicity, Figure 1 The image only shows the first battery B1, the second battery B2, the third battery B3, the fourth battery B4, and the fifth battery B5.

[0030] like Figure 1 As shown, the sampling circuit 100 has two input terminals, which are respectively coupled to the positive and negative terminals of the third battery B3 among a plurality of batteries. The sampling circuit 100 is used to measure the voltages (VIP and VIN) of the third battery B3.

[0031] In some embodiments, the sampling circuit 100 includes a first sampling switch and a second sampling switch. The first sampling switch is coupled between the positive terminal of B3 and the sampling capacitor. The second sampling switch is coupled between the negative terminal of B3 and the sampling capacitor. To control the on and off states of the first and second sampling switches, the sampling circuit 100 further includes a first clock generator and a second clock generator. The first clock generator is configured to generate a first gate drive signal, which is fed into the gate of the first sampling switch. The second clock generator is configured to generate a second gate drive signal, which is fed into the gate of the second sampling switch.

[0032] In some embodiments, the first clock generator includes a first capacitively coupled clock shifter configured to shift a first clock signal potential to obtain a first gate drive signal, a first reset circuit, and a second reset circuit. The detailed structure and operating principle of the first clock generator will be described below. Figure 3 Describe it.

[0033] In some embodiments, the second clock generator includes a second capacitively coupled clock shifter configured to shift a second clock signal potential to obtain a second gate drive signal, a third reset circuit, and a fourth reset circuit. The following will be combined with... Figure 4 Describe the detailed structure and working principle of the second clock generator.

[0034] like Figure 1As shown, the high-voltage side voltage sampling system further includes a common-mode reference voltage (VCM) and a charging processing circuit 120. The common-mode reference voltage (VCM) is coupled to the output of the sampling circuit 100 via a first control switch S1. Detailed connections between the common-mode reference voltage (VCM) and the sampling circuit 100 will be described below. Figure 2 The charging processing circuit 120 is coupled to the output of the sampling circuit 100 via a second control switch S2. The detailed structure of the charging processing circuit 120 will be described below. Figure 2 Describe it.

[0035] Figure 2 Various embodiments according to this disclosure are shown. Figure 1 The diagram shows a high-voltage side voltage sampling system. The sampling circuit 100 includes a first sampling switch Q1, a second sampling switch Q2, a sampling capacitor C1, a first clock generator 102, and a second clock generator 104. Figure 2 As shown, the first sampling switch Q1 is implemented as a p-type transistor, having a source coupled to the first voltage bus VIP, a body connected to the source, and a drain coupled to the sampling capacitor C1. The second sampling switch Q2 is implemented as an n-type transistor, having a source coupled to the second voltage bus VIN, a body connected to the source, and a drain coupled to the sampling capacitor C1. (Back to...) Figure 1 The first voltage bus VIP is coupled to the positive terminal of battery B3. The second voltage bus VIN is coupled to the negative terminal of battery B3.

[0036] like Figure 2 As shown, a first sampling switch Q1 is coupled between a first voltage bus VIP and a sampling capacitor C1. A first clock generator 102 is configured to generate a first gate drive signal CK1B_SHFT fed into the gate of the first sampling switch Q1. In some embodiments, the first clock generator 102 includes a first capacitively coupled clock shifter, a first reset circuit, and a second reset circuit. The first capacitively coupled clock shifter is configured to convert the first clock signal CK1 into the first gate drive signal CK1B_SHFT.

[0037] The second sampling switch Q2 is coupled between the second voltage bus VIN and the sampling capacitor C1. The second clock generator 104 is configured to generate a second gate drive signal CK2_SHFT fed into the gate of the second sampling switch Q2. The second clock generator 104 includes a second capacitively coupled clock shifter, a third reset circuit, and a fourth reset circuit. The second capacitively coupled clock shifter is configured to convert the second clock signal CK2 into the second gate drive signal CK2_SHFT.

[0038] like Figure 2As shown, the first sampling switch Q1 is a p-type switch (e.g., PMOS) coupled to the higher voltage terminal of B3. The second sampling switch Q2 is an n-type switch (e.g., NMOS) coupled to the lower voltage terminal of B3. The source and body of Q1 are connected to the first voltage bus VIP. The gate of Q1 moves near VIP. Once Q1 is turned on, the drain of Q1 is charged to VIP. Q1 floats near VIP so that Q1 can pass through and isolate VIP. Similarly, the source and body of Q2 are connected to the second voltage bus VIN. The gate of Q2 moves near VIN. Once Q2 is turned on, the drain of Q2 is charged to VIN. Q2 floats near VIN so that Q2 can pass through and isolate VIN. The maximum stress voltages (e.g., VGS, VGD, VGB, VDS, VDB, and VSB) on switches Q1 and Q2 are within the input differential voltage (i.e., VIP-VIN). In many applications, the input differential voltage is within a limited range (e.g., 0V-5V). Therefore, Q1 and Q2 can work reliably.

[0039] The common-mode reference voltage VCM is connected to the sampling capacitor C1 via the first control switch S1. The charging processing circuit 120 is connected to the sampling capacitor C1 via the second control switch S2. The first clock signal CK1 is fed into the gate of the first control switch S1. The second clock signal CK2 is fed into the gate of the second control switch S2.

[0040] The charging processing circuit 120 includes an amplifier A1, a capacitor C2, and a switch SW_RST. Capacitor C2 is connected between the first input and output of amplifier A1. Switch SW_RST is coupled between the first input and output of amplifier A1. The second input of amplifier A1 is configured to receive a common-mode reference voltage VCM.

[0041] It should be noted that, as shown by the dashed line connecting to switch SW_RST, SW_RST is an optional component. Depending on the application and design requirements, the charging processing circuit 120 can be configured as an amplifier or an integrator. It should be noted that... Figure 2 The example circuit shown can be configured in a fully differential manner as needed.

[0042] In some embodiments, clock signals CK1 and CK2 are two complementary signals. When CK1 is at a logic high level and CK2 is at a logic low level, the clock signal is in the CK1 phase. On the other hand, when CK2 is at a logic high level and CK1 is at a logic low level, the clock signal is in the CK2 phase.

[0043] In phase CK1, the voltage on the first voltage bus VIP is sampled on C1. In phase CK2, the charge on C1 is transferred to C2. The amount of charge transferred from C1 to C2 can be expressed by the following formula:

[0044] Q=(VIP-VIN)×C1 (1)

[0045] The change in the output voltage of amplifier A1 can be expressed by the following formula:

[0046] VOUT=(VIP-VIN)×C1 / C2 (2)

[0047] In formula (2), VIP is the voltage value on the first voltage bus. VIN is the voltage value on the second voltage bus. C1 is the capacitance value of sampling capacitor C1. C2 is the capacitance value of capacitor C2.

[0048] have Figure 2 An advantageous feature of the high-voltage side voltage sampling system shown is that it does not incur additional power consumption. Furthermore, the high-voltage side voltage sampling system does not introduce various errors, such as offset errors, nonlinearity errors, and gain errors.

[0049] Figure 3 A schematic diagram of a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. A first clock generator 102 includes a first capacitively coupled clock shifter, a first reset circuit 301, and a second reset circuit 302. The first capacitively coupled clock shifter includes a first p-type transistor P1, a first capacitor C11, a second p-type transistor P2, a second capacitor C12, and a first inverter INV1.

[0050] like Figure 3 As shown, the first p-type transistor P1 and the first capacitor C11 are connected in series between the first voltage bus VIP and the first signal bus. Figure 3 As shown, the first clock signal CK1 flows on the first signal bus. The second p-type transistor P2, the second capacitor C12, and the first inverter INV1 are connected in series between the first voltage bus VIP and the first signal bus. The common node of the first p-type transistor P1 and the first capacitor C11 is connected to the gate of the second p-type transistor P2. The common node of the second p-type transistor P2 and the second capacitor C12 is connected to the gate of the first p-type transistor P1. Figure 3 As shown, the output signal CK1B_SHFT of the first clock generator 102 is generated at the common node of the second p-type transistor P2 and the second capacitor C12.

[0051] The first reset circuit 301 is connected to the common node of the first p-type transistor P1 and the first capacitor C11. The second reset circuit 302 is connected to the common node of the second p-type transistor P2 and the second capacitor C12.

[0052] In operation, the first capacitively coupled clock shifter is configured to shift the first clock signal CK1 up to a voltage close to VIP. Specifically, this voltage (CK1B_SHFT) is in the range from VIP-VDD to VIP. VDD is a predetermined voltage (e.g., 3V) higher than the turn-on threshold voltage VGS of Q1. The first reset circuit 301 and the second reset circuit 302 are configured such that once the first clock signal CK1 stops switching, the voltages of CK1B_SHFT and CK1_SHFT are charged upwards to a voltage level equal to VIP. This control mechanism prevents the voltages of CK1B_SHFT and CK1_SHFT from being locked at a random point, such as the midpoint of VIP.

[0053] Figure 4 A schematic diagram of a second capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. The second clock generator 104 includes a second capacitively coupled clock shifter, a third reset circuit 401, and a fourth reset circuit 402. The second capacitively coupled clock shifter includes a first n-type transistor N1, a third capacitor C13, a second n-type transistor N2, a fourth capacitor C14, and a second inverter INV2.

[0054] like Figure 4 As shown, the first n-type transistor N1, the third capacitor C13, and the second inverter INV2 are connected in series between the second voltage bus VIN and the second signal bus. Figure 4 As shown, the second clock signal CK2 flows on the second signal bus. The second n-type transistor N2 and the fourth capacitor C14 are connected in series between the second voltage bus VIN and the second signal bus. The common node of the first n-type transistor N1 and the third capacitor C13 is connected to the gate of the second n-type transistor N2. The common node of the second n-type transistor N2 and the fourth capacitor C14 is connected to the gate of the first n-type transistor N1. Figure 4 As shown, the output signal CK2_SHFT of the second clock generator 104 is generated at the common node of the second n-type transistor N2 and the fourth capacitor C14.

[0055] The third reset circuit 401 is connected to the common node of the first n-type transistor N1 and the third capacitor C13. The fourth reset circuit 402 is connected to the common node of the second n-type transistor N2 and the fourth capacitor C14.

[0056] In operation, the second capacitively coupled clock shifter is configured to shift the second clock signal CK2 up to a voltage close to VIN. Specifically, this voltage (CK2_SHFT) is within the range of VIN to (VIN+VDD). VDD is a predetermined voltage (e.g., 3V) higher than the turn-on threshold voltage VGS of Q2. The third reset circuit 401 and the fourth reset circuit 402 are configured to discharge the voltages of CK2B_SHFT and CK2_SHFT down to a voltage level equal to VIN once the second clock signal CK2 stops switching. This control mechanism prevents the voltages of CK2B_SHFT and CK2_SHFT from being locked at a random point, such as the midpoint of VIN.

[0057] Figure 5 A first implementation of the reset circuit of a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. Figure 5 The schematic diagram shown is Figure 3 The schematic diagrams shown are similar, except that the first reset circuit 301 and the second reset circuit 302 are replaced by the first resistor R1 and the second resistor R2, respectively.

[0058] like Figure 5 As shown, the first resistor R1 is connected between the first voltage bus VIP and the common node of the first p-type transistor P1 and the first capacitor C11. The second resistor R2 is connected between the first voltage bus VIP and the common node of the second p-type transistor P2 and the second capacitor C12.

[0059] In operation, the first resistor R1 and the second resistor R2 are configured to reset the output of the first capacitively coupled clock shifter (e.g., CK1B_SHFT) so that after the first clock signal CK1 stops switching, the output voltage of the first capacitively coupled clock shifter is equal to the voltage on the first voltage bus VIP. Furthermore, the first resistor R1 and the second resistor R2 ensure that the output (CK1B_SHFT) remains in the off state after the first clock signal CK1 stops switching, so that the first sampling switch Q1 is turned off.

[0060] Figure 6 Various embodiments of the present disclosure are shown. Figure 5 The various signals associated with the first capacitively coupled clock shifter are shown. Figure 6 The horizontal axis represents the time interval. Figure 6 There are four lines. The first line represents the signal at the common node of P1 and C11 (CK1_SHFT). The second line represents the signal at the common node of P2 and C12 (CK1B_SHFT). The third line represents the output signal of the first inverter INV1 (CK1B). The fourth line represents the first clock signal (CK1).

[0061] Before t0, CK1_SHFT and CK1B_SHFT are reset to a voltage level equal to VIP (e.g., 40V). At t1, CK1 changes from a logic high state to a logic low state. In response to this change, CK1B changes from a logic low state to a logic high state. The voltages across capacitors C11 and C12 do not change instantaneously. Therefore, at t1, CK1B_SHFT jumps from low to high voltage. Figure 6 As shown, this voltage jump is approximately 3V. CK1_SHFT drops from a high voltage to a low voltage. Figure 6 As shown, the voltage drop of CK1_SHFT is approximately 3V. From t1 to t2, CK1_SHFT rises slightly because C11 is charged by VIP through R1.

[0062] At time t2, CK1 changes from a logic low state to a logic high state. In response to this change, CK1B changes from a logic high state to a logic low state. The voltage across capacitors C11 and C12 cannot change instantaneously. Therefore, at time t2, CK1B_SHFT drops from a high voltage to a low voltage. Figure 6 As shown, the voltage drop is approximately 3V. CK1_SHFT jumps from low voltage to high voltage. Figure 6 As shown, the voltage jump of CK1_SHFT is approximately 3V. From t2 to t3, CK1B_SHFT rises slightly because C12 is charged by VIP through R2.

[0063] At t3, the signal transition is similar to that at t1, so it will not be described in detail here. At t4, CK1 stops switching and remains at a logic low level. CK1B remains at a logic high level. From t4 to t5, CK1_SHFT is charged upwards to VIP through the first resistor R1.

[0064] Figure 7 A first implementation of the reset circuit for a second capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. Figure 7 The schematic diagram shown is Figure 4 The schematic diagrams shown are similar, except that the third reset circuit 401 and the fourth reset circuit 402 are replaced by the third resistor R3 and the fourth resistor R4, respectively.

[0065] like Figure 7 As shown, the third resistor R3 is connected between the second voltage bus VIN and the common node of the first n-type transistor N1 and the third capacitor C13. The fourth resistor R4 is connected between the second voltage bus VIN and the common node of the second n-type transistor N2 and the fourth capacitor C14.

[0066] In operation, the third resistor R3 and the fourth resistor R4 are configured to reset the output of the second capacitively coupled clock shifter (e.g., CK2_SHFT) so that after the second clock signal CK2 stops switching, the output voltage of the second capacitively coupled clock shifter is equal to the voltage on the second voltage bus VIN. Furthermore, the third resistor R3 and the fourth resistor R4 ensure that the output (CK2_SHFT) remains off after the second clock signal CK2 stops switching, so that the second sampling switch Q2 is turned off.

[0067] Figure 8 Various embodiments of the present disclosure are shown. Figure 7 The various signals associated with the second capacitively coupled clock shifter are shown. Figure 8 The horizontal axis represents the time interval. Figure 8 There are four lines. The first line represents the signal at the common node of N1 and C13 (CK2B_SHFT). The second line represents the signal at the common node of N2 and C14 (CK2_SHFT). The third line represents the output signal of the second inverter INV2 (CK2B). The fourth line represents the second clock signal (CK2).

[0068] Before t0, CK2_SHFT and CK2B_SHFT are reset to a voltage level equal to VIN (e.g., 35V). At t1, CK2 changes from a logic high state to a logic low state. In response to this change, CK2B changes from a logic low state to a logic high state. The voltage across capacitors C13 and C14 cannot change instantaneously. Therefore, at t1, CK2B_SHFT jumps from low to high voltage. Figure 8 As shown, this voltage jump is approximately 3V. CK2_SHFT drops from a high voltage to a low voltage. Figure 8 As shown, the voltage drop of CK2_SHFT is approximately 3V. From t1 to t2, CK2B_SHFT drops slightly due to C13 being discharged by VIN through R3.

[0069] At time t2, CK2 changes from a logic low state to a logic high state. In response to this change, CK2B changes from a logic high state to a logic low state. The voltage across capacitors C13 and C14 cannot change instantaneously. Therefore, at time t2, CK2B_SHFT drops from a high voltage to a low voltage. Figure 8 As shown, the voltage drop is approximately 3V. CK2_SHFT jumps from low voltage to high voltage. Figure 8 As shown, the voltage jump of CK2_SHFT is approximately 3V. From t2 to t3, CK2_SHFT drops slightly because C14 is discharged through R4 by VIN.

[0070] At t3, the signal transition is similar to that at t1, so it will not be described in detail here. At t4, CK2 stops switching and remains at a logic low level. CK2B remains at a logic high level. From t4 to t5, CK2B_SHFT discharges to VIN through the first resistor R3.

[0071] Figure 9 A second implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. The first reset circuit 301 includes a third p-type transistor P3, a fifth resistor R5, a first high-voltage n-type transistor NH1, a first current mirror transistor NM1, a second current mirror transistor NM2, and a first current source I1. It should be noted that the reset circuit for the second capacitively coupled clock shifter can be implemented in a similar manner.

[0072] like Figure 9 As shown, the third p-type transistor P3 is connected in parallel with the first p-type transistor P1. The fifth resistor R5, the first high-voltage n-type transistor HN1, and the first current mirror transistor NM1 are connected in series between the first voltage bus VIP and ground. The first current source I1 and the second current mirror transistor NM2 are connected in series between the bias voltage Vb and ground. The first current mirror transistor NM1 and the second current mirror transistor NM2 form the first current mirror.

[0073] The second reset circuit 302 includes a fourth p-type transistor P4, a sixth resistor R6, a second high-voltage n-type transistor HN2, a third current mirror transistor NM3, a fourth current mirror transistor NM4, and a second current source I2.

[0074] like Figure 9 As shown, the fourth p-type transistor P4 is connected in parallel with the second p-type transistor P2. The sixth resistor R6, the second high-voltage n-type transistor HN2, and the third current mirror transistor NM3 are connected in series between the first voltage bus VIP and ground. The second current source I2 and the fourth current mirror transistor NM4 are connected in series between the bias voltage Vb and ground. The third current mirror transistor NM3 and the fourth current mirror transistor NM4 form the second current mirror.

[0075] During operation, a reset (RST) pulse is fed into the gate of HN1. Current flows through the conducting HN1. This current creates a voltage drop across R5. The voltage drop across R5 turns on P3, resetting the output of the first capacitively coupled clock shifter to VIP. Similarly, a reset (RST) pulse is fed into the gate of HN2. Current flows through the conducting HN2. This current creates a voltage drop across R6. The voltage drop across R6 turns on P4, resetting the output (CK1B_SHFT) of the first capacitively coupled clock shifter to VIP.

[0076] Figure 10A third implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. The first reset circuit 301 includes a third p-type transistor and a first dynamic gate drive circuit 1002. (As...) Figure 10 As shown, the third p-type transistor P3 is connected in parallel with the first p-type transistor P1. A first dynamic gate drive circuit 1002 is configured to generate a first adjustable gate drive signal, which is fed into the gate of the third p-type transistor P3. In some embodiments, the first dynamic gate drive circuit 1002 is controlled to make the resistance value of the third p-type transistor P3 equal to a first predetermined resistance value. Through P3, once the first clock signal CK1 stops switching, the output (e.g., CK1_SHFT) is charged up to VIP.

[0077] The second reset circuit 302 includes a fourth p-type transistor P4 and a second dynamic gate drive circuit 1004. For example... Figure 10 As shown, the fourth p-type transistor P4 is connected in parallel with the second p-type transistor P2. The second dynamic gate drive circuit 1004 is configured to generate a second adjustable gate drive signal, which is fed into the gate of the fourth p-type transistor P4. The second dynamic gate drive circuit 1004 is controlled to make the resistance value of the fourth p-type transistor P4 equal to a second predetermined resistance value. Through P4, once the first clock signal CK1 stops switching, the output (e.g., CK1B_SHFT) is charged upwards to VIP. It should be noted that the reset circuit of the second capacitively coupled clock shifter can be similar to... Figure 10 This is achieved as shown.

[0078] Figure 11 A fourth implementation of the reset circuit for a first capacitively coupled clock shifter according to various embodiments of the present disclosure is shown. The first reset circuit 301 includes a first resistor R1, a third resistor R3, and a first switch S1. (As...) Figure 11 As shown, the first resistor R1 is connected in parallel with the first p-type transistor P1. The third resistor R3 and the first switch S1 are connected in series and further connected in parallel with the first resistor R1.

[0079] The second reset circuit 302 includes a second resistor R2, a fourth resistor R4, and a second switch S2. For example... Figure 11 As shown, the second resistor R2 is connected in parallel with the second p-type transistor P2. The fourth resistor R4 and the second switch S2 are connected in series and further connected in parallel with the second resistor R2.

[0080] In operation, when the first and second reset circuits are configured to reset the output of the first capacitively coupled clock shifter such that the output voltage of the first capacitively coupled clock shifter equals the voltage (VIP) on the first voltage bus, the first switch S1 and the second switch S2 are turned on. In some embodiments, the resistance of R3 is much smaller than that of R1. Once CK1 stops switching and R3 is connected in parallel with R1, R3 provides a fast reset response. On the other hand, once CK1 starts switching, R3 is not connected in parallel with R1, and the large resistance value of R1 helps to maintain the amplitude of the output clock. It should be noted that the reset circuit of the second capacitively coupled clock shifter can be configured similarly to... Figure 11 This is achieved as shown.

[0081] Figure 12 Various embodiments of the present disclosure illustrate the generation of [something] for [something] Figure 1 The flowchart shows the method for the gate drive signal of the voltage sampling system. Figure 12 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, Figure 12 The various steps shown can be added, removed, replaced, rearranged, and repeated.

[0082] Reference Figure 1 Multiple batteries are connected in series between VB and ground. The sampling circuit has two inputs coupled to the positive and negative terminals of one of the batteries (e.g., B5). Return to reference Figure 2 The sampling circuit includes a first sampling switch coupled between a first voltage bus and a sampling capacitor. A first clock generator is configured to generate a first gate drive signal, which is fed into the gate of the first sampling switch. (Back) Figure 3 The first clock generator includes a first capacitively coupled clock shifter configured to shift the potential of a first clock signal to obtain a first gate drive signal, a first reset circuit, and a second reset circuit. The sampling circuit also includes a second sampling switch coupled between a second voltage bus and a sampling capacitor. The second clock generator is configured to generate a second gate drive signal that is fed into the gate of the second sampling switch. (Back) Figure 4 The second clock generator includes a second capacitively coupled clock shifter configured to shift the potential of the second clock signal to obtain a second gate drive signal, a third reset circuit, and a fourth reset circuit.

[0083] In step 1202, the potential of the first clock signal is shifted to a first voltage range by a first capacitively coupled clock shifter, the upper limit of which is equal to the voltage on the first voltage bus.

[0084] In step 1204, the first capacitively coupled clock shifter is reset by the first reset circuit and the second reset circuit, so that once the first clock signal stops, the output voltage of the first capacitively coupled clock shifter is equal to the voltage on the first voltage bus.

[0085] In step 1206, the potential of the second clock signal is shifted to a second voltage range via a second capacitively coupled clock shifter, the lower limit of which is equal to the voltage on the second voltage bus.

[0086] In step 1208, the second capacitively coupled clock shifter is reset by the third and fourth reset circuits, so that once the second clock signal stops, the output voltage of the second capacitively coupled clock shifter is equal to the voltage on the second voltage bus.

[0087] Return to reference Figure 3 The first capacitor-coupled clock shifter includes a first p-type transistor and a first capacitor connected in series between a first voltage bus and a first signal bus, and a second p-type transistor, a second capacitor, and a first inverter connected in series between the first voltage bus and the first signal bus. The common node of the first p-type transistor and the first capacitor is connected to the gate of the second p-type transistor, and the common node of the second p-type transistor and the second capacitor is connected to the gate of the first p-type transistor.

[0088] Return to reference Figure 4 The second capacitor-coupled clock shifter includes a first n-type transistor, a third capacitor, and a second inverter connected in series between the second voltage bus and the second signal bus, as well as a second n-type transistor and a fourth capacitor connected in series between the second voltage bus and the second signal bus. The common node of the first n-type transistor and the third capacitor is connected to the gate of the second n-type transistor, and the common node of the second n-type transistor and the fourth capacitor is connected to the gate of the first n-type transistor.

[0089] The method further includes configuring a first reset circuit and a second reset circuit to reset the output of a first capacitively coupled clock shifter such that the output voltage of the first capacitively coupled clock shifter is equal to the voltage on a first voltage bus, wherein the first reset circuit includes a first resistor connected in parallel with a first p-type transistor, and the second reset circuit includes a second resistor connected in parallel with a second p-type transistor; and configuring a third reset circuit and a fourth reset circuit to reset the output of a second capacitively coupled clock shifter such that the output voltage of the second capacitively coupled clock shifter is equal to the voltage on a second voltage bus, wherein the third reset circuit includes a third resistor connected in parallel with a first n-type transistor, and the fourth reset circuit includes a fourth resistor connected in parallel with a second n-type transistor.

[0090] The method further includes configuring a first reset circuit and a second reset circuit to reset the output of the first capacitively coupled clock shifter such that the output voltage of the first capacitively coupled clock shifter is equal to the voltage on the first voltage bus. It should be noted that the third and fourth reset circuits can be configured in a similar manner.

[0091] Return to reference Figure 9 The first reset circuit includes a third p-type transistor connected in parallel with the first p-type transistor, a fifth resistor connected in series between the first voltage bus and ground, a first high-voltage n-type transistor and a first current mirror transistor, and a first current source and a second current mirror transistor connected in series between the bias voltage and ground, wherein the first current mirror transistor and the second current mirror transistor form the first current mirror.

[0092] Return to reference Figure 9 The second reset circuit includes a fourth p-type transistor connected in parallel with the second p-type transistor, a sixth resistor connected in series between the first voltage bus and ground, a second high-voltage n-type transistor and a third current mirror transistor, and a second current source and a fourth current mirror transistor connected in series between the bias voltage and ground, wherein the third current mirror transistor and the fourth current mirror transistor constitute the second current mirror.

[0093] The method further includes dynamically adjusting a first gate drive signal fed into the gate of a third p-type transistor connected in parallel with the first p-type transistor, wherein, as a result of dynamically adjusting the first gate drive signal, the resistance value of the third p-type transistor is equal to a first predetermined resistance value; and dynamically adjusting a second gate drive signal fed into the gate of a fourth p-type transistor connected in parallel with the second p-type transistor, wherein, as a result of dynamically adjusting the second gate drive signal, the resistance value of the fourth p-type transistor is equal to a second predetermined resistance value. It should be noted that the third reset circuit and the fourth reset circuit can be configured in a similar manner.

[0094] The method further includes configuring a first reset circuit and a second reset circuit to reset the output of the first capacitively coupled clock shifter such that the output voltage of the first capacitively coupled clock shifter is equal to the voltage on the first voltage bus. It should be noted that the third and fourth reset circuits can be configured in a similar manner.

[0095] Return to reference Figure 11The first reset circuit includes a first resistor connected in parallel with the first p-type transistor, a third resistor connected in series and further connected in parallel with the first resistor, and a first switch. The second reset circuit includes a second resistor connected in parallel with the second p-type transistor, a fourth resistor connected in series and further connected in parallel with the second resistor, and a second switch. When the first and second reset circuits are configured to reset the output of the first capacitively coupled clock shifter, the first and second switches are turned on.

[0096] The method further includes shifting the potential of a first clock signal to obtain a first gate drive signal fed into a first sampling switch coupled between a first voltage bus and a sampling capacitor, and shifting the potential of a second clock signal to obtain a second gate drive signal fed into a second sampling switch coupled between a second voltage bus and a sampling capacitor. The voltage of the first voltage bus is higher than the voltage of the second voltage bus. The first sampling switch is a p-type transistor having a source coupled to the first voltage bus, a body connected to the source, and a drain coupled to the sampling capacitor. The second sampling switch is an n-type transistor having a source coupled to the second voltage bus, a body connected to the source, and a drain coupled to the sampling capacitor.

[0097] Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0098] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, apparatuses, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the disclosure of this publication, processes, machines, manufactures, compositions of matter, means, methods, or steps that perform substantially the same function, currently exist or will be developed or implemented thereafter, will yield substantially the same results as the corresponding embodiments described herein that are available according to this disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps within their scope.

Claims

1. An apparatus for voltage sampling, comprising: a first sampling switch coupled between a first voltage bus and a sampling capacitor; a first clock generator configured to generate a first gate drive signal that feeds a gate of the first sampling switch, the first clock generator including a first capacitively coupled clock shifter, a first reset circuit, and a second reset circuit, wherein the first and second reset circuits are configured to reset an output of the first capacitively coupled clock shifter such that the output of the first capacitively coupled clock shifter equals a voltage on the first voltage bus when a first clock signal stops switching; a second sampling switch coupled between a second voltage bus and the sampling capacitor; and a second clock generator configured to generate a second gate drive signal that feeds a gate of the second sampling switch, the second clock generator including a second capacitively coupled clock shifter, a third reset circuit, and a fourth reset circuit, wherein the third and fourth reset circuits are configured to reset an output of the second capacitively coupled clock shifter such that the output voltage of the second capacitively coupled clock shifter equals a voltage on the second voltage bus when a second clock signal stops switching.

2. The apparatus of claim 1, wherein the first voltage bus is connected to a positive terminal of a cell of a plurality of series connected cells; and the second voltage bus is connected to a negative terminal of the cell of the plurality of series connected cells.

3. The apparatus of claim 1, wherein the first sampling switch is a p-type transistor having a source coupled to the first voltage bus, a body connected to the source, and a drain coupled to the sampling capacitor; and the second sampling switch is an n-type transistor having a source coupled to the second voltage bus, a body connected to the source, and a drain coupled to the sampling capacitor.

4. The apparatus of claim 1, wherein the first capacitively coupled clock shifter includes: a first p-type transistor and a first capacitor connected in series between the first voltage bus and a first signal bus; and a second p-type transistor, a second capacitor, and a first inverter connected in series between the first voltage bus and the first signal bus, and wherein a common node of the first p-type transistor and the first capacitor is connected to a gate of the second p-type transistor, and a common node of the second p-type transistor and the second capacitor is connected to a gate of the first p-type transistor; and the second capacitively coupled clock shifter includes: a first n-type transistor, a third capacitor, and a second inverter connected in series between the second voltage bus and a second signal bus; and a second n-type transistor and a fourth capacitor connected in series between the second voltage bus and the second signal bus, and wherein a common node of the first n-type transistor and the third capacitor is connected to a gate of the second n-type transistor, and a common node of the second n-type transistor and the fourth capacitor is connected to a gate of the first n-type transistor. ​ ​ 5. The apparatus of claim 4, further comprising a first resistance connected between the first voltage bus and the common node of the first p-type transistor and the first capacitor; and a second resistance connected between the first voltage bus and the common node of the second p-type transistor and the second capacitor, wherein the first and second resistances are used as the first and second reset circuits, respectively.

6. The apparatus of claim 4, further comprising: a third resistance connected between the second voltage bus and the common node of the first n-type transistor and the third capacitor; and a fourth resistance connected between the second voltage bus and the common node of the second n-type transistor and the fourth capacitor, wherein the third and fourth resistances are used as the third and fourth reset circuits, respectively.

7. The apparatus of claim 4, wherein, the first reset circuit comprises: a third p-type transistor connected in parallel with the first p-type transistor; a fifth resistance, a first high-voltage n-type transistor, and a first current mirror transistor connected in series between the first voltage bus and ground, and wherein a common node of the fifth resistance and the first high-voltage n-type transistor is connected to a gate of the third p-type transistor; and a first current source and a second current mirror transistor connected in series between a bias voltage and ground, and wherein the first and second current mirror transistors form a first current mirror; and the second reset circuit comprises: a fourth p-type transistor connected in parallel with the second p-type transistor; a sixth resistance, a second high-voltage n-type transistor, and a third current mirror transistor connected in series between the first voltage bus and ground, and wherein a common node of the sixth resistance and the second high-voltage n-type transistor is connected to a gate of the fourth p-type transistor; and a second current source and a fourth current mirror transistor connected in series between the bias voltage and ground, and wherein the third and fourth current mirror transistors form a second current mirror.

8. The apparatus of claim 4, wherein, the first reset circuit comprises: a third p-type transistor connected in parallel with the first p-type transistor; and a first dynamic gate drive circuit configured to generate a first adjustable gate drive signal fed to a gate of the third p-type transistor, and wherein the first dynamic gate drive circuit is controlled such that a resistance value of the third p-type transistor is equal to a first predetermined resistance value; and the second reset circuit comprises: a fourth p-type transistor connected in parallel with the second p-type transistor; and a second dynamic gate drive circuit configured to generate a second adjustable gate drive signal fed to a gate of the fourth p-type transistor, and wherein the second dynamic gate drive circuit is controlled such that a resistance value of the fourth p-type transistor is equal to a second predetermined resistance value.

9. The apparatus of claim 4, wherein, the first reset circuit comprises: ​ a first resistor connected in parallel with the first p-type transistor; and a third resistor and a first switch connected in series and further connected in parallel with the first resistor; and the second reset circuit comprises: a second resistor connected in parallel with the second p-type transistor; and a fourth resistor and a second switch connected in series and further connected in parallel with the second resistor, and wherein the first switch and the second switch are turned on when the first reset circuit and the second reset circuit are configured to reset the output of the first capacitively coupled clock shifter such that the output voltage of the first capacitively coupled clock shifter is equal to the voltage on the first voltage bus.

10. A method of voltage sampling, comprising: shifting, by a first capacitively coupled clock shifter, a potential of a first clock signal to a first voltage range having an upper limit value equal to a voltage on a first voltage bus; resetting, by a first reset circuit and a second reset circuit, the first capacitively coupled clock shifter when the first clock signal stops such that an output voltage of the first capacitively coupled clock shifter is equal to the voltage on the first voltage bus; shifting, by a second capacitively coupled clock shifter, a potential of a second clock signal to a second voltage range having a lower limit value equal to a voltage on a second voltage bus; and resetting, by a third reset circuit and a fourth reset circuit, the second capacitively coupled clock shifter when the second clock signal stops such that an output voltage of the second capacitively coupled clock shifter is equal to the voltage on the second voltage bus.

11. The method of claim 10, wherein: the first capacitively coupled clock shifter comprises: a first p-type transistor and a first capacitor connected in series between the first voltage bus and a first signal bus; and a second p-type transistor, a second capacitor, and a first inverter connected in series between the first voltage bus and the first signal bus, and wherein a common node of the first p-type transistor and the first capacitor is connected to a gate of the second p-type transistor, and a common node of the second p-type transistor and the second capacitor is connected to a gate of the first p-type transistor; and the second capacitively coupled clock shifter comprises: a first n-type transistor, a third capacitor, and a second inverter connected in series between the second voltage bus and a second signal bus; and a second n-type transistor and a fourth capacitor connected in series between the second voltage bus and the second signal bus, and wherein a common node of the first n-type transistor and the third capacitor is connected to a gate of the second n-type transistor, and a common node of the second n-type transistor and the fourth capacitor is connected to a gate of the first n-type transistor.

12. The method of claim 11, further comprising: configuring a first reset circuit and a second reset circuit to reset an output of the first capacitively coupled clock shifter such that an output voltage of the first capacitively coupled clock shifter is equal to a voltage on the first voltage bus, wherein the first reset circuit includes a first resistor connected in parallel with the first p-type transistor and the second reset circuit includes a second resistor connected in parallel with the second p-type transistor; and configuring a third reset circuit and a fourth reset circuit to reset an output of the second capacitively coupled clock shifter such that an output voltage of the second capacitively coupled clock shifter is equal to a voltage on the second voltage bus, wherein the third reset circuit includes a third resistor connected in parallel with the first n-type transistor and the fourth reset circuit includes a fourth resistor connected in parallel with the second n-type transistor.

13. The method of claim 11, further comprising: configuring a first reset circuit and a second reset circuit to reset an output of the first capacitively coupled clock shifter such that an output voltage of the first capacitively coupled clock shifter is equal to a voltage on the first voltage bus, wherein: the first reset circuit includes: a third p-type transistor connected in parallel with the first p-type transistor; a fifth resistor, a first high voltage n-type transistor, and a first current mirror transistor connected in series between the first voltage bus and ground; and a first current source and a second current mirror transistor connected in series between a bias voltage and ground, and wherein the first current mirror transistor and the second current mirror transistor form a first current mirror; and the second reset circuit includes: a fourth p-type transistor connected in parallel with the second p-type transistor; a sixth resistor, a second high voltage n-type transistor, and a third current mirror transistor connected in series between the first voltage bus and ground; and a second current source and a fourth current mirror transistor connected in series between the bias voltage and ground, and wherein the third current mirror transistor and the fourth current mirror transistor form a second current mirror.

14. The method of claim 11, further comprising: dynamically adjusting a first gate drive signal fed to a gate of a third p-type transistor connected in parallel with the first p-type transistor, wherein a resistance value of the third p-type transistor is equal to a first predetermined resistance value as a result of dynamically adjusting the first gate drive signal; and dynamically adjusting a second gate drive signal fed to a gate of a fourth p-type transistor connected in parallel with the second p-type transistor, wherein a resistance value of the fourth p-type transistor is equal to a second predetermined resistance value as a result of dynamically adjusting the second gate drive signal.

15. The method of claim 11, further comprising: configuring a first reset circuit and a second reset circuit to reset an output of the first capacitively coupled clock shifter such that an output voltage of the first capacitively coupled clock shifter is equal to a voltage on the first voltage bus, wherein: the first reset circuit includes: a third p-type transistor connected in parallel with the first p-type transistor; a fifth resistor, a first high voltage n-type transistor, and a first current mirror transistor connected in series between the first voltage bus and ground; and a first current source and a second current mirror transistor connected in series between a bias voltage and ground, and wherein the first current mirror transistor and the second current mirror transistor form a first current mirror; and the second reset circuit includes: a fourth p-type transistor connected in parallel with the second p-type transistor; a sixth resistor, a second high voltage n-type transistor, and a third current mirror transistor connected in series between the first voltage bus and ground; and a second current source and a fourth current mirror transistor connected in series between the bias voltage and ground, and wherein the third current mirror transistor and the fourth current mirror transistor form a second current mirror. a first resistor connected in parallel with the first p-type transistor; and a third resistor and a first switch connected in series and further connected in parallel with the first resistor; and the second reset circuit comprises: a second resistor connected in parallel with the second p-type transistor; and a fourth resistor and a second switch connected in series and further connected in parallel with the second resistor, and wherein the first switch and the second switch are turned on when the first reset circuit and the second reset circuit are configured to reset the output of the first capacitively coupled clock shifter.

16. The method of claim 11, further comprising: shifting a potential of the first clock signal to obtain a first gate drive signal that feeds a first sampling switch, the first sampling switch being coupled between the first voltage bus and a sampling capacitor; and shifting a potential of the second clock signal to obtain a second gate drive signal that feeds a second sampling switch, the second sampling switch being coupled between the second voltage bus and the sampling capacitor.

17. The method of claim 16, wherein: the voltage of the first voltage bus is higher than the voltage of the second voltage bus; the first sampling switch is a p-type transistor having a source coupled to the first voltage bus, a body connected to the source, and a drain coupled to the sampling capacitor; and the second sampling switch is an n-type transistor having a source coupled to the second voltage bus, a body connected to the source, and a drain coupled to the sampling capacitor.

18. A system for voltage sampling, comprising: a plurality of series-connected batteries; a sampling circuit having two inputs coupled to a positive terminal and a negative terminal, respectively, of one of the plurality of batteries, wherein the sampling circuit comprises: a first sampling switch coupled between a first voltage bus and a sampling capacitor; a first clock generator configured to generate a first gate drive signal that feeds a gate of the first sampling switch, the first clock generator comprising a first capacitively coupled clock shifter configured to shift a potential of a first clock signal to obtain the first gate drive signal, a first reset circuit, and a second reset circuit, the first reset circuit and the second reset circuit being configured to reset an output of the first capacitively coupled clock shifter such that the output of the first capacitively coupled clock shifter is equal to a voltage on the first voltage bus when the first clock signal stops switching; a second sampling switch coupled between a second voltage bus and the sampling capacitor; and a second clock generator configured to generate a second gate drive signal that feeds a gate of the second sampling switch, the second clock generator comprising a second capacitively coupled clock shifter configured to shift a potential of a second clock signal to obtain the second gate drive signal, a third reset circuit, and a fourth reset circuit, the third reset circuit and the fourth reset circuit being configured to reset an output of the second capacitively coupled clock shifter such that the output of the second capacitively coupled clock shifter is equal to a voltage on the second voltage bus when the second clock signal stops switching. ​ a second clock generator configured to generate a second gate drive signal to feed into a gate of the second sampling switch, the second clock generator comprising a second capacitively coupled clock shifter configured to shift a potential of a second clock signal to obtain the second gate drive signal, and a third reset circuit and a fourth reset circuit configured to reset an output of the second capacitively coupled clock shifter such that the output voltage of the second capacitively coupled clock shifter is equal to a voltage on the second voltage bus when the second clock signal stops switching; a common mode reference voltage coupled to an output of the sampling circuit through a first control switch; and a charge handling circuit coupled to the output of the sampling circuit through a second control switch.

19. The system of claim 18, wherein the first capacitively coupled clock shifter comprises: a first p-type transistor and a first capacitor connected in series between the first voltage bus and a first signal bus, wherein the first clock signal flows on the first signal bus; and a second p-type transistor, a second capacitor, and a first inverter connected in series between the first voltage bus and the first signal bus, and wherein a common node of the first p-type transistor and the first capacitor is connected to a gate of the second p-type transistor, and a common node of the second p-type transistor and the second capacitor is connected to a gate of the first p-type transistor; the first reset circuit comprises a first resistor connected in parallel with the first p-type transistor; the second reset circuit comprises a second resistor connected in parallel with the second p-type transistor; and the second capacitively coupled clock shifter comprises: a first n-type transistor, a third capacitor, and a second inverter connected in series between the second voltage bus and a second signal bus, wherein the second clock signal flows on the second signal bus; and a second n-type transistor and a fourth capacitor connected in series between the second voltage bus and the second signal bus, and wherein a common node of the first n-type transistor and the third capacitor is connected to a gate of the second n-type transistor, and a common node of the second n-type transistor and the fourth capacitor is connected to a gate of the first n-type transistor; the third reset circuit comprises a third resistor connected in parallel with the first n-type transistor; the fourth reset circuit comprises a fourth resistor connected in parallel with the second n-type transistor.

20. The system of claim 19, wherein the first clock signal is fed into a gate of the first control switch; the second clock signal is fed into a gate of the second control switch; and the charge handling circuit comprises an amplifier, a capacitor, and a switch, wherein: the capacitor is connected between a first input of the amplifier and an output of the amplifier; the switch is coupled between the first input of the amplifier and the output of the amplifier; and a second input of the amplifier is configured to receive the common mode reference voltage. ​

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