Linear voltage regulator circuit

Abstract

The application discloses a linear voltage stabilizing circuit, comprising: a first transistor, a source of which receives a power supply voltage, and a drain of which outputs an output voltage of the linear voltage stabilizing circuit; a first resistor and a second resistor, which divide the output voltage to generate a feedback voltage; a differential amplification module, which outputs a driving signal to a gate of the first transistor according to the feedback voltage and a reference voltage; and a comparison module, which is used for generating a control current signal according to the output voltage to adjust the gate voltage of the first transistor, the comparison module samples the output voltage when the linear voltage stabilizing circuit is in static operation, and generates the control current signal proportional to the change amount of the output voltage when the output voltage changes. The application can realize adaptive control of the output voltage, the loop control speed is fast, meanwhile, the maximum change amplitude of the overshoot / negative overshoot of the output voltage does not change with the output voltage, and the suppression effect on the output overshoot / negative overshoot can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, in particular to a linear voltage stabilizing circuit. BACKGROUND

[0002] LDO (Low Dropout Regulator) uses a transistor or field effect transistor (FET) running in a linear region to subtract excess voltage from the input voltage to generate an adjusted output voltage. Due to its low cost, low noise and small static current, it is widely used in power supply circuits.

[0003] When the output load current changes rapidly, the LDO needs to make corresponding adjustments. Due to the slow adjustment of the LDO loop itself, a large overshoot / undershoot will appear in the output signal of the LDO, which requires the addition of a fast and effective adjustment circuit to reduce the amplitude of the output overshoot / undershoot. The existing solution is to set a comparison circuit in the LDO circuit, compare the feedback voltage of the LDO circuit with a fixed reference voltage, and generate a control signal to pull up or pull down the gate voltage of the output transistor according to the comparison result, so as to quickly suppress the output voltage overshoot / undershoot of the LDO circuit.

[0004] However, since the output voltage of the existing LDO circuit is variable, and the voltage value of the reference voltage in the LDO circuit compared with the feedback voltage is fixed, only the change amplitude of the feedback voltage can be used to represent the change amplitude of the output voltage, but this will cause the maximum overshoot / undershoot amplitude of the output voltage of the LDO circuit to be amplified accordingly, and will change with the output voltage Vout, affecting the suppression effect of the output voltage overshoot / undershoot. At the same time, the comparison speed of the existing LDO circuit for the feedback voltage and the reference voltage is slow, resulting in slow adjustment speed of the output voltage, and the logic level value of the control signal generated by the existing LDO circuit is fixed, which is easy to cause the phenomenon of excessive or insufficient adjustment of OUT.

[0005] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems in the prior art. SUMMARY

[0006] In order to solve the above technical problems, the present application provides a linear voltage stabilizing circuit, which can realize adaptive control of the output voltage by sampling the error current that changes in direct proportion to the overshoot / undershoot amplitude of the output voltage, and the loop control speed is fast. At the same time, sampling the output voltage of the circuit in the static working state as the reference voltage can make the maximum change amplitude of the output voltage overshoot / undershoot not change with the output voltage, and improve the suppression effect of the output overshoot / undershoot.

[0007] According to a first aspect of the present disclosure, a linear voltage stabilizing circuit is provided, comprising: a first transistor, a source of which receives a power supply voltage, and a drain of which outputs an output voltage of the linear voltage stabilizing circuit;

[0008] a first resistor and a second resistor, which are connected in series between the drain of the first transistor and a reference ground, and generate a feedback voltage by dividing the output voltage;

[0009] a differential amplification module, which receives the feedback voltage and a reference voltage, and outputs a driving signal to a gate of the first transistor;

[0010] a comparison module, which generates a control current signal according to the output voltage to adjust a gate voltage of the first transistor,

[0011] wherein the comparison module samples the output voltage when the linear voltage stabilizing circuit is in a static state, and generates the control current signal according to a variation of the output voltage when the output voltage changes.

[0012] Optionally, the control current signal is in proportional relationship with the variation of the output voltage.

[0013] Optionally, the comparison module comprises:

[0014] a sample-and-hold unit, which samples and holds the output voltage when the linear voltage stabilizing circuit is in the static state, and generates a first sample signal;

[0015] a buffer, which outputs the first sample signal with a gain;

[0016] a current sampling unit, which receives the output voltage and the first sample signal with the gain, and converts a voltage variation of the output voltage into a current when the output voltage changes, to generate a current sample signal;

[0017] a control current signal generation unit, which receives the current sample signal, and outputs the control current signal.

[0018] Optionally, the sample-and-hold unit comprises:

[0019] a third resistor, a first end of which receives the output voltage, and a second end of which outputs the first sample signal;

[0020] a first capacitor, a first end of which is connected to the second end of the third resistor, and a second end of which is connected to the reference ground.

[0021] Optionally, the current sampling unit comprises:

[0022] a second transistor, a source of which receives the output voltage, and a drain of which outputs the current sample signal.

[0023] a third transistor, a source of the third transistor receiving the first sampled signal with gain, a gate of the third transistor being connected with a gate of the second transistor and a drain of the third transistor simultaneously;

[0024] a first current source connected between the drain of the third transistor and a reference ground for providing a first reference current.

[0025] Optionally, the second transistor and the third transistor are both PMOS transistors.

[0026] Optionally, the second transistor and the third transistor both work in saturation region.

[0027] Optionally, the control current signal generating unit comprises:

[0028] a fourth transistor, a drain of the fourth transistor being connected with a gate of the fourth transistor and receiving the current sampled signal, a source of the fourth transistor being connected with a reference ground;

[0029] a fifth transistor, a gate of the fifth transistor being connected with the gate of the fourth transistor, a source of the fifth transistor being connected with the reference ground, a drain of the fifth transistor outputting the control current signal.

[0030] Optionally, the fourth transistor and the fifth transistor are both NMOS transistors.

[0031] Optionally, the current sampling unit comprises:

[0032] a sixth transistor, a source of the sixth transistor receiving the output voltage, a drain of the sixth transistor outputting the current sampled signal;

[0033] a seventh transistor, a source of the seventh transistor receiving the first sampled signal with gain, a gate of the seventh transistor being connected with a gate of the sixth transistor and a drain of the seventh transistor simultaneously;

[0034] a second current source connected between a power voltage input terminal and the drain of the seventh transistor for providing a second reference current.

[0035] Optionally, the sixth transistor and the seventh transistor are both NMOS transistors.

[0036] Optionally, the sixth transistor and the seventh transistor both work in saturation region.

[0037] Optionally, the control current signal generating unit comprises:

[0038] An eighth transistor, a drain of the eighth transistor being connected with a gate of the eighth transistor and receiving the current sampling signal, a source of the eighth transistor being connected with a power voltage input terminal;

[0039] A ninth transistor, a gate of the ninth transistor being connected with the gate of the eighth transistor, a source of the ninth transistor being connected with the power voltage input terminal, a drain of the ninth transistor outputting the control current signal.

[0040] Optionally, the eighth transistor and the ninth transistor are both PMOS transistors.

[0041] The present application has at least the following beneficial effects:

[0042] In the linear voltage stabilizing circuit of the present application, the comparison module generates the control current signal according to the variation of the output voltage to adjust the gate voltage of the first transistor, and in this process, since the current signal is directly sampled, the loop control speed is fast.

[0043] In a further preferred embodiment, the control current signal finally generated is in a positive proportional relationship with the amplitude of the overshoot / undershoot of the output voltage, i.e. the variation of the output voltage, and the adaptive control of the output voltage can be realized.

[0044] In a further preferred embodiment, the comparison module samples the output voltage of the circuit in the static working state as the reference voltage, so that the maximum variation amplitude of the overshoot / undershoot of the output voltage will not change with the output voltage, and the suppression effect of the output overshoot / undershoot is improved.

[0045] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 A structure schematic diagram of an existing low-dropout linear voltage stabilizing circuit is shown;

[0047] Figure 2 A structure schematic diagram of a comparison circuit is shown; Figure 1 A waveform variation schematic diagram of the output voltage and the load current in the overshoot / undershoot is shown;

[0048] Figure 3 A structure schematic diagram of a comparison circuit is shown; Figure 1 A structure schematic diagram of a comparison circuit is shown;

[0049] Figure 4 A structure schematic diagram of a linear voltage stabilizing circuit provided by the present application is shown;

[0050] Figure 5 A structure schematic diagram of a comparison module provided by the first embodiment of the present application is shown;

[0051] Figure 6 A schematic diagram of the structure of the comparison module provided according to the second embodiment of the present invention is shown. Detailed Implementation

[0052] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0053] Figure 1 This diagram illustrates the structure of an existing low-dropout linear regulator circuit (hereinafter referred to as a linear regulator circuit). Figure 1 As shown, the existing linear voltage regulator circuit includes a differential amplifier circuit 10, a transistor M1, and a resistor string consisting of resistors R1 and R2. One input terminal of the differential amplifier circuit 10 receives a reference voltage VREF0, and the other input terminal receives a feedback voltage VFB formed by dividing the output voltage Vout of the linear voltage regulator circuit by the resistor string. At this time, VFB = Vout * R2 / (R1 + R2). The differential amplifier circuit 10 outputs a drive signal for the transistor M1. The source of the transistor M1 receives the power supply voltage VCC, and the drain of the transistor M1 outputs the output voltage Vout of the linear voltage regulator circuit. This existing linear voltage regulator circuit also includes a comparator circuit 20. The comparator circuit 20 adjusts the drive signal of the transistor M1 by comparing the difference between the feedback voltage VFB and the reference voltage, thereby quickly adjusting the output. The reference voltages received by the comparator circuit 20 include a first reference voltage VREF1 and a second reference voltage VREF2, and the first reference voltage VREF1 is greater than the second reference voltage VREF2.

[0054] refer to Figure 2 When the output load ILoad suddenly increases, the output voltage Vout will be suddenly pulled down, and the feedback voltage VFB will also be pulled down accordingly. When the feedback voltage VFB is less than the second reference voltage VREF2, the comparator circuit 20 pulls down the drive signal to increase the charging speed of the output voltage Vout, thereby achieving the purpose of quickly suppressing the negative overshoot of the output voltage Vout. Similarly, when the output load ILoad suddenly decreases, the output voltage Vout will be suddenly pulled up, and the feedback voltage VFB will also be pulled up accordingly. When the feedback voltage VFB is greater than the first reference voltage VREF1, the comparator circuit 20 pulls up the drive signal to decrease the charging speed of the output voltage Vout, thereby achieving the purpose of quickly suppressing the overshoot of the output voltage Vout.

[0055] However, since the potential of the output voltage Vout of the linear voltage stabilizing circuit is variable, and the first reference voltage VREF1 and the second reference voltage VREF2 of the comparison circuit 20 are fixed, only the variation range ΔVFB of the feedback voltage VFB can be used to represent the variation range ΔVout of the output voltage Vout, i.e. ΔVFB = ΔVout*R2 / (R1+R2). Thus, the variation range of the output voltage Vout of the linear voltage stabilizing circuit is attenuated by R1 / (R1+R2) times, resulting in that the maximum overshoot / negative overshoot range of the output voltage Vout controlled by the fixed first reference voltage VREF1 and the second reference voltage VREF2 is ΔVout_MAX = (VFB-VREF)(R1+R2) / R2, and the maximum overshoot / negative overshoot range is also amplified by k = (R1+R2) / R2 times, and the k corresponding to different output voltages Vout is different, resulting in that the maximum overshoot / negative overshoot range ΔVout_MAX is also variable, and the higher the potential configured by the output voltage Vout is, the larger the maximum overshoot / negative overshoot range ΔVout_MAX corresponding thereto is.

[0056] Meanwhile, the internal structure of the comparison circuit 20 in the existing linear voltage stabilizing circuit is as shown in Figure 3 The logic level of the control signal CTRL generated thereby is fixed, and there is no proportional relationship between the logic level and the maximum overshoot / negative overshoot range ΔVout_MAX of the output voltage Vout, which further results in that no matter how large the overshoot / negative overshoot range of the output voltage Vout is, the control signal CTRL will adjust the driving signal GATE of the transistor M1 with the same force, so that it is easy to appear the phenomenon of over-adjustment or under-adjustment of the output voltage Vout. Moreover, the comparison circuit 20 is a two-stage voltage comparator, and the adjustment speed is slow, especially under the condition of low power consumption.

[0057] In view of the above problems existing in the existing linear voltage stabilizing circuit, the present application discloses a new linear voltage stabilizing circuit.

[0058] As Figure 4As shown, the linear voltage stabilizing circuit provided by the embodiment of the present application comprises a first transistor M1, a first resistor R1, a second resistor R2, a differential amplification module 30 and a comparison module 40. The source of the first transistor M1 receives a power supply voltage VCC, and the drain of the first transistor M1 outputs an output voltage Vout of the linear voltage stabilizing circuit. The first resistor R1 and the second resistor R2 are connected in series between the drain of the first transistor M1 and a reference ground, and the first resistor R1 and the second resistor R2 constitute a resistor string for generating a feedback voltage VFB after dividing the output voltage Vout. The first input end of the differential amplification module 30 receives the feedback voltage VFB, the second input end of the differential amplification module 30 receives a reference voltage VREF, and the differential amplification module 30 is configured to output a driving signal to the gate of the first transistor M1 according to the feedback voltage VFB and the reference voltage VREF. The comparison module 40 receives the output voltage Vout and is configured to generate a control current signal I CTRL according to the output voltage Vout, so as to adjust the gate voltage of the first transistor M1, i.e., the voltage value of the driving signal output by the differential amplification module 30 to the gate of the first transistor M1.

[0059] In this embodiment, the comparison module 40 is configured to sample the output voltage Vout when the linear voltage stabilizing circuit is in a static state, and generate a control current signal I CTRL that is proportional to the variation ΔVout of the output voltage when the output voltage Vout changes. In this process, since the current signal is directly sampled, the loop control speed is fast. At the same time, based on the proportional relationship between the control current signal I CTRL and the variation ΔVout of the output voltage, i.e., the amplitude of the overshoot / undershoot of the output voltage, the present application can also realize adaptive control of the output voltage Vout.

[0060] Reference Figure 5 and Figure 6 , the comparison module 40 in the embodiment of the present application further comprises a sample-and-hold unit 41, a buffer 42, a current sampling unit 43 and a control current signal generation unit 44.

[0061] The sample-and-hold unit 41 is configured to sample and hold the output voltage Vout of the circuit when the linear voltage stabilizing circuit is in a static state, and generate a first sampling signal (denoted as Vout0).

[0062] Exemplarily, the sample-and-hold unit 41 further comprises a third resistor R3 and a first capacitor C1. A first end of the third resistor R3 receives the output voltage Vout, a second end of the third resistor R3 outputs a first sample signal Vout0, a first end of the first capacitor C1 is connected with the second end of the third resistor R3, and a second end of the first capacitor C1 is connected with a reference ground. In this embodiment, the third resistor R3 and the first capacitor C1 form an RC filter network to filter the output voltage Vout, and meanwhile, when the working state of the linear voltage stabilizing circuit changes from static to dynamic, i.e., the voltage value of the output voltage Vout changes, the voltage value of the output voltage Vout is kept unchanged for a certain time, achieving the purpose of sampling and holding.

[0063] The buffer 42 is connected with the sample-and-hold unit 41 and is configured to output the first sample signal Vout0 after unit gain. In this embodiment, the buffer 42 is a conventional buffer capable of achieving unit gain, and the first sample signal Vout0 can have a certain driving capability after passing through the buffer 42.

[0064] The current sampling unit 43 receives the output voltage Vout and the first sample signal Vout0 after gain, and is configured to convert the voltage change AVout of the output voltage Vout into a current when the output voltage Vout changes, to generate a current sampling signal.

[0065] The control current signal generating unit 44 is connected with the current sampling unit 43, receives the current sampling signal, and outputs a control current signal I CTRL .

[0066] In the first embodiment of the present application, as shown in Figure 5 , the current sampling unit 43 further comprises a second transistor M8, a third transistor M9 and a first current source I2. The source of the second transistor M8 receives the output voltage Vout, and the drain of the second transistor M8 outputs a current sampling signal (denoted as I3). The source of the third transistor M9 receives the first sample signal Vout0 after gain, and the gate of the third transistor M9 is connected with the gate of the second transistor M8 and the drain of the third transistor M9. The first current source I2 is connected between the drain of the third transistor M9 and the reference ground, and is configured to provide a first reference current (denoted as I2). Exemplarily, in this embodiment, the second transistor M8 and the third transistor M9 are both PMOS transistors, and both of them work in the saturation region.

[0067] , and in the first embodiment of the present application, as shown in Figure 5As shown, the control current signal generating unit 44 further comprises a fourth transistor M10 and a fifth transistor M11. The drain of the fourth transistor M10 is connected with the gate of the fourth transistor M10 and receives the current sampling signal I3, and the source of the fourth transistor M10 is connected with the reference ground. The gate of the fifth transistor M11 is connected with the gate of the fourth transistor M10, the source of the fifth transistor M11 is connected with the reference ground, and the drain of the fifth transistor M11 outputs the control current signal I CTRL In the embodiment, the fourth transistor M10 and the fifth transistor M11 are both NMOS transistors.

[0068] Reference Figure 5 The specific working principle of the comparison module 40 in the first embodiment of the present application is as follows:

[0069] When the linear voltage regulator works statically, the potential VA of the node A in the comparison module 40 (i.e. the potential of the first sampling signal Vout0) is the same as the potential of the output voltage Vout, and after the unit gain and buffering by the buffer 42, the potential VB of the node B in the comparison module 40 (i.e. the potential of the first sampling signal Vout0 after gain) is also the same as the potential of the output voltage Vout, i.e. VB = VA = Vout0. In the current sampling unit 43, since the second transistor M8 and the third transistor M9 are both in the saturation region, and the gate potential of the second transistor M8 is the same as the gate potential of the third transistor M9, and the source potential of the second transistor M8 is also the same as the source potential of the third transistor M9 (both are Vout0), and then the gate-source voltage Vgs_M8 of the second transistor M8 is equal to the gate-source voltage Vgs_M9 of the third transistor M9, so I3 = m1*I2 (m1 is the ratio of the width-length ratio of the second transistor M8 to the width-length ratio of the third transistor M9). In the control current signal generating unit 44, the fourth transistor M10 and the fifth transistor M11 constitute a current mirror structure, so the control current signal I CTRL of the linear voltage regulator at the static time is equal to m2*I3 (m2 is the current ratio between the two branches of the current mirror circuit in the embodiment). Wherein, m1 and m2 are both greater than 0.

[0070] When the linear voltage regulator circuit is operating dynamically, for example, if the output voltage Vout overshoots, causing a change of ΔVout in the output voltage Vout, the potentials of nodes A and B remain almost unchanged due to the RC filter network in the sample-and-hold unit 41, and VB = VA = Vout0. Simultaneously, since the first reference current I2 is constant and the size of the third transistor M9 is constant, the potential of node C remains unchanged at f(Vout0), independent of the change in output voltage Vout ΔVout. Furthermore, since the size of the second transistor M8 is constant and it operates in the saturation region, when the potential of node D (i.e., the output voltage Vout) is greater than the potential of node B (i.e., the potential of the first sampled signal Vout0 after gain), the change in drain current of the second transistor M8 (denoted as ΔI3) is equal to f(ΔVgs_M8) and also equal to f(ΔVout). Therefore, the change in the control current signal ultimately output by the current mirror (denoted as ΔI) is also equal to the change in the drain current signal. CTRL The result is equal to m2*ΔI3, which is equal to m2*f(ΔVout). In other words, in this embodiment of the invention, when the output voltage Vout changes, the control current signal I output by the comparison module 40... CTRL Ultimately, this will also generate a control current signal change ΔI that is proportional to the change in output voltage ΔVout. CTRL When the output voltage overshoot increases / decreases, the control current signal I... CTRL The adjustment of the gate voltage of the first transistor M1 will also increase / decrease accordingly, realizing adaptive overshoot adjustment of the output voltage Vout, effectively avoiding the phenomenon of over- or under-adjustment of the output voltage Vout. Here, f represents the conversion function between current and voltage in the transistor.

[0071] In the second embodiment of the present invention, as Figure 6 As shown, the current sampling unit 43 further includes a sixth transistor M12, a seventh transistor M13, and a second current source I4. The source of the sixth transistor M12 receives the output voltage Vout, and the drain of the sixth transistor M12 outputs a current sampling signal (denoted as I5). The source of the seventh transistor M13 receives the amplified first sampling signal Vout0, and the gate of the seventh transistor M13 is connected to both the gate of the sixth transistor M12 and the drain of the seventh transistor M13. The second current source I4 is connected between the power supply voltage VCC input terminal and the drain of the seventh transistor M13 to provide a second reference current (denoted as I4). Exemplarily, in this embodiment, both the sixth transistor M12 and the seventh transistor M13 are NMOS transistors, and both operate in the saturation region.

[0072] Furthermore, in the second embodiment of the present invention, as...Figure 6 As shown, the control current signal generating unit 44 further comprises an eighth transistor M14 and a ninth transistor M15. The drain of the eighth transistor M14 is connected with the gate of the eighth transistor M14 and receives the current sampling signal I5, and the source of the eighth transistor M14 is connected with the power voltage VCC input terminal. The gate of the ninth transistor M15 is connected with the gate of the eighth transistor M14, the source of the ninth transistor M15 is connected with the power voltage VCC input terminal, and the drain of the ninth transistor M15 outputs the control current signal I CTRL In the embodiment, the eighth transistor M14 and the ninth transistor M15 are both PMOS transistors.

[0073] Reference Figure 6 The specific working principle of the comparison module 40 in the second embodiment of the present application is as follows:

[0074] When the linear voltage stabilizing circuit is in static state, the potential VE of the node E in the comparison module 40 (i.e. the potential of the first sampling signal Vout0) is the same as the potential of the output voltage Vout, and after the unit gain and buffering by the buffer 42, the potential VF of the node F in the comparison module 40 (i.e. the potential of the first sampling signal Vout0 after gain) is also the same as the potential of the output voltage Vout, i.e. VF = VE = Vout0. In the current sampling unit 43, since the sixth transistor M12 and the seventh transistor M13 are both in the saturation region, and the gate potential of the sixth transistor M12 is the same as the gate potential of the seventh transistor M13, and the source potential of the sixth transistor M12 is also the same as the source potential of the seventh transistor M13 (both are Vout0), and further the gate-source voltage Vgs_M12 of the sixth transistor M12 is equal to the gate-source voltage Vgs_M13 of the seventh transistor M13, so I5 = m1*I4 (m1 is the ratio of the width-length ratio of the sixth transistor M13 to the width-length ratio of the seventh transistor M13). In the control current signal generating unit 44, the eighth transistor M14 and the ninth transistor M15 constitute a current mirror structure, so the control current signal I CTRL of the linear voltage stabilizing circuit in static state is equal to m2*I5 (m2 is the current ratio between the two branches of the current mirror circuit in the embodiment).

[0075] When the linear voltage regulator circuit is operating dynamically, for example, if the output voltage Vout experiences a negative impulse, causing a change of ΔVout in the output voltage Vout, the potentials of nodes E and F remain almost unchanged due to the RC filter network in the sample-and-hold unit 41, and VF = VE = Vout0 remains constant. Simultaneously, since the second reference current I4 is constant and the size of the seventh transistor M13 is constant, the potential of node G remains unchanged at f(Vout0), independent of the change in output voltage Vout ΔVout. Furthermore, since the size of the sixth transistor M12 is constant and it operates in the saturation region, when the potential of node H (i.e., the output voltage Vout) is greater than the potential of node F (i.e., the potential of the first sampled signal Vout0 after gain), the change in drain current of the sixth transistor M12 (denoted as ΔI5) is equal to f(ΔVgs_M12) and also equal to f(ΔVout). Therefore, the change in the control current signal ultimately output by the current mirror (denoted as ΔI) CTRL This is equal to m2*ΔI5, which is equal to m2*f(ΔVout). In other words, in this embodiment of the invention, when the output voltage Vout changes, the control current signal I output by the comparison module 40... CTRL Ultimately, this will also generate a control current signal change ΔI that is proportional to the change in output voltage ΔVout. CTRL When the amplitude of the output voltage negative impulse increases / decreases, the control current signal I... CTRL The adjustment of the gate voltage of the first transistor M1 will also be increased / decreased accordingly, realizing adaptive negative impulse adjustment of the output voltage Vout, effectively avoiding the phenomenon of over-adjustment or under-adjustment of the output voltage Vout.

[0076] It is understood that the control current signal I is generated in the above embodiments. CTRL During the process, the overshoot / undershoot amplitude of the output voltage Vout is compared with the signal Vout0 held when the circuit is in static operation, rather than with the attenuated feedback voltage as in the prior art. Therefore, the maximum overshoot / undershoot amplitude ΔVout_max of the output voltage Vout is equal to ΔVout and does not change with the output voltage. Thus, the present invention can achieve better overshoot / undershoot suppression.

[0077] In summary, in the linear voltage regulator circuit of this embodiment, the comparator module generates a control current signal based on the change in output voltage to regulate the gate voltage of the first transistor. In this process, since the current signal is directly sampled, the loop control speed is fast.

[0078] In a further preferred embodiment, the final generated control current signal is in direct proportion to the amplitude of the overshoot / undershoot of the output voltage, i.e. the variation of the output voltage, so that adaptive control of the output voltage can be achieved.

[0079] In a further preferred embodiment, the comparison module samples the output voltage of the circuit in the static working state as the reference voltage, so that the maximum variation amplitude of the overshoot / undershoot of the output voltage will not change with the output voltage, and the suppression effect of the output overshoot / undershoot is improved.

[0080] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the present application, and are not limitations on the embodiments. Based on the above description, other different forms of changes or variations can also be made by those of ordinary skill in the art. Here, it is not necessary and impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A linear voltage regulator circuit, wherein, The application relates to a linear voltage stabilizing circuit, comprising: a first transistor, the source of which receives a power supply voltage, and the drain of which outputs an output voltage of the linear voltage stabilizing circuit; a first resistor and a second resistor, which are connected in series between the drain of the first transistor and a reference ground, and generate a feedback voltage by dividing the output voltage; a differential amplification module, which receives the feedback voltage and a reference voltage, and outputs a driving signal to the gate of the first transistor; a comparison module, which generates a control current signal according to the output voltage to adjust the gate voltage of the first transistor, wherein the comparison module samples the output voltage when the linear voltage stabilizing circuit is in a static state, and generates the control current signal according to the variation of the output voltage when the output voltage changes; the comparison module comprises: a sample-and-hold unit, which samples and holds the output voltage when the linear voltage stabilizing circuit is in a static state, and generates a first sampling signal; a buffer, which outputs the first sampling signal with a gain; a current sampling unit, which receives the output voltage and the first sampling signal with the gain, and converts the variation of the output voltage into a current when the output voltage changes, to generate a current sampling signal; a control current signal generation unit, which receives the current sampling signal, and outputs the control current signal; the current sampling unit comprises: a second transistor, the source of which receives the output voltage, and the drain of which outputs the current sampling signal; a third transistor, the source of which receives the first sampling signal with the gain, and the gate of which is connected to the gate of the second transistor and the drain of the third transistor; a first current source, which is connected between the drain of the third transistor and the reference ground, and is used for providing a first reference current.

2. The linear voltage regulator circuit of claim 1, wherein, The control current signal is in proportional relationship with the variation of the output voltage.

3. The linear voltage regulator circuit of claim 1, wherein, The sample-and-hold unit comprises: a third resistor, the first end of which receives the output voltage, and the second end of which outputs the first sampling signal; a first capacitor, the first end of which is connected to the second end of the third resistor, and the second end of which is connected to the reference ground.

4. The linear voltage regulator circuit of claim 1, wherein, The second transistor and the third transistor are both PMOS transistors, and the second transistor and the third transistor both work in a saturation region.

5. The linear voltage regulator circuit of claim 1, wherein, The control current signal generation unit comprises: a fourth transistor, the drain of which is connected to the gate of the fourth transistor and receives the current sampling signal, and the source of which is connected to the reference ground; a fifth transistor, the gate of which is connected to the gate of the fourth transistor, the source of which is connected to the reference ground, and the drain of which outputs the control current signal.

6. The linear voltage regulator circuit of claim 5, wherein, The fourth transistor and the fifth transistor are both NMOS transistors.

7. A linear voltage regulator circuit, wherein, The application relates to a linear voltage stabilizing circuit, comprising: a first transistor, the source of which receives a power supply voltage, and the drain of which outputs an output voltage of the linear voltage stabilizing circuit; a first resistor and a second resistor, which are connected in series between the drain of the first transistor and a reference ground, and generate a feedback voltage by dividing the output voltage; a differential amplification module, configured to receive the feedback voltage and a reference voltage, and output a driving signal to a gate of the first transistor; a comparison module, configured to generate a control current signal according to the output voltage to adjust a gate voltage of the first transistor, wherein the comparison module samples the output voltage when the linear voltage stabilizing circuit is in static operation, and generates the control current signal according to a variation of the output voltage when the output voltage changes; the comparison module comprises: a sample-and-hold unit, configured to sample and hold the output voltage when the linear voltage stabilizing circuit is in static operation, and generate a first sample signal; a buffer, configured to perform gain output on the first sample signal; a current sampling unit, configured to receive the output voltage and the first sample signal after gain, and perform voltage-to-current conversion on a variation of the output voltage when the output voltage changes, to generate a current sample signal; a control current signal generation unit, configured to receive the current sample signal, and output the control current signal; the current sampling unit comprises: a sixth transistor, a source of the sixth transistor receives the output voltage, and a drain of the sixth transistor outputs the current sample signal; a seventh transistor, a source of the seventh transistor receives the first sample signal after gain, and a gate of the seventh transistor is connected with a gate of the sixth transistor and a drain of the seventh transistor simultaneously; a second current source, connected between a power voltage input end and the drain of the seventh transistor, and configured to provide a second reference current.

8. The linear voltage regulator circuit of claim 7, wherein, The sixth transistor and the seventh transistor are both NMOS transistors, and the sixth transistor and the seventh transistor both operate in a saturation region.

9. The linear voltage regulator circuit of claim 7, wherein, the control current signal generation unit comprises: an eighth transistor, a drain of the eighth transistor is connected with a gate of the eighth transistor and receives the current sample signal, and a source of the eighth transistor is connected with the power voltage input end; a ninth transistor, a gate of the ninth transistor is connected with the gate of the eighth transistor, a source of the ninth transistor is connected with the power voltage input end, and a drain of the ninth transistor outputs the control current signal.

10. The linear voltage regulator circuit of claim 9, wherein, The eighth transistor and the ninth transistor are both PMOS transistors.

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