Semiconductor device and control method

Abstract

A semiconductor device and a control method for performing data transfer between a host device and a memory chip at high speed. The semiconductor device has: a first chip having a terminal that inputs a signal from the host device; a second chip group that is a plurality of second chips electrically connected to the first chip; and a third chip group that is a plurality of third chips electrically connected to the first chip in parallel with the second chip group; the first chip has: a command queue that stores a plurality of read commands received from the host device; and a read buffer memory that buffers read data; the plurality of read commands stored in the command queue are sequentially issued to the second chip group or the third chip group; read data corresponding to the plurality of read commands is stored from the second chip group or the third chip group to the read buffer memory; and based on an execution state of any one of the plurality of read commands, any one of the read data stored in the buffer memory is transmitted to the host device.

Description

[0001] This application claims priority to Japanese Patent Application No. 2021-205982 (Filing date: December 20, 2021). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to a semiconductor device and a control method. BACKGROUND

[0003] There is a semiconductor device configured to be connectable with a host device. Such a semiconductor device has a plurality of memory chips. Further, the semiconductor device has a plurality of channels connected with the plurality of memory chips. Between the host device and the semiconductor device, a command and data are transmitted as objects of the memory chips. It is desired to perform transmission of signals corresponding to the command and the data between the host device and the memory chips at high speed. SUMMARY

[0004] An object of the present application is to provide a semiconductor device and a control method that perform data transmission between a host device and a memory chip at high speed.

[0005] According to one aspect, a semiconductor device has: a first chip having a terminal that inputs a signal from a host device; a second chip group that is a plurality of second chips electrically connected with the first chip; and a third chip group that is a plurality of third chips electrically connected with the first chip in parallel with the second chip group; the first chip has: a command queue that stores a plurality of read commands received from the host device; and a read buffer memory that buffers read data; the plurality of read commands stored in the command queue are sequentially issued to the second chip group or the third chip group; read data corresponding to the plurality of read commands is stored in the read buffer memory from the second chip group or the third chip group; and based on an execution state of any one of the plurality of read commands, any one of the read data stored in the read buffer memory is transmitted to the host device. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a view that shows a structure of a memory system to which the semiconductor device of the first embodiment is applied.

[0007] Figure 2 is a view that shows a structure of the semiconductor device relating to the first embodiment.

[0008] Figure 3 is a view that shows an operation of the semiconductor device relating to the first embodiment.

[0009] Figure 4is a view showing an operation of the semiconductor device according to the second embodiment.

[0010] Figure 5 is a view showing an operation of the semiconductor device according to the third embodiment.

[0011] Figure 6 is a view showing an operation of the semiconductor device according to the fourth embodiment.

[0012] Figure 7 is a view showing another operation of the semiconductor device according to the fourth embodiment.

[0013] Figure 8 is a view showing an operation of the semiconductor device according to the fifth embodiment.

[0014] Figure 9 is a view showing an operation of the semiconductor device according to the sixth embodiment.

[0015] Figure 10 is a view showing an operation of the semiconductor device according to the seventh embodiment.

[0016] Figure 11 is a view showing another operation of the semiconductor device according to the seventh embodiment.

[0017] Figure 12 is a view showing a structure of the semiconductor device according to the eighth embodiment.

[0018] Figure 13 is a view showing an operation of the semiconductor device according to the eighth embodiment.

[0019] Figure 14 is a view showing an operation of the semiconductor device according to the ninth embodiment.

[0020] Figure 15A is a view showing an example of data read out by the status read command according to the ninth embodiment.

[0021] Figure 15B is a view showing an example of data formatted after reading out according to the ninth embodiment.

[0022] Figure 16A is a view showing another example of data read out by the status read command according to the ninth embodiment.

[0023] Figure 16B is a view showing another example of data formatted after reading out according to the ninth embodiment.

[0024] Explanation of Reference Signs

[0025] 1 semiconductor device; 101 controller; 102 read buffer; 103 write buffer; 104 channel interface; BC bridge chip; CP1 chip set; CP2 chip set. DETAILED DESCRIPTION

[0026] A semiconductor device according to an embodiment will be described in detail below with reference to the accompanying drawings. Note that the present application is not limited by this embodiment.

[0027] (First Embodiment)

[0028] A semiconductor device according to an embodiment has an external terminal, a bridge chip, and a plurality of chips which can be connected to a host device. The plurality of chips are connected to the external terminal via the bridge chip. The semiconductor device is connected to the host device via a wired communication line at the external terminal. For the semiconductor device, access from the host device via the wired communication line to the plurality of chips is performed via the bridge chip. Each chip is, for example, a memory chip of a nonvolatile memory such as a NAND-type flash memory.

[0029] In the case where each chip is a memory chip, for the semiconductor device, the number of mounted chips is gradually increasing in order to increase mounting density. For example, mounting density is increased by stacking chips. At this time, in order to reduce load applied to connection to each chip and achieve high speed, a structure in which a bridge chip called an FBI (Frequency Boosting Interface) chip is connected to an external terminal and the bridge chip is connected to a plurality of chips through a plurality of channels is adopted. A plurality of chips can be connected to each channel. The bandwidth of the wired communication line is equal to the bandwidth of each channel and is smaller than the total bandwidth of the plurality of channels. Since one of the plurality of channels is used at a time, there is a tendency that the communication speed between the bridge chip and each chip is slow. Thus, if the semiconductor device receives one command from the host device, the chips of each channel are processed according to the received command, there is a tendency that a waiting time occurs on the host device side.

[0030] Therefore, in the present embodiment, a command queue which can hold a plurality of commands is provided for the semiconductor device, so that commands are executed in parallel in the plurality of channels. Thus, an increase in the data transfer speed between the host device and the plurality of chips via the bridge chip is achieved.

[0031] Specifically, a storage system SYS to which the semiconductor device 1 is applied is configured as illustrated in FIG. 1. Figure 1 FIG. 1 is a diagram illustrating the structure of a storage system SYS to which the semiconductor device 1 is applied. Figure 1 FIG. 1 is a diagram illustrating the structure of a storage system SYS to which the semiconductor device 1 is applied.

[0032] The storage system SYS includes a host device HA and the semiconductor device 1. The semiconductor device 1 has a bridge chip BC and a plurality of chips LUN 0 to LUN 7. The bridge chip BC is an example of a first chip. The chips LUN 0 to LUN 3 are examples of a second chip. The chips LUN 4 to LUN 7 are examples of a third chip. The semiconductor device 1 can be mounted as an MCP (Multi Chip Package) in which the chips LUN 0 to LUN 7 are stacked, respectively. In a case where the semiconductor device 1 is mounted as an MCP, the bridge chip BC and the periphery of the plurality of chips LUN 0 to LUN 7 can be encapsulated with a molding resin. In Figure 1 In the present embodiment, a configuration in which the four chips LUN 0 to LUN 3 are connected to the bridge chip BC via the channel CH1 and the four chips LUN 4 to LUN 7 are connected to the bridge chip BC via the channel CH2 is exemplified. That is, the semiconductor device 1 can be configured as a multi-chip module including a plurality of (here, eight) chips LUN 0 to LUN 7. Each of the chips LUN 0 to LUN 7 is, for example, a memory chip of a nonvolatile memory such as a NAND-type flash memory.

[0033] The host device HA can be a controller or the like, or a processor included in an electronic device such as a computer or a portable terminal, which controls the semiconductor device 1. The semiconductor device 1 can be connected to the host device HA via a wired communication line (for example, a serial bus or the like) CH0. The semiconductor device 1 is connected to the host device HA via the wired communication line CH0 configured based on a prescribed specification. In a case where each of the chips LUN 0 to LUN 7 is a NAND-type flash memory, the prescribed specification is, for example, a Toggle DDR specification or an ONFi specification. The wired communication line CH0 functions as a Toggle DDR interface, for example.

[0034] The bridge chip BC is electrically connected between the external terminal group la and the plurality of (here, 2) channels CH1, CH2. The external terminal group la is electrically connectable with the host device HA via the wired communication line CH0. The plurality of chips LUN 0 - chip LUN 7 are connected with the bridge chip BC via the channels CH1, CH2 constituted based on a prescribed specification. In the case where each of the chips LUN 0 - chip LUN 7 is a NAND type flash memory, the prescribed specification is, for example, a Toggle DDR specification or an ONFi specification. The channels CH1, CH2 function as, for example, Toggle DDR interfaces. Further, the chip group CP1 is a chip group constituted by the chips LUN 0 - chip LUN 3. The chip group CP2 is a chip group constituted by the chips LUN 4 - chip LUN 7. The chip group CP1 is an example of a 2nd chip group. The chip group CP2 is an example of a 3rd chip group.

[0035] Figure 2 is a view showing a detailed structure of the semiconductor device 1. For example, the external terminal group includes a terminal for a chip enable signal CEZ, a terminal for a data signal DQ[7:0], a terminal for a read enable signal RE- / RE, a terminal for a data strobe signal DQS / DQS-, and a terminal for an R / B- signal, as shown in Figure 2

[0036] With the increase in the required access speed, the semiconductor device 1 can perform an operation with respect to a command in synchronization with both edges of a rise and a fall of a signal for timing used for the import of transmission data. The R / B- signal is a signal indicating whether or not the semiconductor device 1 can be accessed. An example of the signal for chip control is the chip enable signal CEZ. An example of the transmission data is the data signal DQ[7:0]. An example of the signal for timing is the data strobe signal DQS / DQS-. The read enable signal RE- and the read enable signal RE constitute a pair of differential signals. The data strobe signal DQS and the data strobe signal DQS- constitute a pair of differential signals. The read enable signal RE- / RE is a signal for timing supplied from the host device HA. The data strobe signal DQS / DQS- is a signal for timing output to the host device HA for a request for reading of data from the host device HA. Thus, the signal for timing can be constituted by a differential signal.

[0037] The bridge chip BC has a controller 101, a read buffer memory 102, a write buffer memory 103, and a channel interface 104.

[0038] ​The controller 101 is configured between a terminal for a chip enable signal CEZ, terminals for data signals DQ[7:0], a terminal for a read enable signal RE- / RE, terminals for data strobe signals DQS / DQS-, and a terminal for an R / B- signal and the channel interface 104. The controller 101 controls exchange of information between the above-mentioned terminals and the channel interface 104 using the read buffer memory 102 and the write buffer memory 103.

[0039] The controller 101 has a command queue 101a, a command decoder 101b, a command queue state management section 101c, a command priority control section 101d, a command issue timing control section 101e, an RE- / RE generation section 101f, and a buffer control section 101g.

[0040] The command queue 101a queues commands (e.g., write commands, read commands, etc.) received from the host HA.

[0041] The command decoder 101b analyzes commands received from the host HA via the terminals for the data signals DQ[7:0], and issues commands to the chip sets CP1, CP2 in accordance with the analysis results. The issued commands are supplied from the channel interface 104 to either of the chip sets CP1, CP2 via either of the channels CH1, CH2. For example, the command decoder 101b sometimes receives a data preparation command or a data output command as a read command from the host HA. The data output command is an example of a read command. The data preparation command is a command that instructs data transfer from an array 111 of memory cells of a chip LUN, which is an object included in the chip sets CP1, CP2, to a buffer memory 113. The data output command is a command that instructs output of data held by the buffer memory 113 of the chip LUN, which is an object included in the chip sets CP1, CP2, from the chip sets CP1, CP2. The command decoder 101b supplies a corresponding command from the channel interface 104 to either of the chip sets CP1, CP2 via either of the channels CH1, CH2 in accordance with reception of each command from the host HA. Further, the command decoder 101b performs decoding processing of a write command or an erase command.

[0042] The command queue state management section 101c refers to execution states of commands held in the command queue 101a, and transmits information of the execution states of the commands to the host HA. Here, the execution state of a command indicates a processing status of read / write, etc. involved in the command at the chip LUN 0, etc. where the command is issued.

[0043] The command priority control section 101d changes an execution order of commands held in the command queue 101a in accordance with a designation from the host HA.

[0044] The command issue timing control section 101e controls the timing of instructing the processing of the command to the chipsets CP1, CP2.

[0045] The RE- / RE generation section 103b autonomously generates a read enable signal RE- / RE in the case where the command is a data output command, in accordance with the analysis result of the command decoder 101b. The generated read enable signal RE- / RE is supplied from the channel interface 104 to either of the chipsets CP1, CP2 via either of the channels CH1, CH2.

[0046] The controller 101 generates a data strobe signal DQS / DQS- in accordance with the received read enable signal RE- / RE in the case where the read enable signal RE- / RE is received from the host device HA, and outputs it to the host device HA.

[0047] The buffer control section 101g controls the reading or writing of data to or from the read buffer memory 102 and the write buffer memory 103.

[0048] The read buffer memory 102 is provided in order to hold data read from the chipset CP1 or the chipset CP2. The read buffer memory 102 can be constituted by, for example, an SRAM.

[0049] The write buffer memory 103 is provided in order to hold data written to the chipset CP1 or the chipset CP2. The write buffer memory 103 can be constituted by, for example, an SRAM.

[0050] The channel interface 104 performs connection between the chipsets CP1, CP2 via the channels CH1, CH2. The channel interface 104 transmits the command, address, or data, and the like supplied from the controller 101 to the chipsets CP1, CP2 via the channels CH1, CH2, or holds the data, and the like supplied from the chipsets CP1, CP2 to the read buffer memory 102, the write buffer memory 103, and supplies it to the controller 101.

[0051] The chips LUN have the terminal groups TM1 to TM4, the memory cell array 111, the peripheral circuit 112, and the buffer memory 113, respectively. The terminal groups TM1 to TM4 are electrically connected to the channel interface 104 via the channel CH1 of one system. The terminal groups TM1 of the plurality of chips LUN 0 to chip LUN 3 are electrically connected to each other, the terminal groups TM2 are electrically connected to each other, the terminal groups TM3 are electrically connected to each other, and the terminal groups TM4 are electrically connected to each other. The terminal groups TM1 to TM4 are electrically connected to the peripheral circuit 112 and one end of the channel CH1. The other end of the channel CH1 is electrically connected to the channel interface 104.

[0052] The terminal group TM1 is a terminal group for a chip enable signal CEZ. The terminal group TM1 includes a number of terminals corresponding to the bit width of the chip enable signal CEZ.

[0053] The terminal group TM2 is a terminal group for data signals DQ[7:0]. The terminal group TM1 includes a number of terminals corresponding to the bit width (for example, 8 bits) of the data signals DQ[7:0].

[0054] The terminal group TM3 is a terminal group for a read enable signal RE- / RE. The terminal group TM2 includes a number of terminals corresponding to the bit width of the read enable signal RE- / RE.

[0055] The terminal group TM4 is a terminal group for a data strobe signal DQS / DQS-. The terminal group TM3 includes a number of terminals corresponding to the bit width of the data strobe signal DQS / DQS-.

[0056] The memory cell array 111 has a configuration in which a plurality of memory cells are arranged two-dimensionally or three-dimensionally. The memory cell array 111 is connected to the peripheral circuit 112. The peripheral circuit 112 is disposed around the memory cell array 111 and is electrically connected to the terminal groups TM1 to TM4, the buffer memory 113, and the memory cell array 111. The peripheral circuit 112 controls, using the buffer memory 113, an access operation (for example, a read operation, a write operation) to each memory cell of the memory cell array 111 in accordance with a command received from the bridge chip BC via the terminal group TM2.

[0057] The buffer memory 113 is a buffer for input and output of each of the chips LUN 0 to LUN 3 of the chip set CP1 via the terminal groups TM1 to TM4 and is also called an input and output data latch or a page buffer. The peripheral circuit 112 temporarily stores data read from the memory cell array 111 in the buffer memory 113 in accordance with a read / data / command received from the bridge chip BC. Therefore, the capacity (or size) of the buffer memory 113 has a data size (for example, 16 [kB]) as a read unit of data of the chip set CP1.

[0058] The peripheral circuit 112 supplies data stored in the buffer memory 113 to the bridge chip BC via the terminal groups TM1 to TM4 and the channel CH1 in accordance with a data output command received from the bridge chip BC. At this time, the controller 101 of the bridge chip BC temporarily stores data received from any one of the chips LUN of the chip set CP1 in the read buffer memory 102.

[0059] Here, the capacity (or size) of the read buffer memory 102 of the bridge chip BC is an integral multiple (for example, 16 x N [kB], N is an arbitrary positive integer) of the data size as a read unit of data of the chip set CP1. Thus, the buffer memory can continuously store read data in the case where the read data is continuously output from the chip set CP1.

[0060] The chip LUN connected to the chip set CP2 of the channel CH2 also has the terminal group TM1 to TM4, the memory cell array 111, the peripheral circuit 112, and the buffer memory 113 in the same manner. As for each structure, it is the same as that of the chip LUN connected to the chip set CPI of the channel CH1, so the description is omitted.

[0061] Next, using Figure 3 The operation of the semiconductor device 1 will be described. Figure 3 The HOST ChO shown indicates signals exchanged between the host device HA and the bridge chip BC via the wired communication line CHO. Figure 3 The NAND Chl shown indicates signals exchanged between the bridge chip BC and the chip set CPI via the channel CHl. Figure 3 The NAND Ch2 shown indicates signals exchanged between the bridge chip BC and the chip set CP2 via the channel CH2.

[0062] Figure 3 The "CMDQ status" table shown indicates information indicating the execution status of the command held in the command queue 101a. The "ST" of the "CMDQ status" table indicates the processing status of each command. In the case where the "ST" is "0", it indicates that the processing of the command is not completed. Further, in the case where the "ST" is "1", it indicates that the processing of the command is completed. Figure 3 The read buffer shown indicates information held in the read buffer memory 102.

[0063] The bridge chip BC receives a data output command CM*r (in the following operation example, the data preparation command CM*s is omitted) after the data transfer from the memory cell array 111 of the target LUN to the buffer memory 113 is completed, after receiving the data preparation command CM*s (the * corresponds to the LUN number) from the host device HA. The data preparation command CM*s is a preparation command of the read processing. In the case where the data output command CM*r is received, the bridge chip BC decodes the data output command CM*r, and holds it in the command queue 101a. Figure 3 In the operation example of the semiconductor device 1, an example in which the host device HA sequentially receives a data output command CMOr for the chip LUN 0, a data output command CM1r for the chip LUN 1, a data output command CM4r for the LUN 4, and a data output command CM5r for the LUN 5 is shown. In this example, the command decoder 101b decodes each of the data output commands CMOr, CM1r, CM4r, and CM5r, and holds it in the command queue 101a.

[0064] The command issue timing control section 101e issues the data output command CM*r in accordance with the free condition of the channel Chl or the channel Ch2. Specifically, if the data output command CM0r is stored to the command queue 101a, the command issue timing control section 101e issues the data output command CM0r to the channel Chl. In addition, the data output command CM0r is set to the state of the "CMDQ state" table for the timing tl, and "0" indicating that the reading from the channel Chl is not completed is set in the "ST". Furthermore, the memory cell array 111 issues the data to be read from the buffer memory 113 to the bridge chip BC.

[0065] In addition, if the data output command CM1r is stored to the command queue 101a, the command issue timing control section 101e does not issue the data output command CM1r to the channel Chl because the channel Chl which is the issue target of the data output command CM1r is in the command execution. In addition, the buffer control section 101g sequentially stores the read data issued from the chip LUN 0 in the period of DOUT to the "CM0r DOUT" area of the read buffer memory 102.

[0066] Next, if the data output command CM4r is stored to the command queue 101a, the command issue timing control section 101e issues the data output command CM4r stored in the command queue 101a to the channel Ch2. In this way, the command issue timing control section 101e sequentially issues the data output commands stored in the command queue 101a to the channel Chl or the channel Ch2.

[0067] In addition, in the "CMDQ state" table for the timing t2, the data output command CM1r and the data output command CM4r are set, and "0" indicating that these commands are not completed is set in the "ST" of these commands. Furthermore, as for the data output command CM0r, the flag information of the data output command CM0r is also "0" because the read data issued from the chip LUN 0 is not all stored in the read buffer memory 102.

[0068] In addition, if the output of the read data from the chip LUN 0 is completed, the command issue timing control section 101e issues the data output command CM1r to the chip LUN 1. Furthermore, the command queue state management section 101c updates the "ST" of "CM0r" of the "CMDQ state" table to "1". The host HA issues the command CQ0 indicating the state confirmation if a prescribed number of commands are issued. The command queue state management section 101c transmits the information of the "CMDQ state" table to the host HA.

[0069] The host HA reads the read data of the data output command whose "ST" is "1" with reference to the information of the "CMDQ state" table. At timing t3, the host HA makes a read request of the read data of the chip LUN 0 corresponding to the data output command CMOr because the "ST" of the CMOr is "1". The buffer control section 101g sends the data of the "CMOr DOUT" area of the read buffer memory 102 to the host HA in correspondence therewith. The command queue state management section 101c deletes the record of the CMOr of the "CMDQ state" table in correspondence with the completion of the sending of the read data of the data output command CMOr to the host HA.

[0070] At timing t4, the "ST" of the CM4r of the "CMDQ state" table becomes "1". The "ST" of the data output command CM5r is "0" because the read data from the chip LUN 5 corresponding to the data output command CM5r issued before timing t4 is not all saved in the read buffer memory 102. At timing t5, the "ST" of the CM1r and the CM5r, which are not completed in reading, becomes "1".

[0071] Thus, the bridge chip BC saves the read data corresponding to the data output command from the first chip set CP1 or the second chip set CP2 to the read buffer memory 102 with respect to the read command saved in the command queue 101a, and sends the read data to the host HA in accordance with the execution state of the command of the command queue 101a. The bridge chip BC can save a plurality of commands in the command queue 101a, execute the commands in order, and send the read data to the host HA in accordance with the state of the read data saved in the read buffer memory 102, so that the processing can be executed without a waiting time between the host HA and the bridge chip BC.

[0072] (Second Embodiment)

[0073] In the first embodiment, the next data output command is issued to the chip after all the read data corresponding to the data output command is saved to the read buffer memory 102. In the second embodiment, the next data output command is issued to the chip after a part of the read data corresponding to the data output command is saved to the read buffer memory 102.

[0074] Use Figure 4 An example of the operation of the second embodiment will be described. The same points as those described with reference to FIG. 10 will be omitted. Figure 3 The same points as those described with reference to FIG. 10 will be omitted. Figure 3The timing t1 in the command queue state management section 101c is the same as the timing t1 in the command queue state management section 101c. The data output command CM0r is issued to the chip LUN 0, and the reception of the read data from the chip LUN 0 is interrupted at the timing at which the buffer control section 101g saves the read data of the prescribed size to the read buffer memory 102 after the timing t11. In correspondence with this, the command issue timing control section 101e issues the data output command CM1r to the LUN 1. The data output command CM0r is an example of the first read command, and the data output command CM1r is an example of the second read command. Further, the command queue state management section 101c updates the "ST" of "CM0r" of the "CMDQ state" table to "1". Due to this, the "ST" of "CM0r" of the "CMDQ state" table becomes "1" at the timing t12.

[0075] Further, the bridge chip BC also updates the "ST" of "CM*r" of the "CMDQ state" table to "1" at the timing at which a part of the read data is saved to the read buffer memory 102 with respect to the other data output commands. That is, the same processing is performed with respect to the data output command CM1r and the data output command CM4r. Thus, after the host device HA has issued the data output commands, the "ST" of "CM0r", "CM1r", and "CM4r" of the "CMDQ state" table becomes "1" at the timing t13 which is the timing at which the command CQ0 which is the command for indicating the status confirmation is issued.

[0076] Further, if the host device HA starts the reading of the read data, the buffer control section 101g saves the remaining read data from the object chip LUN to the read buffer memory 102. For example, if the host device HA performs the read request of the read data of the chip LUN 0 which corresponds to the data output command CM0r, the buffer control section 101g saves the remaining read data from the object chip LUN to the read buffer memory 102.

[0077] Thus, the bridge chip BC with respect to the second embodiment saves a part of the read data which corresponds to the data output command to the read buffer memory 102. Then, the bridge chip BC with respect to the second embodiment saves the remaining read data which corresponds to the data output command from the first chip group CP1 or the second chip group CP2 to the read buffer memory 102 based on the status of the other data output commands. Due to this, the host device HA is able to perform the reading of the read data at an earlier timing compared to the case of the bridge chip BC with respect to the first embodiment. Further, it is also possible to reduce the capacity of the read buffer memory 102.

[0078] (Third Embodiment)

[0079] In the first and second embodiments, the case where the bridge chip BC executes command processing according to the order of commands sent from the master device HA was described. In this embodiment, the order of command processing is changed based on the specification from the master device HA.

[0080] use Figure 5 Explaining an example of operation related to the third embodiment. Regarding... Figure 4 Common points are omitted. Regarding the handling of timers t21 to t23, and... Figure 4 The processing of timers t11 to t13 is common. After issuing the command CQ0 indicating status confirmation, the master device HA issues the command S1 indicating that the data output command CM1r is prioritized. The command issuance timing control unit 101e of the bridge chip BC issues a transmission instruction to the buffer control unit 101g to read the data of LUN1. Correspondingly, the buffer control unit 101g reads the data of chip LUN1 instead of chip LUN0.

[0081] In this way, the bridge chip BC can flexibly change the timing at which the master device HA sends the retrieved read data by changing the data retrieval order in accordance with the instructions from the master device HA.

[0082] (Fourth implementation)

[0083] In the fourth embodiment, the processing when a write command is received from the master device HA will be described. The data write process receives the write data after a predetermined period has elapsed since the data write command was received from the master device. This results in a waiting time with the master device, leading to inefficient execution. Therefore, in this embodiment, by performing the write process via the write buffer memory 103, the write process can be performed efficiently.

[0084] use Figure 6 An example of operation related to the fourth embodiment will be explained. Figures 3-5 The buffer used for reading is shown in the image, while... Figure 6 The write buffer is shown as an intermediary. The master device HA issues a write command CM0w indicating a write operation to chip LUN 0. The command decoder 101b decodes the write command CM0w and saves it to the command queue 101a. In addition, the write command CM0w is set in the "CMDQ status" table of the timer t31, and "0" is set in "ST" to indicate that the write is not completed.

[0085] The master device HA issues a write command CM0w as the DIN of chip LUN 0 and sends the write data to chip LUN 0 to the bridge chip BC. The buffer control unit 101g of the bridge chip BC writes the write data to LUN 0 to the write buffer memory 103. The buffer control unit 101g sets the area for the write data to chip LUN 0 in the write buffer memory 103.

[0086] Furthermore, after sending write data (DIN) to chip LUN 0, the master device HA issues a write command CM4w indicating a write operation to chip LUN 4. Since write data has been written to the write buffer memory 103, the master device HA does not need to consider the waiting time for write data processing between bridge chip BC and chip LUN 0. Therefore, at time t32, before the write operation from bridge chip BC to chip LUN 0 as shown in NAND Ch1 is completed, the write command CM4w is issued as shown in NAND Ch2.

[0087] In addition, at time t33, since the write processing of the data written to the bridge chip BC and the chip LUN 0 has been completed, the "ST" of "CM0w" in the "CMDQ status" table is updated to "1".

[0088] use Figure 7 Other operational examples related to the fourth embodiment are explained. Figure 6 The previous description depicted a case where the write buffer 103 had only one region for writing data corresponding to a command. In this example, there are multiple regions for writing data corresponding to commands.

[0089] In this case, such as Figure 7 As shown, if "CM1w" and "CM2w" are set in the "CMDQ Status" table at time t43, the buffer control unit 101g sets the area for writing data to chips LUN 1 and LUN 2 in the write buffer memory 103. Furthermore, if, as at time t45, "CM1w" is set to complete ("ST" is "1") in the "CMDQ Status" table, and a new "CM4w" is set to incomplete ("ST" is "0"), then at time t46, the buffer control unit 101g sets the area for writing data to chip LUN 4 in the write buffer memory 103. At this time, the buffer control unit 101g deletes the area for writing data to chip LUN 1 from the write buffer memory 103. Thus, the bridge chip BC can process the write processing for chipset CP1 and the write processing for chipset CP2 in parallel.

[0090] In this way, the bridge chip BC sets up a write buffer 103. When it receives a write command (e.g., write command CM0w) from the master device HA, it writes the write data for that command to the write buffer 103. Furthermore, the bridge chip BC writes the write data stored in the write buffer 103 to the chip LUN. In this case, because the bridge chip BC writes the write data to the write buffer 103, the master device HA can issue commands without considering the processing time between the bridge chip BC and the chip LUN.

[0091] (Fifth Embodiment)

[0092] The fifth embodiment is an implementation for handling the situation where multiple commands coexist. In the fifth embodiment, it is assumed that data output commands, write commands, and erase commands coexist.

[0093] use Figure 8 An example of operation in the fifth embodiment will be described. The master device HA issues a data output command CM0r indicating a read operation command to chip LUN0. Next, the master device HA issues a data output command CM1r indicating a read operation command to chip LUN1. Next, the master device HA issues a data output command CM4r indicating a read operation command to chip LUN4. Next, the master device HA issues an erase command CM5e indicating an erase operation command to chip LUN5. Next, the master device HA issues a write command CM6w indicating a write operation command to chip LUN6.

[0094] If the bridge chip BC receives these commands, it saves each command to the command queue 101a. In addition, the bridge chip BC logs records indicating the status of commands in the "CMDQ Status" table. The bridge chip BC deletes the records for data output commands and erase commands after the command is issued and after sending the command status to the master device HA.

[0095] After saving the commands to command queue 101a, bridge chip BC performs the same processing as in the first embodiment for data output commands CM0r, CM1r, and CM4r, and performs the same processing as in the fourth embodiment for write command CM6w. Regarding erase command CM5e, bridge chip BC issues an erase command to the target chip LUN 5 after retrieving it from command queue 101a.

[0096] When the bridge chip BC receives the confirmation command CQ0, it sends the "CMDQ status" table information to the master device HA at time t54. The master device HA then makes a read request for the chip (e.g., chip LUN 0) accordingly.

[0097] As described above, the bridge chip BC can hold not only the data output command but also the write processing command and the erase processing command in the command queue 101a, sequentially execute the commands, and transmit the read data to the host device HA according to the state in which the read data is held in the buffer memory, so that the processing can be executed without the latency between the host device HA and the bridge chip BC even if the write processing command and the erase processing command are mixed.

[0098] (6th Embodiment)

[0099] In the 6th embodiment, in the case where there is a priority command which is a command to be executed in order of priority, the priority command is preferentially executed regardless of the order of the commands issued by the host device HA.

[0100] Use Figure 9 An example of the operation of the 6th embodiment will be described. CM*r is a data output command. Further, CM*s is a data preparation command. It is assumed that the command priority control section 101d preferentially sets the data preparation command.

[0101] The host device HA issues the commands in the order of the data output command CM0r, the data output command CM1r, the data preparation command CM0s, the data preparation command CM1s,..., and the data preparation command CM5s.

[0102] At time t61, only the data output command CM0r is held in the command queue 101a. After time t61, the bridge chip BC issues the commands to the channel Chl in the order of the data preparation command CM0s, the data preparation command CM1s, and the data output command CM1r. At time t62, the data output command CM0r, the data output command CM1r, and the data preparation command CM0s are held in the command queue 101a, and after the output of the read data from the chip LUN 0 is completed, the data output command CM1r is in the order of the issued commands in the host device HA, but the data preparation command CM0s is preferentially executed.

[0103] This is because the data preparation command takes more processing time than the data output command. By thus preferentially processing the command which takes processing time by the bridge chip BC, the performance of the entire system can be improved.

[0104] (7th Embodiment)

[0105] In the 7th embodiment, the peak current suppression control is performed on the chip set CP1 or the chip set CP2. Here, the description will be given separately for the read processing and the write processing.

[0106] An example of the operation of the read processing of the 7th embodiment will be described in Figure 10 Figure 10 ​In the example, the host HA issues data preparation commands CM*s, and issues data output commands CM*r. Assume that the bridge chip BC issues data preparation commands CM0s, CM4s, CM1s, CM5s, CM2s, and CM6s.

[0107] In this state, in a case where the bridge chip BC is also scheduled to issue data preparation commands CM3s and CM7s, the issuance timing of the data preparation commands CM3s and CM7s is suppressed or on standby until a part of the above six data preparation commands is completed. During a period (tR) in which the process of transferring the data of the read target from the memory cell array 111 to the buffer memory 113 is performed, since the processing load of the chip becomes high, it is preferable that the number of the chips can be adjusted during this tR.

[0108] As described above, the bridge chip BC adjusts the number of chips LUN that perform the process of transferring the data of the read target from the memory cell array 111 to the buffer memory 113, whereby the peak current of the chip set CP1 or the chip set CP2 can be reduced.

[0109] In Figure 11 an action example of the write process of the 7th embodiment is shown. In Figure 11 In the example, the host HA issues write commands CM*w. Assume that the bridge chip BC issues write commands CM0w, CM4w, CM1w, CM5w, CM2w, and CM6w.

[0110] In this state, the bridge chip BC suppresses or puts on standby the issuance timing of the write commands CM3w and CM7w until a part of the above six write commands is completed, in a case where the bridge chip BC is also scheduled to issue the write commands CM3w and CM7w.

[0111] During a period (tPROG) in which the process of transferring the data of the write target from the buffer memory 113 to the memory cell array 111 is performed, since the processing load of the chip becomes high, it is preferable that the number of the chips can be adjusted during this tPROG.

[0112] As described above, the bridge chip BC adjusts the number of chips LUN that perform the process of transferring from the buffer memory 113 to the memory cell array 111, whereby the peak current of the chip set CP1 or the chip set CP2 can be reduced.

[0113] (8th Embodiment)

[0114] In the 8th embodiment, the RBZ signal of the chip of the chip set CP1 or the chip set CP2 is monitored, and a command is issued based on the result.

[0115] The use Figure 12The structure of the semiconductor device 1A of the eighth embodiment will be described. The description of the parts overlapping with those shown in FIG. 1A will be omitted. The semiconductor device 1A of the eighth embodiment further has an RBZ control section 101h and an SR format conversion circuit 101i. Figure 2 The RBZ control section 101h monitors and controls an RBZ signal. Here, the RBZ signal is a signal indicating whether the chip LUN of the chip set CP1 or the chip set CP2 is in a state capable of receiving a command from the bridge chip BC. The SR format conversion circuit 101i performs format conversion on data of a status read. Here, the data of the status read is status information of the chip LUN of the chip set CP1 or the chip set CP2. The status read buffer memory 105 is a buffer memory for holding the result of a status read command. The chip LUNs further have a terminal group TM5, respectively. The terminal group TM5 is a terminal group for the RBZ signal.

[0116] The RBZ control section 101h monitors and controls an RBZ signal. Here, the RBZ signal is a signal indicating whether the chip LUN of the chip set CP1 or the chip set CP2 is in a state capable of receiving a command from the bridge chip BC. The SR format conversion circuit 101i performs format conversion on data of a status read. Here, the data of the status read is status information of the chip LUN of the chip set CP1 or the chip set CP2. The status read buffer memory 105 is a buffer memory for holding the result of a status read command. The chip LUNs further have a terminal group TM5, respectively. The terminal group TM5 is a terminal group for the RBZ signal.

[0117] Next, the operation example of the semiconductor device 1 of the eighth embodiment will be described. Figure 13 The operation example of the semiconductor device 1 of the eighth embodiment will be described. Figure 13 The HOST ChO shown in FIG. 10 indicates signals exchanged between the host HA and the bridge chip BC via the wired communication line CHO. Figure 13 The NAND Chl shown in FIG. 10 indicates signals exchanged between the bridge chip BC and the chip set CP1 via the channel CHl.

[0118] Figure 13 The NAND LUNO RBZ shown in FIG. 10 indicates the level of the RBZ signal of the chip LUN 0. Figure 13 The NAND LUNO RBZ shown in FIG. 10 indicates the RBZ signal of the chip LUN 0, and the NAND LUNl RBZ indicates the RBZ signal of the chip LUN 1. Figure 13 The HOST RBZ0 shown in FIG. 10 indicates the RBZ signal of the bridge chip BC.

[0119] Figure 13 The "CMDQ status" table shown in FIG. 10 indicates information indicating the execution status of the command held in the command queue 101a. Figure 13 The read buffer shown in FIG. 10 indicates information held in the read buffer memory 102.

[0120] CM*r is a data output command. Further, CM*s is a data preparation command. The host HA issues the commands in the order of the data preparation command CM0s, the data preparation command CMls, the data output command CM0r, and the data output command CMlr.

[0121] The bridge chip BC issues a data preparation command CM0s to the chip LUN 0 and a data preparation command CM1s to the chip LUN 1. Thus, the RBZ signal of the chip LUN 0 and the RBZ signal of the chip LUN 1 become busy. The RBZ control section 101h monitors these RBZ signals. The command issue timing control section 101e issues a data output command CM0r to the LUN 0 at the time t71 at which the busy state of the RBZ signal of the chip LUN 0 is released.

[0122] Thus, the bridge chip BC monitors the RBZ signals of the chips, and issues a data output command to the chips in accordance with the state of the RBZ signals, so that the data output command can be efficiently executed without issuing a command referring to the state of the LUN from the host HA.

[0123] (9th Embodiment)

[0124] The semiconductor device 1B of the 9th embodiment performs format conversion on the result of the state read command and outputs it. The chips LUN 0 to LUN 7 each have a plurality of parallel action elements (planes). It is assumed that the chips LUN 0 to LUN 7 each have four planes.

[0125] Next, the operation example of the semiconductor device 1B of the 9th embodiment will be described with reference to FIG. 18. Figure 14 The operation example of the semiconductor device 1B of the 9th embodiment will be described. Figure 14 The HOST Ch0 shown in FIG. 18 indicates signals exchanged between the host HA and the bridge chip BC via the wired communication line CH0. The NAND Ch1 indicates signals exchanged between the bridge chip BC and the chip group CP1 via the channel CH1. The NAND Ch2 indicates signals exchanged between the bridge chip BC and the chip group CP2 via the channel CH2.

[0126] Figure 14 The "CMDQ state" table shown in FIG. 18 indicates information indicating the state of the command queue 101a. Figure 14 The state read buffer (LUN0) shown in FIG. 18 indicates information saved in the state read buffer memory 105 for the chip LUN 0. Figure 14 The state read buffer (LUN4) shown in FIG. 18 indicates information saved in the state read buffer memory 105 for the chip LUN 4.

[0127] SR*P# is a state read command. * corresponds to the LUN number. # corresponds to the plane number. DO next to SR*P# of the NAND Ch1 and Ch2 indicates data read corresponding to the state read command.

[0128] The host HA issues state read commands SR0P0, SR0P1, SR0P2, SR0P3, SR4P0, SR4P1, SR4P2, and SR4P3.

[0129] The bridge chip BC issues a state read command SR0P0 or the like to the chip LUN 0 or LUN 4, reads data corresponding to the state read command from the chip LUN 0 or LUN 4, and stores the data in the state read buffer memory 105.

[0130] At the time t81 when all the state read commands are completed, if the host HA issues a state confirmation command CQ, the bridge chip BC transmits the result to the host HA. The state confirmation command CQ is a command that confirms the execution state of the state read command. The host HA issues a merge processing command MSR based on the result. The merge processing command MSR is a command that instructs execution of the merge processing of the state read. The DO of the HOST Ch0 after the MSR indicates transmission of data corresponding to the state read command and the merge processing command MSR. Based on these commands, the SR format conversion circuit 101i of the bridge chip BC converts the information of the state read buffer memory 105 and transmits the information to the host HA.

[0131] In addition, the host HA specifies a template number at the time of issuing the merge processing command MSR. Here, the use of the template number is as follows. Figure 15A Figure 15B An example of conversion of information of the state read command will be described.

[0132] Figure 15A is data read out by the state read command of the planes PL0 to PL3. As shown in Figure 15A , the read-out data contains information of eight items. Figure 15B is a diagram showing an example. As shown in Figure 15B , for example, in the case where the template number 1 is specified, the SR format conversion circuit 101i generates information that extracts the information of the item number 5 and the item number 6 of the planes PL0 to PL3 (a portion surrounded by a thick solid line of Figure 15A ). Further, in the case where the template number 2 is specified, the SR format conversion circuit 101i generates information that extracts the information of the item number 0 and the item number 1 of the planes PL0 to PL3 (a portion surrounded by a thick dashed line of Figure 15A ).

[0133] In addition, as shown in Figure 16A , in the case where data of the state read command of the chip LUN is read, as shown in Figure 16B , data corresponding to the template number set in advance is stored, but it is also possible to discard the read data of other portions. In this case, it is possible to reduce the capacity of the state read buffer memory 105. ​

[0134] Thus, the bridge chip BC converts the information of the status reading buffer memory 105 and transmits it to the host device HA. Thereby, the host device HA does not need to perform the reading of the number of planes, and can reduce the processing load.

[0135] The present application has been described with several embodiments, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and modifications can be made within the scope of the gist of the application. These embodiments and modifications are included in the scope or gist of the application, and are included in the scope of the application and its equivalents as recited in the claims.

Claims

1. A semiconductor device having: a first chip having a terminal that inputs a signal from a host device; and a second chip group that is a plurality of second chips electrically connected to the first chip in parallel, the semiconductor device characterized in that: the first chip has: a command queue that holds a plurality of read commands received from the host device; and a read buffer memory that buffers read data; the first chip issues the plurality of read commands held in the command queue to the second chip group or the third chip group in order; the first chip holds, from the second chip group or the third chip group, read data corresponding to the plurality of read commands to the read buffer memory; and the first chip transmits, to the host device, any of the read data held in the read buffer memory based on an execution state of any of the plurality of read commands.

2. The semiconductor device according to claim 1, wherein an execution order of the plurality of read commands held in the command queue is variable. a second chip set electrically connected to the first chip; and 3. The semiconductor device according to claim 1, wherein the first chip further has a write buffer memory, receives a write command from the host device, holds write data involved in the write command to the write buffer memory, and writes the held write data to the second chip group or the third chip group.

4. The semiconductor device according to claim 1, wherein the first chip receives a command different from the read command from the host device, and further holds the different command to the command queue.

5. The semiconductor device according to claim 1, wherein the first chip, in a case where a priority command that specifies a command to be executed preferentially is received from the host device, executes the command to be executed preferentially held in the command queue in accordance with the received priority command.

6. The semiconductor device according to claim 1, wherein planes of the second chip and the third chip, each of which defines a plurality of parallel operation elements, are defined, and the first chip transmits information that edits a state of each plane to the host device.

7. A control method of controlling a semiconductor device capable of connecting to a host device, the semiconductor device having: a first chip having a command queue that holds a plurality of read commands received from the host device and a read buffer memory that buffers read data; and a second chip group that is a plurality of second chips electrically connected to the first chip, the control method characterized in that: the first chip issues the plurality of read commands held in the command queue to the second chip group or the third chip group in order; the first chip holds, from the second chip group or the third chip group, read data corresponding to the plurality of read commands to the read buffer memory; and the first chip transmits, to the host device, any of the read data held in the read buffer memory based on an execution state of any of the plurality of read commands. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A 3rd chip group which is electrically connected with the 1st chip in parallel with the 2nd chip group, The control method comprises the following steps: The plurality of read commands saved in the command queue are sequentially issued to the 2nd chip group or the 3rd chip group; The read data corresponding to the plurality of read commands are saved from the 2nd chip group or the 3rd chip group to the read buffer memory; Based on the execution state of any one of the plurality of read commands, any one of the read data saved in the read buffer memory is sent to the host device; A part of read data corresponding to a 1st read command of the plurality of read commands is saved from the 2nd chip group or the 3rd chip group to the read buffer memory; Based on the execution state of a 2nd read command other than the 1st read command, the remaining read data corresponding to the 1st read command is saved from the 2nd chip group or the 3rd chip group to the read buffer memory.

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