Multi-core processor stability testing methods, apparatus, electronic devices and storage media

Abstract

This invention discloses a method, apparatus, electronic device, and storage medium for testing the stability of multi-core processors. The method includes: applying pressure to the multi-core processor under test using a target test program at its current operating frequency; determining a target core from among the processor cores of the multi-core processor under test, and updating the current operating frequency of the target core, after determining that the multi-core processor under test has generated current stability test information; returning to the operation of applying pressure to the multi-core processor under test using the target test program at its current operating frequency, until the multi-core processor stability test termination condition is met. The technical solution of this invention can improve the reliability and accuracy of multi-core processor stability testing.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of testing technology, and in particular to a method, apparatus, electronic device and storage medium for testing the stability of multi-core processors. Background Technology

[0002] Currently, various industries have increasingly higher requirements for the stability of equipment platform systems, and processor stability is one of the important factors affecting the operational stability of equipment platform systems. Therefore, it is usually necessary to conduct stability testing on the processor of equipment before it leaves the factory.

[0003] Currently, there are two methods for conducting stability tests on processors: the first relies entirely on manual testing, requiring the user to repeatedly switch the processor's high and low operating frequencies. The second is an automated testing method, which triggers the processor to run a specific test program that switches the processor's high and low operating frequencies, acquires the processor's status data during the execution of the specific test program, and determines whether the processor has experienced abnormal situations such as crashes or restarts, thereby determining the processor's stability test results.

[0004] In the process of developing this invention, the inventors discovered the following shortcomings in existing technologies: Manual testing requires repeated work, wasting significant human resources. Furthermore, manual processor stability testing often involves frequent switching of the processor's operating frequency, potentially triggering overcurrent protection on the processor's power supply chip, and in severe cases, directly damaging the chip and affecting the normal operation of the device platform system. Additionally, in practical applications, the processor's computational load frequently changes, especially for multi-core processors, where the load variations are more complex. Existing automated testing methods maintain a constant processor load, making it difficult to effectively simulate the processor's stability during real-world applications. While some automated testing methods switch the processor's operating frequency to simulate stability, the frequency switching method is simplistic and still fails to accurately reflect the stability of processors, especially multi-core processors, in actual applications. Therefore, the reliability and accuracy of processor stability measurements obtained using traditional technologies are not high. Summary of the Invention

[0005] This invention provides a method, apparatus, electronic device, and storage medium for testing the stability of multi-core processors, which can improve the reliability and accuracy of multi-core processor stability testing.

[0006] According to one aspect of the present invention, a method for testing the stability of a multi-core processor is provided, comprising:

[0007] At the current operating frequency of the multi-core processor under test in the device under test, the target test program is used to apply pressure to the multi-core processor under test.

[0008] If it is determined that the multi-core processor under test of the device under test generates current stability test information, the target core is determined from each processor core of the multi-core processor under test, and the current operating frequency of the target core is updated.

[0009] Return to the current operating frequency of the multi-core processor under test in the device under test, and perform a pressure test on the multi-core processor under test using the target test program until the stability test termination condition of the multi-core processor is met.

[0010] This invention addresses the issues of low reliability and accuracy in existing processor stability testing methods by applying a target test program to the multi-core processor under test at its current operating frequency. If the multi-core processor under test generates current stability test information, a target core is identified from each processor core of the multi-core processor under test, and its current operating frequency is updated. This process continues iteratively until the multi-core processor stability test termination conditions are met. This improves the reliability and accuracy of multi-core processor stability testing.

[0011] Optionally, before applying pressure to the multi-core processor under test using the target test program, the method further includes:

[0012] Obtain the power consumption information of each platform device based on the device configuration table;

[0013] The device to be tested is selected from the platform devices based on the device power consumption information;

[0014] Obtain the current operating frequency of the multi-core processor under test in the device under test and all operating frequencies supported by the multi-core processor under test.

[0015] By selecting the platform device with the highest power consumption as the device under test, and then conducting stability tests on the multi-core processor of the device under test, the power consumption requirements of each platform device can be met.

[0016] Optionally, the step of applying pressure to the multi-core processor under test using a target test program at the current operating frequency of the processor under test includes:

[0017] Determine at least one stability test procedure based on the device type of the device under test;

[0018] Randomly select one of the stability test programs as the target test program;

[0019] A pressure sequence is generated based on the actual operating data of the multi-core processor under test;

[0020] The target test program is used to sequentially apply pressure to the multi-core processor under test according to the pressure sequence.

[0021] By randomly selecting the target test program, the use of a single, fixed test program for stability testing of the multi-core processor under test can be avoided, thereby improving the reliability of stability testing. At the same time, the application of a pressure sequence can effectively simulate the actual operating conditions of the processor, thus improving the accuracy of stability testing.

[0022] Optionally, the number of multi-core processors under test is multiple; determining the target core from each processor core of the multi-core processor under test includes:

[0023] Each of the multi-core processors under test is traversed sequentially, and all processor cores of the currently traversed multi-core processors under test are taken as the target core;

[0024] After the multi-core processor under test has been traversed, all processor cores of the multi-core processor under test are taken as the target core.

[0025] The above technical solution provides a usable method for determining the target kernel. By traversing the target kernel sequentially, all processor kernels can be traversed at all operating frequencies, simulating all operating conditions of the multi-core processor under test, thereby improving the accuracy and reliability of stability testing of the multi-core processor under test.

[0026] Optionally, the number of the multi-core processors under test is multiple; the multi-core processors under test include multiple DIEs (chips); determining the target core from each processor core of the multi-core processor under test includes:

[0027] The DIEs of each multi-core processor under test are traversed sequentially, and all processor cores of the currently traversed DIE of the multi-core processor under test are taken as the target cores.

[0028] After the DIE traversal of the multi-core processor under test is completed, the processor cores of all DIEs of the multi-core processor under test are taken as the target core.

[0029] The above technical solution provides a usable method for determining the target kernel based on DIE. By sequentially traversing the kernels of the DIE to determine the target kernel, all DIEs of the processor can be traversed at all operating frequencies, which can simulate all operating conditions of the DIEs of the multi-core processor under test, thereby improving the accuracy and reliability of stability testing of the multi-core processor under test.

[0030] Optionally, the number of multi-core processors under test is multiple; determining the target core from each processor core of the multi-core processor under test includes:

[0031] The test process iterates through each of the multi-core processors under test in sequence, and randomly selects a portion of the processor cores of the currently traversed multi-core processors under test as the target cores.

[0032] After the multi-core processor under test has been traversed, a portion of the processor cores of each multi-core processor under test are selected as the target cores.

[0033] The above technical solution provides another available method for determining the target kernel. By randomly determining the target kernel and traversing all operating frequencies of the target kernel, the actual operating conditions of the multi-core processor under test can be simulated, thereby improving the accuracy and reliability of stability testing of the multi-core processor under test.

[0034] Optionally, updating the current operating frequency of the target kernel includes:

[0035] The updated operating frequency is determined by sequentially traversing all operating frequencies supported by the multi-core processor under test.

[0036] The target kernel's current operating frequency is updated according to the specified update operating frequency.

[0037] The above-mentioned method of updating the current operating frequency of the target kernel can enable stability testing of all operating frequencies supported by the multi-core processor under test, thereby improving the reliability of stability testing.

[0038] Optionally, the termination condition for the multi-core processor stability test includes at least one of the following:

[0039] Current stability test information includes test failure information; or

[0040] The current test round has reached the set number of tests.

[0041] By setting termination conditions for multi-core processor stability testing, the testing time for different processors under test can be reasonably arranged, and the switching of operating frequencies too frequently can be prevented, which could cause equipment malfunctions and affect the normal use of the equipment under test in the later stages.

[0042] According to another aspect of the present invention, a multi-core processor stability testing apparatus is provided, comprising:

[0043] The pressure processing module is used to apply pressure to the multi-core processor under test using a target test program at the current operating frequency of the multi-core processor under test in the device under test.

[0044] The operating frequency update module is used to determine the target core from each processor core of the multi-core processor under test and update the current operating frequency of the target core when it is determined that the multi-core processor under test of the device under test has generated current stability test information.

[0045] The loop execution module is used to return to the operation of applying pressure to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test in the device under test, until the termination condition of the multi-core processor stability test is met.

[0046] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0047] At least one processor; and

[0048] A memory communicatively connected to the at least one processor; wherein,

[0049] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the multi-core processor stability testing method according to any embodiment of the present invention.

[0050] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the multi-core processor stability testing method according to any embodiment of the present invention.

[0051] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a flowchart of a multi-core processor stability testing method provided in an embodiment of the present invention;

[0054] Figure 2 This is a flowchart of another multi-core processor stability testing method provided in an embodiment of the present invention;

[0055] Figure 3 This is a flowchart illustrating a multi-core processor stability testing method provided in an embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram of a multi-core processor stability testing device provided in an embodiment of the present invention;

[0057] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0058] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0060] Figure 1 This is a flowchart of a multi-core processor stability testing method provided by an embodiment of the present invention. This embodiment is applicable to situations where the kernel operating frequency of a multi-core processor is updated to perform stability testing. This method can be executed by a multi-core processor stability testing device, which can be implemented in software and / or hardware, and is generally integrated into an electronic device. This electronic device can be a terminal device or a server device; the present invention does not limit the specific type of electronic device. Correspondingly, as... Figure 1 As shown, the method includes the following operations:

[0061] S110. At the current operating frequency of the multi-core processor under test in the device under test, the target test program is used to apply pressure to the multi-core processor under test.

[0062] The device under test (DUT) can be any type of device requiring stability testing of its internally installed processor, such as a terminal device or a server device. This embodiment of the invention does not limit the type of device under test. The multi-core processor under test can be a processor with multiple cores installed in the DUT, such as a CPU (Central Processing Unit) or GPU (Graphics Processing Unit). Optionally, the DUT may include multiple multi-core processors under test. The current operating frequency is the frequency used by the multi-core processor under test in its current operating state. The target test program can be a program used to perform stress testing on the multi-core processor.

[0063] In this embodiment of the invention, after determining the device under test (DUT), the current operating frequency of the multi-core processor under test in the DUT can be obtained. Then, at the current operating frequency of the multi-core processor under test, a target test program is used to apply pressure to the multi-core processor under test. To improve the reliability and accuracy of the stability test of the multi-core processor under test, optionally, the target test program can be used to apply different levels of pressure to the multi-core processor under test to simulate the workload of the multi-core processor under actual working conditions as closely as possible.

[0064] S120. If it is determined that the multi-core processor under test of the device under test generates current stability test information, a target core is determined from each processor core of the multi-core processor under test, and the current operating frequency of the target core is updated.

[0065] The current stability test information can be stability test information generated by stress testing the multi-core processor under test at its current operating frequency. This information can characterize whether the multi-core processor under test has passed the stability test at its current operating frequency. For example, it may include, but is not limited to, data on normal changes in processor load with stress testing, or log information generated by the multi-core processor under test during normal operation, as long as it reflects the test results indicating that the processor has passed the stability test. This embodiment of the invention does not limit the specific information content included in the current stability test information. The target kernel can be the kernel in the multi-core processor under test that needs to update its current operating frequency.

[0066] Accordingly, if it is determined that the multi-core processor under test (DUT) of the device under test (DUT) has generated current stability test information, it indicates that the DUT has passed the stability test at its current operating frequency and can operate normally at that frequency. At this point, stability testing of the DUT can continue. It is understandable that since the DUT's DUT has multiple cores, and in actual operation, not all cores are active, only under full load, all cores are active. Therefore, to effectively simulate the actual operation of the DUT's DUT, a target core can be selected from its cores, and only the target core's current operating frequency can be updated. It is understood that the target core can be some or all of the cores of the DUT. The updated operating frequency of the target core can be any frequency supported by the DUT. Updating the target core's current operating frequency effectively simulates the frequency adjustments made by the multi-core processor in response to actual computational load.

[0067] Accordingly, if it is determined that the multi-core processor under test (DUT) has not generated current stability test information—for example, if the DUT experiences a sudden increase in processor load after voltage testing, causing malfunctions in the processor's power supply chip—it indicates that the DUT has failed the stability test at its current operating frequency or the test was not performed. If it is determined that the stability test has failed, the stability test process needs to be terminated to protect the DUT. If it is determined that the stability test was not performed, the voltage testing process can be re-executed.

[0068] S130. Determine if the termination conditions for the multi-core processor stability test are met. If yes, proceed to S140; otherwise, return to S110.

[0069] S140. Terminate the stability test of the multi-core processor under test of the device under test.

[0070] The termination condition for the multi-core processor stability test can be pre-defined and can be determined based on the actual testing requirements and the working status of the equipment. This embodiment of the invention does not limit the specific content of the termination condition for the multi-core processor stability test.

[0071] Accordingly, after updating the current operating frequency of the target kernel, the stability test process can first be determined based on the multi-core processor stability test termination conditions to determine whether the current stability test process needs to be terminated. If it is determined that the multi-core processor stability test termination conditions are met, then the current stability test process needs to be terminated, and the stability test of the multi-core processor under test for the device under test can be terminated. Otherwise, if it is determined that the stability test process for the multi-core processor under test for the device under test needs to continue, the operation of applying pressure to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test can be returned to continue the stability test process.

[0072] Therefore, by selecting target kernels for the multi-core processor under test and updating the operating frequency of the target kernels, and applying pressure to different target kernels at different operating frequencies, the stability test of the multi-core processor under test can be achieved. This ensures that the actual working conditions of the multi-core processor under test are effectively simulated during the stability test, thereby improving the reliability and accuracy of the multi-core processor stability test.

[0073] This invention addresses the issues of low reliability and accuracy in existing processor stability testing methods by applying a target test program to the multi-core processor under test at its current operating frequency. If the multi-core processor under test generates current stability test information, a target core is identified from each processor core of the multi-core processor under test, and its current operating frequency is updated. This process continues iteratively until the multi-core processor stability test termination conditions are met. This improves the reliability and accuracy of multi-core processor stability testing.

[0074] Figure 2 This is a flowchart of another multi-core processor stability testing method provided by an embodiment of the present invention. This embodiment is based on the above embodiment and is further specified. In this embodiment, various specific optional implementation methods are given for performing pressure processing on the multi-core processor under test, determining the target kernel, and updating the current operating frequency of the target kernel. At the same time, the preliminary preparation operations before testing are also given. Correspondingly, as... Figure 2 As shown, the method in this embodiment may include:

[0075] S210. Obtain the power consumption information of each platform device according to the device configuration table.

[0076] The device configuration table can be a list of information configurations for devices on each platform. Essentially, one platform type can have one device configuration table, which can include the configuration information for all devices within that platform. During testing, you can focus on testing one platform at a time. After testing one platform is complete, you can switch to another platform for further testing.

[0077] Understandably, with the rapid development of high-tech industries such as artificial intelligence, cloud computing, and supercomputing centers, processor processing speeds are increasing, and the demands on processor performance are also rising. However, this dual improvement in speed and performance also leads to problems such as high energy consumption. Therefore, considering the need to reduce power consumption, the power consumption of the device under test (DUT) can be introduced during the stability testing of the DUT's multi-core processor to simultaneously achieve the goals of reducing power consumption and ensuring processor stability.

[0078] S220. Select the device to be tested from the platform devices based on the device power consumption information.

[0079] Specifically, before conducting stability testing, the device under test (DUT) can be determined based on power consumption. When determining the DUT, power consumption information for each platform can be obtained from the device configuration table. This power consumption information can then be used to select the DUT from among the platform devices. Optionally, the platform device with the highest power consumption can be selected as the DUT. In this way, once the DUT passes the stability test, the processors of other platform devices do not need to undergo repeated stability testing and can be assumed to have passed the stability test by default.

[0080] S230. Obtain the current operating frequency of the multi-core processor under test in the device under test and all operating frequencies supported by the multi-core processor under test.

[0081] Obtaining all operating frequencies supported by the multi-core processor under test can be used to determine the operating frequencies that the target core can be updated to, and to simulate the actual workload of the multi-core processor under test.

[0082] The above technical solution, by selecting the platform device with the highest power consumption as the device under test, and conducting stability tests on the multi-core processor of the device under test, can meet the power consumption requirements of each platform device.

[0083] S240. At the current operating frequency of the multi-core processor under test in the device under test, the target test program is used to apply pressure to the multi-core processor under test.

[0084] Accordingly, step S240 may specifically include the following operations:

[0085] S241. Determine at least one stability test procedure based on the platform type to which the device under test belongs.

[0086] The stability test program can be any type of test program applicable to the device under test, and can be used to pressurize the device under test for stability testing.

[0087] It is understandable that different platform types of the device under test (DUT) may result in different operating principles of the processors used, and consequently, different stability testing programs for stress testing. Therefore, it is necessary to determine at least one usable stability testing program based on the platform type of the DUT. That is, the multi-core processor stability testing method provided in this embodiment of the invention can be applied to multi-core processors provided by different architecture platforms for stability testing, thereby achieving cross-platform application.

[0088] For example, taking the CPU as a specific example, the platform type of the device under test (DUT) can be determined by querying the CPU model. For instance, the CPU platform of the DUT could be Intel, AMD (Advanced Micro Devices), Hygon, or other architecture platforms. The working principles of CPUs on different architecture platforms are not the same. Furthermore, each architecture platform has dedicated stress testing tools for its CPUs. For example, the stress testing tools provided by Intel can be used to stress test CPUs on Intel platforms, but cannot be used to test CPUs on AMD platforms.

[0089] S242. Randomly select one of the stability test programs as the target test program.

[0090] Accordingly, after identifying multiple available stability test programs for the device under test, one of them can be randomly selected as the target test program.

[0091] For example, assuming the stability test program includes stress test programs for single-precision, double-precision, and multi-precision linear equation systems, one of these stress test programs can be randomly selected as the target test program to modify the workload of the multi-core processor under test of the device under test.

[0092] S243. Generate a pressure sequence based on the actual operating data of the multi-core processor under test.

[0093] The actual operating data can be the operating data of the processor in its actual working state. The pressure sequence can be a sequence composed of multiple pressure values.

[0094] In this embodiment of the invention, optionally, after determining the target test program, in order to further ensure the accuracy of the stability test, the actual operating data of the multi-core processor under test can be obtained, and a corresponding pressure sequence can be generated based on the obtained actual operating data. Alternatively, the actual operating data can also be simulated in a random manner, that is, a series of pressure sequences can also be randomly generated. This embodiment of the invention does not limit the method of generating the pressure sequence.

[0095] In a specific example, a workload variation curve is generated based on the actual operating data of the multi-core processor under test on a certain day, and a corresponding stress-increasing sequence is generated based on the workload variation curve. Alternatively, a stress-increasing sequence can be generated randomly. For example, the stress-increasing sequence could be 10%, 80%, 50%, 100%, idle, 100%, 20%, 70%, 100%, and 30%, etc.

[0096] S244. The target test program is used to sequentially apply pressure to the multi-core processor under test according to the pressure sequence.

[0097] Accordingly, after determining the target test program and generating the pressure sequence, the target test program can be used to apply different levels of pressure to the multi-core processor under test according to the pressure values ​​in the pressure sequence.

[0098] The above technical solution, by randomly selecting the target test program, avoids using a single, fixed test program for stability testing of the multi-core processor under test, thereby improving the reliability of stability testing. Simultaneously, the application of a pressure sequence can effectively simulate the actual operating conditions of the processor, thus improving the accuracy of stability testing.

[0099] S250: Determine whether the multi-core processor under test of the device under test has generated current stability test information. If yes, execute S260; otherwise, execute S270.

[0100] Understandably, if the multi-core processor under test (DUT) does not generate current stability test information, it indicates that the test was not performed or failed at the current operating frequency. Therefore, the first step is to determine why the current stability test information was not generated. If the test was not performed at the current operating frequency, the process needs to return and execute at least one stability test program based on the platform type of the DUT until it is determined that the test was completed at the current operating frequency and current stability test information was generated. If the current test process meets the termination conditions for multi-core processor stability testing, such as failing the test at the current operating frequency or reaching the set test endpoint, then the stability test of the DUT's multi-core processor needs to be terminated.

[0101] S260. Determine the target core from each processor core of the multi-core processor under test, and update the current operating frequency of the target core.

[0102] In an optional embodiment of the present invention, the number of multi-core processors under test can be multiple; determining the target core from each processor core of the multi-core processors under test may include: sequentially traversing each of the multi-core processors under test, and taking all processor cores of the currently traversed multi-core processors under test as the target core; after determining that the traversal of the multi-core processors under test is complete, taking all processor cores of the multi-core processors under test as the target core. Updating the current operating frequency of the target core may include: sequentially traversing all operating frequencies supported by the multi-core processors under test to determine an updated operating frequency; and updating the current operating frequency of the target core according to the updated operating frequency.

[0103] Among them, the currently traversed multi-core processor under test can be the multi-core processor under test that is currently being traversed.

[0104] In a specific example, assuming the multi-core processor under test is a multi-core CPU, there are two CPUs, CPU1 and CPU2, each with 32 cores. All CPUs support the same operating frequency. The method for determining the target core from the cores of each processor under test can be as follows: First, using CPU1 as the current processor, all 32 cores of CPU1 are considered as target cores. Then, the entire range of operating frequencies supported by the processor under test is iterated to determine the currently available update frequency. The current operating frequency of the target core is then uniformly modified according to the available update frequency. During this process, the current operating frequency of CPU2 needs to remain unchanged. After the target core frequency is updated, the operation of applying pressure to the processor under test using the target test program at the current operating frequency of the processor under test can be repeated. After all cores of CPU1 have been iterated through to all operating frequencies supported by the multi-core processor under test, CPU2 is used as the current processor to be iterated through. All 32 cores of CPU2 are used as target cores, and the process iterates through all operating frequencies supported by the multi-core processor under test to determine the currently available update frequency. The current operating frequency of the target cores is then uniformly modified based on the available update frequency. During this process, the current operating frequency of CPU1 must remain unchanged. After the target core frequency is updated, the operation of applying stress to the multi-core processor under test using the target test program at its current operating frequency can be repeated. After all cores of both CPU1 and CPU2 have been iterated through to all operating frequencies supported by the multi-core processor under test, both CPU1 and CPU2 are used as target cores, and the process iterates through all operating frequencies supported by the multi-core processor under test to determine the currently available update frequency. The current operating frequency of the target cores is then uniformly modified based on the available update frequency. After the target core frequency is updated, the operation of applying stress to the multi-core processor under test using the target test program at its current operating frequency can be repeated.

[0105] The above technical solution provides a usable method for determining the target kernel. By traversing the target kernel sequentially, all processor kernels can be traversed at all operating frequencies, simulating all operating conditions of the multi-core processor under test, thereby improving the accuracy and reliability of stability testing of the multi-core processor under test.

[0106] In an optional embodiment of the present invention, the number of the multi-core processors under test can be multiple; the multi-core processors under test can include multiple DIEs; determining the target kernel from each processor core of the multi-core processor under test can include: sequentially traversing the DIEs of each multi-core processor under test, and taking all processor cores of the currently traversed DIE of the multi-core processor under test as the target kernel; after determining that the DIE traversal of the multi-core processor under test is completed, taking the processor cores of all DIEs of the multi-core processor under test as the target kernel.

[0107] The currently traversed DIE can be the DIE currently being traversed in the multi-core processor under test.

[0108] In a specific example, assume the multi-core processor under test is a multi-core CPU, consisting of two CPUs: CPU1 and CPU2. Each CPU has four DIEs (DIE1, DIE2, DIE3, and DIE4), and each DIE has eight cores, resulting in 32 cores per CPU. All CPUs support the same operating frequency. The method for determining the target core from the cores of each processor under test is as follows: First, use CPU1 as the current processor to iterate through the multi-core processors under test. Then, use the eight cores of CPU1's DIE1 as the target cores. Iterate through all the operating frequencies supported by the multi-core processor under test to determine the currently available update frequencies. Modify the current operating frequency of the target cores accordingly. During this process, the current operating frequency of CPU2 must remain unchanged. After updating the target core frequency, the operation of applying pressure to the multi-core processor under test using the target test program at its current operating frequency can be repeated. Next, the eight cores of DIE2 of CPU1 are used as target cores, and the above operation is repeated on the target cores until all four DIEs of CPU1 have been traversed.

[0109] After all cores in all DIEs of CPU1 have been iterated through to all operating frequencies supported by the multi-core processor under test, CPU2 is used as the current multi-core processor to be iterated through. The eight cores of DIE1 in CPU2 are used as target cores, and the entire range of operating frequencies supported by the multi-core processor under test is iterated through sequentially to determine the currently available update frequencies. The current operating frequency of the target cores is then uniformly modified according to the available update frequencies. During this process, the current operating frequency of CPU1 must remain unchanged. After the target core frequency is updated, the operation of applying voltage to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test can be repeated. Then, the eight cores of DIE2 in CPU2 are used as target cores, and the above operation is repeated for the target cores until all four DIEs of CPU2 have been iterated through.

[0110] After all cores in all DIEs of CPU1 and CPU2 have been iterated through to all operating frequencies supported by the multi-core processor under test, the cores of all DIEs of CPU1 and CPU2 are used as target cores. The entire range of operating frequencies supported by the multi-core processor under test is then iterated through to determine the currently available update frequency. The current operating frequency of the target core is then uniformly modified based on the available update frequency. After the target core frequency is updated, the operation of applying voltage to the multi-core processor under test using the target test program at its current operating frequency can be repeated.

[0111] The above technical solution provides a usable method for determining the target kernel based on DIE. By sequentially traversing the kernels of the DIE to determine the target kernel, all DIEs of the processor can be traversed at all operating frequencies, which can simulate all operating conditions of the DIEs of the multi-core processor under test, thereby improving the accuracy and reliability of stability testing of the multi-core processor under test.

[0112] In an optional embodiment of the present invention, the number of multi-core processors under test is multiple; determining the target core from each processor core of the multi-core processors under test may include: sequentially traversing each of the multi-core processors under test, randomly selecting a portion of processor cores of the currently traversed multi-core processors under test as the target core; after determining that the traversal of the multi-core processors under test is completed, randomly selecting a portion of processor cores of each multi-core processor under test as the target core. Updating the current operating frequency of the target core may include: sequentially traversing all operating frequencies supported by the multi-core processors under test to determine an updated operating frequency; updating the current operating frequency of the target core according to the updated operating frequency.

[0113] In a specific example, assuming the multi-core processor under test is a multi-core CPU, there are two CPUs, CPU1 and CPU2, each with 32 cores. All CPUs support the same operating frequency. The method for determining the target core from the cores of each processor under test is as follows: First, using CPU1 as the current processor to iterate through the multi-core processors under test, randomly select a subset of cores from CPU1 as target cores. Then, iterate through all the operating frequencies supported by the multi-core processors under test to determine the currently available update frequencies. Modify the current operating frequency of the target cores uniformly according to the available update frequencies. During this process, the current operating frequency of CPU2 must remain unchanged. After the target core frequency is updated, the operation of applying pressure to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test can be repeated. After CPU1 has iterated through all the operating frequencies supported by the multi-core processor under test, CPU2 is used as the current processor to be iterated through. A subset of cores is randomly selected from CPU2 as target cores, and the process iterates through all the operating frequencies supported by the multi-core processor under test to determine the currently available update frequencies. The current operating frequency of the target cores is then uniformly modified based on these available update frequencies. Throughout this process, the current operating frequency of CPU1 must remain unchanged. After the target core frequency is updated, the operation of applying pressure to the multi-core processor under test using the target test program at its current operating frequency can be repeated. (This process is repeated for both CPU1 and CPU2.)

[0114] The above technical solution provides another available method for determining the target kernel. By randomly determining the target kernel and traversing all operating frequencies of the target kernel, the actual operating conditions of the multi-core processor under test can be simulated, thereby improving the accuracy and reliability of stability testing of the multi-core processor under test.

[0115] S270. Determine whether the termination conditions for the multi-core processor stability test are met. If yes, execute S280; otherwise, return to execute S242.

[0116] In an optional embodiment of the present invention, the termination condition for the multi-core processor stability test may include at least one of the following: the current stability test information includes test failure information; or, the current test round has reached the set number of tests.

[0117] The test failure information may include abnormalities in the device under test (DUT), such as overcurrent protection failure or even damage to the voltage regulator (VR) chip of the multi-core processor under test, or probabilistic crashes or failure to power on. It may also include abnormalities such as stress test results failing to meet test standards and error messages in the logs. This embodiment of the invention does not limit the specific types and content of abnormal problems. The number of test cycles can be set according to actual test requirements or the operating status of the DUT.

[0118] Optionally, the number of tests can be set as the quotient of the set test time and the time of a single test. For example, assuming the device under test requires 0.5 hours to test once, and the set test time is 24 hours, then the number of tests can be set to 48.

[0119] By setting termination conditions for multi-core processor stability testing, the testing time for different processors under test can be reasonably arranged, and the switching of operating frequencies too frequently can be prevented, which could cause equipment malfunctions and affect the normal use of the equipment under test in the later stages.

[0120] S280, terminate the stability test of the multi-core processor under test of the device under test.

[0121] Figure 3 This is a flowchart illustrating a multi-core processor stability testing method provided by an embodiment of the present invention. To more clearly illustrate the technical solution provided by this embodiment, in a specific example, a server is used as the device under test, and the CPU is used as the multi-core processor under test on the server. An automated test script is used to automatically execute the stability test program, such as... Figure 3 As shown, the technical solution provided by the embodiments of the present invention may include the following specific processes:

[0122] Step 1: Select the device with the highest power consumption in the test configuration as the device under test based on the server configuration table using an automated test script.

[0123] Step 2: Input script commands and the number of test cycles into the automated test script. The script commands can be used to trigger subsequent test processes.

[0124] Step 3: The automated test script automatically determines the platform used by the device under test to identify the type of CPU currently in the device under test.

[0125] Step 4: The automated test script obtains the current CPU operating frequency and all supported operating frequencies through instructions.

[0126] For example, an automated test script can obtain the operating frequency supported by the CPU under test from the current CPU's registers via instructions.

[0127] Step 5: The automated test script randomly uses single-precision, double-precision, and multi-precision linear equation system test programs at the current operating frequency to apply different levels of stress to all CPUs, such as 10%, 80%, 50%, 100%, idle, 100%, 20%, 70%, 100%, and 30%, to achieve CPU operation stress test. During the test, check whether the device under test will exhibit abnormal phenomena such as overcurrent protection or even damage to the VR chip due to a sudden increase in CPU loading.

[0128] Step Six: Output Test Results. Optionally, the test results can be output as a test report. If the test result is abnormal, it indicates that the test has failed, and the test can be terminated. If the test result is empty, such as no corresponding test report is generated, you can return to Step Five. If the test is confirmed to have passed, you can continue to Step Seven.

[0129] Step 7: Use an automated test script to modify the operating frequency of all CPUs and individual DIEs sequentially. After each frequency modification, repeat step 5. Once the iteration is complete, proceed to step 8.

[0130] For example, assuming the device under test has two processors, CPU1 and CPU2, each with two DIEs and eight cores, the operating frequencies of all CPUs and individual DIEs can be modified sequentially. Specifically, modifying the operating frequencies of all CPUs sequentially can be done as follows: Iterate through the CPUs, updating the current operating frequency of all 16 cores of CPU1, while leaving the current operating frequency of CPU2 unchanged. Then iterate through CPU2, updating the current operating frequency of all 16 cores of CPU2, while leaving the current operating frequency of CPU1 unchanged. Finally, simultaneously update the current operating frequency of all cores of both CPU1 and CPU2. Similarly, modifying the operating frequency of individual DIEs can be done as follows: Iterate through the CPUs, updating the current operating frequency of all eight cores of DIE1 of CPU1, while leaving the current operating frequencies of DIE2 of CPU1 and CPU2 unchanged. Then iterate through all eight cores of DIE2 of CPU1, updating the current operating frequency of DIE1 of CPU1 and CPU2 unchanged. Furthermore, iterate through CPU2, updating the current operating frequency of all 8 cores in DIE1 of CPU2 sequentially, while keeping the current operating frequencies of DIE2 of CPU2 and CPU1 unchanged. Then, iterate through all 8 cores in DIE2 of CPU2 sequentially, updating their current operating frequencies, while keeping the current operating frequencies of DIE1 of CPU2 and CPU1 unchanged. Finally, iterate through all cores in all DIEs of both CPU1 and CPU2 simultaneously, updating their current operating frequencies sequentially.

[0131] Step 8: After completing the CPU traversal and all operating frequency traversals and performing the voltage increase process, the operating frequency of the cores under each DIE within the CPU is traversed and modified in a random manner. After each operating frequency modification is completed, Step 5 is repeated. After the traversal is completed, Step 9 can be executed.

[0132] Specifically, the operation of randomly modifying the operating frequency of the cores under each DIE within the CPU can be performed as follows: A few cores from the 32 cores of CPU1 are randomly selected and their current operating frequencies are modified uniformly, while the current operating frequency of CPU2 remains unchanged. Then, a few cores from the 32 cores of CPU2 are randomly selected and their current operating frequencies are modified uniformly, while the current operating frequency of CPU1 remains unchanged. Finally, a few cores from all cores of both CPU1 and CPU2 are randomly selected and their current operating frequencies are modified uniformly.

[0133] It is understandable that randomly selecting a kernel is equivalent to randomly selecting a DIE. For example, suppose the randomly selected kernels are kernel 1 and kernel 10 of CPU1, and kernel 1 of CPU1 belongs to DIE1 of CPU1, and kernel 10 of CPU1 belongs to DIE2 of CPU1, then it is equivalent to randomly selecting kernel 1 of DIE1 of CPU1 and kernel 10 of DIE2.

[0134] Step 9: Output the current test result and determine whether the test passed. If the test passed, proceed to Step 10; otherwise, end the test.

[0135] Step 10: Determine if the current number of execution cycles has reached the set number of cycles. If it has, proceed to Step 11; otherwise, return to Step 7.

[0136] Step 11: Output a summary test report. Test complete.

[0137] It should be noted that in the above scheme, steps seven and eight can be performed separately to achieve frequency switching, or the two steps can be performed sequentially. When the two steps are performed sequentially, the order of execution is not restricted. Furthermore, after each modification of the operating frequency, step ten can be executed to determine whether the stability test process needs to be terminated; this embodiment of the invention does not impose any restrictions on this.

[0138] In the above technical solution, the entire stability testing process can be fully automated, thereby saving manpower and time. At the same time, the stability testing method can realistically simulate the processor's usage in real-world scenarios and covers multiple platforms, thus improving the reliability, accuracy, and applicability of the stability test.

[0139] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0140] Figure 4 This is a schematic diagram of a multi-core processor stability testing device provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the device includes: a pressurization processing module 310, a working frequency update module 320, and a loop execution module 330, wherein:

[0141] The pressure processing module 310 is used to apply pressure to the multi-core processor under test using a target test program at the current operating frequency of the multi-core processor under test in the device under test.

[0142] The operating frequency update module 320 is used to determine the target core from each processor core of the multi-core processor under test and update the current operating frequency of the target core when it is determined that the multi-core processor under test of the device under test has generated current stability test information.

[0143] The loop execution module 330 is used to return to the operation of applying pressure to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test in the device under test, until the termination condition of the multi-core processor stability test is met.

[0144] This invention addresses the issues of low reliability and accuracy in existing processor stability testing methods by applying a target test program to the multi-core processor under test at its current operating frequency. If the multi-core processor under test generates current stability test information, a target core is identified from each processor core of the multi-core processor under test, and its current operating frequency is updated. This process continues iteratively until the multi-core processor stability test termination conditions are met. This improves the reliability and accuracy of multi-core processor stability testing.

[0145] Optionally, the multi-core processor stability testing device may further include a working frequency acquisition module, used for: acquiring device power consumption information of each platform device according to the device configuration table; filtering the device under test from the platform devices according to the device power consumption information; and acquiring the current working frequency of the multi-core processor under test in the device under test and all working frequencies supported by the multi-core processor under test.

[0146] Optionally, the pressure processing module 310 is specifically used for: determining at least one stability test program according to the platform type of the device under test; randomly selecting one of the stability test programs as the target test program; generating a pressure sequence according to the actual running data of the multi-core processor under test; and using the target test program to sequentially perform pressure processing on the multi-core processor under test according to the pressure sequence.

[0147] Optionally, the number of multi-core processors under test is multiple; the working frequency update module 320 is specifically used to: sequentially traverse each of the multi-core processors under test, and take all processor cores of the currently traversed multi-core processors under test as the target core; after determining that the traversal of the multi-core processors under test is completed, take all processor cores of the multi-core processors under test as the target core.

[0148] Optionally, the number of multi-core processors under test is multiple; the multi-core processors under test include multiple DIEs; the operating frequency update module 320 is specifically used to: sequentially traverse the DIEs of each multi-core processor under test, and take all processor cores of the currently traversed DIE of the multi-core processor under test as the target core; after determining that the DIE traversal of the multi-core processor under test is completed, take the processor cores of all DIEs of the multi-core processor under test as the target core.

[0149] Optionally, the number of multi-core processors under test is multiple; the working frequency update module 320 is specifically used to: sequentially traverse each of the multi-core processors under test, randomly select a portion of the processor cores of the currently traversed multi-core processors under test as the target cores; after determining that the traversal of the multi-core processors under test is completed, randomly select a portion of the processor cores of each of the multi-core processors under test as the target cores.

[0150] Optionally, the operating frequency update module 320 is specifically used to: sequentially traverse all operating frequencies supported by the multi-core processor under test to determine the updated operating frequency; and update the current operating frequency of the target core according to the updated operating frequency.

[0151] Optionally, the termination condition for the multi-core processor stability test includes at least one of the following: the current stability test information includes test failure information; or, the current test round reaches the set number of tests.

[0152] The aforementioned multi-core processor stability testing device can execute the multi-core processor stability testing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the multi-core processor stability testing method provided in any embodiment of the present invention.

[0153] Figure 5 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0154] like Figure 5As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0155] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0156] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as multi-core processor stability testing methods.

[0157] In some embodiments, the multi-core processor stability testing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the multi-core processor stability testing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the multi-core processor stability testing method by any other suitable means (e.g., by means of firmware).

[0158] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0159] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0160] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0161] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0162] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0163] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0164] This invention also provides a computer storage medium for storing a computer program, which, when executed by a computer processor, performs the multi-core processor stability testing method described in any of the above embodiments of this invention: At the current operating frequency of the multi-core processor under test in the device under test, a target test program is used to apply pressure to the multi-core processor under test; when it is determined that the multi-core processor under test in the device under test generates current stability test information, a target core is determined from each processor core of the multi-core processor under test, and the current operating frequency of the target core is updated; the operation of applying pressure to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test in the device under test is returned to until the multi-core processor stability test termination condition is met.

[0165] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM, or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0166] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0167] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, radio frequency (RF), or any suitable combination thereof.

[0168] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0169] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0170] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for testing the stability of a multi-core processor, characterized in that, include: At the current operating frequency of the multi-core processor under test in the device under test, the target test program is used to apply pressure to the multi-core processor under test. If it is determined that the multi-core processor under test of the device under test generates current stability test information, a target core is determined from each processor core of the multi-core processor under test, and the current operating frequency of the target core is updated; wherein, the target core is some or all of the cores of the multi-core processor under test. Return to the current operating frequency of the multi-core processor under test in the device under test, and use the target test program to apply pressure to the multi-core processor under test until the stability test termination condition of the multi-core processor is met; The step of applying pressure to the multi-core processor under test using a target test program at the current operating frequency of the processor under test includes: Determine at least one stability test procedure based on the platform type to which the device under test belongs; Randomly select one of the stability test programs as the target test program; A pressure sequence is generated based on the actual operating data of the multi-core processor under test; The target test program is used to sequentially apply pressure to the multi-core processor under test according to the pressure sequence. The number of multi-core processors under test is multiple; The step of determining the target core from each processor core of the multi-core processor under test includes: Each of the multi-core processors under test is traversed sequentially, and a portion of the processor cores of the currently traversed multi-core processors under test are randomly selected as the target cores. After the multi-core processor under test has been traversed, a portion of the processor cores of each multi-core processor under test are randomly selected as the target cores. Before applying the target test program to the multi-core processor under test, the method further includes: Obtain the power consumption information of each platform device based on the device configuration table; The device to be tested is selected from the platform devices based on the device power consumption information; Obtain the current operating frequency of the multi-core processor under test in the device under test and all operating frequencies supported by the multi-core processor under test; The step of selecting the device to be tested from the platform devices based on the device power consumption information includes: selecting the platform device with the highest power consumption as the device to be tested.

2. The method according to claim 1, characterized in that, The number of multi-core processors under test is multiple; the step of determining the target core from each processor core of the multi-core processors under test includes: Each of the multi-core processors under test is traversed sequentially, and all processor cores of the currently traversed multi-core processors under test are taken as the target core; After the multi-core processor under test has been traversed, all processor cores of the multi-core processor under test are taken as the target core.

3. The method according to claim 1, characterized in that, The number of multi-core processors under test is multiple; the multi-core processors under test include multiple chip DIEs; determining the target core from each processor core of the multi-core processor under test includes: The DIEs of each multi-core processor under test are traversed sequentially, and all processor cores of the currently traversed DIE of the multi-core processor under test are taken as the target core. After the DIE traversal of the multi-core processor under test is completed, the processor cores of all DIEs of the multi-core processor under test are taken as the target core.

4. The method according to any one of claims 2-3, characterized in that, Updating the current operating frequency of the target kernel includes: The updated operating frequency is determined by sequentially traversing all operating frequencies supported by the multi-core processor under test. The target kernel's current operating frequency is updated according to the specified update operating frequency.

5. A multi-core processor stability testing device, characterized in that, include: The pressure processing module is used to apply pressure to the multi-core processor under test using a target test program at the current operating frequency of the multi-core processor under test in the device under test. The operating frequency update module is used to determine a target core from each processor core of the multi-core processor under test and update the current operating frequency of the target core when it is determined that the multi-core processor under test of the device under test has generated current stability test information; wherein, the target core is some or all of the cores of the multi-core processor under test. The loop execution module is used to return to the operation of applying pressure to the multi-core processor under test using the target test program at the current operating frequency of the multi-core processor under test in the device under test, until it is determined that the multi-core processor stability test termination condition is met; Specifically, the pressurization processing module is used to determine at least one stability test program based on the platform type to which the device under test belongs. Randomly select one of the stability test programs as the target test program; A pressure sequence is generated based on the actual operating data of the multi-core processor under test; The target test program is used to sequentially apply pressure to the multi-core processor under test according to the pressure sequence. The number of multi-core processors under test is multiple; The working frequency update module is specifically used to sequentially traverse each of the multi-core processors under test, randomly select a portion of the processor cores of the currently traversed multi-core processors under test as the target cores; after determining that the traversal of the multi-core processors under test is completed, select a portion of the processor cores of each of the multi-core processors under test as the target cores; The operating frequency acquisition module is used to acquire the device power consumption information of each platform device according to the device configuration table; to filter the device under test from the platform devices according to the device power consumption information; and to acquire the current operating frequency of the multi-core processor under test in the device under test and all operating frequencies supported by the multi-core processor under test. The operating frequency acquisition module is specifically used to: select the platform device with the highest power consumption as the device to be tested.

6. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the multi-core processor stability testing method according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause the processor to execute the multi-core processor stability testing method according to any one of claims 1-4.

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