A signal conflict verification method, device, equipment and storage medium
By using real-time monitoring and signal priority adjustment, the problem of untimely signal conflict detection in chip verification was solved, improving the accuracy and troubleshooting efficiency of signal conflict verification and enabling timely feedback of abnormal information.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUNAN GOKE MICROELECTRONICS CO LTD
- Filing Date
- 2023-03-06
- Publication Date
- 2026-06-16
AI Technical Summary
In chip verification, the feedback of functional abnormalities at test points of complex control modules is not timely, the efficiency of logic troubleshooting is low, and existing technologies are unable to effectively detect signal conflicts and provide timely feedback of abnormal information.
By monitoring the internal signal conflicts of the SRAM module under test in real time, filtering out target signals with low priority, accumulating the number of times they are back-pressed, adjusting the signal priority when the threshold is reached, and using assertion to perform testing, abnormal information is fed back in a timely manner.
It improves the accuracy and error-detection rate of signal conflict verification, ensures that the function operation is consistent with expectations, and promptly detects and handles abnormal situations.
Smart Images
Figure CN116302744B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification, and in particular to a signal collision verification method, apparatus, device, and storage medium. Background Technology
[0002] In chip verification, the main tasks are data comparison and functional verification of the module under test. A common checking mechanism is to collect data from the output of the SRAM (Static Random Access Memory) of the module under test and compare the collected data with the output data of a functionally consistent reference model. While this checking mechanism can meet the verification requirements of most functional modules, for modules with complex controls, it is prone to delayed feedback or even false passes when functional anomalies occur at the test points of interest. Furthermore, the logic debugging efficiency of the SRAM module under test needs improvement. Summary of the Invention
[0003] In view of this, the purpose of this invention is to provide a signal conflict verification method, apparatus, device, and storage medium that can avoid continuously performing corresponding operations on high-priority signals by real-time monitoring of internal signal conflicts, and improve the error correction rate of signal conflict verification by testing preset control signals through assertion and timely feedback of abnormal information. The specific solution is as follows:
[0004] Firstly, this application provides a signal collision verification method, including:
[0005] Acquire the internal conflict signal generated when both write and read request clients simultaneously access the SRAM module under test;
[0006] Using the initial mapping relationship and the access mode corresponding to the signal, the priority of each signal in the internal conflict signals is determined and the target signal with low priority is filtered out.
[0007] Determine whether the target operation corresponding to the target signal is being reverse-pressurized. If so, accumulate the number of times it is reverse-pressurized to obtain a first reverse-pressurization count value.
[0008] Monitor whether the first back pressure count value reaches the preset back pressure number threshold. If so, trigger the preset adjustment process for the initial mapping relationship when the preset control signal is at the rising edge, and perform an assertion test on whether the preset control signal has been pulled high and maintained for the preset number of beats.
[0009] If the assertion test result is yes, it indicates that the preset adjustment process has been completed; if the assertion test result is no, the corresponding assertion error is reported.
[0010] Optionally, determining whether the target operation corresponding to the target signal is being reverse-pressurized includes:
[0011] When the target signal is high, it is determined whether the current target associated signal is high; the target associated signal corresponds to the same access mode as the target signal.
[0012] If the target-associated signal is currently high, it is determined that the target operation corresponding to the target signal is being reverse-pressurized.
[0013] Optionally, the step of accumulating and counting the number of back pressures to obtain a first back pressure count value includes:
[0014] The first back pressure count value is obtained by accumulating and counting the number of times the back pressure is applied using a preset first counter in the verification environment; the verification environment is an environment used to verify the SRAM module under test.
[0015] Optionally, after determining whether the target operation corresponding to the target signal is being reverse-pressurized, the method further includes:
[0016] If not reverse-pressurized, the first counter is cleared and the process jumps back to the step of determining whether the target operation corresponding to the target signal is reverse-pressurized.
[0017] Optionally, after accumulating and counting the number of back pressures to obtain a first back pressure count value, the method further includes:
[0018] The system monitors whether the first back voltage count value, calculated by the first counter, is consistent with the second back voltage count value, calculated by the second counter within the SRAM module under test. The second counter is used to accumulate and count the number of times the system experiences back voltage to obtain the second back voltage count value.
[0019] If there is a discrepancy, an assertion error will be reported through the verification environment.
[0020] If they match, then the step of triggering the assertion error through the verification environment is prohibited.
[0021] Optionally, after monitoring whether the first back pressure count value reaches a preset back pressure count threshold, the method further includes:
[0022] If the target is not reached, the process jumps back to the step of determining whether the target operation corresponding to the target signal is being reverse-pressurized.
[0023] Optionally, the preset adjustment process includes:
[0024] The initial mapping relationship is flipped for the first time to obtain the flipped mapping relationship. The target operation is then performed within the time period corresponding to the preset number of beats. A second flip operation is triggered when the preset control signal is at the falling edge to restore the flipped mapping relationship to the initial mapping relationship.
[0025] Secondly, this application provides a signal collision verification device, comprising:
[0026] The conflict signal acquisition module is used to acquire internal conflict signals generated when the write request end and the read request end simultaneously access the SRAM module under test.
[0027] The target signal filtering module is used to determine the priority of each signal in the internal conflict signals and filter out the target signals with low priority by using the initial mapping relationship and the access mode corresponding to the signal.
[0028] The count module is used to determine whether the target operation corresponding to the target signal is being reverse-pressurized. If so, the count of reverse-pressurization is accumulated to obtain the first reverse-pressurization count value.
[0029] The assertion test module is used to monitor whether the first back pressure count value reaches the preset back pressure number threshold. If so, it triggers the preset adjustment process for the initial mapping relationship when the preset control signal is at the rising edge, and performs an assertion test on whether the preset control signal has been pulled high and maintained for a preset number of beats.
[0030] The assertion error reporting module is used to indicate that the preset adjustment process has been completed if the assertion test result is yes; and to report the corresponding assertion error if the assertion test result is no.
[0031] Thirdly, this application provides an electronic device, comprising:
[0032] Memory, used to store computer programs;
[0033] A processor is used to execute the computer program to implement the aforementioned signal conflict verification method.
[0034] Fourthly, this application provides a computer-readable storage medium for storing a computer program that, when executed by a processor, implements the aforementioned signal conflict verification method.
[0035] In this application, internal conflict signals generated when a write request and a read request simultaneously access the SRAM module under test are acquired; using the initial mapping relationship and the access mode corresponding to the signal, the priority of each signal in the internal conflict signals is determined and the target signal with low priority is filtered out; it is determined whether the target operation corresponding to the target signal is being reverse-pressurized, and if so, the number of reverse-pressurizations is accumulated to obtain a first reverse-pressurization count value; it is monitored whether the first reverse-pressurization count value reaches a preset reverse-pressurization count threshold, and if so, a preset adjustment process for the initial mapping relationship is triggered when the preset control signal is at the rising edge, and an assertion test is performed to determine whether the preset control signal has been pulled high and maintained for a preset number of ticks; if the assertion test result is yes, it indicates that the preset adjustment process has been completed; if the assertion test result is no, a corresponding assertion error is reported. Therefore, this application monitors the internal conflict signals generated when the write request end and read request end simultaneously access the SRAM module under test in real time, and accumulates the number of times the target signal with low priority is reverse-pressed. When the number of reverse-pressed times reaches a preset reverse-pressed number threshold, the priority of the target signal is adjusted accordingly by adjusting the preset control signal, thereby avoiding continuously executing the corresponding functional operation for the signal with high priority in the initial mapping relationship. In addition, this application tests the preset control signal by assertion. When the assertion test result is negative, it indicates that the preset control signal is not pulled high and maintained for the preset number of beats as expected, that is, the priority of the target signal is not adjusted accordingly as expected. This can easily lead to the current functional operation being inconsistent with the expected functional operation. By using assertion error reporting, abnormal information can be fed back in real time, improving the accuracy of signal conflict verification and the error debugging rate. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0037] Figure 1 This is a flowchart of a signal conflict verification method disclosed in this application;
[0038] Figure 2 This is a schematic diagram of a signal conflict disclosed in this application;
[0039] Figure 3 This application discloses a flowchart for signal conflict verification.
[0040] Figure 4 This is a schematic diagram of the structure of a signal collision verification device disclosed in this application;
[0041] Figure 5 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0043] Currently, for complex control modules, when functional abnormalities occur at the test points of interest, feedback is often delayed or even false positives occur. Furthermore, the logic debugging efficiency of the SRAM module under test needs improvement. To address this, this application provides a signal conflict verification method. By monitoring the internal signal conflicts of the SRAM module under test in real time, it avoids continuously performing operations on high-priority signals. It also tests preset control signals using assertions, providing timely feedback on abnormal information and improving the accuracy and debugging rate of signal conflict verification.
[0044] See Figure 1 As shown in the figure, an embodiment of the present invention discloses a signal collision verification method, including:
[0045] Step S11: Obtain the internal conflict signal generated when the write request end and the read request end simultaneously access the SRAM module under test.
[0046] In this embodiment, as Figure 2 As shown, the SRAM chip under test is divided into 16 small SRAM regions, each called a bank, and each bank is a single SRAM module under test. Within each SRAM module under test, only one operation—either read or write—can be performed per clock cycle. When both read and write requests access the SRAM module simultaneously, both read and write signals will be received concurrently. This results in a signal conflict when both the read signal (wvalid) and the write signal (rvalid) are present.
[0047] Step S12: Using the initial mapping relationship and the access mode corresponding to the signal, determine the priority of each signal in the internal conflict signals and filter out the target signal with low priority.
[0048] In this embodiment, when both read and write signals are received simultaneously, the target signal with lower priority needs to be determined from the read and write signals based on the priority configuration of the internal logic. Specifically, an initial mapping relationship is pre-constructed based on access modes and priorities. Different access modes correspond to different priorities, where access modes include read and write modes. Using the initial mapping relationship and the access modes corresponding to the read and write signals respectively, the priorities corresponding to the read and write signals are determined, and the signal with lower priority is selected as the target signal. Meanwhile, for signals with higher priority, the corresponding functional operation can be executed. For example, if the read mode has a higher priority and the write mode has a lower priority in the initial mapping relationship, then by combining the access modes corresponding to the read and write signals respectively, it can be determined that the read signal has a higher priority and the write signal has a lower priority; in this case, the write signal is the target signal. For the high-priority read signal, the read function operation corresponding to the read signal can be executed.
[0049] Step S13: Determine whether the target operation corresponding to the target signal is being reverse-pressed. If so, accumulate the number of times it is reverse-pressed to obtain the first reverse-pressed count value.
[0050] In this embodiment, after the target signal is determined, it is necessary to further determine whether the target operation corresponding to the target signal is being suppressed, that is, whether there is a situation where the target signal is received but the target operation corresponding to the target signal is not allowed to be executed.
[0051] Specifically, upon receiving the target signal (i.e., when the target signal is high), it is further determined whether the current target-related signal is high. This target-related signal corresponds to the same access mode as the target signal. If the current target-related signal is high, it is determined that the target operation corresponding to the target signal is being reverse-pressurized. It should be noted that when the current target-related signal is high, it indicates that the target operation corresponding to the target signal is not allowed to be executed, meaning the target operation corresponding to the target signal is being reverse-pressurized. If the target operation corresponding to the target signal is being reverse-pressurized, the number of reverse-pressurizations is accumulated using a preset first counter within the verification environment to obtain a first reverse-pressurization count value. The initial value of the first counter is 0. The verification environment is used to verify the SRAM module under test. It can be understood that each time a target signal arrives but the target operation corresponding to the target signal is not allowed to be executed, the first counter within the verification environment will increment by one to obtain the first reverse-pressurization count value.
[0052] In this embodiment, if the target signal is high and the current target-related signal is low, it indicates that the target operation corresponding to the target signal is currently allowed to be executed, that is, the target operation corresponding to the target signal is not being reverse-suppressed. If it is not reverse-suppressed, the preset first counter in the verification environment is cleared, and the process jumps back to the step of determining whether the target operation corresponding to the target signal is being reverse-suppressed.
[0053] Step S14: Monitor whether the first back pressure count value reaches the preset back pressure number threshold. If so, trigger the preset adjustment process for the initial mapping relationship when the preset control signal is at the rising edge, and perform an assertion test on whether the preset control signal has been pulled high and maintained for the preset number of beats.
[0054] In this embodiment, the first back-voltage count value, calculated by a preset first counter within the verification environment, is compared with a pre-configured threshold for the number of back-voltage occurrences. If the first back-voltage count value does not reach the preset threshold, the process jumps back to the step of determining whether the target operation corresponding to the target signal is back-voltaged. If the first back-voltage count value reaches the preset threshold, the preset control signal is adjusted through the SRAM module under test. That is, when the preset control signal is at its rising edge, a preset adjustment process for the initial mapping relationship is triggered through the SRAM module under test, and an assertion test is performed in the verification environment to determine whether the preset control signal has been pulled high and maintained for a preset number of beats. The preset number of beats can be set by the user according to their own needs. The preset adjustment process includes performing a first flip operation on the initial mapping relationship to obtain the flipped mapping relationship, performing the corresponding target operation within the time period corresponding to the preset number of beats, and then triggering a second flip operation when the preset control signal is at its falling edge to restore the flipped mapping relationship to the initial mapping relationship. It should be noted that if the preset number of cycles is one cycle, when the preset control signal is on its rising edge, the correspondence between access mode and priority in the initial mapping will be toggled once, resulting in a toggled mapping. Simultaneously, the target operation corresponding to the target signal will be executed during the time period corresponding to the one cycle. When the one cycle ends, the preset control signal will automatically go low, and when the preset control signal is on its falling edge, the correspondence between access mode and priority in the toggled mapping will be toggled again to restore the toggled mapping to the initial mapping. In this way, by toggling the mapping between access mode and priority, the function operation corresponding to the higher priority signal in the initial mapping can be avoided.
[0055] In this embodiment, after accumulating the number of backpressure events to obtain a first backpressure count value, the method may further include monitoring whether the first backpressure count value counted by a first counter is consistent with the second backpressure count value counted by a second counter within the SRAM module under test. The second counter is used to accumulate the number of backpressure events to obtain the second backpressure count value. If they are inconsistent, an assertion error is reported through the verification environment; if they are consistent, the step of reporting an assertion error through the verification environment is prohibited. It is understood that by comparing the first backpressure count value and the second backpressure count value, an assertion error can be reported through the verification environment when they are inconsistent. In this way, by comparing the first backpressure count value in the verification environment with the second backpressure count value in the SRAM module under test in real time, missed detections and false alarms of abnormal situations can be avoided.
[0056] Step S15: If the assertion test result is yes, it indicates that the preset adjustment process has been completed; if the assertion test result is no, the corresponding assertion error is reported.
[0057] In this embodiment, if the assertion test result is yes, it indicates that the preset control signal is pulled high and maintained for the preset number of beats as expected, and the currently executed function operation is consistent with the expected function operation; if the assertion test result is no, it indicates that the preset control signal is not adjusted as expected, and a corresponding assertion error will be reported to warn the user that an abnormal situation has occurred, thereby realizing real-time feedback of abnormal information.
[0058] Therefore, this application monitors the internal conflict signals generated when the write request end and read request end simultaneously access the SRAM module under test in real time, and accumulates the number of times the target signal with low priority is reverse-pressed. When the number of reverse-pressed times reaches a preset reverse-pressed number threshold, the priority of the target signal is adjusted accordingly by adjusting the preset control signal, thereby avoiding continuously executing the corresponding functional operation for the signal with high priority in the initial mapping relationship. In addition, this application tests the preset control signal by assertion. When the assertion test result is negative, it indicates that the preset control signal is not pulled high and maintained for the preset number of beats as expected, that is, the priority of the target signal is not adjusted accordingly as expected. This can easily lead to the current functional operation being inconsistent with the expected functional operation. By using assertion error reporting, abnormal information can be fed back in real time, improving the accuracy of signal conflict verification and the error debugging rate.
[0059] See Figure 3 As shown in the figure, an embodiment of the present invention discloses a signal collision verification method, including:
[0060] When both write and read request ends access the SRAM module under test simultaneously, internal conflict signals, including the write signal `wvalid` and the read signal `rvalid`, are generated simultaneously. Based on the initial mapping relationship between access modes and priorities, and the access modes corresponding to different signals, a target signal with lower priority can be selected from the internal conflict signals. If the write mode has a lower priority in the initial mapping relationship, then the target signal is the write signal `wvalid`. When the write signal `wvalid` is high, and the write-related signal `write_unallow`, which indicates that write operations are not currently allowed, is also high, it is determined that the write operation corresponding to the write signal is being reverse-pressurized, meaning that a write request exists but the actual write operation cannot be performed. At this time, a first counter preset within the verification environment is used to accumulate and count the number of reverse-pressurizations to obtain a first reverse-pressurization count value. That is, each time a write request arrives and writes are not allowed, the first counter within the verification environment is incremented by one. If the write signal wvalid is high and the write-associated signal write_unallow is low, it indicates that the write operation corresponding to the current write signal is not being reverse-pressurized. In this case, the first counter will be cleared and the process will jump back to the step of determining whether the write operation corresponding to the current write signal is being reverse-pressurized.
[0061] After determining that the write operation corresponding to the write signal has been reverse-pressurized and obtaining the corresponding first reverse-pressurization count, it is necessary to determine whether the first reverse-pressurization count has reached a preset reverse-pressurization count threshold. If it has not reached the threshold, the process jumps back to the step of determining whether the write operation corresponding to the current write signal has been reverse-pressurized, so as to continue to accumulate and count the number of reverse-pressurizations. If it has reached the threshold, a preset adjustment process for the preset control signal is triggered through the SRAM module under test when the preset control signal priority_ack is on its rising edge. An assertion test is then performed in the verification environment to verify whether the preset control signal priority_ack has been pulled high and held for one clock cycle. If the assertion test result is yes, it indicates that the currently executed functional operation meets the expected functional operation. If the assertion test result is no, it indicates that the currently executed functional operation does not meet the expected functional operation, and a corresponding assertion error is reported. The preset adjustment process includes performing a first flip operation on the initial mapping relationship when the preset control signal priority_ack is on its rising edge to obtain the flipped mapping relationship. At this time, the priority of the write signal is higher than the priority of the read signal. The corresponding write operation is performed within the time period corresponding to the pull-up step. Then, when the preset control signal priority_ack is at the falling edge, the second flip operation is triggered to restore the flipped mapping relationship to the initial mapping relationship, and the priority of the read signal is made higher than the priority of the write signal again. At the same time, the first counter in the verification environment will also start counting again.
[0062] In addition, after obtaining the first reverse voltage count value, it is also necessary to monitor whether the first reverse voltage count value counted by the first counter is consistent with the second reverse voltage count value counted by the second counter in the SRAM module under test; if they are inconsistent, an assertion error is reported through the verification environment; if they are consistent, the above-mentioned step of assertion error reporting through the verification environment is prohibited.
[0063] Therefore, this application monitors the internal conflict signals generated when the write request end and the read request end simultaneously access the SRAM module under test in real time, and accumulates the number of times the low-priority write signal is reverse-pressed. When the number of reverse-pressed times reaches a preset reverse-pressed number threshold, the priority of the write signal is adjusted accordingly by adjusting the preset control signal, thereby avoiding continuously executing the corresponding read function operation for the high-priority read signal in the initial mapping relationship. In addition, this application tests the preset control signal by assertion. When the assertion test result is negative, abnormal information can be fed back in real time, improving the accuracy of signal conflict verification and the error correction rate.
[0064] See Figure 4 As shown, an embodiment of the present invention discloses a signal collision verification device, comprising:
[0065] The conflict signal acquisition module 11 is used to acquire the internal conflict signal generated when the write request end and the read request end simultaneously access the SRAM module under test;
[0066] The target signal filtering module 12 is used to determine the priority of each signal in the internal conflict signals and filter out the target signals with low priority by using the initial mapping relationship and the access mode corresponding to the signal.
[0067] The count module 13 is used to determine whether the target operation corresponding to the target signal is being reverse-pressurized. If so, the count of reverse-pressurization is accumulated to obtain a first reverse-pressurization count value.
[0068] The assertion test module 14 is used to monitor whether the first back pressure count value reaches the preset back pressure number threshold. If so, it triggers the preset adjustment process for the initial mapping relationship when the preset control signal is at the rising edge, and performs an assertion test on whether the preset control signal has been pulled high and maintained for a preset number of beats.
[0069] The assertion error reporting module 15 is used to indicate that the preset adjustment process has been completed if the assertion test result is yes; and to report the corresponding assertion error if the assertion test result is no.
[0070] Therefore, this application monitors the internal conflict signals generated when the write request end and read request end simultaneously access the SRAM module under test in real time, and accumulates the number of times the target signal with low priority is reverse-pressed. When the number of reverse-pressed times reaches a preset reverse-pressed number threshold, the priority of the target signal is adjusted accordingly by adjusting the preset control signal, thereby avoiding continuously executing the corresponding functional operation for the signal with high priority in the initial mapping relationship. In addition, this application tests the preset control signal by assertion. When the assertion test result is negative, it indicates that the preset control signal is not pulled high and maintained for the preset number of beats as expected, that is, the priority of the target signal is not adjusted accordingly as expected. This can easily lead to the current functional operation being inconsistent with the expected functional operation. By using assertion error reporting, abnormal information can be fed back in real time, improving the accuracy of signal conflict verification and the error debugging rate.
[0071] In some specific embodiments, the frequency counting module 13 may specifically include:
[0072] The level judgment unit is used to determine whether the current target associated signal is high when the target signal is high; the target associated signal corresponds to the same access mode as the target signal;
[0073] The back pressure determination unit is used to determine that the target operation corresponding to the target signal is under back pressure if the target association signal is currently high.
[0074] In some specific embodiments, the frequency counting module 13 may specifically include:
[0075] The count unit is used to accumulate and count the number of times the device is back-pressed by a preset first counter in the verification environment to obtain a first back-press count value; the verification environment is an environment used to verify the SRAM module under test.
[0076] In some specific embodiments, the signal collision verification device may further include:
[0077] The counter clearing unit is used to clear the first counter if it is not reverse-voltaged, and then jump back to the step of determining whether the target operation corresponding to the target signal is reverse-voltaged.
[0078] In some specific embodiments, the signal collision verification device may further include:
[0079] The counting value monitoring unit is used to monitor whether the first back voltage count value counted by the first counter is consistent with the second back voltage count value counted by the second counter in the SRAM module under test; the second counter is used to accumulate and count the number of times the back voltage is applied to obtain the second back voltage count value.
[0080] An assertion error reporting unit is used to report an assertion error through the verification environment if there is a discrepancy.
[0081] The trigger-disable unit is used to prevent the triggering of the assertion error reporting step through the verification environment if the results are consistent.
[0082] In some specific embodiments, the signal collision verification device may further include:
[0083] The step jump unit is used to jump back to the step of determining whether the target operation corresponding to the target signal is under back pressure if the target is not reached.
[0084] In some specific embodiments, the signal collision verification device may specifically include:
[0085] The first flipping unit is used to perform a first flipping operation on the initial mapping relationship to obtain the flipped mapping relationship;
[0086] The second flipping unit is used to perform the target operation within the time period corresponding to the preset number of beats, and then trigger a second flipping operation when the preset control signal is at the falling edge, so as to restore the flipped mapping relationship to the initial mapping relationship.
[0087] Furthermore, embodiments of this application also disclose an electronic device, Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.
[0088] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the signal conflict verification method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.
[0089] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0090] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0091] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the signal conflict verification method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.
[0092] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned signal conflict verification method. The specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0094] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0095] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0096] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0097] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A signal collision verification method, characterized in that, include: Acquire the internal conflict signal generated when both write and read request clients simultaneously access the SRAM module under test; Using the initial mapping relationship and the access mode corresponding to the signal, the priority of each signal in the internal conflict signals is determined and the target signal with low priority is filtered out. Determine whether the target operation corresponding to the target signal is being reverse-pressurized. If so, accumulate the number of times it is reverse-pressurized to obtain a first reverse-pressurization count value. Monitor whether the first back pressure count value reaches the preset back pressure number threshold. If so, trigger the preset adjustment process for the initial mapping relationship when the preset control signal is at the rising edge, and perform an assertion test on whether the preset control signal has been pulled high and maintained for the preset number of beats. If the assertion test result is yes, it indicates that the preset adjustment process has been completed. If the assertion test result is negative, then the corresponding assertion error will be reported. The preset adjustment process includes: performing a first flip operation on the initial mapping relationship to obtain a flipped mapping relationship, performing the corresponding target operation within the time period corresponding to the preset number of beats, and then triggering a second flip operation when the preset control signal is at the falling edge to restore the flipped mapping relationship to the initial mapping relationship.
2. The signal collision verification method according to claim 1, characterized in that, The step of determining whether the target operation corresponding to the target signal is being reverse-pressurized includes: When the target signal is high, it is determined whether the current target associated signal is high; the target associated signal corresponds to the same access mode as the target signal. If the target-associated signal is currently high, it is determined that the target operation corresponding to the target signal is being reverse-pressurized.
3. The signal collision verification method according to claim 1, characterized in that, The cumulative statistical analysis of the number of back pressure events to obtain the first back pressure count value includes: The first back pressure count value is obtained by accumulating and counting the number of times the back pressure is applied using a preset first counter in the verification environment; the verification environment is an environment used to verify the SRAM module under test.
4. The signal collision verification method according to claim 3, characterized in that, After determining whether the target operation corresponding to the target signal is being reverse-pressurized, the method further includes: If not reverse-pressurized, the first counter is cleared and the process jumps back to the step of determining whether the target operation corresponding to the target signal is reverse-pressurized.
5. The signal collision verification method according to claim 3, characterized in that, After accumulating and counting the number of back pressures to obtain the first back pressure count value, the method further includes: The system monitors whether the first back voltage count value, calculated by the first counter, is consistent with the second back voltage count value, calculated by the second counter within the SRAM module under test. The second counter is used to accumulate and count the number of times the system experiences back voltage to obtain the second back voltage count value. If there is a discrepancy, an assertion error will be reported through the verification environment. If they match, then the step of triggering the assertion error through the verification environment is prohibited.
6. The signal collision verification method according to claim 1, characterized in that, After monitoring whether the first back pressure count value has reached a preset back pressure count threshold, the method further includes: If the target is not reached, the process jumps back to the step of determining whether the target operation corresponding to the target signal is being reverse-pressurized.
7. A signal collision verification device, characterized in that, include: The conflict signal acquisition module is used to acquire internal conflict signals generated when the write request end and the read request end simultaneously access the SRAM module under test. The target signal filtering module is used to determine the priority of each signal in the internal conflict signals and filter out the target signals with low priority by using the initial mapping relationship and the access mode corresponding to the signal. The count module is used to determine whether the target operation corresponding to the target signal is being reverse-pressurized. If so, the count of reverse-pressurization is accumulated to obtain the first reverse-pressurization count value. The assertion test module is used to monitor whether the first back pressure count value reaches the preset back pressure number threshold. If so, it triggers the preset adjustment process for the initial mapping relationship when the preset control signal is at the rising edge, and performs an assertion test on whether the preset control signal has been pulled high and maintained for a preset number of beats. An assertion error reporting module is used to indicate that the preset adjustment process has been completed if the assertion test result is yes. If the assertion test result is negative, then the corresponding assertion error will be reported. The preset adjustment process includes: performing a first flip operation on the initial mapping relationship to obtain a flipped mapping relationship, performing the corresponding target operation within the time period corresponding to the preset number of beats, and then triggering a second flip operation when the preset control signal is at the falling edge to restore the flipped mapping relationship to the initial mapping relationship.
8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the signal collision verification method as described in any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, Used to store a computer program, which, when executed by a processor, implements the signal collision verification method as described in any one of claims 1 to 6.