Methods, apparatus, media, and test equipment for verifying multiple chips

Abstract

This invention relates to a method, apparatus, medium, and test equipment for verifying multiple chips. The method includes: configuring multiple inter-chip interconnect interfaces (IPAs) included in the test equipment such that the device identifier configured on each IPA corresponds to a chip in the interconnect topology under test; in response to receiving an IPA request from a source device to a destination device among the multiple chips, sending a data packet from a first IPA to a second IPA; and determining a correspondence between the device identifier of the destination device indicated by the received data packet and the device identifier configured on the second IPA, so as to verify the IPA transmission status from the source device to the destination device based on the determined correspondence. This invention enables verification of the interconnection of multiple chips in a chip cluster, while significantly reducing the resource consumption required for verification and maintaining verification flexibility.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of chip verification, and more specifically to a method for verifying multiple chips, a computing device, a computer-readable storage medium, and a test apparatus for verifying multiple chips. Background Technology

[0002] To meet the demands of increased computing power, multiple chips are interconnected to form chip clusters (e.g., but not limited to, accelerator card clusters). Traditional methods for verifying multiple chips involve building instances of the chips on a verification platform to actually verify the interconnections between them. The resources consumed by these traditional methods are proportional to the number of chips. This has a significant impact on the resource consumption of the verification platform, especially when verifying chip clusters with large design scales, and also significantly increases the verification time overhead.

[0003] In summary, the shortcomings of traditional solutions for verifying multiple chips are that when verifying the interconnection of multiple chips in a chip cluster, it is difficult to reduce the resource consumption required for verification while also reducing the verification time. Summary of the Invention

[0004] This invention provides a method, computing device, computer-readable storage medium, and test equipment for verifying multiple chips. Even when verifying the interconnection of multiple chips in a chip cluster, it can significantly reduce the resource consumption required for verification while maintaining verification flexibility.

[0005] According to a first aspect of the present invention, a method for verifying multiple chips is provided. The method includes: configuring a plurality of inter-chip interconnect interfaces (ICIs) included in a test device such that a device identifier configured on each ICI corresponds to a chip in an interconnect topology under test, the interconnect topology being composed of the plurality of interconnected chips; in response to receiving an ICI request for an interconnect from a source device to a destination device among the plurality of chips, sending a data packet from a first ICI to a second ICI, the first ICI corresponding to a source device; and determining a correspondence between a device identifier of the destination device indicated by the received data packet and a device identifier configured on the second ICI, so as to verify the ICI transmission status from the source device to the destination device based on the determined correspondence.

[0006] According to a second aspect of the present invention, a computing device is also provided. The computing device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the computing device to perform the method of the first aspect of the present invention.

[0007] According to a third aspect of the present invention, a computer-readable storage medium is also provided. The computer-readable storage medium stores a computer program that, when executed by a machine, performs the method of the first aspect of the present invention.

[0008] According to a fourth aspect of the present invention, a test apparatus for verifying multiple chips is also provided. The test apparatus includes: multiple inter-chip interconnect interfaces, each inter-chip interconnect interface being configured with a device identifier corresponding to a chip in the interconnect topology under test, each inter-chip interconnect interface including a corresponding address translation module, a transmitting port, and a receiving port; and a computing device according to a second aspect of the present invention.

[0009] In some embodiments, verifying the inter-chip interconnection transmission status from the source device to the destination device based on the determined correspondence includes: determining, via the address translation module of the second inter-chip interconnection interface, whether the device identifier of the destination device indicated by the received data packet corresponds to the device identifier configured in the second inter-chip interconnection interface; and determining that the inter-chip interconnection transmission from the source device to the destination device has passed verification in response to determining that the device identifier of the destination device indicated by the received data packet corresponds to the device identifier configured in the second inter-chip interconnection interface.

[0010] In some embodiments, verifying the inter-chip interconnection transmission status from the source device to the destination device based on the determined correspondence includes: in response to determining that the device identifier of the destination device indicated by the received data packet does not correspond to the device identifier configured on the second inter-chip interconnection interface, sending the data packet from the second inter-chip interconnection interface to the next inter-chip interconnection interface interconnected with the second inter-chip interconnection interface, until the address translation module of the current inter-chip interconnection interface that receives the data packet determines that the device identifier of the destination device indicated by the data packet corresponds to the device identifier configured on the current inter-chip interconnection interface.

[0011] In some embodiments, each of the plurality of inter-chip interconnect interfaces includes: a corresponding address translation module, each address translation module including a configured lookup table, the lookup table including at least: a device identifier where the inter-chip interconnect interface is located and topology information for indicating the selected route for interconnect access from the device to the destination device; a sending port for sending data packets; and a receiving port for receiving data packets.

[0012] In some embodiments, configuring the multiple inter-chip interconnect interfaces included in the test equipment includes: interconnecting two inter-chip interconnect interfaces via external chip interconnects to form one or more pairs of interconnects, each pair of interconnects being used to simulate interconnect access between a source device and a destination device in the interconnect topology under test; selecting one inter-chip interconnect interface from the multiple inter-chip interconnect interfaces of the test equipment to be used as a simulated transmission port for interconnect access from the source device to the destination device; configuring a lookup table for the address translation module corresponding to the selected inter-chip interconnect interface, such that the lookup table includes at least: the device identifier configured for the selected inter-chip interconnect interface and the topology information of the selected route for interconnect access from the source device to the destination device; and configuring the other inter-chip interconnect interfaces of the test equipment as simulated receiving ports of the destination device.

[0013] In some embodiments, configuring other inter-chip interconnect interfaces of the test device as simulated receiving ports of the destination device includes: configuring a lookup table included in the address translation module corresponding to the other inter-chip interconnect interfaces of the test device, such that the lookup table includes at least: the device identifier configured for the other inter-chip interconnect interfaces, and the topology information for interconnection access from any source device to the destination device.

[0014] In some embodiments, the method for verifying multiple chips further includes: in response to determining that the destination device indicated by the received data packet corresponds to the device identifier configured in the current inter-chip interconnect interface, terminating the inter-chip interconnect associated with the inter-chip interconnect request from the source device to the destination device; and handing over the data packet received by the current inter-chip interconnect interface to the on-chip bus associated with the destination device so as to route the data packet to an execution unit, which is a memory or a processing unit, via the on-chip bus.

[0015] In some embodiments, the method for verifying multiple chips further includes: determining whether there is return information regarding an inter-chip interconnect request; and in response to determining that there is return information regarding an inter-chip interconnect request, returning the return information to an inter-chip interconnect interface corresponding to the source device; and in response to confirming that the return information received by the inter-chip interconnect interface corresponding to the source device meets predetermined conditions, determining that the inter-chip interconnect transmission status between the source device and the destination device has been verified.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] The above and other features, advantages, and aspects of the various embodiments of the present invention will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0018] Figure 1A The diagram illustrates a test system for verifying multiple chips according to an embodiment of the present invention.

[0019] Figure 1B A schematic diagram of the interconnect topology under test according to an embodiment of the present invention is shown. Figure 2 A flowchart of a method for verifying multiple chips according to an embodiment of the present invention is shown.

[0020] Figure 3 A schematic diagram of the interconnect topology under test according to an embodiment of the present invention is shown.

[0021] Figure 4 A schematic diagram of a test apparatus according to an embodiment of the present invention is shown.

[0022] Figure 5 A schematic diagram of a test apparatus according to an embodiment of the present invention is shown.

[0023] Figure 6 A flowchart illustrating a method for configuring multiple inter-chip interconnect interfaces according to an embodiment of the present invention is shown.

[0024] Figure 7 A flowchart of a method for verifying the transmission status from a destination device to a source device according to an embodiment of the present invention is shown.

[0025] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0026] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0027] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0028] As described above, the traditional approach for verifying multiple chips has the shortcoming that when verifying the interconnection of multiple chips in a chip cluster, it is difficult to reduce the resource consumption required for verification while maintaining the flexibility of verification.

[0029] To at least partially address one or more of the aforementioned problems and other potential issues, exemplary embodiments of the present invention propose a method for verifying multiple chips. In this method, by configuring multiple inter-chip interconnect interfaces (ICIs) included in a test device, such that each ICI interface, configured with a device identifier corresponding to a chip in the interconnect topology under test, allows the present invention to simulate interconnections between multiple chips to be verified using the ICIs included in a single test device. Furthermore, by sending data packets from a first ICI interface corresponding to the source device to a second ICI interface when an ICI request from a source device to a destination device is received; and by verifying the ICI transmission status from the source device to the destination device of multiple chips in the interconnect topology under test based on the correspondence between the device identifier of the destination device indicated by the received data packet and the device identifier of the second ICI interface, the present invention can verify the source-to-destination ICI transmission status between chips using the limited physical resources of a single test device. Therefore, even when verifying the interconnection of multiple chips in a chip cluster, the present invention does not require actually constructing instances of multiple chips through a verification platform, thus significantly reducing the resource consumption required for verification while maintaining verification flexibility.

[0030] Figure 1A The diagram illustrates a test system for verifying multiple chips according to an embodiment of the present invention. Figure 1B A schematic diagram of the interconnect topology under test according to an embodiment of the present invention is shown. Figure 1A As shown, the test system 100 includes a processor 150 and a test device 130. The processor 150 is used for configuring and managing the test device 130. The test device 130 is used for implementation and verification. Figure 2 The example topology of the interconnect topology 120 under test is the verification target of this invention.

[0031] Regarding processor 150, which is, for example, but not limited to, a central processing unit (CPU) external to the test equipment, it is used to configure and manage test equipment 130. For example, processor 150 configures a plurality of bidirectional inter-chip interconnect interfaces included in test equipment 130 such that the device identifier configured for each inter-chip interconnect interface corresponds to a chip in the interconnect topology under test, and configures a lookup table for the address translation module included in each inter-chip interconnect interface. In some embodiments, the on-chip computing device 110 included in test equipment 130 may also configure each inter-chip interconnect interface and its corresponding address translation module's lookup table. In some embodiments, processor 150 is used to support a verification environment.

[0032] Regarding the interconnection topology 120 under test, it is the verification target of this invention. For example... Figure 1B As shown, the interconnect topology 120 under test is, for example, formed by interconnecting multiple chips to be verified. The device addresses of the multiple chips in the interconnect topology under test are uniformly assigned. The multiple chips include, for example, a first chip 122, a second chip 124 through an Nth chip 128. The first chip 122, the second chip 124 through an Nth chip 128 are used, for example, to construct a chip cluster. Each chip includes, for example, multiple ports (e.g., port P1, port P2, and port P3, such as...). Figure 1B As shown, the number of device ports included in each chip is the same as the number of inter-chip interconnect interfaces included in the test device 130. In some embodiments, the multiple chips are, for example, multiple general-purpose computing on graphics processing units (GPGPUs). In some embodiments, the chips are, for example, accelerator cards. Regarding the test device 130, it is a means of implementing and verifying the interconnect topology under test. Figure 1AAs shown, the test device 130 includes: multiple inter-chip interconnect interfaces and a computing device 110 (the computing device 110 is an on-chip computing resource). In some embodiments, the test device 130 further includes an on-chip bus 140. The on-chip bus 140 is used to connect the multiple inter-chip interconnect interfaces and the computing device 110. The multiple inter-chip interconnect interfaces included in the test device 130 are, for example, a first inter-chip interconnect interface 132, a second inter-chip interconnect interface 134 to an Mth inter-chip interconnect interface 138. Each inter-chip interconnect interface is bidirectional and includes, for example, a corresponding address translation module, a transmitting port, and a receiving port. Each address translation module includes a configured lookup table, which includes at least: the device identifier configured for the inter-chip interconnect interface (the device identifier is, for example, the device number of the current device where the address translation module is located) and topology information for indicating the selected route for interconnection access from the host device (i.e., the current device where the translation module is located) to the destination device. Specifically, this topology information includes, for example, which on-chip interconnect interface should be selected when traveling from the current device to the destination device to achieve interconnection. The index of the lookup table is the device number of the destination device. This device number is carried by the data packets transmitted through the inter-chip interconnect interface where each address translation module is located. The lookup table included in each address translation module can be configured via a processor 150 (e.g., CPU) outside the test device, or via the on-chip computing device 110 of the test device.

[0033] like Figure 1AAs shown, one or more pairs of inter-chip interconnect interfaces (ICIs) can be externally interconnected via chips, as indicated by labels 160-1 and 160-2, to form one or more interconnects. Each pair of interconnects is used to simulate interconnect access between a source device (also referred to as a "source chip") and a destination device (also referred to as a "destination chip") in the interconnect topology under test 120. The computing device 110 is used to verify the multiple chips. Specifically, the computing device 110 is used to configure the multiple ICIs included in the test equipment such that the device identifier configured for each ICI corresponds to a chip in the interconnect topology under test; if an ICI request for an interconnect from the source device to the destination device is received, a data packet is sent from the first ICI corresponding to the source device to the second ICI; and the ICI transmission status from the source device to the destination device in the multiple chips is verified based on the correspondence between the device identifier of the destination device indicated by the received data packet and the device identifier configured for the second ICI. In some embodiments, the computing device 110 may have one or more processing units, including dedicated processing units such as graphics processing units (GPUs), field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs), as well as general-purpose processing units such as CPUs.

[0034] The following will combine Figure 2 , Figures 3 to 5 A method 200 for verifying multiple chips according to an embodiment of the present invention is described. Figure 2 A flowchart of a method 200 for verifying multiple chips according to an embodiment of the present invention is shown. Figure 3 A schematic diagram of an interconnect topology 300 under test according to an embodiment of the present invention is shown. Figure 4 A schematic diagram of a test apparatus 400 according to an embodiment of the present invention is shown. Figure 5 A schematic diagram of a test apparatus 500 according to an embodiment of the present invention is shown. It should be understood that method 200 may be performed, for example, at the computing device 110 described in FIG. 1. Method 200 may also include additional actions not shown and / or the actions shown may be omitted, and the scope of the invention is not limited in this respect.

[0035] In step 202, the computing device 110 configures multiple inter-chip interconnect interfaces included in the test equipment, such that the device identifier configured for each inter-chip interconnect interface corresponds to a chip in the interconnect topology under test, which is composed of multiple interconnected chips.

[0036] The interconnect topology under test, which is the verification target of this invention, is, for example, composed of multiple interconnected chips. Each chip, for example, includes multiple ports. Figure 3 As shown, the interconnect topology 300 under test includes four chips: a first chip 302, a second chip 304, a third chip 306, and a fourth chip 308. Each chip includes three ports: port P1, port P2, and port P3. The ports of each chip in the interconnect topology 300 are interconnected with the ports of the other chips in pairs, thus connecting the first chip 302, the second chip 304, the third chip 306, and the fourth chip 308 to form the interconnect topology 300. In some embodiments, the interconnect topology 300 is formed by fully interconnecting the four chips. It should be understood that the interconnect topology under test may include a larger number of chips, and the device addresses of multiple chips in the interconnect topology under test are uniformly assigned.

[0037] The test equipment is the means of implementing and verifying the interconnect topology under test (UTP). The test equipment includes multiple inter-chip interconnect interfaces. If the UTP includes N chips (N is a natural number greater than or equal to 3), and the UTP is formed by interconnecting these N chips in pairs, then the test equipment includes at least N-1 inter-chip interconnect interfaces. Each inter-chip interconnect interface can be configured via a processor external to the test equipment (e.g., a CPU) or via the on-chip computing device of the test equipment. The device identifier configured for each inter-chip interconnect interface corresponds to a chip in the UTP. For example... Figure 4 As shown, the test equipment 400 is used to test multiple chips in the interconnect topology 300 under test (the computing devices included in the test equipment 400 are...). Figure 4 (Not shown in the image). The test equipment 400 includes three inter-chip interconnect interfaces: the first inter-chip interconnect interface 402, the second inter-chip interconnect interface 404, and the third inter-chip interconnect interface 406. Each inter-chip interconnect interface includes a corresponding address translation module. Figure 4 The diagram schematically illustrates the corresponding address translation modules configured for the first inter-chip interconnect interface 402, the second inter-chip interconnect interface 404, and the third inter-chip interconnect interface 406, namely, the first address translation module 412, the second address translation module 414, and the third address translation module 416. A method for configuring multiple inter-chip interconnect interfaces included in a test device may, for example, involve interconnecting two inter-chip interconnect interfaces via external interconnects (as indicated by reference numeral 420) to form one or more pairs of interconnects, each pair used to simulate interconnect access between a source device (e.g., a source chip) and a destination device (e.g., a destination chip) in the interconnect topology under test. Figure 4As shown, the test device 400's first inter-chip interconnect interface 402 and second inter-chip interconnect interface 404 are interconnected via the first chip external interconnect 420, and the first inter-chip interconnect interface 402 and third inter-chip interconnect interface 406 are interconnected via the second chip external interconnect 422, forming two pairs of interconnects. For example, the pair of interconnects formed by the first inter-chip interconnect interface 402 and the second inter-chip interconnect interface 404 is used to simulate the interconnect from the first chip 302 as the source device to the second chip 304 as the destination device (e.g., from...). Figure 3 The interconnection between port P2 of the first chip 302 and port P3 of the second chip 304 is shown. Additionally, as... Figure 4 As shown, another pair of interconnects formed between the first inter-chip interconnect interface 402 and the third inter-chip interconnect interface 406 is used, for example, to simulate the interconnection from the first chip 302 as the source device to the third chip 306 as the destination device (e.g., from...). Figure 3 The interconnection between port P3 of the first chip 302 and port P2 of the third chip 306 is shown.

[0038] In some embodiments, the method for configuring multiple inter-chip interconnect interfaces further includes: selecting one inter-chip interconnect interface from among the multiple inter-chip interconnect interfaces of the test device to be used as a simulated transmitting port for interconnect access from the source device to the destination device; configuring a lookup table for the address translation module corresponding to the selected inter-chip interconnect interface, such that the lookup table includes at least: the device identifier where the selected inter-chip interconnect interface is located and the topology information of the selected route for interconnect access from the source device to the destination device; and configuring other inter-chip interconnect interfaces of the test device as simulated receiving ports of the destination device. The following will combine... Figure 6 The method 600 for configuring multiple inter-chip interconnect interfaces is described below and will not be repeated here. At step 204, the computing device 110 determines whether an inter-chip interconnect request from a source device to a destination device among the multiple chips has been received. If it is determined that no inter-chip interconnect request from the source device to the destination device has been received, the device continues to wait at step 204 until an inter-chip interconnect request from the source device to the destination device is received. It should be understood that if the link is not established, the transmission will always fail.

[0039] Regarding the inter-chip interconnection request from the source device to the destination device, it refers to the inter-chip interconnection request for interconnection access between any two chips in the interconnection topology under test. It should be understood that the computing device 110 can sequentially verify the inter-chip interconnection transmission status from the source device to the destination device involved in each inter-chip interconnection request for interconnection access between two chips, until the verification of the inter-chip interconnection transmission status of all chips in the interconnection topology under test is completed.

[0040] At step 206, if the computing device 110 receives an inter-chip interconnection request from a source device to a destination device, it sends a data packet from a first inter-chip interconnection interface to a second inter-chip interconnection interface among a plurality of inter-chip interconnection interfaces, the first inter-chip interconnection interface corresponding to the source device.

[0041] Regarding the data packets sent by the first inter-chip interconnect interface, they at least indicate the device identifier of the source device and the device identifier of the destination device. For example, the data packet carries: the identifier of the inter-chip interconnect interface used by the source device for outgoing data, which the computing core needs to carry when routing within the device, and the device identifier of the destination device (the device identifier of the destination device is, for example, but not limited to, the device address or device number of the destination device).

[0042] The second inter-chip interconnect interface is one of the multiple inter-chip interconnect interfaces connected to the first inter-chip interconnect interface, but different from the first inter-chip interconnect interface. The second inter-chip interconnect interface can be an inter-chip interconnect interface located adjacent to the first inter-chip interconnect interface, or it can be another inter-chip interconnect interface located at an interval from the first inter-chip interconnect interface.

[0043] At step 208, the computing device 110 determines the correspondence between the device identifier of the destination device indicated by the received data packet and the device identifier configured on the second inter-chip interconnect interface, so as to verify the inter-chip interconnect transmission status from the source device to the destination device based on the determined correspondence. For example, the address translation module 414 corresponding to the second inter-chip interconnect interface 404 parses the device number of the destination device included in the data packet, and then obtains the device identifier configured on the second inter-chip interconnect interface 404 (i.e., the device identifier of the local device or the current device) by querying the lookup table of the corresponding address translation module, so as to determine whether the parsed device identifier of the destination device corresponds to the device identifier configured on the second inter-chip interconnect interface 404 (i.e., the device identifier of the local device or the device of the current device). If they correspond, it indicates that the transmission endpoint involved in the inter-chip interconnect request is on the second inter-chip interconnect interface 404 (i.e., the local device or the device of the current device).

[0044] A method for verifying the inter-chip interconnection transmission status from a source device to a destination device includes, for example, the following steps: The computing device 110 determines, via an address translation module of a second inter-chip interconnection interface, whether the device identifier of the destination device indicated by a received data packet corresponds to the device identifier configured on the second inter-chip interconnection interface; and in response to determining that the device identifier of the destination device indicated by the received data packet corresponds to the device identifier configured on the second inter-chip interconnection interface, determines that the inter-chip interconnection transmission from the source device to the destination device has passed verification. If the computing device 110 determines that the device identifier of the destination device indicated by the received data packet does not correspond to the device identifier configured on the second inter-chip interconnection interface, the data packet is sent from the second inter-chip interconnection interface to the next inter-chip interconnection interface interconnected with the second inter-chip interconnection interface (the next inter-chip interconnection interface is, for example, but not limited to, a third inter-chip interconnection interface), until the address translation module of the current inter-chip interconnection interface receiving the data packet determines that the device identifier of the destination device indicated by the data packet corresponds to the device identifier configured on the current inter-chip interconnection interface.

[0045] For example, such as Figure 5As shown, each inter-chip interconnect interface is configured via an external processor or an on-chip computing device of the test equipment, such that the device configured for each inter-chip interconnect interface simulates different chips in the interconnect topology under test. The first inter-chip interconnect interface 504 (the first inter-chip interconnect interface 502, for example, includes an address translation module 512) simulates, for example, the source device associated with the inter-chip interconnect request. Upon receiving the inter-chip interconnect request, the first inter-chip interconnect interface 502 sends a data packet to the second inter-chip interconnect interface 504. If the on-chip computing unit 110 of the test device determines, via the address translation module 514 corresponding to the second inter-chip interconnect interface 504, that the device identifier of the destination device indicated by the data packet received by the second inter-chip interconnect interface 504 from the first inter-chip interconnect interface 502 does not correspond to the device identifier configured in the second inter-chip interconnect interface 504, the data packet is sent from the second inter-chip interconnect interface 504 to the third inter-chip interconnect interface 506. The address translation module 516 corresponding to the third inter-chip interconnect interface further determines whether the device identifier of the destination device indicated by the received data packet corresponds to the device identifier configured in the third inter-chip interconnect interface 506. If it is determined that the device identifier of the destination device indicated by the received data packet still does not correspond to the device identifier configured in the third inter-chip interconnect interface, the data packet continues to be sent from the third inter-chip interconnect interface 506 to the fourth inter-chip interconnect interface, until the address translation module corresponding to the fourth inter-chip interconnect interface determines that the device identifier of the destination device indicated by the data packet corresponds to the device identifier configured in the fourth inter-chip interconnect interface. Thus, the data packet eventually reaches the inter-chip interconnect interface corresponding to the destination device after multiple forwardings. Through the above methods, the present invention can conveniently and flexibly verify the inter-chip interconnection transmission status from the source device to the destination device.

[0046] In some embodiments, the method further includes a verification step of the return information transmission status from the destination device to the source device. For example, if the computing device 110 determines that the device identifier of the destination device indicated by the received data packet corresponds to the device identifier configured in the current inter-chip interconnect interface, the inter-chip interconnect associated with the inter-chip interconnect request from the source device to the destination device is terminated; the data packet received by the current inter-chip interconnect interface is handed over to the on-chip bus associated with the destination device so that the data packet is routed to an execution unit, which is a memory or a processing unit, via the on-chip bus; it is determined whether there is return information regarding the inter-chip interconnect request (the return information is issued by the inter-chip interconnect interface corresponding to the destination device); if it is determined that there is return information regarding the inter-chip interconnect request, the return information is returned to the inter-chip interconnect interface corresponding to the source device; and if it is confirmed that the return information received by the inter-chip interconnect interface corresponding to the source device meets predetermined conditions (e.g., meets expectations), it is determined that the inter-chip interconnect transmission status between the source device and the destination device has been verified. Thus, the present invention can realize the verification of the inter-chip interconnect transmission status from the destination device to the source device.

[0047] It should be understood that in some embodiments, after the computing device 110 completes the verification of the inter-chip interconnect transmission status between the source device and the destination device involved in the current inter-chip interconnect request, the computing device 110 can continue to verify the inter-chip interconnect transmission status between the next source device and the next destination device involved in the next inter-chip interconnect request, and so on, until the verification of the inter-chip interconnect transmission status of all chips in the interconnect topology under test is completed. In other embodiments, the computing device 110 can complete the verification of the inter-chip interconnect transmission status between the source device and the destination device involved in multiple inter-chip interconnect requests in parallel. It should be understood that when the computing device 110 concurrently completes the verification of the interconnect paths involved in multiple inter-chip interconnect requests, the inter-chip interconnect interfaces involved in different inter-chip interconnect requests need to be isolated from each other. In the above method 200, by configuring multiple inter-chip interconnect interfaces included in the test device, such that the device configured for each inter-chip interconnect interface corresponds to a chip in the interconnect topology under test, the present invention can simulate the interconnection between multiple chips to be verified using the inter-chip interconnect interfaces included in a single test device. Furthermore, by sending data packets from a first inter-chip interconnect interface corresponding to the source device to a second inter-chip interconnect interface when an inter-chip interconnect request from a source device to a destination device is received in multiple chips; and verifying the inter-chip interconnect transmission status from the source device to the destination device based on the correspondence between the device identifier of the destination device indicated by the received data packet and the device identifier configured in the second inter-chip interconnect interface, the present invention can verify the inter-chip interconnect transmission status from the source device to the destination device between multiple chips using the physical resources of a single test device. Therefore, even when verifying the interconnection of multiple chips in a chip cluster, the present invention can significantly reduce the resource consumption required for verification while maintaining verification flexibility.

[0048] The following will combine Figure 5 and Figure 6 A method 600 for configuring multiple inter-chip interconnect interfaces according to an embodiment of the present invention is described. Figure 6 A flowchart illustrating a method 600 for configuring multiple inter-chip interconnect interfaces according to an embodiment of the present invention is shown. It should be understood that method 600 can be performed, for example, at the computing device 110 described in FIG. 1. It should also be understood that method 600 may include additional actions not shown and / or the actions shown may be omitted, and the scope of the invention is not limited in this respect.

[0049] In step 602, the two inter-chip interconnect interfaces are interconnected via external interconnects to form one or more pairs of interconnects. Each pair of interconnects is used to simulate the interconnect access between the source device and the destination device in the interconnect topology under test.

[0050] For example, in a test interconnect topology consisting of N+1 chips (e.g., the device identifiers of the N+1 chips are n0 to nN), assume the device identifier of the source device is n0. Figure 5 As shown, the connection from the first inter-chip interconnect interface 502 to the second inter-chip interconnect interface 504, the second inter-chip interconnect interface 504 to the third inter-chip interconnect interface 506, and the connection from the third inter-chip interconnect interface 506 to the Mth inter-chip interconnect interface 508 (M is a natural number) via external chip interconnects. Regarding the interconnection method of the inter-chip interconnect interfaces, it can be implemented using data lines between the inter-chip interconnect interfaces during the testing phase; while during the verification phase, it can be implemented using simulated signal connections. For example... Figure 5 As shown, the first inter-chip interconnect interface 502 in the test device 500 is equipped with a corresponding address translation module 512, the second inter-chip interconnect interface 504 is equipped with a corresponding address translation module 514, the third inter-chip interconnect interface 506 is equipped with a corresponding address translation module 516, and the Mth inter-chip interconnect interface 508 is equipped with a corresponding address translation module 518. In addition, each inter-chip interconnect interface is also equipped with a transmit port for sending data packets and a receive port for receiving data packets.

[0051] At step 604, the computing device 110 selects one inter-chip interconnect interface from among the multiple inter-chip interconnect interfaces of the test device to be used as a simulated transmission port for interconnect access from the source device to the destination device.

[0052] Regarding the source device, it can be any chip in the interconnect topology under test, for example, the source device is the Nth chip in the interconnect topology under test, where N is a natural number greater than or equal to 3.

[0053] Regarding the destination device, it is, for example, any chip in the interconnect topology under test other than the source device, such as the Kth (K is a natural number) chip.

[0054] For example, such as Figure 5 As shown, the first inter-chip interconnect interface 502 of the test device 500 is selected as the simulated transmission port for the access path from the Nth chip to the Kth chip, that is, the simulated transmission port corresponding to the source device, to send a data packet regarding the inter-chip interconnect request when an inter-chip interconnect request is detected from the Nth chip as the source device to the Kth chip as the destination device. The data packet, for example, indicates the device identifier of the source device and the device identifier of the final destination device.

[0055] At step 606, the computing device 110 configures the lookup table of the address translation module corresponding to the selected inter-chip interconnect interface so that the lookup table includes at least: the device identifier configured for the selected inter-chip interconnect interface and the topology information of the selected route for interconnect access from the source device to the destination device.

[0056] For example, the internal device (such as an address translation module) of the inter-chip interconnect interface used as a transmission port contains a lookup table configurable by a computing device. For instance, in a test interconnect topology consisting of N+1 chips (the device identifiers of the N+1 chips are, for example, n0 to nN), each chip has M+1 TX ports for inter-chip interconnection (TX ports are transmission ports, and the M+1 TX ports include, for example, ports m0 to mM). Table 1 below exemplarily illustrates the lookup table contained in the address translation module of the inter-chip interconnect interface used as a data packet transmission port, configured by the computing device. This lookup table, for example, includes multiple rows of configuration information, where the first row of configuration information, for example, indicates T(n0) = m0, indicating which TX port is used to transmit data in the source device or intermediate device, as indicated by m0 obtained by looking up the device identifier n0 of the destination device.

[0057] Table 1

[0058] Device identification for destination devices TX port identifier used n0 m0 …… nN mM

[0059] At step 608, the computing device 110 configures other inter-chip interconnect interfaces of the test device as simulated receiving ports of the destination device. Specifically, the computing device 110 configures the lookup table included in the address translation module corresponding to the other inter-chip interconnect interfaces of the test device, such that the configured lookup table includes at least: the device identifier of the device to which the other inter-chip interconnect interfaces are configured, and the topology information of interconnection access from any source device to the destination device. In some embodiments, the lookup table included in the corresponding address translation module is configured via a CPU outside the test device or via a verification environment. For example, the address translation module corresponding to the inter-chip interconnect interface that serves as the data packet receiving end includes a lookup table that can be configured via a CPU outside the test device. For example, in a test interconnection topology consisting of N+1 chips (e.g., the device identifiers of the N+1 chips are n0 to nN), each chip has M+1 RX ports for inter-chip interconnection (e.g., the M+1 RX ports include: ports m0 to mM, where the RX ports are receiving ports). The lookup table may include multiple rows of configuration information. The first row, for example, indicates that R(n0) = m0, meaning that m0, obtained by looking up the device identifier n0 of the destination device, indicates which TX port should be used as the next hop for data forwarding in the source or intermediate device. As described earlier, the data sent by the sender carries the destination device identifier. The receiver matches the destination device identifier with the device identifier of the receiver's own device. If they do not match, the receiver will continue forwarding data to the port indicated by m0 using the TX port of its own device. If they match, the interconnection transmission associated with the current inter-chip interconnection request is terminated.

[0060] It should be understood that if an inter-chip interconnect interface receiving a data packet can confirm that the device identifier of the destination device indicated by the data packet corresponds to the device identifier configured on the inter-chip interconnect interface by querying the lookup table of the inter-chip interconnect interface, then the interconnect access from the source device (e.g., source chip) to the destination device (e.g., destination chip) is verified.

[0061] By adopting the above-mentioned methods, the present invention can flexibly simulate the interconnection access between multiple chips to be verified using a single test equipment resource, for testing the chip under test and the interconnection topology under test, without requiring significant changes to the verification platform.

[0062] The following will combine Figure 7 A method 700 for verifying the transmission status from a destination device to a source device according to an embodiment of the present invention is described. Figure 7 A flowchart of a method 700 for verifying the transmission status from a destination device to a source device according to an embodiment of the present invention is shown. It should be understood that method 700 can be performed, for example, at the computing device 110 described in FIG. 1. Method 700 may also include additional actions not shown and / or the actions shown may be omitted; the scope of the invention is not limited in this respect.

[0063] At step 702, if the computing device 110 determines that the device identifier of the destination device indicated by the received data packet corresponds to the device identifier configured in the current inter-chip interconnect interface, the inter-chip interconnect associated with the inter-chip interconnect request from the source device to the destination device is terminated.

[0064] At step 704, the computing device 110 hands over the data packet received by the current inter-chip interconnect interface to the on-chip bus associated with the destination device so that the data packet can be routed to the execution unit, which is a memory or a processing unit, via the on-chip bus.

[0065] At step 706, computing device 110 determines whether there is any return information regarding the inter-chip interconnection request. It should be understood that if the path test is normal, there must be return information. If computing device 110 determines that there is no return information regarding the inter-chip interconnection request, at step 712, it indicates that the test path is abnormal.

[0066] At step 708, if the computing device 110 determines that there is a return message regarding the inter-chip interconnect request, it returns the return message to the inter-chip interconnect interface corresponding to the source device. For example, if the computing device 110 determines that there is a return message or response, it may rely on the associated transport ID (e.g., a transaction ID using the AXI4 protocol, which indicates, for example, the path for writing / reading data, the path for writing / reading addresses, and the write reply path information) to return the return message or response to the inter-chip interconnect interface corresponding to the source device along the original path.

[0067] In step 710, if the computing device 110 confirms that the return information received by the inter-chip interconnect interface corresponding to the source device meets predetermined conditions, it determines that the inter-chip interconnect transmission status between the source device and the destination device has passed verification. The predetermined conditions include, for example, that the data indicated by the received return information matches the expected data. When the inter-chip interconnect interface corresponding to the source device receives return information and the data indicated by the return information matches the expected data, the verification is considered successful.

[0068] By employing the above methods, the present invention can conveniently simulate inter-chip access and effectively verify the transmission status from the destination device to the source device.

[0069] The various processes and procedures described above, such as methods 200, 600, and 700, can be executed by a computing device. This computing device may include, for example, at least one processor (at least one graphics processor and at least one central processing unit); and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor. In some embodiments, methods 200, 600, and 700 can be implemented as computer software programs tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program can be loaded and / or installed on the computing device via read-only memory (ROM) and / or a communication unit. When the computer program is loaded into random-access memory (RAM) and executed by the GPU and CPU, one or more actions of methods 200, 600, and 700 described above can be performed.

[0070] This invention can be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention. The computer-readable storage medium may be a tangible device capable of holding and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof.

[0071] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. Various aspects of the invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0072] These computer-readable program instructions can be provided to the central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the central processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0073] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0074] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0075] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors.

Claims

1. A method for authenticating a plurality of chips, said plurality of chips having inter-chip access therebetween, characterized by, The method comprises: configuring a plurality of bidirectional inter-chip interconnect interfaces comprised by a test device, such that a device identity configured for each inter-chip interconnect interface corresponds to a chip in an interconnect topology to be tested, the interconnect topology to be tested being formed by interconnecting a plurality of chips; in response to receiving an inter-chip interconnect request from a source device to a destination device among the plurality of chips, sending a data packet from a first inter-chip interconnect interface to a second inter-chip interconnect interface among the plurality of inter-chip interconnect interfaces, the first inter-chip interconnect interface corresponding to the source device; and determining a correspondence between a device identity of the destination device indicated by the received data packet and a device identity configured for the second inter-chip interconnect interface, so as to verify an inter-chip interconnect transmission status from the source device to the destination device based on the determined correspondence, wherein each inter-chip interconnect interface among the plurality of inter-chip interconnect interfaces comprises: a corresponding address translation module, each address translation module comprising a lookup table configured to include at least: the device identity configured for the inter-chip interconnect interface and topology information indicating a selected route for an interconnect access from the device to the destination device; a sending port for sending a data packet; and a receiving port for receiving a data packet, and wherein configuring the plurality of inter-chip interconnect interfaces comprised by the test device comprises: interconnecting the two inter-chip interconnect interfaces via an off-chip interconnect, so as to form one or more pairs of interconnects, each pair of interconnects being used to simulate an interconnect access between the source device and the destination device in the interconnect topology to be tested; selecting an inter-chip interconnect interface among the plurality of inter-chip interconnect interfaces of the test device to serve as a simulated sending port for the interconnect access from the source device to the destination device; configuring a lookup table of the corresponding address translation module of the selected inter-chip interconnect interface, such that the lookup table includes at least: the device identity configured for the selected inter-chip interconnect interface and topology information indicating a selected route for the interconnect access from the device to the destination device; and configuring other inter-chip interconnect interfaces of the test device as simulated receiving ports of the destination device.

2. The method of claim 1, wherein, Verifying the inter-chip interconnect transmission status from the source device to the destination device based on the determined correspondence comprises: determining, via the address translation module of the second inter-chip interconnect interface, whether the device identity of the destination device indicated by the received data packet corresponds to the device identity configured for the second inter-chip interconnect interface; and in response to determining that the device identity of the destination device indicated by the received data packet corresponds to the device identity configured for the second inter-chip interconnect interface, determining that the inter-chip interconnect transmission from the source device to the destination device passes verification.

3. The method of claim 1, wherein, Verifying the inter-chip interconnect transmission status from the source device to the destination device based on the determined correspondence comprises: in response to determining that the device identifier of the destination device indicated by the received data packet does not correspond to the local device identifier configured for the second inter-chip interconnect interface, sending the data packet from the second inter-chip interconnect interface to a next inter-chip interconnect interface interconnected with the second inter-chip interconnect interface until the address translation module of the current inter-chip interconnect interface receiving the data packet determines that the device identifier of the destination device indicated by the data packet corresponds to the local device identifier configured for the current inter-chip interconnect interface.

4. The method of claim 1, wherein, configuring the other inter-chip interconnect interface of the test device as a simulated receiving port of the destination device comprises: configuring a lookup table included in the address translation module corresponding to the other inter-chip interconnect interface of the test device such that the lookup table includes at least the device identifier of the local device configured for the other inter-chip interconnect interface and topology information of inter-chip interconnect access from any source device to the destination device.

5. The method of claim 1, wherein, further comprising: in response to determining that the device identifier of the destination device indicated by the received data packet corresponds to the local device identifier configured for the current inter-chip interconnect interface, ending the inter-chip interconnect request associated with the inter-chip interconnect from the source device to the destination device; and handing over the data packet received by the current inter-chip interconnect interface to an intra-chip bus associated with the destination device so as to route the data packet to an execution unit via the intra-chip bus, the execution unit being a memory or a processing unit.

6. The method of claim 1, further comprising: determining whether there is return information about the inter-chip interconnect request; in response to determining that there is return information about the inter-chip interconnect request, returning the return information to the inter-chip interconnect interface corresponding to the source device; and in response to confirming that the return information received by the inter-chip interconnect interface corresponding to the source device meets a predetermined condition, determining that the status of the inter-chip interconnect transmission between the source device and the destination device is verified. comprising:

7. A computing device, comprising: at least one processor; and a memory communicatively connected with the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6. a computer program is stored on the computer readable storage medium, the computer program being executed by a machine to perform the method of any one of claims 1-6.

8. A computer-readable storage medium, characterized in that, comprising:

9. A test apparatus for verifying multiple chips, characterized in that, a plurality of inter-chip interconnect interfaces, each inter-chip interconnect interface configured with a local device identifier corresponding to one chip in the interconnect topology to be tested, each inter-chip interconnect interface including a corresponding address translation module, a sending port and a receiving port; and the computing device of claim 7. ​

Images