Read data amount processing device, method, chip, electronic device, and storage medium

Abstract

The application relates to a data read amount processing device, method, chip, electronic equipment and storage medium. The device comprises a processor and a first storage unit. The processor is used for writing first record information in the first storage unit at an address corresponding to a read request ID of a read request. The first record information at least comprises a first start address of first response data, a second start address of second response data and a data amount of the first response data. The processor is also used for reading the first record information from a storage address corresponding to a read operation ID tag of received response data in the first storage unit when an identification signal of the last data of the received response data returned by a bus is received. When it is determined that a target read request queue exists in a read request queue, the read data amount information of the target read request queue is updated according to the first record information. The device can improve the performance of a chip.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data volume processing apparatus, method, chip, electronic device, and storage medium. Background Technology

[0002] With the development of data processing technology, a technique has emerged that uses a linked list + shared cache structure to manage bus read data storage for multiple queues during chip design. The shared cache can allocate data storage space for different queues and count the amount of data that each queue has obtained from the bus. Subsequent modules can then send data requests to the shared cache based on the data volume information of each queue.

[0003] In traditional technologies, bus read data returns are typically out-of-order and interleaved. Therefore, to count the amount of read data in a shared buffer, it's necessary to start counting from the head of each queue. Currently, the method for counting the amount of data a queue obtains from the bus is usually by setting registers to mark the return status of different read data from different queues. That is, the shared buffer marks the return status of cache units in the shared buffer by setting corresponding registers, and each queue can count the amount of data starting from the head of the queue by querying the corresponding link relationship.

[0004] However, the above method requires the use of a large number of registers to mark the return status of data read from each queue. The number of registers will be directly related to the number of cache units. At the same time, the use of a large number of registers will increase the circuit area, thereby reducing the performance of the chip. Summary of the Invention

[0005] Therefore, it is necessary to provide a read data processing device, method, chip, electronic device, and storage medium that can increase chip performance in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a data read processing apparatus, comprising: a processor and a first storage unit; wherein,

[0007] The processor is configured to write first record information into the first storage unit at the address corresponding to the read request ID of the read request; wherein the first record information includes at least a first starting address for storing first response data, a second starting address for storing second response data, and the amount of data of the first response data, the first response data being the response data of the current read request corresponding to the read request ID, the second response data being the response data of the next read request of the current read request, and the current read request and the next read request being triggered by the same read request queue;

[0008] The processor is further configured to read the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit when receiving a bus return identification signal, and update the read data volume information of the target read request queue according to the first record information when it is determined that there is a target read request queue in the read request queue; wherein, the identification signal is a prompt signal of the last data of the response data, and the target read request queue is a read request queue in the read request queue whose starting address is the same as the first starting address.

[0009] In one embodiment, the device further includes: a second storage unit; the processor is specifically configured to: update the read data volume information of the target read request queue using the data volume in the first record information; read corresponding second record information from the address in the second storage unit corresponding to the second starting address in the first record information; the second record information includes at least the data volume of the first response data, the second starting address, and feedback status information of the first response data; when the feedback status information in the second record information indicates that the corresponding first response data is in a returned state, update the read data volume information of the target read request queue using the data volume of the first response data in the read second record information; continue to read second record information from the address in the second storage unit corresponding to the second starting address in the read second record information until the feedback status information in the second record information indicates that its corresponding first response data is in a non-feedback state, otherwise update the read data volume information of the target read request queue using the data volume in the second record information.

[0010] In one embodiment, the processor is further configured to: when the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, update the first address of the target read request queue to the first starting address where the non-returned first response data is stored.

[0011] In one embodiment, the processor is further configured to: when it is determined that the target read request queue does not exist in the read request queue, write second record information into the storage address corresponding to the first starting address in the second storage unit.

[0012] Secondly, this application also provides a method for processing read data volume, the method comprising:

[0013] Write first record information at the address corresponding to the read request ID of the read request in the first storage unit. The first record information includes at least a first starting address for storing the first response data, a second starting address for storing the second response data, and the amount of the first response data. The first response data is the response data of the current read request corresponding to the read request ID, and the second response data is the response data of the next read request of the current read request. The current read request and the next read request are triggered by the same read request queue.

[0014] Upon receiving a bus return identification signal, the first record information is read from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit. When it is determined that a target read request queue exists in the read request queue, the read data volume information of the target read request queue is updated according to the first record information. The identification signal is a prompt signal for the last data of the response data, and the target read request queue is a read request queue whose starting address is the same as the first starting address.

[0015] In one embodiment, updating the read data volume information of the target read request queue according to the first record information specifically includes: updating the read data volume information of the target read request queue using the data volume in the first record information; reading the corresponding second record information from the address in the second storage unit corresponding to the second starting address in the first record information; the second record information includes at least the data volume of the first response data, the second starting address, and the feedback status information of the first response data; when the feedback status information in the second record information indicates that the corresponding first response data is in a returned state, updating the read data volume information of the target read request queue using the data volume of the first response data in the read second record information; continuing to read the second record information from the address in the second storage unit corresponding to the second starting address in the read second record information until the feedback status information in the second record information indicates that the corresponding first response data is in a non-feedback state, otherwise updating the read data volume information of the target read request queue using the data volume in the second record information.

[0016] In one embodiment, the data reading processing method further includes: when the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, updating the first address of the target read request queue to the first starting address where the non-returned first response data is stored.

[0017] In one embodiment, the read data volume processing method further includes: when it is determined that the target read request queue does not exist in the read request queue, writing second record information into the storage address corresponding to the first starting address in the second storage unit.

[0018] Thirdly, this application also provides a chip including a read data volume processing device as described in any embodiment of the first aspect.

[0019] Fourthly, this application also provides an electronic device including a chip as described in any embodiment of the third aspect.

[0020] Fifthly, this application also provides a computer-readable storage medium, wherein when the computer program is executed by a processor, it implements the steps of the method described in any of the embodiments of the first aspect.

[0021] The aforementioned read data volume processing apparatus, method, chip, electronic device, and storage medium include: a processor and a first storage unit; wherein the processor is configured to write first record information at the address corresponding to the read request ID in the first storage unit; wherein the first record information includes at least a first starting address for storing first response data, a second starting address for storing second response data, and the data volume of the first response data, the first response data being the response data of the current read request corresponding to the read request ID, the second response data being the response data of the next read request of the current read request, and the current read request and the next read request being triggered by the same read request queue; the processor is further configured to read the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit when a bus return identification signal is received, and to update the read data volume information of the target read request queue according to the first record information when it is determined that a target read request queue exists in the read request queue; wherein the identification signal is a prompt signal for the last data of the response data, and the target read request queue is a read request queue whose starting address is the same as the first starting address. This application provides a first storage unit in a shared cache. When a request is initiated, the processor can write first record information into the address corresponding to the read request ID in the first storage unit. Upon receiving the identifier signal of the last data corresponding to the response data returned by the bus, the processor can read the first record information corresponding to the response data from the storage address corresponding to the read operation ID tag of the first storage unit, and determine whether the first starting address stored in the first record information is the starting address of a certain read request queue. If so, the first record information can be used to update the read data volume information of the read request queue, thereby realizing the update of the read data volume information of the read request queue. Furthermore, the above method does not require setting registers to mark the return status of different read data in different queues, thus reducing the circuit area and improving the chip performance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a data reading processing device in one embodiment;

[0023] Figure 2 This is a schematic diagram illustrating the use of id_RAM in one embodiment;

[0024] Figure 3 This is a schematic diagram of the data reading processing device in another embodiment;

[0025] Figure 4 This is a schematic diagram illustrating the use of cal_RAM in one embodiment;

[0026] Figure 5 This is an application environment diagram of a data volume processing method in one embodiment;

[0027] Figure 6 This is a flowchart illustrating a method for handling read data volume in one embodiment;

[0028] Figure 7 This is a schematic diagram of the process for updating the read data volume information of the target read request queue in one embodiment;

[0029] Figure 8 This is a schematic diagram illustrating the changes in the contents of cal_RAM during a sequential bus return in one embodiment;

[0030] Figure 9 This is a schematic diagram illustrating the changes in the contents of cal_RAM during a bus out-of-order return in one embodiment.

[0031] Figure 10 This is a schematic diagram of the chip structure in one embodiment;

[0032] Figure 11 This is a schematic diagram of the structure of an electronic device in one embodiment. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] In one embodiment, such as Figure 1 As shown, a data reading processing device is provided, which may include: a processor 101 and a first storage unit 102; wherein,

[0035] The processor 101 is used to write first record information at the address corresponding to the read request ID in the first storage unit 102; wherein, the first record information includes at least a first starting address for storing first response data, a second starting address for storing second response data, and the amount of data of the first response data, the first response data is the response data of the current read request corresponding to the read request ID, the second response data is the response data of the next read request of the current read request, and the current read request and the next read request are triggered by the same read request queue;

[0036] The processor 101 is further configured to read the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit 102 when receiving the bus return identification signal, and update the read data volume information of the target read request queue according to the first record information when it is determined that there is a target read request queue in the read request queue; wherein, the identification signal is the prompt signal of the last data of the response data, and the target read request queue is the read request queue in the read request queue whose starting address is the same as the first starting address.

[0037] In this embodiment, there can be multiple read request queues. Since many objects in the shared cache can use the shared cache, many objects are abstracted into different queues. An object that uses the shared cache can be abstracted into a queue, and different values ​​of the signal correspond to different queues.

[0038] Specifically, after the shared cache receives the request information of each read request triggered by the read request queue, the processor 101 assigns a corresponding read request ID to each read request and writes the corresponding first record information into the address of the first storage unit 102 corresponding to the read request ID, thereby realizing the storage of the first record information of each of the above read requests into the storage address of the first storage unit 102.

[0039] Combination Figure 2For example, read requests triggered by a read request queue may include read request A, read request B, and read request C. The read request IDs corresponding to these three read requests are addresses 10, 20, and 30, respectively, and the corresponding first record information is first record information A, first record information B, and first record information C, respectively. Therefore, the corresponding first record information can be stored in the storage address corresponding to each read request ID in the first storage unit 102. That is, first record information A is stored at address 10 in the first storage unit 102, first record information B is stored at address 20 in the first storage unit 102, and first record information C is stored at address 30 in the first storage unit 102. The first record information stored at address 10 may include the first starting address for storing the response data of the read request corresponding to read request A, i.e., CELL0, the second starting address for storing the response data of the next read request B, i.e., CELL8, and the data size of the response data corresponding to read request A is DATA_CNT0. Similarly, the first record information stored in address 20 may include the first starting address for storing the response data corresponding to read request B, namely CELL8, the second starting address for storing the response data of the next read request C, namely CELL20, and the data volume of the response data corresponding to read request B is DATA_CNT1.

[0040] After the processor sends a read request to the bus, it is also used to receive the response data returned by the bus. When the bus returns the response data, it carries a read operation ID tag, which is the same address indicated by the read request ID.

[0041] Specifically, when the processor 101 receives the identification signal for the last data of the response data returned by the bus, it can read the first record information stored in the first storage unit 102 from the corresponding storage address according to the read operation ID tag.

[0042] For example, if the read requests triggered by queue 1 are sequentially read request A, read request B, and read request C, then for the current read request A, the next read request will be read request B. In the first record information A corresponding to read request A, the starting cache address of read request B's response data in the shared cache (CELL8) can be stored, and CELL8 will be used as the second starting address in the first record information A. For the current read request B, the starting address of the next read request (read request C)'s response data in the shared cache (CELL20) can be stored in the first record information B, and CELL20 will be used as the second starting address in the first record information B. For read request C, the starting address of the next read request's response data in the shared cache can be pre-allocated, such as CELL50, and CELL50 will be used as the second starting address in the first record information C.

[0043] Subsequently, the processor 101 can also compare the first starting address stored in the obtained first record information with the queue head address of each read request queue. In this embodiment, the shared cache can also store the queue head address of each read request queue. The processor 101 can also compare the obtained first starting address with the queue head address of each queue to determine whether there is a queue head address that is the same as the first starting address. If there is, the read request queue with the queue head address is taken as the target read request queue, thereby using the first record information to update the read data volume information of the target read request queue. This can be done by using the data volume of the first response data stored in the first record information to update the read data volume information.

[0044] For example, the read request queues initiating read requests may include queue 1 and queue 2. The read request order triggered by queue 1 is read request A - read request B - read request C, while the read request order triggered by queue 2 is read request D - read request E. The starting address of queue 1, i.e., the starting address of the response data corresponding to read request A stored in the shared cache, can be CELL0, while the starting address of queue 2, i.e., the starting address of the response data corresponding to read request D stored in the shared cache, can be CELL3. After obtaining the first starting address stored in the first record information, processor 101 can compare the first starting address with CELL0 and CELL3 respectively to determine whether a target read request queue exists. If the first starting address stored in the first record information obtained by processor 101 is CELL0, and it matches CELL0 in the queue's starting address, then queue 1 becomes the target read request queue. Furthermore, the processor 101 can also use the data volume in the first record information, which can be DATA_CNT0, to update the read data volume information of queue 1, that is, add DATA_CNT0 to the read data volume information of queue 1. And if the first starting address stored in the first record information obtained by the processor 101 is CELL3, and queue 2 is used as the target read request queue, the processor 101 can also use the data volume in the first record information to update the read data volume information of queue 1, that is, add the data volume from the first record information to the read data volume information of queue 1.

[0045] The aforementioned read data volume processing device includes a processor 101 and a first storage unit 102. The processor 101 is configured to write first record information into the first storage unit 102 at the address corresponding to the read request ID. The first record information includes at least a first starting address for storing first response data, a second starting address for storing second response data, and the data volume of the first response data. The first response data is the response data of the current read request corresponding to the read request ID, and the second response data is the response data of the next read request following the current read request. The current read request and the next read request are triggered by the same read request queue. The processor 101 is also configured to read the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit when a bus return identification signal is received. When a target read request queue is determined to exist in the read request queue, the processor updates the read data volume information of the target read request queue according to the first record information. The identification signal is a prompt signal for the last data of the response data, and the target read request queue is a read request queue whose starting address is the same as the first starting address. By providing a first storage unit 102 in the shared cache, when a request is initiated, the processor 101 can write first record information into the address corresponding to the read request ID in the first storage unit 102. When receiving the identification signal of the last data corresponding to the response data returned by the bus, the processor can read the first record information corresponding to the response data from the storage address corresponding to the read operation ID tag in the first storage unit 102, and determine whether the first starting address stored in the first record information is the starting address of a certain read request queue. If so, the first record information can be used to update the read data volume information of the read request queue, thereby realizing the update of the read data volume information of the read request queue. Furthermore, the above method does not require setting registers to mark the return status of different read data in different queues, thus reducing the circuit area and improving the chip performance.

[0046] In one embodiment, such as Figure 3As shown, the read data processing device, in addition to the processor 101 and the first storage unit 102, may also include a second storage unit 103; the processor 101 is specifically used to: update the read data volume information of the target read request queue using the data volume in the first record information; read the corresponding second record information from the address in the second storage unit 103 corresponding to the second starting address in the first record information; the second record information includes at least the data volume of the first response data, the second starting address, and the feedback status information of the first response data; when the feedback status information in the second record information indicates that the corresponding first response data is in a returned state, update the read data volume information of the target read request queue using the data volume of the first response data read in the second record information; continue to read the second record information from the address in the second storage unit 103 corresponding to the second starting address in the read second record information until the feedback status information in the second record information indicates that the corresponding first response data is in a non-feedback state, otherwise update the read data volume information of the target read request queue using the data volume in the second record information.

[0047] For example, the first record information A stores DATA_CNT0, the response data of the read request corresponding to read request A, the first starting address of the response data of the read request A (i.e., CELL0), and the second starting address of the response data of the next read request (i.e., read request B) (i.e., CELL8). Then, the second record information recorded in CELL0 of the second storage unit 103 includes the second starting address of the response data of the next read request B (i.e., the second starting CELL8 of the response data of the read request corresponding to read request B), DATA_CNT0, the response data of the read request corresponding to read request A, and the feedback status information of the read request corresponding to read request A.

[0048] like Figure 2 and Figure 4For the first record information stored at address 10 in the first storage unit id_RAM, it can include: a first starting address for storing the response data corresponding to read request A, i.e., CELL0; a second starting address for storing the response data of the next read request B, i.e., CELL8; and the data size of the response data of read request A is DATA_CNT0. Then, in the second storage unit 103, i.e., cal_RAM, the address corresponding to the first starting address, i.e., CELL0, can store the data size of the response data corresponding to read request A, DATA_CNT0; the second starting address for storing the response data of the next read request B, CELL8; and the feedback status information corresponding to the read request, which can be represented by a 1-bit return flag. Similarly, for the first record information stored at address 20 in id_RAM, it can include: a first starting address for storing the response data of read request B, i.e., CELL8; a second starting address for storing the response data of the next read request, i.e., CELL20; and the data size of the read request is DATA_CNT1. In cal_RAM, the data amount DATA_CNT1 of the read request B, the second starting address CELL20 of the response data of the next read request C, and the feedback status information corresponding to the read request can be stored at the address corresponding to the first starting address, namely CELL8. The feedback status information can be represented by a 1-bit return flag.

[0049] Furthermore, the response data is not necessarily returned in the order in which the read requests were initiated. That is, the order of the requests might be read request A - read request B - read request C, but the returned read data could be response data B - response data A - response data C. To further improve the efficiency of data acquisition, in this case, the processor 101 can first obtain the first record information B from the first storage unit 102 based on the read request ID of read request B, and store its related information as second record information B in the address in the second storage unit 103 that matches the first starting address in the first record information B. This related information is the second starting address in the first record information B, and the amount of data in the first record information B is also stored in the second storage unit 103. Simultaneously, since the response data for read request B has been returned, the feedback status information corresponding to read request B is a response data return indicator. Then, the processor 101 obtains the first record information A of the response data of read request A from the first storage unit 102, and can further obtain the second starting address stored in the first record information A. Since the second starting address in the first record information corresponding to read request A is the same as the first starting address of read request B, and since the second record information B is already stored in the address corresponding to the second starting address in the first record information A in the second storage unit 103, and the feedback status information of the second record information B indicates that the first response data of the second record information B has been returned, i.e., the response data of read request B has been returned, the processor 101 can update the read data volume information of the target read request queue again through the amount of data stored in the second record information B, thereby realizing the continuous update of the read data volume of the request queue.

[0050] Subsequently, the processor 101 can further obtain the corresponding second starting address from the second record information B. This second starting address is the first starting address of the read request C. Then, the processor 101 will further read the new second record information, i.e., the second record information C, from the address corresponding to the second starting address. At the same time, since the response data of the read request C has not yet been returned, the feedback status information corresponding to the second record information C indicates that its corresponding first response data, i.e., the response data of the read request C, is in a non-feedback state. At this time, the processor 101 will stop using the amount of data stored in the second record information C to update the read data volume information of the target read request queue. If the returned read data is response data B-response data C-response data A, then the feedback status information corresponding to the second record information C indicates that the response data of the read request C is in a fedback state. Then, the processor 101 will continue to use the amount of data stored in the second record information C to update the read data volume information of the target read request queue.

[0051] Specifically, after updating the read data volume information of the target read request queue using the data volume in the first record information, the processor 101 can also obtain its stored second starting address from the first record information. Then, the processor 101 can further obtain the second record information from the storage address corresponding to the second starting address in the second storage unit 103, and determine whether the feedback status information in the second record information indicates that the response data has been returned. If the feedback status information indicates that the response data has been returned, the processor 101 can obtain the data volume of the first response data stored in the second record information and update the read data volume information of the target read request queue again. Simultaneously, the processor 101 can also use the second starting address in the second record information stored in the second storage address as a new second starting address, and use this new second storage address to read new second record information again, until the feedback status information in the second record information indicates that its corresponding response data is in a non-feedback state, and then use the first starting address corresponding to the non-feedback response data to update the head address of the target queue.

[0052] For example, the read requests triggered by queue 1 could be read request A - read request B - read request C. Then, the current queue head address of queue 1 could be the first starting address of read request A, which could be CELL0. If the return order of the read data is read request B's response data - read request A's response data - read request C's response data, meaning read request B's response data returns before read request A's response data, then when read request B's response data returns, since the first starting address is different from the queue head address CELL0, the update of the read data volume of queue 1 is not performed. Instead, the second record information B is stored in the address corresponding to CELL8 of the second storage unit 103 at the first starting address of read request B's response data. The second record information B can contain the second starting address (CELL20) from the first record information corresponding to read request B, the data volume DATA_CNT1, and feedback status information indicating that read request B's response data has been returned. If the processor 101 receives the response data of read request A, after updating the read data volume of queue 1, it can further obtain the stored second starting address (CELL8) from the first record information. The processor 101 can then retrieve the feedback status information of the second record information B stored in CELL8 of the second storage unit 103, and determine whether the response data has been returned. Since the feedback status information stored in CELL8 currently indicates that the response data has been returned, the processor 101 can further utilize the data amount DATA_CNT1 in the second record information stored in CELL8 to update the read data amount of queue 1. Furthermore, the processor 101 can use the second starting address stored in CELL8, namely CELL20, as the new second starting address to retrieve the second record information stored in CELL20 again and determine whether the response data corresponding to CELL20 has been returned. Since the response data for read request C has not been returned, the feedback status information in the second record information indicates that its corresponding response data is in a non-feedback state. Therefore, the processor 101 stops using the data amount in the second record information stored in CELL20 to update the read data amount of queue 1, and simultaneously updates the queue head address to CELL20.

[0053] In this embodiment, after the read data volume information of the target read request queue is updated, the processor 101 can also determine, based on the feedback status information, whether to continue using the data volume stored in the second starting address to update the read data volume information of the target read request queue from the address corresponding to the second starting address in the second storage unit 103 and the first record information. This achieves improved efficiency in obtaining read data volume while ensuring the accuracy of read data volume acquisition when read data is returned out of order.

[0054] In one embodiment, the processor 101 is further configured to: when the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, update the first address of the target read request queue to the first starting address where the non-returned first response data is stored.

[0055] In this embodiment, if the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, then in order to ensure that the starting address of the target read request queue can be updated in real time, the starting address of the target read request queue can also be updated to the first starting address where the non-returned first response data is stored.

[0056] Taking the response data return order as response data of read request A - response data of read request B - response data of read request C as an example, after response data A is returned and the read data volume information of queue 1 is updated using the first record information A, since the response data of read request B has not been returned, the processor 101 determines from the second storage unit 103 that the feedback status information in the second record information B is that the response data has not been returned. Then, the starting address of queue 1 can be updated to the first starting address of the response data of read request B. Then, when the response data of read request B is returned, after the processor 101 obtains the first starting address of the response data of read request B from the first record information B, since the starting address of queue 1 has been updated to the first starting address of the response data of read request B, the read data volume information of queue 1 can be updated again using the data volume stored in the first record information B.

[0057] Similarly, taking the response data return order as response data of read request B - response data of read request A - response data of read request C as an example, after the response data of read request A is returned and the read data volume information of queue 1 is updated using the data volume stored in the first record information A, since the response data of read request B has been returned but the response data of read request C has not been returned, the processor 101 determines from the second storage unit 103 that the feedback status information in the second record information C is that the response data of read request C has not been returned, and can then update the starting address of queue 1 to the first starting address of the response data of read request C. Then, when the response data of read request C is returned, after the processor 101 obtains the first starting address of the response data of read request C from the first record information C, since the starting address of queue 1 has been updated to the first starting address of the response data of read request C, the read data volume information of queue 1 can be updated again using the data volume stored in the first record information C.

[0058] In this embodiment, the processor 101 can also update the starting address of the target read request queue to the first starting address where the non-returned first response data is stored when the feedback status information indicates that the corresponding first response data is in a non-returned state. This can ensure that the starting address of the target read request queue is continuously updated, so as to ensure the update of the read data volume information of the target read request queue in the next time.

[0059] In one embodiment, the processor 101 is further configured to: when it is determined that there is no target read request queue in the read request queue, write second record information into the storage address corresponding to the first starting address in the second storage unit 103.

[0060] If there is no target read request queue matching the first starting address in the read request queue, for example, if the read requests triggered by queue 1 could be read request A-read request B-read request C, and the response data corresponding to read request B is returned before the response data corresponding to read request A, then processor 101 can stop updating the read data volume information of the target read request queue according to the first record information, and can obtain the second starting address and the data volume of the first response data from the first record information. Afterwards, processor 101 can write the obtained second starting address and the data volume of the first response data into the storage address corresponding to the first starting address in the second storage unit 103, and characterize the feedback status information corresponding to that storage address as the response data having been returned, thereby storing it along with the obtained second starting address and the data volume of the first response data as second record information, and returning to execute the step of reading the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit 102 when the identification signal of the last data of the response data returned by the bus is received.

[0061] For example, if the processor 101 obtains the first starting address as CELL8, and there is no matching target read request queue at this time, then the processor 101 can write the second starting address (which could be CELL20) and the amount of the first response data (which could be DATA_CNT1) from the first record information into the storage address corresponding to the first starting address in the second storage unit 103, i.e., CELL8. At the same time, the processor 101 can also represent the corresponding feedback status information stored in CELL8 as the response data having been returned and wait to receive the next rlast signal.

[0062] In this embodiment, if the target read request queue does not exist in the read request queue, then the update of the read data volume information of the target read request queue is stopped, and the second record information is written into the storage address corresponding to the first starting address in the second storage unit 103, and waits for the next rlast signal, thereby ensuring the sequential execution of read data volume statistics and further improving the accuracy of read data volume acquisition.

[0063] In one embodiment, a method for handling read data volume is provided, which can be applied to, for example... Figure 5 In the application environment shown, the shared cache is connected to the subsequent modules and the bus. The subsequent modules can initiate data requests to the shared cache, which can then send the data requests to the bus. The bus returns read data to the shared cache, and the subsequent modules can obtain the corresponding amount of read data from the shared cache based on the requested read data volume. Simultaneously, the shared cache can carry a processor and a first storage unit. The processor can write the first record information of each read request—for example, the first starting address storing the first response data of each read request, the second starting address storing the second response data of the next read request, and the data volume of the first response data—into the address corresponding to the read request ID of each read request in the first storage unit. Upon receiving a bus return identification signal, the processor can also read the first record information stored in the first storage unit from the storage address corresponding to the read operation ID tag of the response data, and obtain the first starting address from the first record information, comparing it with the starting address corresponding to each read request queue. If a target read request queue with the same starting address exists in the read request queue, the first record information can be used to update the read data volume information of the target read request queue.

[0064] In one embodiment, such as Figure 6 As shown, a method for processing read data volume is provided, including the following steps:

[0065] Step S601: Write first record information at the address corresponding to the read request ID in the first storage unit. The first record information includes at least a first starting address for storing the first response data, a second starting address for storing the second response data, and the amount of the first response data. The first response data is the response data of the current read request corresponding to the read request ID, and the second response data is the response data of the next read request of the current read request. The current read request and the next read request are triggered by the same read request queue.

[0066] The first storage unit is used to record the first record information of each read request. This first record information is used to characterize information related to each read request, such as the first starting address for storing the response data of the read request, the second starting address for storing the response data of the next read request, and the amount of data in the response data of the read request. The read request ID is used to identify each read request and corresponds one-to-one with each read request.

[0067] Specifically, after the read request queue triggers each read request, the processor can write the first record information of each read request to the storage address in the first storage unit corresponding to the read request ID of each read request.

[0068] Step S602: Upon receiving the bus return identification signal, read the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit. When it is determined that a target read request queue exists in the read request queue, update the read data volume information of the target read request queue according to the first record information. Here, the identification signal is the prompt signal of the last data of the response data, and the target read request queue is the read request queue whose starting address is the same as the first starting address in the read request queue.

[0069] The starting address refers to the cache start address information of the first response data of each read request queue in the cache. If the processor receives an identification signal for the last data of the response data returned by the bus, such as the rlast signal, it can determine the read operation ID tag corresponding to the response data. Then, it can obtain the stored first record information from the corresponding storage address of the first storage unit according to the read operation ID tag, and can also obtain the stored first starting address from the first record information. The first starting address is compared with the starting address corresponding to each read request queue. If there is a target read request queue with the same starting address as the first starting address in the read request queue, the read data volume information of the target read request queue can be updated using the first record information.

[0070] In the above-described data volume processing method, the processor writes first record information to the address corresponding to the read request ID in the first storage unit. The first record information includes at least a first starting address for storing the first response data, a second starting address for storing the second response data, and the data volume of the first response data. The first response data is the response data of the current read request corresponding to the read request ID, and the second response data is the response data of the next read request after the current read request. The current read request and the next read request are triggered by the same read request queue. When a bus return identification signal is received, the first record information is read from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit. When it is determined that a target read request queue exists in the read request queue, the data volume information of the target read request queue is updated according to the first record information. The identification signal is the prompt signal of the last data of the response data, and the target read request queue is the read request queue whose starting address is the same as the first starting address. By providing a first storage unit in the shared cache, when a request is initiated, the processor can write first record information into the address corresponding to the read request ID in the first storage unit. Upon receiving the identifier signal of the last data corresponding to the response data returned by the bus, the processor can read the first record information corresponding to the response data from the storage address corresponding to the read operation ID tag of the first storage unit, and determine whether the first starting address stored in the first record information is the starting address of a certain read request queue. If so, the first record information can be used to update the read data volume information of the read request queue, thereby realizing the update of the read data volume information of the read request queue. Furthermore, the above method does not require setting registers to mark the return status of different read data in different queues, thus reducing the circuit area and improving the chip performance.

[0071] In one embodiment, such as Figure 7 As shown, step S602 may further include:

[0072] Step S701: Update the read data volume information of the target read request queue using the data volume in the first record information.

[0073] Specifically, since the first record information stores the data volume information of the returned response data, after the processor reads the first record information, it can obtain the data volume corresponding to the first record information, and then use the data volume to update the read data volume information of the target read request queue.

[0074] Step S702: Read the corresponding second record information from the address in the second storage unit that corresponds to the second starting address in the first record information; the second record information includes at least the data volume of the first response data, the second starting address, and the feedback status information of the first response data.

[0075] The second storage unit refers to the storage unit used to store the second record information. The second record information may include feedback status information representing the return status of the response data corresponding to the read request, the data volume of the response data of the read request, and the starting cache address of the response data of the next read request, i.e., the second starting address. Specifically, after the processor obtains the first record information, it can further obtain the second starting address stored in the first record information, and read the second record information stored in the second storage unit from the address with the same second starting address.

[0076] Step S703: When the feedback status information in the second record information indicates that the corresponding first response data has been returned, update the read data volume information of the target read request queue using the data volume of the first response data read in the second record information.

[0077] If the feedback status information in the second record indicates that the corresponding response data has been returned, and if the response data of the next read request of the read request has been returned, the amount of the first response data stored in the second record can be obtained, and the read data amount information of the target read request queue can be updated again.

[0078] Step S704: Continue reading the second record information from the address corresponding to the second starting address in the second record information in the second storage unit until the feedback status information in the second record information indicates that the corresponding first response data is in a no-feedback state; otherwise, update the read data volume information of the target read request queue using the data volume in the second record information.

[0079] Simultaneously, the processor can continue to read new second record information from the address corresponding to the second starting address of the second record information in the second storage unit, and determine again whether the response data corresponding to the second record information has been returned. This can be done by determining whether the feedback status information in the second record information indicates that the corresponding first response data has been returned. If the first response data has been returned, the processor updates the read data volume information of the target read request queue again using the data volume in the second record information. If the feedback status information in the second record information indicates that the corresponding first response data has not been returned, the processor stops updating the read data volume information of the target read request queue and waits again for the identifier signal of the last data to receive the response data.

[0080] In this embodiment, after the read data volume information of the target read request queue is updated, the processor can also determine, based on the feedback status information, whether to continue using the data volume stored in the second starting address to update the read data volume information of the target read request queue from the address corresponding to the second starting address in the second storage unit and the first record information. This achieves improved efficiency in obtaining read data volume while ensuring the accuracy of read data volume acquisition when read data is returned out of order.

[0081] In one embodiment, the read data volume processing method may further include: when the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, updating the first address of the target read request queue to the first starting address where the non-returned first response data is stored.

[0082] In this embodiment, if the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, then in order to ensure that the starting address of the target read request queue can be updated in real time, the starting address of the target read request queue can also be updated to the first starting address where the non-returned first response data is stored.

[0083] In this embodiment, when the feedback status information indicates that the corresponding first response data is not returned, the processor can also update the starting address of the target read request queue to the first starting address where the unreturned first response data is stored, thereby ensuring the continuous updating of the starting address of the target read request queue to ensure the update of the read data volume information of the target read request queue in the next iteration.

[0084] In one embodiment, the read data volume processing method may further include: when it is determined that there is no target read request queue in the read request queue, writing second record information into the storage address corresponding to the first starting address in the second storage unit.

[0085] If there is no target read request queue in the read request queue that matches the first starting address, then the processor 101 can stop updating the read data volume information of the target read request queue according to the first record information, and can obtain the second starting address and the data volume of the first response data from the first record information. Afterwards, the processor can write the obtained second starting address and the data volume of the first response data into the storage address corresponding to the first starting address in the second storage unit, and represent the feedback status information corresponding to that storage address as the response data having been returned, thereby storing it along with the obtained second starting address and the data volume of the first response data as the second record information, and returning to execute the step of reading the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit when the identification signal of the last data of the response data returned by the bus is received.

[0086] In this embodiment, if the target read request queue does not exist in the read request queue, then the update of the read data volume information of the target read request queue is stopped, and the second record information is written into the storage address corresponding to the first starting address in the second storage unit, and the system waits for the last data identifier signal of the next response data, thereby ensuring the sequential execution of read data volume statistics and further improving the accuracy of read data volume acquisition.

[0087] For example, queue A sends three read requests sequentially to the bus: Read Request A, Read Request B, and Read Request C. The processor assigns corresponding read request IDs (rid signals) to these requests at addresses 10, 20, and 30, respectively. Based on the requested data volume, the processor allocates memory spaces for CELL0-CELL4, CELL8-CELL10, and CELL20-CELL25 for these three requests, respectively. Since Read Request A is the first read command initiated by queue A, queue A uses registers to remember that the current queue head is CELL0. Simultaneously, a pre-allocation mechanism is used; after allocating space for each read command, a CELL is pre-allocated for the next read request. For example, after Read Request A, CELL8 is pre-allocated for the next command, Read Request B. Here, it is assumed that CELL50 is pre-allocated after Read Request C. The contents stored at addresses 10, 20, and 30 are as follows:

[0088] Address 10: The starting address for storing the data read this time is CELL0. The starting address for storing the data read in the next read request is CELL8. The amount of data requested this time is DATA_CNT0.

[0089] Address 20: The starting address for storing the data read this time is CELL8. The starting address for storing the data read in the next read request is CELL20. The amount of data requested this time is DATA_CNT1.

[0090] Address 30: The starting address for storing the data read this time is CELL20. The starting address for storing the data read in the next read request is CELL50. The amount of data requested this time is DATA_CNT2.

[0091] like Figure 8 As shown: When the three read commands return sequentially, the contents stored in cal_ram will change as follows. Figure 8The changes are shown below. Specifically, the rlast signal corresponding to read request A triggers a read of id_ram. The read data of id_ram shows that the starting cell where the read data returned by the bus is stored is the head cell of queue A, which is CELL0. Therefore, the data volume of queue A is directly updated to DATA_CNT0, the head cell of queue A is updated to CELL8, and CELL8 is read. If no return is found, id_ram is no longer read and the queue enters a waiting state. After the rlast signal corresponding to read request B returns, the data volume of queue A is updated to DATA_CNT0 through the same mechanism. The process starts with +DATA_CNT1, updates the head cell of queue A to cell 20, and reads cell 20. Finding no return, it stops reading cal_ram and enters a waiting state. Once the rlast signal corresponding to read request C returns, the same mechanism is used to update the data size of queue A to DATA_CNT0 + DATA_CNT1 + DATA_CNT2, update the head cell of queue A to cell 50, and read cell 50. Since cell 50 is pre-allocated, it definitely hasn't returned, so it waits for the next write operation to cal_ram.

[0092] like Figure 9 As shown: When three read commands are returned out of order, for example, read request C is returned first. response data It reads the response data from request B, and finally reads the response data from request A. The contents stored in cal_ram will be as follows: Figure 9The changes are illustrated below. Specifically, when the `rlast` signal corresponding to read request C triggers a read of `id_ram`, the `id_ram` read data shows that the cache starting address of this read data is `CELL20`, not `CELL0`, which is where queue A is waiting. Queue A continues to wait. The read data from `id_ram` is stored in `cal_ram` at `CELL20` according to the storage starting address `CELL20` in the read data. After the `rlast` signal corresponding to read request B returns, the same mechanism is used to find that the cache starting address of this read data is `CELL8`, not `CELL0`, which is where queue A is waiting. Queue A continues to wait, and the read data from `id_ram` is stored in `cal_ram` at `CELL8` according to the storage starting address `CELL8` in the read data. After the `rlast` signal corresponding to `CMDA0` returns, the same mechanism is used to find that the read data from `id_ram` shows that the cache starting address of this read data is indeed the head of queue A, `CELL0`. Therefore, the data size of queue A is directly updated to `DATA_CNT`. 0. Update the head cell of queue A to CELL8 and read CELL8. Finding it has returned, update the data size of queue A to DATA_CNT0 + DATA_CNT1. Update the head cell of queue A to CELL20 and read CELL20. Finding it has returned, update the data size of queue A to DATA_CNT0 + DATA_CNT1 + DATA_CNT2. Update the head cell of queue A to CELL50 and continue reading CELL50. Since CELL50 is pre-allocated, it has not returned yet, so wait for the next write operation to cal_ram.

[0093] The 1-bit return flag at each address in cal_ram needs to be cleared to zero during module initialization, or cleared to 0 after the data in CELL is requested to be output by the subsequent module. For example, after the data in CELL0 has been output to the subsequent module, all zeros need to be written to address 0 of cal_ram.

[0094] In this embodiment, instead of using registers to record the return status of each cell, the data volume information of multiple requests from each queue is directly recorded in RAM, which reduces the circuit area, simplifies the implementation difficulty of back-end layout and routing, improves the operating frequency of the circuit, and thus improves the performance of the chip.

[0095] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0096] In one embodiment, a chip, such as Figure 10 As shown, the chip may include a read data processing device as described in any of the preceding embodiments.

[0097] In one embodiment, an electronic device, such as Figure 11 As shown, the electronic device may include a chip as described in any of the preceding embodiments.

[0098] In one embodiment, a computer-readable storage medium is also provided, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the preceding embodiments.

[0099] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data processing device, characterized in that, include: The processor and the first memory unit; wherein, The processor is configured to write first record information into the first storage unit at the address corresponding to the read request ID; wherein the first record information includes at least a first starting address for storing first response data, a second starting address for storing second response data, and the amount of data of the first response data, the first response data being the response data of the current read request corresponding to the read request ID, the second response data being the response data of the next read request of the current read request, and the current read request and the next read request being triggered by the same read request queue; The processor is further configured to read the first record information from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit when receiving a bus return identification signal, and update the read data volume information of the target read request queue according to the first record information when it is determined that there is a target read request queue in the read request queue; wherein, the identification signal is the prompt signal of the last data of the response data, and the target read request queue is the read request queue in the read request queue whose starting address is the same as the first starting address.

2. The apparatus according to claim 1, characterized in that, The device further includes: a second storage unit; the processor is specifically used for: Update the read data volume information of the target read request queue using the data volume in the first record information; Read the corresponding second record information from the address in the second storage unit that corresponds to the second starting address in the first record information; the second record information includes at least the data volume of the first response data, the second starting address, and the feedback status information of the first response data. When the feedback status information in the second record information indicates that the corresponding first response data is in a returned state, the read data volume information of the target read request queue is updated using the data volume of the first response data read in the second record information. Continue reading the second record information from the address corresponding to the second starting address in the second record information read in the second storage unit until the feedback status information in the second record information indicates that the corresponding first response data is in a no-feedback state; otherwise, update the read data volume information of the target read request queue using the data volume in the second record information.

3. The apparatus according to claim 2, characterized in that, The processor is also used for: When the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, the first address of the target read request queue is updated to the first starting address where the non-returned first response data is stored.

4. The apparatus according to claim 2, characterized in that, The processor is also used for: When it is determined that the target read request queue does not exist in the read request queue, the second record information is written into the storage address corresponding to the first starting address in the second storage unit.

5. A method for processing read data volume, characterized in that, The method includes: Write first record information at the address corresponding to the read request ID in the first storage unit. The first record information includes at least a first starting address for storing the first response data, a second starting address for storing the second response data, and the data volume of the first response data. The first response data is the response data of the current read request corresponding to the read request ID, and the second response data is the response data of the next read request of the current read request. The current read request and the next read request are triggered by the same read request queue. Upon receiving a bus return identification signal, the first record information is read from the storage address corresponding to the read operation ID tag of the returned response data in the first storage unit. When it is determined that a target read request queue exists in the read request queue, the read data volume information of the target read request queue is updated according to the first record information. The identification signal is the prompt signal of the last data of the response data, and the target read request queue is the read request queue whose starting address is the same as the first starting address.

6. The method according to claim 5, characterized in that, The step of updating the read data volume information of the target read request queue according to the first record information specifically includes: Update the read data volume information of the target read request queue using the data volume in the first record information; Read the corresponding second record information from the address in the second storage unit that corresponds to the second starting address in the first record information; the second record information includes at least the data volume of the first response data, the second starting address, and the feedback status information of the first response data. When the feedback status information in the second record information indicates that the corresponding first response data is in a returned state, the read data volume information of the target read request queue is updated using the data volume of the first response data read in the second record information. Continue reading the second record information from the address corresponding to the second starting address in the second record information read in the second storage unit until the feedback status information in the second record information indicates that the corresponding first response data is in a no-feedback state; otherwise, update the read data volume information of the target read request queue using the data volume in the second record information.

7. The method according to claim 6, characterized in that, The method further includes: When the feedback status information in the second record information indicates that the corresponding first response data is in a non-returned state, the first address of the target read request queue is updated to the first starting address where the non-returned first response data is stored.

8. The method according to claim 6, characterized in that, The method further includes: When it is determined that the target read request queue does not exist in the read request queue, the second record information is written into the storage address corresponding to the first starting address in the second storage unit.

9. A chip, characterized in that, Includes the data reading processing device as described in any one of claims 1-4.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

11. A computer-readable storage medium, characterized in that, When a computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 8.

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