Link status detection for high-speed signaling interconnection

Abstract

The present disclosure relates to link condition detection for high-speed signaling interconnects. A system includes a first device and a second device coupled to a link having one or more paths associated with a transmit clock signal. The first device is to transmit a set of bits associated with a pattern via the one or more paths. The set of bits is transmitted using a first clock signal having a first frequency, the first frequency being less than a second frequency associated with a data transfer operation. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits within a first period, and determine that the number of pulses associated with the set of bits satisfies a predetermined condition related to the number of pulses of the first period. The second device is to initiate training of the link in response to determining that the number of pulses satisfies the predetermined condition.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating high-speed communications.For example, at least one embodiment relates to techniques for link condition detection in ground reference signaling (GRS) interconnects. Background Art

[0002] A communication system transmits a signal from a transmitter to a receiver via a communication channel or medium (e.g., a cable, a printed circuit board, a link, wireless, etc.). To ensure that data is communicated reliably when performing chip-to-chip (C2C) communication, the communication channel (e.g., a link) can be trained before the data is transmitted. Before training the link, each chip can determine whether the other chip is ready to start link training - for example, whether the other chip is powered on and ready for link training. Some communication systems attempt to detect link status (e.g., whether the other chip is ready for link training) by using software-managed initialization. For example, a communication system can enable the software of one chip to communicate with the software of other chips. In a communication system that utilizes multiple chips with different software stacks (e.g., software protocols), where the link is the primary form of communication between chips, software communication may be unreliable or infeasible. Other communication systems may utilize additional hardware to communicate link status. Such an approach may utilize additional area, be more costly, and consume additional resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1 is an example communication system employing a method for link condition detection in accordance with at least some embodiments;

[0005] Figure 2 An example communication system employing methods for link condition detection in accordance with at least some embodiments is shown;

[0006] Figure 3 is an example communication system employing a method for link condition detection in accordance with at least some embodiments;

[0007] Figure 4 is a flow chart of a method for link condition detection in a high-speed interconnect system according to at least some embodiments;

[0008] Figure 5 An example computer system including a transceiver including a chip-to-chip interconnect for link condition detection is shown in accordance with at least some embodiments. DETAILED DESCRIPTION

[0009] Communication systems transmit signals from a transmitter to a receiver via a communication channel or medium (e.g., a cable, a printed circuit board, a link, wireless, etc.). Some communication systems train the communication channel or medium (e.g., a link) during an initialization sequence (e.g., before transmitting data) to ensure that signals are reliably transmitted. Prior to training the link, each device or chip in the communication system can determine whether other devices in the communication system are powered on and ready for link training - e.g., determine link status. If the other devices are not ready (e.g., not initialized), the link training can fail - e.g., certain components of each device can be initialized prior to the link training occurring. Some communication systems can include multiple devices that execute separate (e.g., isolated) software stacks. For example, a communication system can include a first device (e.g., a first integrated circuit (IC) or chip) and a second device (e.g., a second IC or chip) and communicate data via a ground reference signaling (GRS) link - e.g., the communication system can be a chip-to-chip (C2C) interconnect with two devices that include a transmitter and a receiver. The first device and the second device can execute isolated software stacks, which can cause the first device and the second device to be out of sync in their initialization sequences - e.g., the first device can be powered on and ready for training, while the second device is powered off. That is, due to the isolated software stacks, neither device can rely on software to determine whether the other device is powered on, powered off, initialized, exited from reset, etc., and thus link training cannot be initiated via software.

[0010] In some communication systems, sending a static pattern indicating link status can be unreliable. For example, when a link is not trained, there can be channel noise or receiver skew - e.g., data can be received through a data lane or data path of the link at different times. The channel noise or receiver skew can cause aliasing of the transmitted static pattern, resulting in false detection and initialization failure - e.g., a first device receiving the static pattern can falsely determine that a second device is ready for link training due to aliasing of the static pattern. For example, in a GRS communication system, channel noise can occur when data is not effectively driven due to the link referencing ground and the terminals also being grounded. In such an example, a receiver of either device can receive an aliased static pattern due to channel noise and falsely determine that the other device is ready for link training. Similarly, due to channel noise, it is not feasible to look for voltage transitions to determine link status - e.g., a receiver of the first or second device cannot determine whether a voltage transition is a result of a signal transmitted by the other device or a result of channel noise. Furthermore, adding a dedicated pin to indicate link readiness can reduce area on the link, increase cost, and consume additional resources - e.g., adding a general purpose input / output (GPIO) pin to indicate link readiness can be traced on a PCB, increase cost, and consume additional resources.

[0011] Advantageously, aspects of the present disclosure can address the aforementioned deficiencies and other challenges by providing a method for link status detection using a dynamic pattern transmitted via a link's clock channel. For example, when each device powers on (e.g., exits reset or begins initialization), each device can initialize its receiver and then its transmitter. Each device can begin transmitting the dynamic pattern via the link's clock channel at a slower clock speed. For example, each device can transmit the pattern at a clock speed that is lower than the clock speed associated with data transmission (e.g., lower than the speed required for high-speed communication). Because the pattern is transmitted at a slower clock speed, the pattern is less affected by channel noise and offset. Furthermore, each device can utilize its receiver to detect any incoming pattern. For example, each device can configure counter logic to determine the number of pulses received within a configurable time period—for example, a device can determine the average frequency of an incoming pattern by detecting edges in the pattern within that time period. The device can set a longer or shorter time period based on the amount of channel noise or offset present in the system—for example, if the system has a relatively large amount of channel noise or offset, a longer time period can be selected for counting pulses. Each device can then compare the determined number of pulses with an expected pulse count (e.g., the expected average frequency for dynamic mode). When a device determines that the number of pulses determined during the period matches the expected number of pulses, the device can determine that the link is ready for training—for example, determining that the other device has powered on and initialized. The device can also stop transmitting in slow clock mode, switch to full clock speed, and resume the initialization sequence and link training.

[0012] For example, a first device may power up, initialize, and begin transmitting a pattern at a slow clock speed over the link to a second device. The first device may also begin detection at the receiver by determining the number of pulses received during this period. Later, a second device may power up, initialize, and begin transmitting a slow clock speed over the link to the first device. The second device may also begin detection at the receiver by determining the number of pulses received during this period. Thus, the first device receiver may receive the pattern transmitted by the second device at a slow clock speed and determine that the link is ready for training, while the second device receiver may also receive the pattern from the first device at a slow clock speed and determine that the link is ready for training. In this way, even if the initialization of the first and second devices begins asynchronously, at some point during initialization, each device may simultaneously transmit a pattern at a slow clock speed and detect the pattern at a slow clock speed at the receiver. In such an example, both devices can determine whether the other is ready for link training, stop transmitting the pattern at the slow clock speed, and switch to a high-speed clock.

[0013] By utilizing the clock lane of the link to transmit the slow clock speed dynamic pattern, each device of the communication system can determine the status of the link. Because the pattern is transmitted on the clock lane, the communication system can avoid utilizing additional hardware - for example, transmitting the pattern at the slow clock speed on the data lane would result in additional hardware being added to the system. Moreover, the communication system can reliably detect the link status without the need for software intervention or additional GIPO pins dedicated to link status readiness. Thus, embodiments of the present application allow for a more reliable method of training the link in a high speed interconnect system.

[0014] Figure 1 An example communication system 100 is shown in accordance with at least one example embodiment. The system 100 includes a device 110, a communication network 108 including a communication channel 109, and a device 112. In at least one example embodiment, the devices 110 and 112 correspond to one or more of a personal computer (PC), a laptop computer, a tablet computer, a smartphone, a server, a collection of servers, etc. In some embodiments, the devices 110 and 112 can correspond to any suitable type of device that communicates with other devices connected to a common type of communication network 108. In accordance with embodiments, the receiver 104 of the device 110 or 112 can correspond to a graphics processing unit (GPU), a switch (e.g., a high speed network switch), a network adapter, a central processing unit (CPU), a storage device, an input / output (I / O) device, other peripheral devices or components on a system on a chip (SoC), or other devices and components that receive or measure signals, etc. As another specific, but non-limiting, example, the devices 110 and 112 can correspond to a server that provides information resources, services, and / or application programs to user devices, client devices, or other hosts in the system 100.

[0015] Examples of the communication network 108 that can be used to connect the devices 110 and 112 include an Internet Protocol (IP) network, an Ethernet network, an InfiniBand (IB) network, a Fibre Channel network, the Internet, a cellular communication network, a wireless communication network, a ground reference signaling (GRS) link, combinations thereof (e.g., Fibre Channel over Ethernet), and variants thereof, etc. In one specific, but non-limiting, example, the communication network 108 is a network that enables data transfer between the devices 110 and 112 using data signals (e.g., digital, optical, wireless signals).

[0016] The device 110 includes a transceiver 116 for transmitting and receiving signals (e.g., data signals). The data signals can be digital signals or optical signals modulated with data, or other suitable signals for carrying data.

[0017] The transceiver 116 may include a digital data source 120, a transmitter 102, a receiver 104, and processing circuitry 132 for controlling the transceiver 116. The digital data source 120 may include suitable hardware and / or software for outputting data in a digital format (e.g., binary code and / or thermometer code). The digital data output by the digital data source 120 may be retrieved from a memory (not shown) or generated based on input (e.g., user input).

[0018] Transmitter 124 includes suitable software and / or hardware for receiving digital data from digital data source 120 and outputting a data signal based on the digital data for transmission to receiver 104 of device 112 via communication network 108. Additional details of the structure of transmitter 124 are discussed in greater detail below with reference to the accompanying drawings.

[0019] The receiver 104 of devices 110 and 112 may include suitable hardware and / or software for receiving signals, such as data signals from the communication network 108. For example, the receiver 104 may include components for receiving and processing signals to extract data for storage in a memory, as described below with respect to Figure 2-Figure 4 Detailed description. In at least one embodiment, the receiver 104 may include a clock circuit 115. In some embodiments, the clock circuit 115 may be configured to receive a clock signal from a clock channel of the communication network 108. In some embodiments, the clock circuit 115 may detect the link condition of the communication network 108 before the link is trained - for example, the clock circuit 115 may detect the link condition when the first device 110 and / or the second device 112 are powered on and initialized. For example, during an initialization sequence, the transmitter 124 may transmit a dynamic pattern at a low clock speed (e.g., at a clock speed slower than the clock speed associated with data transmission) over the clock channel. In such an embodiment, the receiver 104 may be configured to receive the pattern at the low clock speed and determine the number of pulses detected within a predefined period or duration. If the receiver 104 determines that the number of pulses matches the expected number of pulses for the duration, the device 110 or the device 112 may determine that the link is ready to be trained. Additional details regarding link condition detection will be referred to. Figure 2-Figure 4 Provide a description.

[0020] The processing circuit 132 can include software, hardware, or a combination thereof. For example, the processing circuit 132 can include a memory that includes executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory can correspond to any suitable type or types of memory devices or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that can be used include flash memory, random access memory (RAM), read only memory (ROM), variations and combinations thereof, and the like. In some embodiments, the memory and the processor can be integrated into a common device (e.g., a microprocessor can include integrated memory). Additionally or alternatively, the processing circuit 132 can include hardware such as an application specific integrated circuit (ASIC). Other non-limiting examples of the processing circuit 132 include an integrated circuit (IC) chip, a central processing unit (CPU), a general purpose processing unit (GPU), a microprocessor, a field programmable gate array (FPGA), a collection of logic gates, transistors, resistors, capacitors, inductors, diodes, and the like. Some or all of the processing circuit 132 can be provided on a printed circuit board (PCB) or collection of PCBs. It will be appreciated that any suitable type or collection of electrical components can be suitable for inclusion in the processing circuit 132. The processing circuit 132 can send and / or receive signals to and from other elements of the transceiver 116 to control the overall operation of the transceiver 116.

[0021] The transceiver 116, or selected elements of the transceiver 116, can take the form of a pluggable card or controller for the device 110. For example, the transceiver 116, or selected elements of the transceiver 116, can be implemented on a network interface card (NIC).

[0022] The device 112 can include a transceiver 136 for transmitting and receiving signals, such as data signals, over the channel 109 of the communication network 108. The same or similar structure of the transceiver 116 can apply to the transceiver 136, and therefore, the structure of the transceiver 136 is not described separately.

[0023] Although not explicitly shown, it will be appreciated that the devices 110 and 112, and the transceivers 116 and 120, can include other processing devices, storage devices, and / or communication interfaces that are generally associated with computing tasks, such as transmitting and receiving data.

[0024] Figure 2 An example communication system 200 is shown in accordance with at least one example embodiment. The system 200 includes the device 110 and the device 112, as described with reference to Figure 1 The device 110 and the device 112 can be coupled to a link 220. In at least one embodiment, the link 220 can be an example of the communication network 108, as described with reference to Figure 1described. In at least one embodiment, link 220 can be an example of a high-speed interconnect. For example, link 220 can be an example of a ground reference signaling (GRS) link 220. In an embodiment, GRS link 220 can be a signaling scheme for serial data transmission between devices 110 and 112. In at least one embodiment, GRS link 220 can be a high-speed link (e.g., 40 gigabits per second (GBPS) at a frequency of 20 gigahertz when performing high-speed communication). In at least one embodiment, link 220 can include an RC-dominated channel and an LC transmission line. In addition, GRS link 220 can be an on-chip link, a link across a substrate (e.g., an organic package), or a link signaling on a printed circuit board (PCB). In some examples, GRS link 220 can use a ground network as a signal reference voltage—for example, grounding can be return signaling.

[0025] In at least one embodiment, link 220 may include data channel 202 and data channel 203 configured to transmit signals, data, messages, etc. between device 110 and device 112. For example, data channel 202 may be associated with communicating signals, data, or messages from device 110 to device 112. Data channel 203 may be associated with communicating signals, data, or messages from device 112 to device 110—for example, data channel 202 may be associated with transmitter 102 of device 110, and data channel 203 may be associated with a transmitter of device 112. In at least one embodiment, link 220 may include the same number of data channels 202 and data channels 203. In this embodiment, data channel 202 may be associated with data channel 203—for example, data channel 202-a and data channel 203-a may be a single transmitter / receiver data channel pair 204. In at least one embodiment, link 220 may include "N" data channel pairs—for example, "N" data channels 202 and data channels 203. In some embodiments, data lane 202 can be associated with forwarding clock lane 205-a, and data lane 203 can be associated with forwarding clock lane 205-b. In at least one embodiment, each clock lane can be associated with two or more data lanes—e.g., at least two data lanes 202 or data lanes 203. In at least one embodiment, data lane 202 transmits data to device 112. In such an embodiment, the data is latched onto the forwarding clock at the receiver of device 112. In some embodiments, data lane 202 and the corresponding data lane 203 are identical—e.g., each data lane 202 and the corresponding data lane 203 support the same signaling speed and include the same drivers and hardware.

[0026] In at least one embodiment, device 110 and device 112 may execute isolated (e.g., different) software stacks. In such an embodiment, link 220 may be the primary communication between device 110 and device 112—e.g., device 110 and device 112 may not rely on software-managed initialization. In at least one embodiment, device 110 and device 112 may initialize asynchronously. That is, device 110 and device 112 may power up at different times, come out of reset at different times, or be at different stages of the initialization process.

[0027] In at least one embodiment, link 220 can be trained before communicating data (e.g., functional data) to ensure that the data is reliably communicated—e.g., to avoid different delays across data lanes 202 and data lanes 203. To train link 220, devices 110 and 112 can be powered on and have completed some initialization—e.g., initializing a receiver and a transmitter coupled to link 220. Thus, each device 110 and 112 can determine whether the other device is ready for link training before initiating link training—e.g., each device can determine the link status before initiating link training. Because devices 110 and 112 cannot communicate using software, devices 110 and 112 can communicate their link status (e.g., whether the devices are ready for link training) via clock lane 205 in order to proceed with link training as described herein.

[0028] For example, device 110 and device 112 may begin initialization upon power-up or upon exiting reset. In some embodiments, device 110 and device 112 may first initialize the receiver (e.g., receiver 104) and then initialize the transmitter (e.g., transmitter 124)—for example, device 110 or device 112 may be initialized to receive and detect incoming signals before beginning to transmit signals. After initializing the receiver and transmitter, device 110 or device 112 may begin transmitting a low-speed (e.g., at a speed slower than the high-speed clock) pattern on clock channel 205. In some embodiments, the low speed may be between 0.5 GHz and 2.5 GHz. In some embodiments, when another device is initialized, the other device may also begin transmitting the low-speed pattern on clock channel 205 in the other direction. For example, if device 110 is initialized first, device 110 may first begin detecting and transmitting the low-speed pattern, and when device 112 is initialized, device 112 may also begin detecting and transmitting the low-speed pattern. Thus, although device 110 and device 112 may begin the initialization sequence asynchronously, at some point in time, both device 110 and device 112 may be transmitting the low speed pattern simultaneously.

[0029] In an embodiment, while transmitting the low-speed pattern, device 110 or device 112 can also detect the incoming signal on clock channel 205. For example, device 110 or device 112 can detect the number of pulses received within a predefined time period. Device 110 or device 112 can compare the detected number of pulses with the expected number of pulses for the incoming low-speed pattern. Therefore, when the detected number of pulses meets (e.g., matches or is equal to) the expected number of pulses for the low-speed pattern, device 110 or device 112 can determine the link status. That is, when both device 110 and device 112 are transmitting the low-speed pattern, the other device can determine that the link is ready by detecting the low-speed pattern. In such an embodiment, device 110 and device 112 can stop transmitting the low-speed pattern, switch from the low-speed mode to the high-speed mode, and start link training or perform other remaining initializations before starting link training.

[0030] Figure 3 An example communication system 300 is shown according to at least one example embodiment. In at least one embodiment, the communication system 300 is an example of the communication system 100 or 200, as shown in FIG. Figure 1 and Figure 2 System 300 includes device 110 and device 112, as described in reference Figure 1 Device 110 and device 112 may be coupled to link 220, as described with reference to Figure 2 As described—for example, GRS link 220. Device 110 may include transmitter 124, as described with reference to Figure 1 As described, the device 112 may include a receiver 104, as described with reference to Figure 1 In at least one embodiment, the components shown in receiver 104 may be considered to be part of clock circuit 115, as described in reference to FIG. Figure 1 described. Figure 3 The circuit corresponding to the clock channel 205-a is shown, but the communication system 300 may include circuits corresponding to the clock channel 205-a. Figure 2The described clock lane 205-b corresponds to similar circuitry. That is, the device 110 can also include a receiver 104 and the device 112 can include a transmitter 124 associated with the clock lane 205-b. The transmitter 124 can include a DQ pattern generator 305 and a driver 315. The receiver 104 can include a sampler 320, one or more dividers 325, a multiplexer 330, a low pass filter (LPF) 335, a local phase-locked loop (PLL) 340, a clock counter 345, and an expected pulse count 350. In some embodiments, the LPF 335, the local PLL 340, the expected pulse count 350, and the clock counter 345 can be digital logic. In at least one embodiment, the clock counter 345 and the expected pulse count 350 can be coupled to a controller or otherwise controlled by a signal received as described with reference to FIG. 1. Figure 1 The described processing circuit 132 receives a signal that controls.

[0031] In some embodiments, the device 110 can power up, exit reset, or otherwise perform an initialization step. In such embodiments, the device 110 can first initialize its receiver 104, and then initialize the transmitter 124. After initializing the transmitter 124, the transmitter 124 can begin transmitting a low clock speed pattern as described with reference to FIG. 1. Figure 2 In such embodiments, the DQ pattern generator 305 can be configured to generate the pattern to be transmitted. For example, the DQ pattern generator 305 can generate a set of bits corresponding to the pattern. In some embodiments, the DQ pattern generator 305 can be configured to receive a local link condition 310 from the receiver 104 at the device 110. In some embodiments, the local link condition 310 can indicate whether the receiver at the device 110 has detected a low speed clock pattern or signal from the device 112. That is, the DQ pattern generator 305 can be configured to generate the pattern from the time the device 110 is initialized until a low speed clock pattern is detected from another device— for example, the DQ pattern generator 305 can be configured to generate the pattern until the receiver 104 of the device 110 detects a low speed pattern from the device 112. For example, if the local link condition 310 indicates that the link is not ready for training (e.g., no low speed pattern has been detected from the device 112), the DQ pattern generator 305 can continue to generate the pattern and transmit the pattern to the driver 315. If the local link condition 310 indicates that the link is ready for training (e.g., the receiver 104 of the device 110 has detected a low speed pattern from the device 112), the DQ pattern generator 305 can stop generating the pattern and stop transmitting bits to the driver 315.

[0032] In an embodiment, the driver 315 is configured to drive (e.g., transmit) a group of bits generated by the DQ pattern generator 305 at a low speed through the clock channel 205-a. For example, the driver 315 can use a clock signal having a low speed frequency (e.g., a first frequency) to transmit a group of bits corresponding to the pattern. In some embodiments, the first frequency can be between 0.5-2.5 GHz, as shown in FIG. Figure 2 As described. That is, the driver 315 is configured to drive the pattern at a frequency less than the frequency associated with the data transfer operation. In some embodiments, the driver 315 may include circuitry for transferring the pattern at a low clock speed. In some embodiments, the driver 315 may include a serializer to serialize a set of bits received from the DQ generator 305 via the clock channel 205-a—for example, converting a set of parallel bits into serial bits and transferring the set of bits via the clock channel 205-a.

[0033] In an embodiment, sampler 320 may be configured to receive a group of bits and sample the group of bits. In at least one embodiment, sampler 320 may pass the received sampled group of bits to frequency divider 325. In some embodiments, sampler 320 may pass the sampled group of bits to multiplexer 330—for example, to avoid passing the sampled group of bits to frequency divider 325. In some embodiments, frequency divider 325 may be configured to divide down the frequency of the group of bits received from device 110. For example, frequency divider 325 may be configured to divide the received clock speed by 2, 4, 8, 16, etc. In some embodiments, device 112 may configure frequency divider 325 during initialization of receiver 104. That is, device 112 may determine that the low-speed clock pattern transmitted via clock channel 205-b is too fast—for example, channel noise from data skew may cause the low-speed clock pattern transmitted by transmitter 124 of device 112 to be unreliably transmitted. There may be a limit to how slowly transmitter 124 can transmit a signal. In embodiments where the minimum clock speed is unreliable, device 112 can configure divider 325 to further divide the clock speed received from device 110 to ensure that the clock pattern received from device 110 is reliable. Although one divider 325 is shown, receiver 104 can include multiple dividers—e.g., 2, 4, 8, 16, etc.—based on the preferred clock speed of device 104. Divider 325 can be configured to pass the divided clock pattern (e.g., the divided sampled set of bits) to multiplexer 330. In some embodiments, multiplexer 330 is configured to multiplex the set of bits received from sampler 320 or the divided set of bits received from divider 325 and pass the multiplexed bits to low-pass filter 335.

[0034] In an embodiment, low-pass filter 335 can be configured to further refine the sampled set of bits (or divided samples) from multiplexer 330. That is, the low-pass filter can remove short-term fluctuations and reduce noise on the sampled set of bits, so that clock counter 345 can receive an improved sample or signal. In at least one embodiment, low-pass filter 335 can be coupled to local PLL 340. In some embodiments, local PLL 340 can generate an output signal for low-pass filter 335. For example, local PLL 340 can be initialized or configured to operate at a high-speed frequency (e.g., a frequency used for data transmission operations). In such an embodiment, local PLL 340 can be used to sample the samples received at low-pass filter 335. Local PLL 340 and low-pass filter 335 can be used to remove high-frequency components from the output of the phase detector—for example, removing higher frequencies to produce a noise-reduced signal for clock counter 345.

[0035] In one embodiment, clock counter 345 can be configured to detect the number of pulses in a sampled set of bits (e.g., a detected pattern) received from low-pass filter 335 (e.g., or from multiplexer 330 in embodiments where low-pass filter 335 is not used) during a predefined time period. In some embodiments, clock counter 345 can detect the number of pulses by determining the number of edges (e.g., the number of times a signal rises or falls) during a predefined duration. The clock counter can determine the average frequency of the sampled set of bits—e.g., the average frequency of the pattern received at receiver 104 from device 110. In some embodiments, the predefined time period can be configurable. For example, processing circuitry 132 or a controller coupled to clock counter 345 can select the time period for detecting the number of pulses—e.g., processing circuitry 132 can select a time period from a programmed list of possible time periods. In some embodiments, a larger time period can reduce the likelihood of noise affecting the received signal—e.g., allowing for more accurate detection of low-speed clock patterns. In some embodiments, a smaller time period can allow for faster determination of link status—e.g., reducing overall initialization time. Thus, processing circuit 132 may select a time period based on a weighted consideration between accuracy and time—for example, processing circuit 132 may select a smaller time period when there is less noise in communication system 300, and a larger time period when there is more noise in communication system 300. After detecting the number of pulses within the time period, clock counter 350 may compare the detected number of pulses with the expected number of pulses received from expected pulse count 350. That is, expected pulse count 350 may store the expected number of pulses for the low-speed clock mode of transmission and reception in communication system 300.

[0036] In some embodiments, if the detected number of pulses differs from the expected number of pulses, clock counter 345 may determine that the other device (e.g., device 110) is not ready to train the link—e.g., determine that the link is not ready to be trained. In such an embodiment, clock counter 345 may transmit local link status 355 to transmitter 124 of device 112, indicating that the link is not ready to be trained. Therefore, transmitter 124 may continue to transmit a low-speed clock pattern to device 110. That is, if second device 112 is initialized first, device 112 may detect the low-speed clock pattern and transmit the low-speed clock pattern to device 110. Because device 110 may not be initialized while device 112 is transmitting and detecting the low-speed clock pattern, clock counter 345 may determine that the received number of pulses differs from the expected number of pulses and instruct transmitter 124 of device 112 to continue transmitting the low-speed pattern.

[0037] In some embodiments, if the detected number of pulses is the same as the expected number of pulses (e.g., meets the expected number of pulses), clock counter 345 can determine that the other device (e.g., device 110) is ready to train the link—e.g., determine that the link is ready to be trained. In such an embodiment, clock counter 345 can transmit a local link status 355 to transmitter 124 of device 112, indicating that the link is ready to be trained. Consequently, transmitter 124 of device 112 can cease transmitting the low-speed clock pattern. That is, if device 112 detects the low-speed clock pattern from device 110, device 110 can also detect the low-speed clock pattern from device 112, and thus, both devices 110 and 112 can cease transmitting the low-speed clock pattern. In such an embodiment, even if device 110 and device 112 begin initialization asynchronously, at some point, devices 110 and 112 simultaneously transmit the low-speed clock pattern and determine that the other device is ready for link training.

[0038] In some embodiments, the clock counter 345 can be configured to detect the number of pulses as being the same as the expected number of pulses for a plurality of time periods. For example, the clock counter 345 can be configured to detect the number of pulses as being the same as the expected number of pulses for two (2) time periods, where each time period has the same value. In other embodiments, the clock counter 345 can detect the number of pulses as being the same as the expected number of pulses for greater than two (2) time periods. That is, the clock counter 345 can refrain from indicating that the link is ready for training until a low-speed clock pattern is detected within a specified number of time periods. In some embodiments, having the specified number of time periods be greater than one (1) can improve accuracy and reduce false positives.

[0039] In some embodiments, device 110 and device 112 may perform link training after determining the link status—e.g., after determining that the link is ready for training. In other examples, device 110 or device 112 may wait for a second period of time—e.g., a device may be configured to wait for a second period of time after determining the link status to ensure that the other end also detects the link status or that the other end completes performing other initialization steps before continuing with link training. In some embodiments, device 110 or device 112 may perform the remaining steps of the initialization process before starting link training—e.g., a device may complete any remaining steps in the initialization process before continuing with link training.

[0040] Figure 4 A flow chart of a method 400 for link condition detection in a high-speed interconnect is shown. For example, the method 400 illustrates transmitting and detecting a low-speed clock pattern on a clock channel of a high-speed interconnect. The method 400 may be performed by processing logic including hardware, software, firmware, or any combination thereof. In at least one embodiment, the method 400 is performed by a transmitter 124 or a receiver 104 of a first device 110 or a second device 112, as described with reference to FIG. Figure 4 In some embodiments, messages may be communicated over the GRS link 220, as described in reference Figure 2 Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other diagrams illustrating methods for link training via handshake are possible.

[0041] At operation 405, the first device 110 may initialize the receiver 104 and the transmitter 124. In some embodiments, the device 110 (e.g., the first device or the second device) may initialize the receiver 104 before initializing the transmitter 124. In some embodiments, the device 110 may initialize the local PLL 340 while initializing the receiver 104—for example, setting the local PLL 340 to a high-speed frequency. In some embodiments, the device 110 may initialize the clock counter 345 during the initialization of the receiver 104. For example, the device 110 may select a time period for detecting multiple pulses, such as a reference pulse. Figure 3As described—for example, device 110 or device 112 (e.g., the first device or the second device) may select a first time period during which a number of pulses is determined from a plurality of time periods, each time period having a different value. In some embodiments, device 110 may also select a number of detection time periods during which the number of pulses detected matches the expected pulses before determining that the link is ready for training, as described with reference to FIG. Figure 4 As described—for example, detecting that the number of pulses matches the expected number of pulses for two (2) or more time periods. For example, device 110 or device 112 may determine that the number of pulses satisfies a predetermined condition related to the number of pulses within a plurality of time periods, each of the plurality of time periods having the same value, and wherein the number of time periods satisfies a threshold number of time periods for determining the number of pulses. In at least one embodiment, device 110 may also initialize one or more frequency dividers 325, as described with reference to Figure 3 In some embodiments, device 110 may initialize the local PLL of transmitter 124 during initialization of transmitter 124. In such embodiments, device 110 may configure transmitter 124 to transmit at a low speed—for example, using a PLL having a higher speed than that used for data transmission operations (as described in reference to FIG. Figure 3 The first clock signal of the first frequency which is smaller than the second clock signal of the first clock signal (described) is transmitted.

[0042] At operation 410, device 110 may transmit a set of bits associated with a pattern via one or more paths associated with a transmit clock signal. For example, device 110 may generate a set of bits at DQ pattern generator 305 and transmit the set of bits at a first frequency using a first clock signal. In some embodiments, transmitter 124 may transmit the set of bits on clock lane 205-a, for example, on a forwarded clock lane of GRS link 220.

[0043] At operation 415, device 112 may receive a set of bits from device 110. In at least one embodiment, device 112 may be initialized (e.g., powered on or out of reset) before receiving the set of bits. That is, device 112 may initialize its receiver 104 (e.g., enable clock counter 345) and then initialize its transmitter 124, as described with reference to operation 405. In some embodiments, device 112 may sample the set of bits received at the sampler, as described with reference to operation 405. Figure 3 As described - for example, the device 112 may determine the number of pulses in response to sampling a group of bits. In at least one embodiment, the device 112 may further divide the first clock signal down using one or more frequency dividers 325, as described with reference to FIG. Figure 3As described - for example, the device 112 may determine the number of pulses in response to dividing the first clock signal. In at least one embodiment, the device 112 may utilize a low pass filter 335 and a local PLL 340 to increase the reliability of the first clock signal, as described with reference to FIG. Figure 3 As described—for example, device 112 may determine the number of pulses in a time period in response to passing the first clock signal through low-pass filter 335 .

[0044] In some embodiments, device 112 may transmit a second set of bits corresponding to the pattern at the first frequency while receiving a set of bits from device 110, as described with reference to FIG. Figure 3 For example, device 112 may transmit the second set of bits at a first time that is different from the second time at which the first device transmits the set of bits—for example, device 112 may transmit the second set of bits after device 110 transmits the first set of bits. Wherein, device 110 and device 112 may start initialization asynchronously, as described with reference to Figure 3 In such an embodiment, device 110 and device 112 may synchronize while detecting link conditions, as described in reference to Figure 3 As described. For example, during a portion of the second time period, the second set of bits may be transmitted concurrently with the first set of bits. In some embodiments, device 110 and device 112 may be initialized synchronously. In such embodiments, device 112 may transmit the second set of bits during the second time period, wherein during a portion of the second time period, the second set of bits are transmitted concurrently with the first set of bits transmitted by device 110.

[0045] At operation 420, device 112 may determine a number of pulses associated with the group of bits during the first time period. For example, device 112 may detect a number of edges in a sampled (e.g., or sampled and divided) first clock signal. In some embodiments, device 112 may determine an average frequency of the first clock signal during the first time period. In some embodiments, device 110 may determine a number of pulses associated with a second group of bits simultaneously with device 112 determining the number of pulses associated with the group of bits. In some embodiments, device 110 may determine a number of pulses associated with a second group of bits simultaneously with device 112 determining the number of pulses associated with the group of bits during a portion of the first time period. In other words, device 110 may determine the link status simultaneously with device 112.

[0046] At operation 425, device 112 may determine whether the detected number of pulses satisfies a predetermined condition related to a number of pulses. For example, clock count 345 may compare the number of pulses detected during the first period with the expected number of pulses received from expected pulse count 350. In at least one embodiment, if the determined number of pulses satisfies (e.g., matches or is equal to) the expected number of pulses, receiver 104 of device 112 may indicate a link condition to transmitter 124 of device 112—e.g., receiver 104 may indicate that the link is ready for training. In such an embodiment, device 112 may stop transmitting the second set of bits after determining that the number of pulses satisfies the predetermined condition related to a number of pulses. In some embodiments, device 112 may wait after determining that the number of pulses satisfies the predetermined condition—e.g., device 112 may wait for device 110 to perform additional initialization operations before initiating link training. In some embodiments, device 110 may also determine that the detected number of pulses satisfies the predetermined condition related to a number of pulses and stop transmitting the set of bits. In some embodiments, if the determined number of pulses does not meet the expected number of pulses, the receiver 104 of the device 112 may indicate to the transmitter 124 of the device 112 that the link is not ready to be trained. In such an embodiment, the transmitter 124 may continue to transmit the second set of bits, and the receiver 104 may continue to detect incoming patterns or signals.

[0047] In operation 430, device 112 may initiate link training in response to determining that a number of pulses satisfies a predetermined condition related to the number of pulses. For example, device 112 may switch from a low-speed clock signal to a high-speed clock signal—e.g., to a second frequency. For example, device 112 may transmit a third set of bits corresponding to the second clock signal via one or more paths associated with the transmit clock signal after initiating the link, the third set of bits being transmitted at the second frequency. In some embodiments, device 112 may transmit the third set of bits after a second period of time, e.g., after a waiting period of time. In some embodiments, device 110 may also switch its transmitter 124 from low-speed operation to high-speed operation. In some embodiments, device 110 and device 112 may perform link training after detecting a link condition—e.g., after determining that the other device is ready for link training.

[0048] Figure 5A computer system 500 including a transceiver including a chip-to-chip interconnect is shown, according to at least one embodiment. In at least one embodiment, computer system 500 can be a system with interconnected devices and components, an SOC, or some combination. In at least one embodiment, computer system 500 is formed from a processor 502 that can include execution units to execute an instruction. In at least one embodiment, computer system 500 can include, without limitation, components such as processor 502 to employ execution units including logic to execute an algorithm for processing data. In at least one embodiment, computer system 500 can include a processor such as a Pentium® XScale™ and / or StrongARM™, Core TM or Nervana TM microprocessors, although the scope of the embodiments is not so limited. In at least one embodiment, computer system 500 can execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington. In at least one embodiment, other

[0049] In at least one embodiment, computer system 500 can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor (“DSP”), a System-on-a-Chip

[0050] In at least one embodiment, computer system 500 can include, without limitation, a processor 502 that can include, without limitation, one or more execution units 507 that can be configured to execute a compute unified device architecture (“CUDA”) ( (developed by NVIDIA Corporation of Santa Clara, California). In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 500 is a single-processor desktop or server system. In at least one embodiment, computer system 500 may be a multi-processor system. In at least one embodiment, processor 502 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, processor 502 may be coupled to a processor bus 510 that may transmit data signals between processor 502 and other components in computer system 500.

[0051] In at least one embodiment, processor 502 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 504. In at least one embodiment, processor 502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 502. In at least one embodiment, processor 502 may also include a combination of internal and external caches. In at least one embodiment, register file 506 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0052] In at least one embodiment, an execution unit 507, including but not limited to logic for performing integer and floating point operations, is also located in the processor 502. The processor 502 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 502 may include logic for processing a packed instruction set 509. In at least one embodiment, by including the packed instruction set 509 in the instruction set of the general-purpose processor 502, as well as associated circuitry for executing the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 502. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0053] In at least one embodiment, the execution unit may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, the computer system 500 may include, but is not limited to, a memory 520. In at least one embodiment, the memory 520 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. The memory 520 may store one or more instructions 519 and / or data 521 represented by data signals that may be executed by the processor 502.

[0054] In at least one embodiment, the system logic chip can be coupled to the processor bus 510 and the memory 520. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 516, and the processor 502 can communicate with the MCH 516 via the processor bus 510. In at least one embodiment, the MCH 516 can provide a high-bandwidth memory path 518 to the memory 520 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 516 can direct data signals between the processor 502, the memory 520, and other components in the computer system 500, and bridge data signals between the processor bus 510, the memory 520, and the system I / O 522. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 516 can be coupled to the memory 520 via the high-bandwidth memory path 518, and the graphics / video card 512 can be coupled to the MCH 516 via an Accelerated Graphics Port ("AGP") interconnect 514.

[0055] In at least one embodiment, the computer system 500 may use a system I / O 522, which is a proprietary hub interface bus, to couple the MCH 516 to an I / O controller hub ("ICH") 530. In at least one embodiment, the ICH 530 may provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 520, the chipset, and the processor 502. Examples may include, but are not limited to, an audio controller 529, a firmware hub ("Flash BIOS") 528, a transceiver 526, a data store 524, a traditional I / O controller 523 including a user input interface 525 and a keyboard interface, a serial expansion port 527 (such as USB), and a network controller 534. The data store 524 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. In an embodiment, the transceiver 526 includes a constrained FFE 508.

[0056] In at least one embodiment, Figure 5 A system is shown that includes interconnected hardware devices or "chips" in a transceiver 526 - for example, the transceiver 526 includes a chip-to-chip interconnect that includes a first device 110 and a second device 112, as shown in FIG. Figure 1 In at least one embodiment, Figure 5 An exemplary SOC may be shown. In at least one embodiment, Figure 5 The devices shown in FIG. 1 may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof, and utilize GRS links 220, as shown in FIG. Figure 2 In at least one embodiment, one or more components of system 500 are interconnected using a Compute Express Link ("CXL") interconnect. In an embodiment, transceiver 526 may include clock circuit 115, as described in reference Figure 1 As described. In such an embodiment, the clock circuit 115 can facilitate a method for link condition detection on a high-speed interconnect as described above. In an embodiment, the clock circuit 115 can detect a received pattern. For example, the clock circuit 115 can detect an incoming pattern at a low clock speed and detect the number of pulses in the pattern within a predefined period. The clock circuit 115 can compare the detected number of pulses to an expected number of pulses. If the clock circuit 115 determines that the detected number of pulses meets the expected number of pulses (e.g., the detected number of pulses is the same as the expected number of pulses), the clock circuit 115 can determine that the link is ready for training. Thus, the clock circuit can be configured for link condition detection, as described with reference to Figure 2-Figure 4 described.

[0057] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0058] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"), unless otherwise noted. The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. In at least one embodiment, unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0059] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like, which may be A or B or C, or any non-empty subset of the set of A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to a plurality (e.g., "a plurality of items" refers to a plurality of items). In at least one embodiment, the number of items in the plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0060] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively stores all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors.

[0061] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0062] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0063] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0064] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0065] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “compute,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0066] In a similar manner, the term "processor" may refer to any device or portion of memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. In at least one embodiment, the terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0067] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0068] Although the description herein sets forth example embodiments of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. Furthermore, although specific assignments of responsibilities are defined above for descriptive purposes, the various functions and responsibilities may be assigned and divided in different ways depending on the circumstances.

[0069] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A system comprising: a link comprising one or more paths associated with transmitting data and one or more paths associated with transmitting a clock signal; A first device coupled to the link and comprising a transmitter, the first device being configured to: transmitting a set of bits associated with a pattern via the one or more paths associated with transmitting the clock signal, wherein the set of bits is transmitted using a first clock signal having a first frequency that is less than a second frequency associated with a second clock signal used for data transfer operations; as well as a second device coupled to the link and comprising a receiver, the second device being configured to: receiving the set of bits associated with the pattern; determining a number of pulses associated with the set of bits during a first time period; determining that the number of pulses associated with the set of bits satisfies a predetermined condition related to the number of pulses for the first time period; as well as In response to determining that the number of pulses satisfies the predetermined condition associated with the number of pulses, training of the link is initiated.

2. The system according to claim 1, wherein the second device further comprises a transmitter, the second device being further configured to: A second set of bits associated with the pattern is transmitted to a receiver of the first device during a second time period, wherein the second set of bits is transmitted simultaneously with the first set of bits during a portion of the second time period.

3. The system according to claim 2, wherein the second device is further configured to: After determining that the number of pulses satisfies the predetermined condition associated with the number of pulses, the transmission of the second group of bits is stopped.

4. The system according to claim 1, wherein the second device further comprises a transmitter, the second device being further configured to: A second set of bits associated with the pattern is transmitted to a receiver of the first device at a first time, wherein the first time is different from a second time at which the first device transmits the set of bits.

5. The system according to claim 1, wherein the first device is further configured to: After initiating training of the link, ceasing transmission of the set of bits associated with the pattern; and A second set of bits corresponding to the second clock signal is transmitted via the one or more paths associated with transmitting the clock signal, wherein the second set of bits is transmitted at the second frequency.

6. The system of claim 1 , wherein the second device further comprises a sampler configured to sample the set of bits, and wherein the second device is configured to determine the number of pulses associated with the set of bits in response to sampling the set of bits.

7. The system according to claim 1, wherein the second device is further configured to: The first time period is selected, during which the number of pulses is determined from a plurality of time periods, each time period being associated with a different value.

8. The system according to claim 1, wherein the second device is further configured to: The number of pulses is determined to satisfy the predetermined condition relating to the number of pulses within a plurality of time periods, each of the plurality of time periods having the same value, and wherein the number of the plurality of time periods satisfies a threshold number of time periods for determining the number of pulses.

9. A method comprising: receiving, by a first device, a set of bits associated with a pattern, wherein the set of bits is received as a first clock signal having a first frequency that is less than a second frequency associated with a second clock signal used for a data transfer operation; determining, at the first device, a number of pulses associated with the set of bits within a first time period; determining, at the first device, that the number of pulses associated with the set of bits satisfies a predetermined condition related to the number of pulses for the first time period; as well as In response to determining that the number of pulses satisfies the predetermined condition associated with the number of pulses, training of the link is initiated.

10. The method according to claim 9, further comprising: A second set of bits associated with the pattern is transmitted by the first device to a second device during a second time period, wherein the second set of bits is transmitted concurrently with receiving the set of bits during a portion of the second time period.

11. The method according to claim 10, further comprising: After determining that the number of pulses satisfies the predetermined condition related to the number of pulses, the transmission of the second group of bits is stopped.

12. The method according to claim 11, further comprising: After stopping the transmission of the second set of bits, waiting for a second period of time; as well as After the second period, a third set of bits corresponding to the second clock signal is transmitted via one or more paths of the link associated with transmitting the first and second clock signals, wherein the third set of bits is transmitted at the second frequency.

13. The method of claim 10, wherein the set of bits is transmitted at a first time and the second set of bits is transmitted at a second time, the first time being different from the second time.

14. The method according to claim 9, further comprising: After initiating the training of the link, a second set of bits corresponding to the second clock signal is transmitted via one or more paths of the link associated with transmitting the second clock signal, wherein the second set of bits is transmitted at the second frequency.

15. The method according to claim 9, further comprising: The first time period is selected, during which the number of pulses is determined from a plurality of time periods, each time period being associated with a different value.

16. The method according to claim 9, further comprising: The number of pulses is determined to satisfy the predetermined condition relating to the number of pulses within a plurality of time periods, each of the plurality of time periods having the same value, and wherein the number of the plurality of time periods satisfies a threshold number of time periods for determining the number of pulses.

17. The method according to claim 9, further comprising: activating a receiver of the first device; as well as In response to activating the receiver, a transmitter of the first device is activated, wherein the transmitter is activated prior to receiving the set of bits corresponding to the pattern.

18. The method according to claim 9, further comprising: The first clock signal is divided at a frequency divider, wherein determining the number of pulses within the first time period is based at least in part on dividing the first clock signal.

19. A device comprising: A receiver coupled to a link, the link comprising one or more paths associated with transmitting data and one or more paths associated with transmitting a clock signal, the device being configured to: receiving a set of bits associated with a pattern, wherein the set of bits is received as a first clock signal having a first frequency that is less than a second frequency associated with a second clock signal used for a data transfer operation; determining a number of pulses associated with the set of bits within a first time period; determining that the number of pulses associated with the set of bits satisfies a predetermined condition related to the number of pulses for the first time period; as well as In response to determining that the number of pulses satisfies the predetermined condition associated with the number of pulses, training of the link is initiated.

20. The apparatus of claim 19, further comprising: a transmitter coupled to the link, the transmitter configured to: A second set of bits associated with the pattern is transmitted during a second time period, wherein the second set of bits is transmitted concurrently with receiving the set of bits during at least a portion of the second time period.

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