A dataflow-driven reconfigurable processor chip and a reconfigurable processor cluster

Abstract

The application discloses a data flow driven reconfigurable processor chip and a reconfigurable processor cluster. The reconfigurable processor chip comprises a plurality of reconfigurable processing units based on distributed storage, and the components of the reconfigurable processing units are logically interconnected, wherein the components comprise a reconfigurable computing component for computing data, a data flow controller adopting a data flow driven mode, the data flow driven mode controls the start and end of computing and data transmission tasks according to data flow information of a computing task and message transmission of upstream and downstream reconfigurable processing units, a distributed storage for realizing data storage of the corresponding reconfigurable processing unit, and a programmable data routing unit for realizing communication between the plurality of reconfigurable processing units, for controlling the direction of data packets and realizing flexible data packet transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of reconfigurable computing, in particular to a data flow driven reconfigurable processor chip and a reconfigurable processor cluster. BACKGROUND

[0002] At present, with the expansion of the application range and the increase of the task difficulty in the field of artificial intelligence, the artificial intelligence algorithm represented by the deep neural network gradually evolves towards the trend of super large scale model. The super large scale model such as GPT-3 has a parameter quantity of hundreds of billions. Training a large scale model such as GPT-3 needs to use thousands of GPU servers to train for about a month. Therefore, the performance improvement of the intelligent computing processing system is crucial to the training of the large model.

[0003] The parallel processing of the large scale model on the GPU cluster usually needs to adopt multiple parallel strategies to fully exert the parallel degree of the calculation, and the parallel ways include data parallelism, model parallelism and pipeline parallelism. On the one hand, the algorithm mainly adopts the data parallelism on a GPU card, and cannot mine the parallelism of other dimensions of the algorithm, which is easy to cause the problem of low actual computing power utilization rate. On the other hand, the distributed parallelism of the algorithm increases a large amount of communication demand, and the communication problem becomes one of the main factors affecting the system performance. At present, the GPU is based on the shared storage architecture, and the stream processors in the chip mainly communicate through the shared storage, which is easy to cause the problem of memory bottleneck. The traditional AI chip architecture, such as the TPU of Google, is also mainly designed based on the shared storage architecture. The increased communication demand of the distributed parallelism aggravates the problem of communication bottleneck. In view of the above problems, one of the development trends of the distributed AI hardware acceleration system design is to adopt the data flow driven mode, the data flow architecture is more close to the characteristics of the AI algorithm, and the calculation and communication can be separated as much as possible to alleviate the communication bottleneck problem under the distributed calculation of the large model.

[0004] In the large scale cluster computing scene, the data transfer efficiency is low and the delay is high due to the data cross-chip transmission between the GPU computing cards, which also becomes one of the main factors affecting the performance improvement of the system. The GPU cross-server communication also needs to adopt a high-speed network switch, which not only has a large communication cost, but also has a high cost of the high-speed network switch, and the cost of establishing a large scale GPU cluster is also difficult to reduce. SUMMARY

[0005] In view of the deficiencies in the prior art, the present application provides a data flow driven reconfigurable processor chip and a reconfigurable processor cluster.

[0006] According to an aspect of the present application, a reconfigurable processor chip is provided, comprising: a plurality of reconfigurable processing elements based on distributed storage, the components of the reconfigurable processing elements being logically interconnected, wherein the components comprise:

[0007] a reconfigurable computing component for computing data;

[0008] a data flow controller using a data flow driven mode to control the start and end of computing and data transmission tasks according to data flow information of the computing task and message passing of upstream and downstream reconfigurable processing elements;

[0009] a distributed storage for realizing data storage of the corresponding reconfigurable processing element;

[0010] a programmable data routing unit for realizing communication between the plurality of reconfigurable processing elements, for controlling the direction of data packets, and realizing flexible data packet transmission.

[0011] Optionally, the programmable data routing unit uses a software programmable routing strategy and changes the routing direction and destination of the data packet in real time through software configuration.

[0012] Optionally, the reconfigurable processing elements exchange data through an on-chip network, an inter-chip interface, and a network cable within the storage capacity range of the storage space.

[0013] Optionally, the reconfigurable processor chip further comprises: a plurality of computing areas divided from the plurality of reconfigurable processing elements according to algorithm mapping requirements, wherein

[0014] In the data driven mode of the data flow controller, the communication connection relationship of the programmable data routing unit is changed in real time by changing the execution graph configuration in the reconfigurable processing element, and the division of the computing area is changed according to the communication connection relationship.

[0015] Optionally, the plurality of computing areas perform pipelined computing or perform different computing tasks assigned.

[0016] According to another aspect of the present application, a reconfigurable processor cluster is provided, comprising: a plurality of reconfigurable processor chips, wherein the reconfigurable processor chips are composed of a plurality of reconfigurable processing elements based on distributed storage, the components of the reconfigurable processing elements being logically interconnected, comprising:

[0017] a reconfigurable computing component for computing data;

[0018] a data flow controller using a data flow driven mode to control the start and end of computing and data transmission tasks according to data flow information of the computing task and message passing of upstream and downstream RPEs;

[0019] Distributed memory for realizing data storage of corresponding reconfigurable processing units;

[0020] Programmable data routing unit for realizing communication between multiple reconfigurable processing units, for controlling the direction of data packets, realizing flexible data packet transmission.

[0021] Optionally, the reconfigurable processor cluster further comprises a routing control module for realizing data communication between multiple reconfigurable processor chips, and

[0022] The reconfigurable processing units between multiple reconfigurable processor chips realize data communication through the network via the programmable data routing unit and the routing control module, and the programmable data routing unit and the routing control module on the reconfigurable processor chip are connected through the network on the reconfigurable processor chip, wherein

[0023] The routing control module is used for receiving or sending network data packets between reconfigurable processor chips.

[0024] Optionally, the routing control module has bidirectional Ethernet data transceiving function, realizing sending of read request, write request, read response, write response control information;

[0025] The routing control module has flow control mechanism, has sending buffer back pressure and receiving buffer back pressure functions to control data transmission of the receiving end and the sending end.

[0026] Optionally, the reconfigurable processor cluster further comprises: according to algorithm mapping requirements, multiple reconfigurable processing units on the reconfigurable processor chip are divided into multiple computing areas, and

[0027] The reconfigurable processor cluster supports flexible division of computing areas, and supports asynchronous parallel computing of the computing areas.

[0028] Optionally, the reconfigurable processor cluster supports multiple computing modes of data parallelism, pipeline parallelism or model parallelism; and / or

[0029] The resources of the reconfigurable processor cluster are allocated to multiple task parallel computing.

[0030] Thus, the reconfigurable processing unit in the reconfigurable processor chip provided by the application adopts a data flow driven computing mode, and the start and end of a computing task are controlled according to data flow information of the computing task and message passing of upstream and downstream reconfigurable processor units, so that asynchronous parallel computing of each operation unit can be realized. The reconfigurable processor processing unit adopts distributed memory, each processor unit has an independent data routing module inside, and the processing units do not need to exchange data through a shared storage unit. The storage wall problem caused by large-scale central data transmission and the communication delay problem of large-scale centralized memory access are avoided. The reconfigurable processor processing unit adopts a software programmable routing strategy, and the data packet routing direction and destination can be changed in real time through software configuration. When a damaged processing unit is encountered, the routing path can be modified through software configuration to bypass the damaged processing unit or chip. At the same time, the mapping of the computing area is modified, the task is redistributed on the RPE that is working normally, and the data routing information and data flow information of the RPE are modified.

[0031] The above and other objects, advantages and features of the present application will become more apparent from the following detailed description of some embodiments thereof, when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] Some specific embodiments of the present application will be described in detail below with reference to the accompanying drawings, which are presented by way of illustration and not of limitation. The same reference numbers in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that the drawings are not necessarily drawn to scale. In the drawings:

[0033] Figure 1 is a schematic diagram of a reconfigurable processor chip architecture according to a first aspect of embodiments of the present application;

[0034] Figure 2 is a schematic diagram of a parallel mode of a reconfigurable processor according to embodiments of the present application;

[0035] Figure 3 is a schematic diagram of a parallel reconfigurable processor chip cluster according to a second aspect of embodiments of the present application;

[0036] Figure 4 is a fault-tolerant mechanism of a reconfigurable processing chip according to a second aspect of embodiments of the present application. DETAILED DESCRIPTION

[0037] It should be noted that the embodiments and features in the present disclosure can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0038] In order to make the person skilled in the art better understand the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in the embodiments of the present disclosure in combination with the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present disclosure.

[0039] It should be noted that the terms "first", "second" and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the terms thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] It should be noted that the terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should be understood that when the terms "comprise" and / or "include" are used in the specification, there is a feature, step, operation, device, component and / or combination thereof.

[0041] Figure 1 is the architecture schematic diagram of the reconfigurable processor chip according to the first aspect of the embodiments of the present application, referring to Figure 1 The reconfigurable processor chip includes a plurality of reconfigurable processing units based on distributed storage, and the components of the reconfigurable processing units are logically interconnected, wherein the components include:

[0042] A reconfigurable computing component is configured to perform data computation.

[0043] A data flow controller adopts a data flow driven mode, which controls the start and end of the computation and data transmission task according to the data flow information of the computation task and the message passing of the upstream and downstream reconfigurable processing units.

[0044] A distributed storage is configured to realize the data storage of the corresponding reconfigurable processing unit.

[0045] A programmable data routing unit is configured to realize the communication between the plurality of reconfigurable processing units, to control the direction of the data packet and realize flexible data packet transmission.

[0046] Optionally, the programmable data routing unit adopts a software programmable routing strategy and changes the routing direction and destination of the data packet in real time through software configuration.

[0047] Optionally, the reconfigurable processing unit exchanges data through the on-chip network, the inter-chip interface, and the network cable within the storage capacity range of the storage space.

[0048] Optionally, the reconfigurable processor chip further comprises: dividing the plurality of reconfigurable processing units into a plurality of computing areas according to algorithm mapping requirements, wherein

[0049] In the data-driven mode of the data flow controller, the communication connection relationship of the programmable data routing unit is changed in real time by changing the execution graph configuration in the reconfigurable processing unit, and the division of the computing area is changed according to the communication connection relationship.

[0050] Optionally, the plurality of computing areas perform pipelined computation or perform different computing tasks assigned.

[0051] In detail, the processor of the reconfigurable processor chip is composed of a plurality of reconfigurable processing units (RPEs). Unlike the traditional instruction flow driven computing unit, the RPE adopts a data flow driven mode, controls the start and end of the computing task according to the data flow information of the computing task and the message passing of the upstream and downstream RPEs, and belongs to a data flow driven processing unit. In addition, unlike the traditional GPU stream processor, the RPE internally adopts an independent storage space, which is not shared with other RPEs. The RPEs communicate through the autonomously controlled programmable data routing unit (DRU). The DRU is tightly coupled with the on-chip routing control module, controls the direction of the data packet on the on-chip interconnection through the DRU, and configures the interconnection in real time to realize the transmission of the data packet. The DRU adopts a software programmable routing strategy, can change the routing direction and destination of the data packet in real time through software configuration, and can modify the routing path through software configuration to bypass the damaged processing unit or chip when a damaged processing unit is encountered.

[0052] In addition, to support the needs of large-scale model expansion and parallel mode, the reconfigurable processor chip supports dividing the RPEs into a plurality of computing areas. The computing areas can perform pipelined computation, or support assigning different computing tasks between the computing areas. At the same time, under the data flow driven mode, the communication connection relationship of the data routing component is changed in real time by changing the execution graph configuration in the RPE, the division of the computing area is changed, and the parallel needs of different task segments are met.

[0053] For example, the reconfigurable processor chip can be used in the following fields: Figure 2As shown, the reconfigurable processor chip is divided into three computing areas, and three different computing tasks are executed asynchronously in different computing areas. In computing area 1, the RPEs communicate with each other through the DRU, and the arrows represent the communication relationship between the RPEs.

[0054] In addition, Figure 3 A schematic diagram of a reconfigurable processor cluster according to a second aspect of the embodiments of the present application is shown. Referring to Figure 3 As shown, the reconfigurable processor cluster includes a plurality of reconfigurable processor chips, wherein each reconfigurable processor chip is composed of a plurality of reconfigurable processing units based on distributed storage, and the components of each reconfigurable processing unit are logically interconnected, including:

[0055] A reconfigurable computing component for computing data;

[0056] A data flow controller using a data flow driven mode to control the start and end of computing and data transmission tasks according to the data flow information of the computing task and the message passing of the upstream and downstream RPEs;

[0057] A distributed storage for realizing the data storage of the corresponding reconfigurable processing unit;

[0058] A programmable data routing unit for realizing the communication between the plurality of reconfigurable processing units, for controlling the direction of data packets, and realizing flexible data packet transmission.

[0059] Optionally, the reconfigurable processor cluster further includes a routing control module for realizing the data communication between the plurality of reconfigurable processor chips, and

[0060] The reconfigurable processing units between the plurality of reconfigurable processor chips communicate data through the programmable data routing unit and the routing control module, and the programmable data routing unit and the routing control module on the reconfigurable processor chip are connected through the network on the reconfigurable processor chip, wherein

[0061] The routing control module is used for receiving or sending network data packets between the reconfigurable processor chips.

[0062] Optionally, the routing control module has bidirectional Ethernet data transceiving function to realize sending read request, write request, read response, and write response control information.

[0063] The routing control module has flow control mechanism and has sending buffer back pressure and receiving buffer back pressure functions to control the data transmission of the receiving end and the sending end.

[0064] Optionally, the reconfigurable processor cluster further includes dividing the plurality of reconfigurable processing units on the reconfigurable processor chip into a plurality of computing areas according to the algorithm mapping requirements, and

[0065] The reconfigurable processor cluster supports flexible division of a computing area and supports asynchronous parallel computing of the computing area.

[0066] Optionally, the reconfigurable processor cluster supports multiple computing modes of data parallelism, pipeline parallelism or model parallelism; and / or

[0067] Resources of the reconfigurable processor cluster are allocated to parallel computing of multiple tasks.

[0068] Specifically, referring to Figure 3 As shown in the figure, multiple reconfigurable processor chips can be expanded into a large-scale distributed computing chip cluster based on a distributed storage architecture, forming a large-scale parallel reconfigurable processing cluster.

[0069] The reconfigurable processor chips can communicate through an inter-chip routing control module (C2C CTRL), and can be interconnected through a physical interface and a network cable without conversion through a switch. The RPEs between the chips can communicate through the control of the DRU and the C2C CTRL.

[0070] The C2C CTRL can receive or send network data packets between chips, convert the data packets sent by the RPEs in the chips into network data packets, and perform chip-to-chip transmission through a network interface (such as a 100GE or 10GE optical fiber interface). Meanwhile, the C2C CTRL can also convert network data packets into a data packet format used by the RPEs on the chip and send the data packets to the RPE units on the chip. The module has the ability of bidirectional Ethernet data transmission and can send control information such as read requests, write requests, read responses and write responses. The module has a flow control mechanism and has functions of sending and receiving buffer back pressure to control the data transmission of the receiving end and the sending end. Meanwhile, the module supports a data packet retransmission mechanism to ensure the reliability of system transmission.

[0071] In a server cluster composed of traditional CPU or GPU processors, data transmission between processors first transmits data to external memory (such as HBM), and then data is copied multiple times in memory and transported by RDMA to the external memory in the destination server through network transmission. In a large-scale server scenario, network communication through a switch is usually required. The method proposed in the present application can complete the data transmission of the reconfigurable processor across chips or across networks through the C2C CTRL module. Within the RPE memory capacity range, the RPEs can directly transmit data through the on-chip network, inter-chip interface, and network cable without passing through external storage and network switches. This realizes large-scale and flexible expansion of multiple chips, while reducing the cost of cross-chip data communication. Another key feature is that the data packet routing direction and destination can be changed in real time through software configuration. When a damaged processing unit is encountered, the routing path can be modified through software configuration to bypass the damaged processing unit or chip.

[0072] At the same time, the computing cluster composed of multiple chips also supports flexible division of computing areas and supports asynchronous parallel computing of computing areas. Large-scale intelligent computing tasks can be flexibly mapped to the chip cluster, supporting multiple parallel computing modes such as data parallelism, pipeline parallelism, or model parallelism. Figure 3 As shown in FIG. 1, multiple reconfigurable processor chips form a large-scale parallel reconfigurable processing cluster. The entire computing task is flexibly mapped to the reconfigurable chip cluster, and the performance of the overall intelligent computing task can be optimized by adjusting the parallel mode or resource allocation. For example, Figure 3 In FIG. 2, the convolution layer 1 of the reconfigurable processor chip uses 4 RPEs for parallel computing, while the convolution layer 2 uses 8 RPEs for parallel computing. Meanwhile, the matrix multiplication and softmax also use 4 RPEs for parallel operation. At the same time, the computing area of the convolution layer 1 and the computing areas of the convolution layer 2, matrix multiplication, and softmax form a pipeline parallel relationship. This parallelizes the deep neural network model on the chip cluster and maximizes the utilization of chip processor resources to fully realize parallelism. When the RPEs in different chip computing areas communicate, data is transmitted through the DRU in the RPE. The DRU in the RPE on the communication route can have data forwarding function, and data across chips does not need to pass through switches and other devices for communication.

[0073] In addition, the computing resources of the cluster also support multiple tasks to be simultaneously expanded, and the resources of the cluster can be allocated to multiple tasks for parallel computing. Figure 3The simultaneous execution of recurrent neural network layers, convolution layers or matrix multiplication tasks, etc. is exemplified. In the reconfigurable distributed computing architecture, each computing area also adopts a full-asynchronous execution mode, without global synchronization control, and the RPEs in each computing area execute tasks under the driving of data flow according to their internal configuration information. Once the computing data arrives, the RPEs in the computing area can start to execute the corresponding computing tasks.

[0074] The allocation of computing resources by the chip takes into account the fault-tolerant mechanism for the chip and the processing units in the chip. When the chip or the processing unit has an accident or is damaged, if the RPEs in the computing area are damaged, the mapping of the computing area is modified by reallocating the tasks in the computing area, the mapping of the computing area is modified, and the tasks are redistributed on the normally working RPEs, and the data routing information and the data flow information of the RPEs are modified. As shown in the left figure, the original task allocation is shown, and the arrow is the routing path of the computing node. In the right figure, two RPEs in the computing area are damaged, and then the computing area is divided according to the number of available computing units, the computing task is changed, the configuration information of the task allocation and the data routing mode is changed, and the problems such as reconfiguration of software and hardware and influence on system work caused by damage of the chip node or the processing unit are avoided. Figure 4

[0075] Therefore, the chip-to-chip data transmission mechanism is optimized, the cost of cross-chip data transmission is reduced, and the optimization of the performance and cost of a large-scale chip cluster is very critical.

[0076] The data flow driven reconfigurable processor chip and the reconfigurable processor cluster provided by the application have the following technical advantages:

[0077] 1) The reconfigurable processing unit adopts a data flow driven computing mode, the start and end of the computing task are controlled according to the data flow information of the computing task and the message passing of the upstream and downstream RPEs, and asynchronous concurrent computing of each operation unit can be realized.

[0078] 2) The processor single chip and the chip cluster can support dynamic reconfiguration of the computing area according to the data flow characteristics of the task, support data parallel, pipeline parallel and other modes of the computing task, and flexibly expand the allocation of computing power. By optimizing the parallel computing mode, the utilization rate of computing power can be improved under the same computing power, and the distributed processing performance of the artificial intelligence algorithm is optimized.

[0079] ​3) Real-time reconfigurable distributed data exchange mode, no central data exchange node, to alleviate the data communication congestion and delay problem of large-scale parallel artificial intelligence algorithm. The reconfigurable processor processing unit adopts distributed storage unit, each processor unit has independent data routing module, and the processing units do not need to exchange data through shared storage unit. Avoid the storage wall problem caused by large-scale central data transmission, and the communication delay problem of large-scale centralized memory access.

[0080] 4) When a chip or internal processing unit is damaged, software configuration can be used to avoid damage. The reconfigurable processor processing unit adopts software programmable routing strategy, which can change the data packet routing direction and destination in real time through software configuration. When a damaged processing unit is encountered, the routing path can be modified through software configuration to bypass the damaged processing unit or chip.

[0081] 5) Flexible and scalable between reconfigurable chips, through the inter-chip routing module to complete the data transmission of reconfigurable processor chips across chips or across networks. RPEs can not pass through high-delay external storage, but directly exchange data through on-chip networks, inter-chip interfaces, and network cables, without the need for communication through switches, which can effectively reduce the cost of cross-chip data communication and alleviate the communication bottleneck problem of artificial intelligence tasks in multi-chip parallel.

[0082] Unless specifically stated otherwise, the relative arrangement of the components and steps illustrated in these embodiments and the numerical expressions and values are not limiting of the scope of the present disclosure. It should be understood that the dimensions of the various parts shown in the drawings are not necessarily to scale. Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the disclosure if appropriate. In all examples shown and discussed herein, any specific value should be interpreted as merely an example, and not as a limitation. Therefore, other examples of the exemplary embodiments can have different values. It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0083] For purposes of the description hereinafter, spatial or directional terms, such as, for example, "above", "below", "upper", "lower", "horizontal", "vertical", "top", "bottom", and the like, relative to the orientation of the device as shown in the drawings, are used. It is to be understood that the spatial and directional terms are used for purposes of the description and illustration and that the device can assume various orientations, except where the context of use dictates otherwise. For example, the device can be inverted, rotated 90 degrees or otherwise positioned, and the spatial and directional terms used herein are to be interpreted accordingly.

[0084] In the description of the present disclosure, it needs to be understood that the orientation words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal" and "top, bottom" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, only for the convenience of describing the present disclosure and simplifying the description, these orientation words do not indicate and imply that the device or element referred to must have a particular orientation or be constructed and operated in a particular orientation, therefore cannot be understood as a limitation on the protection scope of the present disclosure; the orientation words "inner, outer" refer to the inner and outer relative to the contour of each component itself.

[0085] The above description is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A reconfigurable processor chip, characterized by Comprise: A plurality of reconfigurable processing units based on distributed storage, the components of each of which are logically interconnected, wherein each component comprises: A reconfigurable computing component for computing data; A data flow controller using a data flow driven mode to control the start and end of computing and data transmission tasks according to data flow information of a computing task and message passing of upstream and downstream reconfigurable processing units; A distributed memory for realizing data storage corresponding to the reconfigurable processing units; A programmable data routing unit for realizing communication between a plurality of reconfigurable processing units, for controlling the direction of data packets, and realizing flexible data packet transmission; the programmable data routing unit uses a software programmable routing strategy and changes the routing direction and destination of data packets in real time through software configuration; The reconfigurable processor chip further comprises: dividing a plurality of reconfigurable processing units on the reconfigurable processor chip into a plurality of computing areas according to algorithm mapping requirements, wherein In the data flow driven mode of the data flow controller, the communication connection relationship of the programmable data routing unit is changed in real time by changing the execution graph configuration in the reconfigurable processing unit, and the division of the computing area is changed according to the communication connection relationship.

2. The reconfigurable processor chip of claim 1, wherein, The reconfigurable processing units exchange data within the storage capacity range of the corresponding storage space through an on-chip network, an inter-chip interface, and a network cable.

3. The reconfigurable processor chip of claim 1, wherein, A plurality of computing areas perform pipelined computing or perform different computing tasks assigned.

4. A reconfigurable processor cluster composed of the reconfigurable processor chip according to any one of claims 1 to 3, characterized by Comprise: A plurality of reconfigurable processor chips, wherein the reconfigurable processor chips are composed of a plurality of reconfigurable processing units based on distributed storage, the components of each of which are logically interconnected, comprising: A data flow controller using a data flow driven mode to control the start and end of computing and data transmission tasks according to data flow information of a computing task and message passing of upstream and downstream reconfigurable processing units.

5. The reconfigurable processor cluster of claim 4, wherein, Further comprising: A routing control module to realize data communication between a plurality of reconfigurable processor chips, and The reconfigurable processing units between the plurality of reconfigurable processor chips communicate data through the programmable data routing unit and the routing control module through a network, and the programmable data routing unit and the routing control module on the reconfigurable processor chip are connected through the network on the reconfigurable processor chip, wherein The routing control module is used to receive or send network data packets between the reconfigurable processor chips.

6. The reconfigurable processor cluster of claim 5, wherein, The routing control module has bidirectional Ethernet data transceiver function to realize sending read request, write request, read response, and write response control information; The routing control module has flow control mechanism and has sending buffer back pressure and receiving buffer back pressure functions to control data transmission of the receiving end and the sending end.

7. The reconfigurable processor cluster of claim 4, wherein, Further comprising: Dividing a plurality of reconfigurable processing units on the reconfigurable processor chip into a plurality of computing areas according to algorithm mapping requirements, and The reconfigurable processor cluster supports flexible division of computing areas and supports asynchronous parallel computing of the computing areas.

8. The reconfigurable processor cluster of claim 6, wherein: the reconfigurable processor cluster supports multiple computing modes of data parallel, pipelined parallel, or model parallel; and / or resources of the reconfigurable processor cluster are allocated to multiple task parallel computations.

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