Optimization method and system for fpga technology mapping

Abstract

The present application relates to the technical field of field programmable gate array circuits, and discloses a method and system for optimizing FPGA technology mapping. The method first divides the input register transfer level circuit into several sub-circuits, and then transmits the user-specified original circuit input and output timing constraints to the input and output ends of each sub-circuit according to the "basic logic gate delay model", and performs technology mapping on each sub-circuit under this constraint. Then, the mapped sub-circuit is recalculated and its timing constraints are updated according to the "lookup table delay model", and technology mapping is performed again after adjustment. The two steps of updating the sub-circuit timing constraints and re-technology mapping are repeated until the timing constraints on all sub-circuits converge numerically. The present application can obtain an FPGA circuit with more optimized timing performance.

Description

Technical Field

[0001] The present application relates to the technical field of field programmable gate array (FPGA), and in particular to an optimization technology for technology mapping. Background Art

[0002] For FPGA circuit design, technology mapping is a very important step. It aims to map the technology-independent logic diagram according to a given lookup table technology library into a lookup table-based circuit, which can be implemented by FPGA hardware.

[0003] However, the timing constraints of sub-circuits in the FPGA integrated circuit technology mapping in the prior art, that is, the accuracy of the settings of the input port arrival time constraints and the output port required time constraints, is not high enough, which affects the timing optimization effect of the technology mapping of the sub-circuit under this constraint and reduces the timing performance of the circuit. Summary of the Invention

[0004] The purpose of this application is to provide an optimization method and system for FPGA technology mapping, which can obtain FPGA circuits with more optimized timing performance.

[0005] This application discloses an optimization method for FPGA technology mapping, including:

[0006] Step A: Split the register transfer level original circuit input by the user into a plurality of gate-level sub-circuits composed of basic logic gates, wherein the timing constraints of the input and output ports of the original circuit are set to user-specified values ​​and remain unchanged during the update process;

[0007] Step B: setting current timing constraints for each sub-circuit according to the timing constraints of the input and output ports of the original circuit, performing technology mapping on each sub-circuit based on a lookup table delay model using the current timing constraints to obtain a sub-circuit based on the lookup table; and on this basis, recalculating and updating the timing constraints of each sub-circuit based on the lookup table delay model according to the timing constraints of the original circuit;

[0008] Step C: Repeat step B until the timing constraints of the various sub-circuits based on the lookup table converge, thereby obtaining the final sub-circuits based on the lookup table.

[0009] In a preferred embodiment, the step of performing technology mapping on each sub-circuit comprises performing look-up table based technology mapping on each sub-circuit, wherein each sub-circuit composed of a logic gate or a look-up table is first converted into a corresponding logic sub-graph, and then the logic sub-graph is converted into a look-up table based sub-circuit using the current timing constraints of the sub-circuit.

[0010] In a preferred embodiment, the step of recalculating and updating the timing constraints of each look-up table based sub-circuit according to the timing constraints of the input and output ports of the original circuit comprises updating the timing constraints of each sub-circuit by using a delay model of the look-up table to propagate the timing constraints of the original circuit in each sub-circuit according to the connection relationship of the sub-circuit in the original circuit.

[0011] In a preferred embodiment, the timing constraints of each look-up table based sub-circuit are determined to be converged by comparing the timing constraints of each sub-circuit with the previous timing constraints of the sub-circuit and determining whether the timing constraints of each sub-circuit are all converged according to a pre-set convergence threshold.

[0012] In a preferred embodiment, the step of setting the current timing constraints of each sub-circuit comprises setting the timing constraints of the original circuit as the initial timing constraints of each sub-circuit, and then setting the initial timing constraints of each sub-circuit as the current timing constraints of the sub-circuit.

[0013] In a preferred embodiment, the method further comprises:

[0014] Step D: obtaining a look-up table based complete circuit from the final look-up table based sub-circuits and outputting.

[0015] In a preferred embodiment, before the step A, the method further comprises:

[0016] a user inputs a register transfer level original circuit, timing constraints of each input and output port of the original circuit, and a basic logic gate delay model and a look-up table delay model.

[0017] The application also discloses an optimization system for FPGA technology mapping, comprising:

[0018] a sub-circuit partition unit configured to partition a register transfer level original circuit input by a user into a plurality of gate level sub-circuits composed of basic logic gates, wherein the timing constraints of the input and output ports of the original circuit are set as values specified by the user and remain unchanged during the updating process;

[0019] a technology mapping and timing constraint updating unit configured to set current timing constraints of the sub-circuits according to timing constraints of the original circuit input and output ports, perform technology mapping on the sub-circuits based on a lookup table delay model using the current timing constraints, and recompute and update timing constraints of the sub-circuits based on the lookup table delay model according to the timing constraints of the original circuit input and output ports;

[0020] a convergence unit configured to repeatedly perform the technology mapping and timing constraint updating unit until the timing constraints of the sub-circuits reach convergence, thereby obtaining final sub-circuits based on a lookup table.

[0021] The application also discloses an FPGA technology mapping optimization system, which comprises:

[0022] a memory configured to store computer executable instructions; and

[0023] a processor configured to implement steps in the method as described above when executing the computer executable instructions.

[0024] The application also discloses a computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and the computer executable instructions are executed by a processor to implement steps in the method as described above.

[0025] In the embodiment, the input register transfer level circuit is first divided into sub-circuits. Then, user-specified original circuit input and output port timing constraints are conducted to input and output ports of the sub-circuits according to a basic logic gate delay model, and technology mapping is performed on the sub-circuits under the constraints. Next, input and output port arrival and required time constraints of the mapped sub-circuits are recomputed and updated according to a lookup table delay model, and technology mapping is performed again after adjustment. The two steps of sub-circuit timing constraint updating and technology mapping are repeated, and after multiple iterations, the timing constraints on all sub-circuits converge in value.

[0026] The application has the following technical effects: by using a lookup table delay model that is more matched with a lookup table-based circuit, and using the current obtained lookup table-based sub-circuit to conduct the timing constraint of the input and output ports of the original circuit, the timing constraint of each sub-circuit can be more accurately updated, thereby effectively solving the problem of inaccurate setting of the timing constraint on the sub-circuit in the technology mapping stage, further, using more accurate arrival and required time constraints to re-perform technology mapping on each sub-circuit, and finally obtaining an FPGA circuit with more optimized timing performance. It is worth mentioning that this method can be compatible with the existing technology for adjusting the lookup table delay model, that is, a plurality of different lookup table delay models can be used for the above-mentioned technology mapping, and the optimal result is selected from them.

[0027] A large number of technical features are described in the specification of the application, distributed in various technical solutions. If all possible combinations of technical features (i.e. technical solutions) of the application are listed, the specification will be too long. In order to avoid this problem, each technical feature disclosed in the above invention content of the application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined to form various new technical solutions (these technical solutions are considered to have been described in the specification), unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means that play the same role, and only one can be used in technology, and feature E can be combined with feature C in technology. Therefore, the scheme of A+B+C+D should not be considered to have been described because it is technically infeasible, and the scheme of A+B+C+E should be considered to have been described. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a flowchart of an optimization method of FPGA technology mapping according to the first embodiment of the application;

[0029] Figures 2-8 is a schematic diagram in the timing constraint iteration update process in the optimization method of FPGA technology mapping according to the first embodiment of the application.

[0030] Figure 9 is a structural schematic diagram of an optimization system of FPGA technology mapping according to the second embodiment of the application. DETAILED DESCRIPTION

[0031] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one ordinarily skilled in the art that the application can be practiced without the specific details and that numerous implementation variations and modifications from these implementations can be possible.

[0032] Explanation of partial concepts:

[0033] FPGA (field programmable gate array): field programmable logic gate array circuit

[0034] Arrival time: the time at which a signal arrives at a certain point in a circuit

[0035] Required time: the time at which a signal needs to arrive at a certain point in a circuit before it

[0036] LUT (look-up table): one of the basic logic device units in an FPGA, a look-up table is a programmable logic element whose function is to look up the input value to determine the output value. The implementation of a look-up table is to store a set of predetermined mapping relationships between input values and output values in the internal storage, and to determine the output by reading the set of mapping relationships.

[0037] Logic subgraph: a local circuit separated from the entire circuit, represented by a graph composed of nodes and edges. Usually represented by an AIG (and-inverter graph).

[0038] DFF (D-flip flop): a circuit element used to control the transmission of a data signal by a clock signal.

[0039] Timing constraint: the timing requirement that needs to be met at an input and output port of a circuit. Usually the arrival time constraint needs to be met at the input port, and the required time constraint needs to be met at the output port, i.e. the arrival time of the signal at the output port should not be greater than the required time, otherwise it violates the timing constraint at this point. In this specification, the timing constraint is the arrival time constraint at the input port and the required time constraint at the output port.

[0040] Timing propagation: refers to the transmission of arrival time or required time at a port in a circuit between logic gates or nodes.

[0041] Delay model: A model of the delay of a logic gate, a lookup table, or a connection line used to calculate the delay of a circuit.

[0042] Technology mapping: The process of mapping a logic graph to a circuit composed of devices from a given technology library. For FPGAs, technology mapping is the process of mapping a logic graph to a corresponding lookup table-based circuit using a given library of lookup tables.

[0043] Cut: In technology mapping, a cut is used to cover all nodes in a logic graph, and each cut can be implemented by a corresponding lookup table, thus obtaining a lookup table-based circuit.

[0044] Topological order: In a directed acyclic graph or its corresponding circuit network, the order in which each node, electronic device, or logic block is arranged according to the following requirements: Before any node appears in this sequence, all its input nodes have already appeared in this sequence. In a topological order, if node A is arranged before node B, then A is the predecessor of B, and B is the successor of A.

[0045] Register-transfer level (RTL): The level of a circuit composed of registers and basic logic gates

[0046] The following outlines some of the innovations of the present application:

[0047] The inventors of the present application have found that the prior art first divides the FPGA integrated circuit before performing technology mapping, and sets the arrival and required arrival time constraints of the input and output terminals of the obtained sub-circuits, in the following specific method: first, set the arrival and required arrival time constraints specified by the user for the input and output terminals of the input circuit. Then, disconnect the input circuit at each D flip-flop, and divide it into several sub-circuits. These sub-circuits are now gate-level circuits, i.e. circuits composed of basic logic gates (such as AND gates, OR gates, NOT gates, multiplexers, etc.). Next, through the delay model of the basic logic gates, the constraints are time-conducted and transmitted to the input and output terminals of each sub-circuit as the arrival and required arrival time constraints of the input and output terminals. For each sub-circuit, the arrival and required arrival time constraints of the input and output terminals will be used to guide the selection of the internal minimum cut in the technology mapping stage, thereby affecting the timing quality of the lookup table-based circuit obtained after technology mapping of the sub-circuit. However, this prior art only conducts the internal timing of the circuit once for the timing constraints specified by the user for the input and output terminals of the original circuit, to set the timing constraints of the input and output terminals of each sub-circuit, and does not update the timing constraints of each sub-circuit again.

[0048] Meanwhile, the present inventors find that the prior art focuses on adjusting the delay values in the lookup table delay model, so as to obtain more optimized results through technology mapping. However, the optimization effect on the mapping results is limited by merely modifying the delay values in the lookup table delay model. The reason is that a circuit requiring technology mapping is often a multi-stage circuit containing D flip-flops, and the D flip-flops need to be disconnected first during technology mapping, so as to obtain a plurality of sub-circuits for technology mapping. However, how to accurately transfer the timing constraints specified by the user at the input and output ends of the circuit to each sub-circuit is still a problem to be solved. The prior art transfers the timing constraints at the input and output ends of the circuit to the ports of each sub-circuit at one time through the "basic logic gate delay model" before technology mapping of the sub-circuit, and then performs technology mapping of each sub-circuit according to the timing constraints, i.e. converts it into a lookup table-based circuit based on the "lookup table delay model". However, the two delay models of "basic logic gate delay model" and "lookup table delay model" cannot be completely matched, so that it is unreasonable and inaccurate to guide the technology mapping of the sub-circuit based on the "lookup table delay model" using the timing constraints obtained by conducting the "basic logic gate delay model". Secondly, when a sub-circuit is mapped into a lookup table-based circuit, its circuit structure changes, so that the timing conduction calculation process is different from that of the previous basic logic gate-based circuit. If the sub-circuit has a preposed or postposed sub-circuit in topological order, it will also cause the arrival time constraints of the output port of the preposed sub-circuit and the arrival time constraints of the input port of the postposed sub-circuit to be different from those before technology mapping. Therefore, the prior art still cannot accurately set and update the timing constraints of the sub-circuit port by merely adjusting the "lookup table delay model", so as to cause the timing optimization effect of the technology mapping of the sub-circuit under this constraint to decrease, thereby reducing the timing performance of the obtained lookup table-based circuit.

[0049] To this end, the inventors of the present application have creatively proposed an FPGA technology mapping optimization method and system. In view of the inaccurate setting of arrival and required time constraints of input and output terminals of sub-circuits in the FPGA integrated circuit technology mapping stage, the method proposes a method of improving the accuracy of arrival and required time constraints of sub-circuits by multiple iterations to optimize the circuit timing performance in the technology mapping stage. The method first divides the input register transfer level circuit into several gate-level sub-circuits composed of basic logic gates. Then, the user-specified original circuit input and output terminal timing constraints are conducted to the input and output terminals of each sub-circuit according to the "basic logic gate delay model", and the technology mapping is performed on each sub-circuit under the constraints. Next, according to the "lookup table delay model", the arrival and required time constraints of the input and output terminals of the already mapped sub-circuit are recalculated and updated, and the technology mapping is performed again after adjustment. The two steps of updating the timing constraints of the sub-circuit and re-mapping the technology are repeated, and after multiple iterations, the timing constraints on all sub-circuits converge in value.

[0050] Since the lookup table delay model more matched with the lookup table-based circuit is used in the above scheme, and the timing constraints are conducted using the currently obtained lookup table-based sub-circuit, the method can more accurately update the timing constraints of each sub-circuit, thereby effectively solving the problem of inaccurate setting of timing constraints on sub-circuits in the technology mapping stage. On this basis, the more accurate arrival and required time constraints are used to re-map the technology of each sub-circuit, and finally the FPGA circuit with more optimized timing performance is obtained. It is worth mentioning that this method can be compatible with the adjustment of the lookup table delay model in the prior art, i.e. multiple different lookup table delay models can be used for the above technology mapping, and the optimal result can be selected from them.

[0051] To make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0052] First embodiment

[0053] Figure 1 An FPGA technology mapping optimization method related to the first embodiment of the present application is shown, which includes the following main steps:

[0054] Step A: The user input register transfer level original circuit is divided into several gate-level sub-circuits composed of basic logic gates, wherein the timing constraints of the original circuit input and output ports are set to the values specified by the user and remain unchanged during the updating process;

[0055] Step B: setting current timing constraints of each sub-circuit according to timing constraints of input and output ports of the original circuit, using the current timing constraints, performing technology mapping of each sub-circuit based on a lookup table delay model to obtain a lookup table-based sub-circuit; and on this basis, recalculating and updating timing constraints of each lookup table-based sub-circuit according to timing constraints of input and output ports of the original circuit based on the lookup table delay model;

[0056] Step C: repeating Step B until timing constraints of each lookup table-based sub-circuit reach convergence, thereby obtaining final each lookup table-based sub-circuit.

[0057] Specifically, in the above method, as shown in Figure 2 , the step of dividing the original circuit into N sub-circuits can include:

[0058] First, a register transfer level input circuit (original circuit) composed of basic logic gates, in which a solid square represents a D flip-flop. Mark the user-specified timing constraints on its input and output ports. ATC i (1≤i≤m) and RTC j (1≤j≤n) are user-specified arrival time constraints of m input ports and required time constraints of n output ports of the original circuit, respectively, as shown in Figure 2 (1);

[0059] Then, divide the original circuit into N sub-circuits at the D flip-flops in the original circuit, as shown in Figure 2 (2);

[0060] Then, according to the connection relationship of each sub-circuit in the original circuit, use the basic logic gate delay model to pass the timing constraints of the original circuit to the input and output ports of each sub-circuit. The timing constraints of the kth sub-circuit are marked in the figure: m k input port arrival time constraints ATC k,i (1≤i≤m k ) and n k output port required time constraints RTC k,j (1≤j≤n k ), as shown in Figure 2 (3).

[0061] Further, in the above method, as shown in Figure 3 , the step of performing technology mapping for each sub-circuit can include:

[0062] First, a sub-circuit composed of basic logic gates obtained by dividing the original circuit, as shown in Figure 3 (1);

[0063] Then, this subcircuit is converted into a logic subgraph, such as Figure 3 (2) shown;

[0064] Then, using the timing constraints of its input and output terminals, the technology mapping is performed on this subcircuit according to the lookup table delay model to obtain the subcircuit based on the lookup table, such as Figure 3 (3) shown.

[0065] In the above method, if Figure 4 As shown, in the step of transferring the timing constraints and updating the timing constraints of the input and output ports of each sub-circuit according to the delay model of the lookup table, according to the connection relationship of each sub-circuit in the original circuit and according to the delay model of the lookup table, the timing constraint values ​​set for the input and output ports of the original circuit are transferred to the input and output ports of each sub-circuit, as shown in FIG. Figure 4 (1) The updated timing constraint of the kth subcircuit is: k Input port arrival time constraint ATC′ k,i (1≤i≤m k ) and n k Output ports need to be time-constrained RTC′ k,j (1≤j≤n k ),like Figure 4 (2) shown.

[0066] The following combination Figure 1 Before the steps start, the user first inputs the original circuit of the register transfer level (the number of input and output ports is m, n respectively), and the timing constraints of each input and output port of the original circuit ATC i (1≤i≤m) and RTC j (1≤j≤n), as well as basic logic gate delay model and lookup table delay model.

[0067] Steps 110-130: Split the original register transfer level circuit input by the user into several gate-level sub-circuits composed of basic logic gates, wherein the timing constraints of the input and output ports of the original circuit are set to the values ​​specified by the user and remain unchanged during the update process. The details are as follows:

[0068] Step 110: Figure 2 As shown in (1), the input port arrival time constraint and output port required arrival time constraint of the original circuit are set to the user-specified values. During the following sub-circuit timing constraint update process, the timing constraints of the original circuit input and output ports remain unchanged.

[0069] Step 120: Figure 2(2) as shown, the original circuit is divided at each D flip-flop, and N sub-circuits are obtained which need to be technology mapped. At this time, these sub-circuits are gate-level circuits composed of basic logic gates.

[0070] Step 130: as shown in Figure 2 (3) as shown, using the input port arrival time constraint and the output port required arrival time constraint of the original circuit, the timing constraints are transmitted to the input and output ports of each of the sub-circuits as the initial input port arrival time constraint and the initial output port required arrival time constraint of each of the sub-circuits by using the "basic logic gate delay model". At this time, the input port arrival time constraint and the output port required arrival time constraint of the N groups of sub-circuits are obtained.

[0071] Steps 140-160: setting the current timing constraints of each of the sub-circuits, using the current timing constraints, technology mapping is performed on each of the sub-circuits according to the lookup table delay model to obtain a lookup table-based sub-circuit; and according to the lookup table delay model, the values of the timing constraints of the input and output ports of the original circuit are transmitted to the input and output ports of each of the lookup table-based sub-circuits, and the timing constraints of each of the lookup table-based sub-circuits are recalculated and updated. Specifically as follows:

[0072] Step 140: setting of the current timing constraints of the sub-circuit:

[0073] The initial input port arrival time constraint and the output port required arrival time constraint of each of the sub-circuits are set as the current input port arrival time constraint and the output port required arrival time constraint of the sub-circuit.

[0074] Step 150: technology mapping of the sub-circuit:

[0075] As shown in Figure 3 , using the current timing constraints, technology mapping based on the lookup table is performed on each of the sub-circuits. Specifically, each sub-circuit composed of logic gates (or lookup tables) is first converted into a corresponding logic subgraph Figure 3 (1)), and then using the current timing constraints, technology mapping based on the lookup table is performed to convert the logic subgraph into a lookup table-based sub-circuit Figure 3 (2)), and then using the current timing constraints, technology mapping based on the lookup table is performed to convert the logic subgraph into a lookup table-based sub-circuit Figure 3 (3)).

[0076] Step 160: updating of the timing constraints of the lookup table-based sub-circuit:

[0077] As shown in Figure 4 , when all the sub-circuits complete a round of technology mapping, the timing constraints set at the input and output ports of the original circuit are transmitted in each of the sub-circuits according to the connection relationship thereof in the original circuit by using the delay model of the lookup table Figure 4(1)). In this way, the original circuit timing constraints are transmitted to the input and output terminals of each sub-circuit, and the input and output terminal timing constraints of each sub-circuit are updated Figure 4 (2)). At this time, the input port arrival time constraints and the output port required arrival time constraints of the N groups of sub-circuits are obtained.

[0078] Steps 170-180: The "setting the current timing constraints, the technology mapping of the sub-circuit, and the updating of the timing constraints of the sub-circuit based on the lookup table" steps are repeatedly executed until the timing constraints of all the sub-circuits based on the lookup table converge after multiple iterations, so as to obtain the final each sub-circuit based on the lookup table. Specifically as follows:

[0079] Step 170: Compare the N groups of timing constraints with the previous N groups of timing constraints, and determine whether the timing constraints converge according to the pre-set convergence threshold e TC Determine whether the timing constraints of the sub-circuit converge, if yes, execute step 180, that is, output the current each sub-circuit as the technology mapping result; otherwise, return to step 140, set the new N groups of sub-circuit timing constraints as the current timing constraints of the sub-circuit, and then execute step 150 and step 160 to re-perform the technology mapping of each sub-circuit. Repeat steps 140-160 until the timing constraints converge, then execute step 180, that is, output the current each sub-circuit as the technology mapping result.

[0080] Step 180: When the timing constraints converge, the final technology mapping result is obtained, that is, N sub-circuits based on the lookup table.

[0081] Step 190: Obtain and output the complete circuit based on the lookup table according to the final each sub-circuit based on the lookup table. Specifically as follows:

[0082] Connect the N sub-circuits through D flip-flops according to the connection relationship in the original circuit to obtain the complete circuit based on the lookup table. Output the complete circuit based on the lookup table as the result. The circuit can be implemented by FPGA hardware circuit.

[0083] The implementation of the convergence step of step 170 is further described below by way of non-limiting examples:

[0084] Figure 5 The timing constraints of the input and output ports of the sub-circuit k before and after updating are shown. Wherein, Figure 5 (1) is the timing constraint value of each sub-circuit port after the qth iteration; Figure 5 (2) is the timing constraint value of each sub-circuit port after the (q+1)th iteration.

[0085] In the above step 170, the specific description of the condition for determining whether the timing constraints converge is as follows:

[0086] Assume that the entire circuit is divided into N subcircuits, where the kth subcircuit has m k input ports and n k output ports. In the process of iteratively updating the timing constraints of all sub-circuit input and output ports, such as Figure 5 As shown, assuming that the input and output port timing constraints obtained in the qth iteration are ATC k,i (1≤i≤m k ) and RTC k,j (1≤j≤n k ), and the input and output port timing constraints obtained in the q+1th iteration are ATC′ k,i (1≤i≤m k ) and RTC′ k,j (1≤j≤n k ). At the beginning of the program, the user enters the timing constraints of the circuit at both ends ATC i (1≤i≤m) and RTC j (1≤j≤n) Calculate the subcircuit timing closure threshold e TC , whose formula is

[0087]

[0088] Where p is an internal parameter, and the recommended range is 0.01≤p≤0.05. Generally speaking, a larger p value results in faster convergence, but the resulting timing quality degrades. A smaller p value results in slower convergence, but better timing quality.

[0089] For the kth subcircuit, define the maximum absolute error (MAE) of the input arrival time constraint in two consecutive iterations. ATC,k And the maximum absolute error MAE required for the output to reach the time constraint RTC,k as follows:

[0090]

[0091] If and only if MAE ATC，k and MAE RTC，k When the following conditions are met at the same time

[0092]

[0093] The timing constraints of the input and output ports of this subcircuit converge. Similarly, if and only if all N subcircuits simultaneously meet the conditions in the above formula (3), that is, simultaneously meet

[0094]

[0095] Only when the timing constraints are met in step 170 is it said that the timing constraints are converged.

[0096] Figure 6 The original circuit is shown being split into 3 sub-circuits by disconnecting at all D-flip-flops. Figure 7 The original circuit's input and output port timing constraints are shown. Figure 8 The sub-circuit input and output port timing constraints before and after update are shown. Figure 8 (1) is the sub-circuit port timing constraint values after the 4th iteration; Figure 8 (2) is the sub-circuit port timing constraint values after the 5th iteration.

[0097] For example, as shown in Figure 6 , assume the original circuit is split into 3 sub-circuits C1, C2, and C3. The original circuit's input and output port timing constraints are shown in Figure 7 . Assume ATC1=200ps, ATC2=180ps, RTC1=1000ps, RTC2=1100ps. The internal parameter p is set to 0.02. The sub-circuit timing convergence threshold e TC =16ps can be obtained from equation (1).

[0098] According to the flowchart in Figure 1 , the 3 sub-circuits are technology mapped while their input and output port timing constraints are iteratively updated. As shown in Figure 8 (1), assume in the 4th iteration, the input and output port timing constraints on sub-circuit C1 are ATC 1，1 =200ps, ATC 1，2 =180ps, and RTC 1，1 =500ps, RTC 1，2 =400ps, RTC 1，3 =700ps, respectively.

[0099] The input and output port timing constraints on sub-circuit C2 are ATC 2，1 =400ps, ATC 2，2 =300ps, ATC 2，3 =600ps, and RTC 2，1 =800ps, RTC 2，2 =900ps, respectively.

[0100] The input and output port timing constraints on sub-circuit C3 are ATC 3，1 =700ps, ATC 3，2 =800ps, and

[0101] RTC 3，1 =1000ps, RTC 3，2 =1100ps, respectively.

[0102] As Figure 8 (2) shows, assume that in the 5th round of iteration, the timing constraints of the input and output terminals of the three sub-circuits are updated as follows:

[0103] The input and output port timing constraints on sub-circuit C1 are ATC' 1，1 = 200 ps, ATC' 1，2 = 180 ps, RTC' 1，1 = 485 ps, RTC' 1，2 = 405 ps, RTC' 1， 3 = 710 ps;

[0104] The input and output port timing constraints on sub-circuit C2 are ATC' 2，1 = 412 ps, ATC' 2，2 = 290 ps, ATC' 2，3 = 605 ps, and RTC' 2，1 = 814 ps, RTC' 2，2 = 895 ps;

[0105] The input and output port timing constraints on sub-circuit C3 are ATC' 3，1 = 710 ps, ATC' 3，2 = 790 ps, and RTC' 3，1 = 1000 ps, RTC' 3，2 = 1100 ps.

[0106] For the three sub-circuits, the maximum absolute difference values of the 4th round and the 5th round of timing constraints are as follows:

[0107] For sub-circuit C1, MAE ATC，1 = 0, MAE RTC，1 = 15 ps;

[0108] For sub-circuit C2, MAE ATC，2 = 12 ps, MAE RTC，2 = 14 ps;

[0109] For sub-circuit C3, MAE ATC，3 = 10 ps, MAE RTC，3 = 0.

[0110] Since the sub-circuit timing convergence threshold e TC = 16 ps at this time, the three sub-circuits at this time all satisfy the port timing constraint convergence condition in formula (4), that is, the "timing constraint convergence" in step 7.

[0111] It should be noted that in the proposed method, the updating of the input and output timing constraints of each sub-circuit and the adjustment of the technology mapping of each sub-circuit are performed alternately. When the timing constraints of the sub-circuit meet the convergence condition, each sub-circuit also converges to a lookup table-based circuit that meets the timing constraints. In addition, those skilled in the art can understand that the concept of "timing constraint convergence" proposed in the optimization method of FPGA technology mapping of the embodiments of the present application and the "timing convergence" frequently mentioned in circuit design are not directly related.

[0112] The above embodiments have the following technical effects:

[0113] 1. The "lookup table delay model" is used, and the input and output timing constraints of the sub-circuit are updated multiple times to guide the re-mapping of each sub-circuit. Compared with obtaining the timing constraints of the sub-circuit only once using the "basic logic gate delay model", the timing constraints of the sub-circuit are updated multiple times using the "lookup table delay model", which can adjust the constraints more reasonably and accurately, thereby improving the timing quality of the lookup table-based circuit obtained after technology mapping.

[0114] 2. For the iterative updating of the timing constraints of the sub-circuit, if the timing constraints of the sub-circuit are updated in each iteration, the technology mapping of the sub-circuit based on the lookup table is performed again to obtain a new lookup table-based sub-circuit. Thus, the more accurate timing constraints of the sub-circuit can be effectively used to optimize the technology mapping of the sub-circuit.

[0115] 3. A method for judging "timing constraint convergence" is proposed to effectively determine whether the input and output timing constraints of each sub-circuit converge, thereby determining whether the program is terminated and whether the circuit optimized by technology mapping is output as the result.

[0116] The second embodiment of the present application relates to an optimization system for FPGA technology mapping, which has the structure as shown in Figure 9 The optimization system for FPGA technology mapping comprises:

[0117] An input unit for a user to input a register transfer level original circuit, timing constraints of each input and output port of the original circuit, and a basic logic gate delay model and a lookup table delay model;

[0118] A sub-circuit partitioning unit for partitioning the register transfer level original circuit input by the user into a plurality of gate level sub-circuits composed of basic logic gates, wherein the timing constraints of the input and output ports of the original circuit are set to the values specified by the user and remain unchanged during the updating process;

[0119] a technology mapping and timing constraint updating unit configured to set current timing constraints of the sub-circuits according to timing constraints of the input and output ports of the original circuit, perform technology mapping on the sub-circuits based on a lookup table delay model using the current timing constraints, and obtain lookup table based sub-circuits, and based on the lookup table delay model, recompute and update the timing constraints of the lookup table based sub-circuits according to the timing constraints of the input and output ports of the original circuit;

[0120] a convergence unit configured to repeatedly execute the technology mapping and timing constraint updating unit until the timing constraints of the lookup table based sub-circuits reach convergence, thereby obtaining final lookup table based sub-circuits; and

[0121] an output unit configured to obtain a complete lookup table based circuit according to the final lookup table based sub-circuits and output the complete lookup table based circuit.

[0122] The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.

[0123] It should be noted that the implementation functions of the modules shown in the embodiments of the FPGA technology mapping optimization system described above can be understood with reference to the related descriptions of the FPGA technology mapping optimization method described above. The functions of the modules shown in the embodiments of the FPGA technology mapping optimization system described above can be implemented by programs (executable instructions) running on a processor, or by specific logic circuits. The FPGA technology mapping optimization system described above in the embodiments of the present application, if implemented in the form of software function modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. The storage medium mentioned above includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various storage media that can store program codes. Thus, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0124] Correspondingly, the embodiments of the present application also provide a computer storage medium, which stores computer executable instructions. When the computer executable instructions are executed by a processor, the methods of the embodiments of the present application are implemented.

[0125] Furthermore, the embodiments of the present application also provide an optimization system for FPGA technology mapping, comprising a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above-mentioned method embodiments when executing the computer executable instructions in the memory. The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The memory can be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk or a solid state disk, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as hardware processor execution, or be executed by a combination of hardware and software modules in the processor.

[0126] It should be noted that in the application file of the present patent, "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "comprises one" does not exclude the presence of another identical element in the process, method, article or equipment including the element. In the application file of the present patent, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, which includes two cases: the action is performed only according to the element, and the action is performed according to the element and other elements. The expressions of multiple, multiple times, multiple varieties, etc. include 2, 2 times, 2 varieties and more than 2, more than 2 times, more than 2 varieties.

[0127] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other examples. Similarly, the term "example" does not require that all examples include the feature, advantage, or mode of operation discussed. The use of the terms "in one example," "an example," "in a feature," and / or "a feature" in this specification does not necessarily refer to the same features and / or examples. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. In addition, at least a portion of the apparatus described herein may be configured to perform at least a portion of the method described herein.

[0128] The terms used herein are for the purpose of describing particular examples only and are not intended to be limiting of the examples of the present disclosure.As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0129] It should be noted that the terms "connect," "couple," or any variant thereof, mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of an intermediate element between two elements that are "connected" or "coupled" together via the intermediate element. The coupling and / or connection between elements may be physical, logical, or a combination thereof. As used herein, elements may be "connected" or "coupled" together using one or more wires, cables, and / or printed electrical connections, as well as by using electromagnetic energy. Electromagnetic energy may have a wavelength in the radio frequency region, microwave region, and / or light (both visible and invisible) region. These are several non-limiting and non-exhaustive examples.

[0130] Any reference to the elements of the names of the present invention such as "first", "second" etc. does not limit the quantity and / or order of these elements. More precisely, these names are used as a convenient method to distinguish two or more elements and / or element instances. Therefore, reference to the first and second elements does not mean that only two elements can be adopted, or that the first element must necessarily be before the second element. In addition, unless otherwise stated, the element set may include one or more elements. In addition, the term "at least one of A, B or C" used in this description or claims can be interpreted as "A or B or C or any combination of these elements."

[0131] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A method for optimizing FPGA technology mapping, characterized in that: include: Step A: Split the register transfer level original circuit input by the user into a plurality of gate-level sub-circuits composed of basic logic gates, wherein the timing constraints of the input and output ports of the original circuit are set to user-specified values ​​and remain unchanged during the update process; Step B: setting current timing constraints for each sub-circuit according to the timing constraints of the input and output ports of the original circuit, performing technology mapping on each sub-circuit based on a lookup table delay model using the current timing constraints to obtain a sub-circuit based on the lookup table; and on this basis, recalculating and updating the timing constraints of each sub-circuit based on the lookup table delay model according to the timing constraints of the original circuit; Step C: Repeat step B, compare the timing constraints of each sub-circuit with the previous timing constraints of the sub-circuit, and It is determined whether all the timing constraints of the sub-circuits are converged, until the timing constraints of the sub-circuits based on the lookup tables are converged, thereby obtaining the final sub-circuits based on the lookup tables.

2. The method according to claim 1, wherein In the step of performing technology mapping on each sub-circuit, technology mapping based on a lookup table is performed on each sub-circuit, wherein each sub-circuit composed of logic gates or lookup tables is first converted into a corresponding logic sub-graph, and then technology mapping based on a lookup table is performed using the current timing constraints of the sub-circuit to convert the logic sub-graph into a sub-circuit based on a lookup table.

3. The method according to claim 2, wherein In the step of recalculating and updating the timing constraints of each sub-circuit based on the lookup table according to the timing constraints of the input and output ports of the original circuit, the timing constraints of the original circuit are transferred to each sub-circuit according to the connection relationship of the sub-circuit in the original circuit by using the delay model of the lookup table, so as to update the timing constraints of the sub-circuit.

4. The method according to claim 1, wherein In the step of setting the current timing constraints of each sub-circuit, the timing constraints of the input and output ports of the original circuit are used as the initial timing constraints of each sub-circuit, and then the initial timing constraints of each sub-circuit are set as the current timing constraints of the sub-circuit.

5. The method of claim 1, wherein: Also includes: Step D: Obtain a complete circuit based on the lookup table according to the final sub-circuits based on the lookup table and output it.

6. The method of claim 1, wherein: Before step A, the method further includes: The user inputs the register transfer level original circuit, the timing constraints of each input and output port of the original circuit, and the basic logic gate delay model and the lookup table delay model.

7. An optimization system for FPGA technology mapping, characterized in that: include: An input unit, used for the user to input the register transfer level original circuit, the timing constraints of each input and output port of the original circuit, and the basic logic gate delay model and the lookup table delay model; a subcircuit segmentation unit, configured to segment a register transfer-level original circuit input by a user into a plurality of gate-level subcircuits composed of basic logic gates, wherein the timing constraints of the input and output ports of the original circuit are set to user-specified values ​​and remain unchanged during the update process; a technology mapping and timing constraint updating unit, configured to set current timing constraints for each of the sub-circuits based on the timing constraints of the input and output ports of the original circuit, perform technology mapping on each of the sub-circuits based on a lookup table delay model using the current timing constraints to obtain a sub-circuit based on the lookup table; and on this basis, recalculate and update the timing constraints of each sub-circuit based on the lookup table delay model according to the timing constraints of the input and output ports of the original circuit; The convergence unit is used to repeatedly execute the technology mapping and timing constraint update unit, compare the timing constraints of each sub-circuit with the previous timing constraints of the sub-circuit, and update the timing constraints according to the preset convergence threshold. Determining whether all timing constraints of the sub-circuits are converged, until the timing constraints of the sub-circuits based on the lookup tables are converged, thereby obtaining the final sub-circuits based on the lookup tables; and An output unit is configured to obtain and output a complete circuit based on the lookup table according to the final sub-circuits based on the lookup table.

8. An optimization system for FPGA technology mapping, characterized in that: include: a memory for storing computer-executable instructions; as well as, A processor, configured to implement the steps of the method according to any one of claims 1 to 6 when executing the computer-executable instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the steps of the method according to any one of claims 1 to 4.

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