A chip and its time synchronization method

Abstract

This invention discloses a chip and its time synchronization method. The chip includes: multiple clock modules connected in a grid pattern, each clock module including multiple interconnected sub-clocks; each sub-clock has a register, which is used to configure one of the multiple clock modules as a global clock module and the rest as local clock modules; the global clock module updates its global clock value based on an external clock value and transmits it to each local clock module connected to it; the local clock modules update their own clock value based on the clock value transmitted from the previous level clock module and transmit it to the next level clock module. This application can dynamically configure the global clock module and the local clock modules by setting registers in each sub-clock.

Description

Technical Field

[0001] This invention relates to the field of chips, and in particular to a chip and a time synchronization method thereof. Background Technology

[0002] In chip design, the clocks of multiple clock modules need to be synchronized to ensure data transmission. Typically, each chip has a global clock module that updates the chip's global clock based on a calibration clock source, and then synchronizes the various local clocks on the chip according to the updated global clock.

[0003] like Figure 1 As shown, Figure 1 This is a current on-chip H-tree clock tree structure. Triangles represent master clocks, and circles represent slave clocks. This method uses the chip's center point as the global clock and connects the master and slave clocks at various locations through four clock trees, ensuring that the distance from the center point to each leaf node is equal. In this type of chip, the positions of the global clock, master clock, and slave clocks are fixed at the factory. Ideally, each path of clock value transmission is absolutely balanced, with no clock deviation. However, in actual manufacturing processes, due to factors such as periodic errors, interconnection errors, and environmental changes, the distance from the center point to each leaf node is not always equal, leading to clock deviation. Therefore, for chips with fixed global clock, master clock, and slave clock positions at the factory, users cannot eliminate clock deviation by adjusting the positions of the global clock, master clock, and slave clocks. Summary of the Invention

[0004] The main objective of this invention is to propose a chip and its time synchronization method, which aims to solve the problem that the current clock module structure on chips cannot be freely configured by users in the future.

[0005] To achieve the above objectives, this invention proposes a chip and a time synchronization method thereof, the chip comprising:

[0006] Multiple clock modules are connected in a grid-like communication manner, and each clock module includes multiple sub-clocks, all of which are connected to each other;

[0007] Each of the sub-clocks is provided with a register, and each register is used to configure one of the multiple clock modules as a global clock module and configure the remaining clock modules as local clock modules.

[0008] The global clock module is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the global clock value to each local clock module connected to it.

[0009] The local clock module is used to update its own clock value based on the clock value transmitted by the previous level clock module, and then transmit the updated clock value to the next level clock module.

[0010] In the embodiments of this application, any upper-level clock module and its communication-connected lower-level clock module transmit clock values ​​only through a sub-clock in their respective clock modules.

[0011] In this embodiment of the application, each register in the global clock module is further configured to configure one of the multiple sub-clocks in the global clock module as the global clock and configure the remaining sub-clocks as slave clocks;

[0012] The global clock is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the updated global clock value to each local clock module that is connected to it in communication.

[0013] In this embodiment of the application, each register in any local clock module is further configured to, based on the multiple sub-clocks in the local clock module, configure one of the sub-clocks as the master clock and the remaining sub-clocks as slave clocks;

[0014] The master clock in any of the local clock modules is used to update its own clock value based on the clock value transmitted from the previous level clock module, and to transmit the updated clock value to the next level clock module.

[0015] In this embodiment of the application, the global clock module and any local clock module connected to it are configured to transmit the global clock value only through the global clock of the global clock module and the master clock of the local clock module.

[0016] In this embodiment of the application, any upper-level local clock module and its communication-connected lower-level local clock module are configured to transmit clock values ​​only through the master clock of their respective local clock modules.

[0017] In this embodiment of the application, the global clock is configured as follows:

[0018] In response to receiving a clock value from a calibration clock source, the first stacking step is determined based on the received clock value and the value of its own timer.

[0019] The first clock value is obtained by superimposing the value of its own timer on the first superposition step number.

[0020] The global clock value is updated based on the first clock value and the transmission delay between the global clock and the calibration clock source.

[0021] In this embodiment of the application, the global clock is further configured as follows:

[0022] The first superposition step number is transmitted to each slave clock in the global clock module;

[0023] Each slave clock of the global clock module is configured as follows:

[0024] In response to receiving the first stacking step count, the values ​​of each slave clock timer are stacked based on the first stacking step count to obtain the second clock value corresponding to each slave clock.

[0025] The clock values ​​of each slave clock are updated based on the second clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock, and the transmission delay between the master clock and the calibration clock source.

[0026] In this embodiment of the application, the master clock in each of the local clock modules is configured as follows:

[0027] In response to receiving the clock value transmitted by the previous clock module, the second superposition step number is determined based on the received clock value and the value of its own timer.

[0028] Based on the second stacking step, the value of its own timer is stacked to obtain the third clock value;

[0029] The clock value of the master clock is updated based on the third clock value and the transmission delay between the master clock and the previous level clock module.

[0030] In this embodiment of the application, the master clock in any local clock module is further configured as follows:

[0031] The second superposition step number is transmitted to each slave clock in the local clock module corresponding to the master clock;

[0032] The slave clock in any local clock module is configured as follows:

[0033] In response to receiving the second superposition step number transmitted by the master clock of its local clock module, the value of its own timer is superimposed on the second superposition step number to obtain the fourth clock value;

[0034] The clock value of the slave clock is updated based on the fourth clock value, the transmission delay between the slave clock and the master clock in its local clock module, and the transmission delay between the master clock in its local clock module and the next-level clock module.

[0035] In the embodiments of this application, each of the registers is configured to configure the clock module located at the center of the grid as a global clock module and the remaining clock modules as local clock modules.

[0036] In this embodiment of the application, each of the registers is further configured as follows:

[0037] Each of the local clock modules is configured to receive only the clock value transmitted from the upper-level clock module.

[0038] In this embodiment of the application, when any clock module receives clock values ​​from multiple upstream clock modules, the clock module is configured to update its own clock value based on the multiple clock values.

[0039] This application also proposes a chip time synchronization method, wherein the chip includes: multiple clock modules, the multiple clock modules being connected in a grid-like communication manner, each clock module including multiple sub-clocks, each sub-clock being interconnected, and each sub-clock having a register, the method comprising:

[0040] Based on each of the aforementioned registers, one of the multiple clock modules is configured as a global clock module, and the remaining clock modules are configured as local clock modules;

[0041] Based on the calibration clock source, the global clock value is updated using the global clock module;

[0042] The global clock value is transmitted to each local clock module connected to the global clock module;

[0043] The clock values ​​of each local clock module are updated based on the clock values ​​received from the previous level clock module, and the updated clock values ​​of each local clock module are transmitted to the next level clock module.

[0044] In this embodiment of the application, the method further includes: any upper-level clock module and the lower-level clock module connected to it transmit clock values ​​only through a sub-clock of their respective clock modules.

[0045] In this embodiment of the application, after configuring the global clock module, the method further includes:

[0046] Based on the registers in the global clock module, one of the multiple sub-clocks in the global clock module is configured as the global clock, and the remaining sub-clocks are configured as slave clocks;

[0047] Based on the clock value of the calibration clock source, the global clock value is updated using the global clock;

[0048] Based on the global clock, the updated global clock value is transmitted to each local clock module that is communicatively connected to the global clock module.

[0049] In this embodiment of the application, the method further includes:

[0050] Based on the registers in each local clock module, the multiple sub-clocks in each local clock module are configured such that one sub-clock is the master clock and the remaining sub-clocks are slave clocks.

[0051] Based on the master clock in any local clock module, receive the clock value transmitted by the previous level clock module, and update the clock value of the master clock of the local clock module.

[0052] Based on the master clock of any local clock module, the updated clock value of the master clock in the local clock module is transmitted to the next level clock module.

[0053] In this embodiment of the application, the step of transmitting the updated global clock value to each local clock module communicatively connected to the global clock module based on the global clock includes:

[0054] The global clock value is transmitted only through the global clock of the global clock module and the master clock of the local clock module that is communicatively connected to the global clock module.

[0055] In this embodiment of the application, the step of transmitting the updated clock value of the master clock in any local clock module to the next-level clock module based on the master clock of the local clock module includes:

[0056] Clock values ​​are transmitted only through the master clock of the local clock module and the master clock of the next-level clock module that is communicatively connected to the local clock module.

[0057] In this embodiment of the application, updating the global clock value using the global clock based on the clock value of the calibration clock source includes:

[0058] The first stacking step is determined based on the clock value of the calibration clock source and the value of the global clock timer.

[0059] The values ​​of the global clock timer are superimposed based on the first superposition step to obtain the first clock value;

[0060] The global clock value is updated based on the first clock value and the transmission delay between the global clock and the calibration clock source.

[0061] In this embodiment of the application, after determining the first stacking step, the method further includes:

[0062] The first superposition step number is transmitted to each slave clock in the global clock module;

[0063] Based on the first stacking step, the values ​​of each slave clock timer are stacked to obtain each second clock value corresponding to each slave clock.

[0064] The clock values ​​of each slave clock are updated based on the second clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock, and the transmission delay between the master clock and the calibration clock source.

[0065] In this embodiment of the application, receiving the clock value transmitted from the previous-level clock module based on the master clock in any local clock module, and updating the clock value of the master clock of the local clock module, includes:

[0066] The second superposition step is determined based on the clock value received from the previous level clock module by the master clock in any local clock module, and the value of the master clock timer in that local clock module.

[0067] Based on the second superposition step, the value of the master clock timer is superimposed to obtain the third clock value;

[0068] The clock value of the master clock is updated based on the third clock value and the transmission delay between the master clock and the previous level clock module.

[0069] In this embodiment of the application, after determining the second stacking step number, the method further includes:

[0070] The second superposition step number corresponding to any local clock is transmitted to each slave clock in the local clock module where the local clock is located;

[0071] Based on the second superposition step, the values ​​of each slave clock timer in the local clock module where the local clock is located are superimposed to obtain the fourth clock value corresponding to each slave clock;

[0072] The clock values ​​of each slave clock are updated based on the fourth clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock in the local clock module, and the transmission delay between the master clock and the previous level clock module.

[0073] In this embodiment of the application, the method further includes: configuring the clock module located at the center of the grid as a global clock module, and configuring the remaining clock modules as local clock modules.

[0074] In this embodiment of the application, the method further includes:

[0075] Each of the local clock modules is configured to receive only the clock value transmitted from the upper-level clock module.

[0076] In this embodiment of the application, when any clock module receives clock values ​​from multiple upstream clock modules, the method further includes: updating the clock value of the clock module based on the received multiple clock values.

[0077] This application sets the clock structure on the chip as a grid composed of multiple clock modules, and sets multiple interconnected sub-clocks within each clock module. Each sub-clock has a register, which allows users to easily configure which is the global clock module and which is the local clock module. After configuration, the global clock module can receive clock values ​​from the calibration clock source and update the global clock value, which is then transmitted level by level to each local clock module so that each local clock module can update its own clock value. Attached Figure Description

[0078] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0079] Figure 1 This is a structural diagram of a current chip clock module;

[0080] Figure 2 This is a structural diagram of another type of chip clock module;

[0081] Figure 3 This is a structural diagram of the on-chip clock module in one embodiment of the present invention;

[0082] Figure 4 This is a structural diagram of a clock module on a chip according to another embodiment of the present invention;

[0083] Figure 5 for Figure 3 The structure diagram of the clock module after chip configuration;

[0084] Figure 6 for Figure 5 Transmission diagram after chip configuration;

[0085] Figure 7 for Figure 6 A schematic diagram showing the transmission between the global clock module and the calibration clock source on the chip.

[0086] Figure 8 A schematic diagram illustrating the handshake mechanism between the global clock module and the calibration clock source;

[0087] Figure 9This is a flowchart illustrating the steps of a chip time synchronization method in one embodiment of the present invention.

[0088] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0089] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0090] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0091] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0092] like Figure 3 As shown in the figure, this application provides a chip including: multiple clock modules, which are connected in a grid-like communication manner, each clock module including multiple sub-clocks, and each sub-clock is connected to each other;

[0093] Each of the sub-clocks is provided with a register, and each register is used to configure one of the multiple clock modules as a global clock module and configure the remaining clock modules as local clock modules.

[0094] The global clock module is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the global clock value to each local clock module connected to it.

[0095] The local clock module is used to update its own clock value based on the clock value transmitted by the previous level clock module, and then transmit the updated clock value to the next level clock module.

[0096] Specifically, such as Figure 3 As shown, the chip has multiple clock modules, and the specific number of clock modules can be set according to the location and requirements of each processing unit on the chip. Figure 3 The chip shown has nine clock modules (numbered 1-9), which are connected in a grid pattern to form a 3x3 grid-like clock communication connection structure. It should be noted that the specific number of clock modules is not limited in this embodiment. Figure 3 The chip shown has nine clock modules, but in other embodiments, such as Figure 4 The chip shown can also be configured with 49 clock modules, numbered 1 to 49.

[0097] In addition, each clock module contains multiple sub-clocks, all of which are interconnected. It should be noted that there is no limit to the specific number of sub-clocks within each clock module. For example, in... Figure 3 In the clock module structure shown, each clock module contains four sub-clocks, but in other embodiments, there may be more or fewer sub-clocks.

[0098] Each sub-clock contains a register (not shown in the diagram). These registers allow for the configuration of the global clock module and local clock modules within each clock module. The registers receive user configuration commands, which change the clock type of the sub-clock containing that register. Clock types include global clock, master clock, and slave clock. Furthermore, the clock module containing the global clock is the global clock module, used to receive the clock value from the calibration clock source and update the chip's global clock value. Therefore, when configuring the global clock module through the registers of each sub-clock, one sub-clock within the desired clock module can be configured as the global clock module, making that module the global clock module. The remaining clock modules will then function as local clock modules.

[0099] After receiving the clock value from the calibration clock source and updating the global clock value, the global clock module can transmit the global clock value to each local clock module connected to it. For example, in... Figure 4In the chip shown, clock module 25 is configured as a global clock module, while the other clock modules 1-24 and 26-49 are local clock modules. After the global clock module 25 receives the clock value from the calibration clock source and updates it to obtain the global clock value, it can transmit the updated global clock value to local clock modules 18, 24, 26, and 32. For local clock modules 18, 24, 26, and 32, after receiving the global clock value transmitted by the global clock module 25, they can update their own clock values ​​based on the global clock value. After updating their own clock values, local clock modules 18, 24, 26, and 32 can further transmit their updated clock values ​​to the next-level clock modules. For example, after updating its own clock value, local clock module 18 can transmit its updated clock value to local clock modules 11, 17, and 19. Similarly, local clock module 24 can transmit its updated clock value to local clock modules 17, 23, and 31, and so on. Thus, the global clock value updated by the global clock module can be transmitted step by step to each local clock module, so that each local clock module can update its own clock value.

[0100] In addition, the calibration clock source is used to provide a clock reference for the chip's global clock module. It can be an external clock source or other reference clock sources.

[0101] In the chip embodiments of this application, at the time of chip manufacturing, there is no distinction between which clock module is the global clock module and which is the local clock module. Furthermore, within each clock module, there is no distinction between which sub-clock is the global clock, which is the master clock, and which is the slave clock. This application addresses this by setting the clock structure on the chip as a grid composed of multiple clock modules, with multiple interconnected sub-clocks within each clock module. Each sub-clock has a register, allowing users to easily configure which is the global clock module and which is the local clock module. After configuration, the global clock module receives clock values ​​from the calibration clock source and updates the global clock value, which is then transmitted level by level to each local clock module for individual clock value updates.

[0102] In this embodiment of the application, any upstream clock module and downstream clock module transmit clock values ​​only through one sub-clock within their respective clock modules. For example... Figure 2 As shown, Figure 2This is a common clock structure on current chips, where each grid intersection has a clock, and the clocks are interconnected in a mesh. Chips with this clock structure do not have a factory-defined global clock, master clock, or slave clock, allowing users to configure them later. However, in this structure, each grid intersection clock needs to be connected to other clocks via four communication lines, resulting in longer interconnects and greater transmission delay. Figure 4 As shown in the embodiments of this application, the global clock module 25 and the local clock module 24 are a pair of upper-level and lower-level clock modules, respectively, and they transmit clock values ​​only through their respective sub-clocks. For example, as... Figure 3 As shown, assuming clock module 5 is the upstream clock module of clock module 4, clock module 5 has only one sub-clock that transmits clock values ​​with one sub-clock in clock module 4. This application embodiment is similar to... Figure 2 Compared to the chip shown, Figure 2 Each intersection point represents a clock, and the four clocks correspond to one clock module in the embodiments of this application, such as... Figure 2 The four clocks within the dashed box shown require eight communication lines (1-8) to connect with other clocks. In contrast, a clock module in this application (containing four or more sub-clocks) only requires four communication lines to connect with other clock modules. This reduces the wiring length between clocks on the chip and minimizes transmission delay.

[0103] In this embodiment of the application, each register in the global clock module is further configured to configure one of the multiple sub-clocks in the global clock module as the global clock and configure the remaining sub-clocks as slave clocks; the global clock is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the updated global clock value to each local clock module that is communicatively connected to it.

[0104] Within the chip, each slave clock's register has a specific address. Therefore, during configuration, specific values ​​can be written into the registers, each value representing a different type. For example, 2'b00 represents the global clock, 2'b01 represents the master clock, and 2'b10 represents the slave clock. After writing the specific value, the slave clock located at that address is configured with the corresponding clock type.

[0105] Based on this, such as Figure 3 , Figure 5As shown, assuming you want to set clock module 5 as a global clock module, you can select one of the sub-clocks in clock module 5 as the global clock. When one of the sub-clocks in a clock module is configured as the global clock, the clock module is configured as a global clock. That is, select any one of the sub-clocks in clock module 5 and configure it as the global clock, and clock module 5 will be configured as a global clock module.

[0106] Specifically, assuming that clock module 5 needs to be set as a global clock module, and the bottommost sub-clock in clock module 5 needs to be set as a global clock, then 2'b00 can be written into the register of the bottommost sub-clock in clock module 5. At this time, the bottommost sub-clock in clock module 5 is configured as a global clock, and then the clock value of the calibration clock source can be received through the bottommost sub-clock in clock module 5, thereby updating the global clock value of the chip.

[0107] In addition, after configuring the bottommost sub-clock in clock module 5 as the global clock, several other sub-clocks can be configured as slave clocks. For example, if 2'b10 is written into the register of another sub-clock in clock module 5, then the sub-clock in the register where 2'b10 is written will be the slave clock in the global clock module.

[0108] Since the sub-clocks in any clock module of the chip in this embodiment are all connected to each other, for the selected global clock module, no matter which sub-clock is selected as the global clock, the global clock obtained after configuration can communicate with other slave clocks, which makes it convenient for users to configure according to actual conditions.

[0109] like Figure 5 As shown in the embodiments of this application, each register in any local clock module is further configured to configure one of the sub-clocks as the master clock and the remaining sub-clocks as slave clocks based on the multiple sub-clocks in the local clock module; the master clock in any local clock module is configured to update its own clock value based on the clock value transmitted by the upper-level clock module, and transmit the updated clock value to the next-level clock module.

[0110] Specifically, also Figure 5 Taking clock module 5 as an example, which is the global clock module, then clock modules 1-4 and 6-9 are local clock modules. When configuring the master and slave clocks in the local clock modules, the same method of writing specific values ​​into the registers can be used.

[0111] For example, for local clock module 1, assuming we want to set the bottommost sub-clock as the master clock and the others as slave clocks, we can write 2'b01 to the register of the bottommost sub-clock and 2'b10 to the registers of the others. After configuring the master and slave clocks, the master clock can communicate with each slave clock. Similarly, since the sub-clocks in any clock module of the chip in this embodiment are interconnected, for each local clock module, regardless of which sub-clock is selected as the master clock, the master clock obtained after configuration can communicate with all other slave clocks, making it convenient for users to configure according to actual needs.

[0112] In this embodiment, the global clock module and any locally connected local clock module are configured to transmit the global clock value only through the global clock of the global clock module and the master clock of the local clock module. Any upstream local clock module and its downstream local clock module are configured to transmit clock values ​​only through the master clock of their respective local clock modules.

[0113] like Figure 5 As shown, after configuring the global clock module, local clock module, global clock and each slave clock in the global clock module, and master clock and each slave clock in the local clock module, the global clock in the global clock module updates the global clock value according to the clock value of the calibration clock source, and transmits the updated global clock value to each master clock of the local clock module connected to it. For example, the global clock in global clock module 5 transmits the global clock value to each master clock in local clock modules 2, 4, 6, and 8. After receiving the global clock value, the master clock in the local clock module updates its own clock value and further transmits the updated clock value to the master clock of the next level local clock module, and so on, until the time synchronization of all clock modules on the chip is completed.

[0114] In this embodiment of the application, the global clock is configured as follows:

[0115] In response to receiving a clock value from a calibration clock source, the first stacking step number is determined based on the received clock value from the calibration clock source and the value of its own timer.

[0116] The first clock value is obtained by superimposing the value of its own timer on the first superposition step number.

[0117] The global clock value is updated based on the first clock value and the transmission delay between the global clock and the calibration clock source.

[0118] like Figure 6As shown, after configuring the global clock module and the main unit module, timing can begin. Initially, all sub-clocks within the chip can be reset to zero, including the global clock and slave clock of the global clock module, and the master clock and slave clock of the local clock module. For example... Figure 7 As shown, assuming that at a certain moment the calibration clock source sends a clock value T to the global clock module, when the global clock in the global clock module receives T, it compares it with the setting of its own internal timer to determine the number of timer steps that need to be added, i.e. the first superposition step.

[0119] Assuming the global clock receives a value of T_outer when it is T_full, and its own timer value is t_full, then by using (T_outer - t_full), we can determine the first stacking step tick1 = (T_outer - t_full). At this point, we can add the first stacking step to the value of our own timer to obtain the first clock value T_full', as follows:

[0120] T_total' = T_total + tick1

[0121] =T_total + T_external - t_total

[0122] In addition, since there is a transmission delay between the calibration clock source and the global clock, that is, there is a certain delay when the calibration clock source transmits T to the global clock, the global clock also needs to take the transmission delay into account when updating the global clock value.

[0123] like Figure 8 As shown, the transmission delay between the calibration clock source and the global clock can be calculated using a handshake mechanism. Assuming the calibration clock source sends a ping signal to the global clock at time t1, and the global clock receives the ping signal and returns an echo signal to the calibration clock source, and the calibration clock source receives the echo signal at time t2, and assuming the transmission delay between the calibration clock source and the global clock source is t, then:

[0124] t = (t2 - t1) / 2

[0125] Therefore, the final updated global clock T_full = T_full' + t

[0126] The "T_full" mentioned above refers to the global clock updated after the global clock receives the clock value from the calibration clock source.

[0127] In this embodiment of the application, the global clock module is further configured as follows:

[0128] The first superposition step number is transmitted to each slave clock in the global clock module;

[0129] Each slave clock of the global clock module is configured as follows:

[0130] In response to receiving the first stacking step count, the values ​​of each slave clock timer are stacked based on the first stacking step count to obtain the second clock value corresponding to each slave clock.

[0131] The clock values ​​of each slave clock are updated based on the second clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock, and the transmission delay between the master clock and the calibration clock source.

[0132] like Figure 7 As shown, after determining the first stacking step tick1, the global clock is configured to transmit the first stacking step tick1 to each slave clock 1, 2, 3 within the global clock module.

[0133] After receiving tick1 from clocks 1, 2, and 3, each clock adds up the value of its own timer according to the first stacking step tick1, thus obtaining a second clock value.

[0134] Similarly, there is a transmission delay between the global clock and each slave clock in the global clock module. Therefore, after the first stacking step is added, each slave clock needs to have its own transmission delay with the global clock added. The transmission delays between slave clocks 1, 2, and 3 and the global clock can also be calculated using the handshake mechanism described above, which will not be elaborated here. After the first stacking step is added to each slave clock, the transmission delay between each slave clock and the global clock is added to obtain their updated clock values.

[0135] In this embodiment of the application, the master clock in each of the local clock modules is configured as follows:

[0136] In response to receiving the clock value transmitted by the previous clock module, the second superposition step number is determined based on the received clock value and the value of its own timer.

[0137] Based on the second stacking step, the value of its own timer is stacked to obtain the third clock value;

[0138] The clock value of the master clock is updated based on the third clock value and the transmission delay between the master clock and the previous level clock module.

[0139] Taking the global clock update to the global clock value "T_full" as an example, after the global clock update obtains the global clock value "T_full", the updated global clock value "T_full" can be transmitted to the master clock of each local clock module connected to it, such as... Figure 6As shown, the global clock can transmit the global clock value "T_full" to each master clock within local clock modules 2, 4, 6, and 8. After receiving the global clock value "T_full", each master clock within local clock modules 2, 4, 6, and 8 can update its own clock value based on the global clock value "T_full", as follows:

[0140] Taking local clock module 6 as an example, assuming that when the master clock in local clock module 6 receives the global clock value T_full from the global clock, its own clock is T6, and the timer value is displayed as t6, then based on the global clock value T_full and t6, the number of steps that the timer of the master clock in local clock module 6 needs to be superimposed, i.e., the second superposition step number, can be calculated. Assuming the second superposition step number is tick2, then:

[0141] tick2 = T_all - t6

[0142] After obtaining tick2, the value of the master clock timer in the local clock module 6 is superimposed with the number of steps of tick2 to obtain the third clock value, assuming it is T6', then:

[0143] T6' = T6 + tick2

[0144] Furthermore, due to the transmission delay between the master clock in local clock module 6 and the global clock, an additional transmission delay needs to be added to T6' to obtain the final updated clock value. The transmission delay between the master clock in local clock module 6 and the global clock can also be calculated using a handshake mechanism, which will not be elaborated here. Assuming it is t', the final updated clock value T6" obtained by the master clock in local clock module 6 is:

[0145] T6”=T6'+t'

[0146] In addition, after the master clock in the local clock module 6 receives the updated clock value, it can also transmit the clock value T6” to the master clock of the next level clock module for clock value synchronization.

[0147] In this embodiment of the application, the master clock in any local clock module is further configured as follows:

[0148] The second superposition step number is transmitted to each slave clock in the local clock module corresponding to the master clock;

[0149] The slave clock in any local clock module is configured as follows:

[0150] In response to receiving the second superposition step number transmitted from the master clock of its local clock module, the value of its own timer is superimposed on the second superposition step number to obtain a fourth clock value;

[0151] The clock value of the slave clock is updated based on the fourth clock value, the transmission delay between the slave clock and the master clock in its local clock module, and the transmission delay between the master clock in its local clock module and the next-level clock module.

[0152] Taking local clock module 6 as an example, after its master clock calculates the second superposition step tick2, it can transmit the second superposition step tick2 to each slave clock of local clock module 6. After each slave clock of local clock module 6 receives tick2, it superimposes the tick2 value on the value of its respective timer to obtain its corresponding fourth clock value. Since there is a transmission delay between each slave clock and the master clock, the clock value updated by each slave clock also needs to be increased by the transmission delay between itself and the master clock on the basis of its corresponding fourth clock value. The transmission delay between each slave clock and the master clock can also be calculated using a handshake mechanism, which will not be elaborated here.

[0153] In this application, only the number of steps is transmitted between the master clock and slave clock within each clock module, or between the global clock and slave clock. Therefore, for the same clock module, each time update of its sub-clocks can be accumulated according to the same number of steps, enabling more accurate synchronization between the clock modules. In addition, the timer of each clock module only accumulates, and the clock value is accumulated according to the number of steps when updating, without abrupt changes. Even if the transmitted clock value is incorrect, it is gradually accumulated according to the number of steps, which can be adjusted in time without abrupt changes, thus preventing huge errors when the clock value is transmitted incorrectly. Furthermore, between each clock module, such as between the calibration clock source and the global clock, between the global clock and the master clock of the local clock module, and between the master clocks of the local clock modules, only the specific clock value is transmitted, without transmitting the superposition steps of the timers of each clock module. As a result, the clock values ​​received by each clock module in each level are the same as those of the previous level. Therefore, if the clock value of a clock module in a certain level is significantly different from that of other clock modules in the same level, it can be determined that the clock module is malfunctioning. Thus, it is possible to detect which clock module is malfunctioning in a timely manner and make it easier to correct it promptly.

[0154] In addition, in this application, after the first and second stacking steps are determined, they can be accumulated step by step. However, when the first or second stacking steps are too large, the gradual accumulation is cumbersome. Therefore, different thresholds can be used to accumulate steps.

[0155] For example, when tick (including tick1 and tick2) ≥ 256, increment by 256 steps each time;

[0156] When 1 < tick < 256, increment by 2 steps each time;

[0157] When tick = 1, increment gradually;

[0158] When tick < 0, it is not accumulated.

[0159] Additionally, when stacking in 2 or 256 steps at a time, if the stacking reaches a point where there are fewer than 2 or 256 steps, then stacking in smaller steps again until all ticks are stacked.

[0160] In addition, such as Figure 3-6 As shown in this embodiment, the clock module located at the center of the grid is configured as the global clock module, and the other clock modules are configured as local clock modules. This allows the global time of the global clock module to be evenly transmitted to each local clock module on the chip. However, it is not necessary to place the global clock module at the center; the specific location of the global clock module can be determined according to specific requirements.

[0161] like Figure 4 As shown, some local clock modules may receive clock values ​​transmitted from multiple other local clock modules. For example, local clock module 17 can receive clock values ​​transmitted from local clock modules 24 and 18, and local clock module 19 can receive clock values ​​transmitted from local clock modules 18 and 26. A clock module that can receive clock values ​​from multiple clock modules can be configured to receive all of them or to receive only one.

[0162] For example, such as Figure 4 As shown, the local clock module 17 can be configured to accept only the clock value transmitted by the local clock module 24 or the local clock module 18, thereby reducing clock power consumption.

[0163] If the configuration is to receive all values, then for local clock module 17, it is necessary to combine the clock values ​​transmitted by local clock module 24 and local clock module 18, and then update them.

[0164] This application sets the clock structure on the chip as a grid composed of multiple clock modules, and sets multiple interconnected sub-clocks within each clock module. Each sub-clock has a register, which allows users to easily configure which is the global clock module and which is the local clock module. After configuration, the global clock module can receive clock values ​​from the calibration clock source and update the global clock value, which is then transmitted level by level to each local clock module so that each local clock module can update its own clock value.

[0165] This application also proposes a chip time synchronization method. The chip includes: multiple clock modules connected in a grid pattern, each clock module including multiple sub-clocks, all sub-clocks being interconnected, and each sub-clock having a register, such as... Figure 9 As shown, the method includes the following steps:

[0166] Step S100: Based on each of the registers, configure one of the multiple clock modules as a global clock module and configure the remaining clock modules as local clock modules.

[0167] Step S200: Update the global clock value using the global clock module based on the calibration clock source.

[0168] Step S300: Transmit the global clock value to each local clock module connected to the global clock module.

[0169] Step S400: Update the clock value of each local clock module based on the clock value received from the previous level clock module, and transmit the updated clock value of each local clock module to the next level clock module.

[0170] The specific methods for steps S100-S400 described above are as described in the various chip embodiments above, and will not be repeated here.

[0171] In the application embodiment, the method further includes: any upper-level clock module and the lower-level clock module connected to it transmit clock values ​​only through a sub-clock of their respective clock modules.

[0172] In the application embodiment, after configuring the global clock module, the method further includes:

[0173] Based on the registers in the global clock module, one of the multiple sub-clocks in the global clock module is configured as the global clock, and the remaining sub-clocks are configured as slave clocks;

[0174] Based on the clock value of the calibration clock source, the global clock value is updated using the global clock;

[0175] Based on the global clock, the updated global clock value is transmitted to each local clock module that is communicatively connected to the global clock module.

[0176] In this application implementation, the method further includes:

[0177] Based on the registers in each local clock module, the multiple sub-clocks in each local clock module are configured such that one sub-clock is the master clock and the remaining sub-clocks are slave clocks.

[0178] Based on the master clock in any local clock module, receive the clock value transmitted by the previous level clock module, and update the clock value of the master clock of the local clock module.

[0179] Based on the master clock of any local clock module, the updated clock value of the master clock in the local clock module is transmitted to the next level clock module.

[0180] In this application implementation, the step of transmitting the updated global clock value to each local clock module communicatively connected to the global clock module based on the global clock includes:

[0181] The global clock value is transmitted only through the global clock of the global clock module and the master clock of the local clock module that is communicatively connected to the global clock module.

[0182] In this application, the step of transmitting the updated clock value of the master clock in any local clock module to the next-level clock module based on the master clock of the local clock module includes:

[0183] Clock values ​​are transmitted only through the master clock of the local clock module and the master clock of the next-level clock module that is communicatively connected to the local clock module.

[0184] In this application, updating the global clock value using the global clock based on the clock value of the calibration clock source includes:

[0185] The first stacking step is determined based on the clock value of the calibration clock source and the value of the global clock timer.

[0186] The values ​​of the global clock timer are superimposed based on the first superposition step to obtain the first clock value;

[0187] The global clock value is updated based on the first clock value and the transmission delay between the global clock and the calibration clock source.

[0188] In this application, after determining the first stacking step, the method further includes:

[0189] The first superposition step number is transmitted to each slave clock in the global clock module;

[0190] Based on the first stacking step, the values ​​of each slave clock timer are stacked to obtain each second clock value corresponding to each slave clock.

[0191] The clock values ​​of each slave clock are updated based on the second clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock, and the transmission delay between the master clock and the calibration clock source.

[0192] In this application, the step of receiving the clock value transmitted from the previous-level clock module based on the master clock in any local clock module, and updating the clock value of the master clock of the local clock module, includes:

[0193] The second superposition step is determined based on the clock value received from the previous level clock module by the master clock in any local clock module, and the value of the master clock timer in that local clock module.

[0194] Based on the second superposition step, the value of the master clock timer is superimposed to obtain the third clock value;

[0195] The clock value of the master clock is updated based on the third clock value and the transmission delay between the master clock and the previous level clock module.

[0196] In this application implementation, after determining the second overlay step, the method further includes:

[0197] The second superposition step number corresponding to any local clock is transmitted to each slave clock in the local clock module where the local clock is located;

[0198] Based on the second superposition step, the values ​​of each slave clock timer in the local clock module where the local clock is located are superimposed to obtain the fourth clock value corresponding to each slave clock;

[0199] The clock values ​​of each slave clock are updated based on the fourth clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock in the local clock module, and the transmission delay between the master clock and the previous level clock module.

[0200] In this application implementation, the method further includes: configuring the clock module located at the center of the grid as a global clock module, and configuring the remaining clock modules as local clock modules.

[0201] In this application implementation, the method further includes:

[0202] Each of the local clock modules is configured to receive only the clock value transmitted from the upper-level clock module.

[0203] In this application, when any clock module receives clock values ​​from multiple upstream clock modules, the method further includes: updating the clock value of the clock module based on the received multiple clock values.

[0204] In this embodiment of the application, through various registers, it is possible to configure which of the multiple clock modules in a grid-like structure is the global clock module and which is the local clock module. After the configuration is completed, the global clock module receives the clock value from the calibration clock source and updates the global clock value, which is then transmitted level by level to each local clock module so that each local clock module can update its own clock value.

[0205] Finally, it should be noted that the above-described embodiments are merely specific implementations of the invention, used to illustrate the technical solutions of the invention, and not to limit it. The scope of protection of the invention is not limited thereto. Although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the scope of the technology disclosed in the invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the invention embodiments, and should all be covered within the scope of protection of the invention. Therefore, the scope of protection of the invention should be determined by the scope of the claims.

[0206] Based on the above description, the embodiments of this application provide at least the following technical solutions, but are not limited thereto:

[0207] 1. A chip comprising: a plurality of clock modules, the plurality of clock modules being connected in a grid-like manner, each clock module including a plurality of sub-clocks, and each of the sub-clocks being connected to each other;

[0208] Each of the sub-clocks is provided with a register, and each register is used to configure one of the multiple clock modules as a global clock module and configure the remaining clock modules as local clock modules.

[0209] The global clock module is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the global clock value to each local clock module connected to it.

[0210] The local clock module is used to update its own clock value based on the clock value transmitted by the previous level clock module, and then transmit the updated clock value to the next level clock module.

[0211] 2. As described in technical solution 1, in any upstream clock module and the downstream clock module connected to it, clock values ​​are transmitted only through a sub-clock in each clock module.

[0212] 3. The chip as described in any one of technical solutions 1-2, wherein each register in the global clock module is further configured to configure one of the multiple sub-clocks in the global clock module as the global clock, and configure the remaining sub-clocks as slave clocks;

[0213] The global clock is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the updated global clock value to each local clock module that is connected to it in communication.

[0214] 4. In the chip described in any one of technical solutions 1-3, each register in any local clock module is further used to configure one of the sub-clocks as the master clock and the remaining sub-clocks as slave clocks based on the multiple sub-clocks in the local clock module;

[0215] The master clock in any of the local clock modules is used to update its own clock value based on the clock value transmitted from the previous level clock module, and to transmit the updated clock value to the next level clock module.

[0216] 5. The chip as described in any one of technical solutions 1-4, wherein the global clock module and any local clock module connected to it are configured to transmit the global clock value only through the global clock of the global clock module and the master clock of the local clock module.

[0217] 6. In the chip described in any one of technical solutions 1-5, any upper-level local clock module and the lower-level local clock module connected to it are configured to transmit clock values ​​only through the master clock of their respective local clock modules.

[0218] 7. The chip as described in any one of technical solutions 1-6, wherein the global clock is configured as follows:

[0219] In response to receiving a clock value from a calibration clock source, the first stacking step is determined based on the received clock value and the value of its own timer.

[0220] The first clock value is obtained by superimposing the value of its own timer on the first superposition step number.

[0221] The global clock value is updated based on the first clock value and the transmission delay between the global clock and the calibration clock source.

[0222] 8. The chip as described in any one of technical solutions 1-7, wherein the global clock is further configured as follows:

[0223] The first superposition step number is transmitted to each slave clock in the global clock module;

[0224] Each slave clock of the global clock module is configured as follows:

[0225] In response to receiving the first stacking step count, the values ​​of each slave clock timer are stacked based on the first stacking step count to obtain the second clock value corresponding to each slave clock.

[0226] The clock values ​​of each slave clock are updated based on the second clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock, and the transmission delay between the master clock and the calibration clock source.

[0227] 9. In the chip described in any one of technical solutions 1-8, the master clock in each of the local clock modules is configured as follows:

[0228] In response to receiving the clock value transmitted by the previous clock module, the second superposition step number is determined based on the received clock value and the value of its own timer.

[0229] Based on the second stacking step, the value of its own timer is stacked to obtain the third clock value;

[0230] The clock value of the master clock is updated based on the third clock value and the transmission delay between the master clock and the previous level clock module.

[0231] 10. In the chip described in any one of technical solutions 1-9, the master clock in any local clock module is further configured as follows:

[0232] The second superposition step number is transmitted to each slave clock in the local clock module corresponding to the master clock;

[0233] The slave clock in any local clock module is configured as follows:

[0234] In response to receiving the second superposition step number transmitted by the master clock of its local clock module, the value of its own timer is superimposed on the second superposition step number to obtain the fourth clock value;

[0235] The clock value of the slave clock is updated based on the fourth clock value, the transmission delay between the slave clock and the master clock in its local clock module, and the transmission delay between the master clock in its local clock module and the next-level clock module.

[0236] 11. The chip as described in any one of technical solutions 1-10, wherein each of the registers is configured to configure the clock module located at the center of the grid as a global clock module and the remaining clock modules as local clock modules.

[0237] 12. The chip as described in any one of technical solutions 1-10, wherein each of the registers is further configured as follows:

[0238] Each of the local clock modules is configured to receive only the clock value transmitted from the upper-level clock module.

[0239] 13. The chip as described in any one of technical solutions 1-12, wherein when any clock module receives clock values ​​from multiple upstream clock modules, the clock module is configured to update its own clock value based on the multiple clock values.

[0240] 14. A chip time synchronization method, the chip comprising: a plurality of clock modules, the plurality of clock modules being interconnected in a grid pattern, each clock module including a plurality of sub-clocks, each of the sub-clocks being interconnected with each other, each sub-clock being provided with a register, the method comprising:

[0241] Based on each of the aforementioned registers, one of the multiple clock modules is configured as a global clock module, and the remaining clock modules are configured as local clock modules;

[0242] Based on the calibration clock source, the global clock value is updated using the global clock module;

[0243] The global clock value is transmitted to each local clock module connected to the global clock module;

[0244] The clock values ​​of each local clock module are updated based on the clock values ​​received from the previous level clock module, and the updated clock values ​​of each local clock module are transmitted to the next level clock module.

[0245] 15. The chip time synchronization method as described in technical solution 14, the method further includes: any upper-level clock module and the lower-level clock module connected to it transmit clock values ​​only through a sub-clock of their respective clock modules.

[0246] 16. The chip time synchronization method as described in technical solution 14 or 15, after configuring the global clock module, the method further includes:

[0247] Based on the registers in the global clock module, one of the multiple sub-clocks in the global clock module is configured as the global clock, and the remaining sub-clocks are configured as slave clocks;

[0248] Based on the clock value of the calibration clock source, the global clock value is updated using the global clock;

[0249] Based on the global clock, the updated global clock value is transmitted to each local clock module that is communicatively connected to the global clock module.

[0250] 17. The chip time synchronization method as described in any one of technical solutions 14-16, the method further comprising:

[0251] Based on the registers in each local clock module, the multiple sub-clocks in each local clock module are configured such that one sub-clock is the master clock and the remaining sub-clocks are slave clocks.

[0252] Based on the master clock in any local clock module, receive the clock value transmitted by the previous level clock module, and update the clock value of the master clock of the local clock module.

[0253] Based on the master clock of any local clock module, the updated clock value of the master clock in the local clock module is transmitted to the next level clock module.

[0254] 18. The chip time synchronization method as described in any one of technical solutions 14-17, wherein transmitting the updated global clock value based on the global clock to each local clock module communicatively connected to the global clock module includes:

[0255] The global clock value is transmitted only through the global clock of the global clock module and the master clock of the local clock module that is communicatively connected to the global clock module.

[0256] 19. The chip time synchronization method as described in any one of technical solutions 14-18, wherein transmitting the updated clock value of the master clock in any local clock module to the next-level clock module based on the master clock of any local clock module includes:

[0257] Clock values ​​are transmitted only through the master clock of the local clock module and the master clock of the next-level clock module that is communicatively connected to the local clock module.

[0258] 20. The chip time synchronization method according to any one of technical solutions 14-19, wherein updating the global clock value based on the clock value of the calibration clock source using the global clock includes:

[0259] The first stacking step is determined based on the clock value of the calibration clock source and the value of the global clock timer.

[0260] The values ​​of the global clock timer are superimposed based on the first superposition step to obtain the first clock value;

[0261] The global clock value is updated based on the first clock value and the transmission delay between the global clock and the calibration clock source.

[0262] 21. The chip time synchronization method as described in any one of technical solutions 14-20, after determining the first superposition step number, the method further includes:

[0263] The first superposition step number is transmitted to each slave clock in the global clock module;

[0264] Based on the first stacking step, the values ​​of each slave clock timer are stacked to obtain each second clock value corresponding to each slave clock.

[0265] The clock values ​​of each slave clock are updated based on the second clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock, and the transmission delay between the master clock and the calibration clock source.

[0266] 22. The chip time synchronization method as described in any one of technical solutions 14-21, wherein receiving the clock value transmitted from the previous-level clock module based on the master clock in any local clock module, and updating the clock value of the master clock of the local clock module, includes:

[0267] The second superposition step is determined based on the clock value received from the previous level clock module by the master clock in any local clock module, and the value of the master clock timer in that local clock module.

[0268] Based on the second superposition step, the value of the master clock timer is superimposed to obtain the third clock value;

[0269] The clock value of the master clock is updated based on the third clock value and the transmission delay between the master clock and the previous level clock module.

[0270] 23. The chip time synchronization method as described in any one of technical solutions 14-22, after determining the second superposition step number, the method further includes:

[0271] The second superposition step number corresponding to any local clock is transmitted to each slave clock in the local clock module where the local clock is located;

[0272] Based on the second superposition step, the values ​​of each slave clock timer in the local clock module where the local clock is located are superimposed to obtain the fourth clock value corresponding to each slave clock;

[0273] The clock values ​​of each slave clock are updated based on the fourth clock value corresponding to each slave clock, the transmission delay between each slave clock and the master clock in the local clock module, and the transmission delay between the master clock and the previous level clock module.

[0274] 24. The chip time synchronization method as described in any one of technical solutions 14-23, the method further comprising: configuring the clock module located at the center of the grid as a global clock module, and configuring the remaining clock modules as local clock modules.

[0275] 25. The chip time synchronization method as described in any one of technical solutions 14-24, the method further comprising:

[0276] Each of the local clock modules is configured to receive only the clock value transmitted from the upper-level clock module.

[0277] 26. The chip time synchronization method as described in any one of technical solutions 14-25, wherein when any clock module receives clock values ​​from multiple upstream clock modules, the method further includes: updating the clock value of the clock module based on the received multiple clock values.

Claims

1. A chip, characterized in that, include: Multiple clock modules are connected in a grid-like communication manner, and each clock module includes multiple sub-clocks, all of which are connected to each other; Each of the sub-clocks is equipped with a register. Each register is used to configure one of the multiple clock modules as a global clock module and configure the remaining clock modules as local clock modules. The register is used to receive configuration instructions from the user and change the clock type of the sub-clock where the register is located according to the user's configuration instructions. The clock type includes global clock, master clock, and slave clock. The clock module containing the global clock is the global clock module, and the remaining clock modules are local clock modules. When configuring the global clock module through the registers of each sub-clock, one of the sub-clock modules that needs to be set as the global clock module is configured as the global clock, and the remaining clock modules are local clock modules. The global clock module is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the global clock value to each local clock module connected to it. The local clock module is used to update its own clock value based on the clock value transmitted by the previous level clock module, and then transmit the updated clock value to the next level clock module.

2. The chip as described in claim 1, characterized in that, Between any upstream clock module and its downstream clock module, clock values ​​are transmitted only through a sub-clock in each module.

3. The chip as described in claim 1, characterized in that, Each register in the global clock module is also used to configure one of the multiple sub-clocks in the global clock module as the global clock and configure the remaining sub-clocks as slave clocks. The global clock is used to update the global clock value based on the clock value of the calibration clock source, and to transmit the updated global clock value to each local clock module that is connected to it in communication.

4. The chip as described in claim 3, characterized in that, Each register in any local clock module is also used to configure one of the sub-clocks as the master clock and the remaining sub-clocks as slave clocks, based on the multiple sub-clocks in the local clock module. The master clock in any of the local clock modules is used to update its own clock value based on the clock value transmitted from the previous level clock module, and to transmit the updated clock value to the next level clock module.

5. The chip as described in claim 4, characterized in that, The global clock module and any local clock module connected to it are configured to transmit the global clock value only through the global clock of the global clock module and the master clock of the local clock module.

6. A chip time synchronization method, characterized in that, The chip includes: multiple clock modules connected in a grid pattern, each clock module including multiple sub-clocks, all sub-clocks interconnected, and each sub-clock having a register for receiving user configuration commands. The register changes the clock type of the sub-clock containing the register according to the user's configuration commands. The clock types include global clock, master clock, and slave clock. The clock module containing the global clock is the global clock module, and the remaining clock modules are local clock modules. When configuring the global clock module through the registers of each sub-clock, one sub-clock in the clock module that needs to be set as the global clock is configured as the global clock, and the remaining clock modules are local clock modules. The method includes: Based on each of the aforementioned registers, one of the multiple clock modules is configured as a global clock module, and the remaining clock modules are configured as local clock modules; Based on the calibration clock source, the global clock value is updated using the global clock module; The global clock value is transmitted to each local clock module connected to the global clock module; The clock values ​​of each local clock module are updated based on the clock values ​​received from the previous level clock module, and the updated clock values ​​of each local clock module are transmitted to the next level clock module.

7. The chip time synchronization method as described in claim 6, characterized in that, The method further includes: any upper-level clock module and its communication-connected lower-level clock module transmit clock values ​​only through one sub-clock in their respective clock modules.

8. The chip time synchronization method as described in claim 6, characterized in that, After configuring the global clock module, the method further includes: Based on the registers in the global clock module, one of the multiple sub-clocks in the global clock module is configured as the global clock, and the remaining sub-clocks are configured as slave clocks; Based on the clock value of the calibration clock source, the global clock value is updated using the global clock; Based on the global clock, the updated global clock value is transmitted to each local clock module that is communicatively connected to the global clock module.

9. The chip time synchronization method as described in claim 8, characterized in that, The method further includes: Based on the registers in each local clock module, the multiple sub-clocks in each local clock module are configured such that one sub-clock is the master clock and the remaining sub-clocks are slave clocks. Based on the master clock in any local clock module, receive the clock value transmitted by the previous level clock module, and update the clock value of the master clock of the local clock module. Based on the master clock of any local clock module, the updated clock value of the master clock in the local clock module is transmitted to the next level clock module.

10. The chip time synchronization method as described in claim 9, characterized in that, The step of transmitting the updated global clock value to each local clock module communicatively connected to the global clock module based on the global clock includes: The global clock value is transmitted only through the global clock of the global clock module and the master clock of the local clock module that is communicatively connected to the global clock module.

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