Chip layout and routing method and device, computer equipment and readable storage medium

Abstract

Embodiments of the present application provide a chip layout and wiring method, device, computer equipment and readable storage medium, the method comprises: according to the preset prevention voltage drop cell attribute information, determine a plurality of to be encrypted units, wherein the prevention voltage drop cell attribute information includes at least one of the following: the cell type is main clock gating, the fanout of the cell is greater than the preset fanout value, the drive of the cell is greater than the preset drive value;The position of each to-be-encrypted unit is determined respectively;According to the position of each to-be-encrypted unit, the bottom Powermesh of the plurality of to-be-encrypted units is encrypted to obtain the encrypted position of each to-be-encrypted unit. Through the method, the problem of voltage drop can be solved in advance, and the problems of affecting timing and low efficiency caused by solving the problem of voltage drop after the layout and wiring stage can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, in particular, relates to a chip layout and wiring method and device, computer equipment and readable storage medium. BACKGROUND

[0002] Voltage drop (IR_drop) refers to the phenomenon of voltage drop or rise on the power supply and ground network in integrated circuits. In the field of chip design, as the chip process size becomes smaller and smaller, the influence of voltage drop on the timing of the chip is more and more obvious. Therefore, how to solve the problem of voltage drop is an important problem in the field of chip design.

[0003] At present, mainly after the placement and routing (PR) stage, the problem unit of unreasonable voltage drop is identified through power rail analysis (RA), and then the problem unit and / or power mesh area are processed. Then RA analysis needs to be performed again. After multiple iterations, the problem of voltage drop is solved.

[0004] However, the above method is executed after the PR stage, which may need to make large adjustments to the underlying routing resources laid out in the PR stage, and thus may cause a large impact on the timing. At the same time, the above method needs to be executed multiple times, resulting in low design efficiency. SUMMARY

[0005] The purpose of the present application is to solve the problem of low efficiency and impact on timing caused by solving the problem of voltage drop after the PR stage in the prior art, and to provide a chip layout and wiring method, device, computer equipment and readable storage medium.

[0006] To achieve the above purpose, the technical scheme adopted by the embodiments of the present application is as follows:

[0007] In a first aspect, the embodiments of the present application provide a chip layout and wiring method, comprising:

[0008] According to the preset voltage drop prevention unit attribute information, a plurality of units to be encrypted are determined, wherein the voltage drop prevention unit attribute information includes at least one of the following: the unit type is the main clock gating, the fan-out of the unit is greater than the preset fan-out value, and the drive of the unit is greater than the preset drive value;

[0009] The positions of the units to be encrypted are determined respectively;

[0010] According to the positions of the plurality of units to be encrypted, the underlying Powermesh of the plurality of units to be encrypted is encrypted to obtain the encrypted positions of the plurality of units to be encrypted.

[0011] As a possible implementation, the method further comprises:

[0012] According to the positions of the plurality of units to be encrypted, the M1 layer Powermesh of the plurality of units to be encrypted is encrypted to obtain the encrypted positions of the plurality of units to be encrypted.

[0013] As a possible implementation, the method further comprises:

[0014] The signal line in the target region of the M1 layer is deleted.

[0015] Based on the preset encryption parameters, the M1 layer Powermesh at the positions of the plurality of units to be encrypted is encrypted to obtain the encrypted positions of the plurality of units to be encrypted in the target region.

[0016] As a possible implementation, the method further comprises:

[0017] According to the encrypted positions of the plurality of units to be encrypted, holes are added between the M1 layer and the adjacent layer of the M1 layer.

[0018] As a possible implementation, the method further comprises:

[0019] The movement attribute of each unit to be encrypted is adjusted to be non-movable.

[0020] As a possible implementation, the method further comprises:

[0021] A hard placement blocking region is added to the unit to be encrypted, the hard placement blocking region is centered on the encrypted position of the unit to be encrypted, and the area range of the hard placement blocking region is a preset range.

[0022] As a possible implementation manner, the determining the plurality of units to be encrypted according to the preset unit attribute information of preventing voltage drop comprises:

[0023] determining units in the chip belonging to the main clock gating, and taking each unit belonging to the main clock gating as one of the units to be encrypted;

[0024] determining units in the chip with a fan-out value greater than the preset fan-out value, and taking each unit with a fan-out value greater than the preset fan-out value as one of the units to be encrypted;

[0025] determining units in the chip with a drive value greater than the preset drive value, and taking each unit with a drive value greater than the preset drive value as one of the units to be encrypted.

[0026] In a second aspect, an embodiment of the present application provides a chip layout and wiring device, comprising:

[0027] a first determining module configured to determine a plurality of units to be encrypted according to preset unit attribute information of preventing voltage drop, wherein the unit attribute information of preventing voltage drop comprises at least one of the following: a unit type is a main clock gating, a fan-out of a unit is greater than a preset fan-out value, and a drive of a unit is greater than a preset drive value;

[0028] a second determining module configured to determine a position of each of the units to be encrypted;

[0029] an encryption module configured to perform encryption processing on a bottom layer power network Powermesh of the plurality of units to be encrypted according to the position of each of the units to be encrypted, to obtain an encrypted position of each of the units to be encrypted.

[0030] As a possible implementation manner, the encryption module is specifically configured to:

[0031] perform encryption processing on an M1 layer Powermesh of the plurality of units to be encrypted according to the position of each of the units to be encrypted, to obtain the encrypted position of each of the units to be encrypted.

[0032] As a possible implementation manner, the encryption module is specifically configured to:

[0033] delete a signal line in a target region of the M1 layer;

[0034] perform encryption on the M1 layer Powermesh at the position of each of the units to be encrypted based on preset encryption parameters, to obtain the encrypted position of each of the units to be encrypted in the target region.

[0035] As a possible implementation manner, the encryption module is further configured to:

[0036] According to the encrypted positions of the units to be encrypted, holes are added between the M1 layer and the adjacent layer of the M1 layer.

[0037] As a possible implementation, the encryption module is further configured to:

[0038] Adjust the movement attribute of each unit to be encrypted to be non-movable.

[0039] As a possible implementation, the encryption module is further configured to:

[0040] Add a hard placement blocking area to the unit to be encrypted, the hard placement blocking area is centered at the encrypted position of the unit to be encrypted, and the area range of the hard placement blocking area is a preset range.

[0041] As a possible implementation, the first determination module is specifically configured to:

[0042] Determine the units in the chip that belong to the main clock gating, and each unit that belongs to the main clock gating is regarded as one unit to be encrypted;

[0043] Determine the units in the chip whose fan-out value is greater than the preset fan-out value, and each unit whose fan-out value is greater than the preset fan-out value is regarded as one unit to be encrypted;

[0044] Determine the units in the chip whose drive value is greater than the preset drive value, and each unit whose drive value is greater than the preset drive value is regarded as one unit to be encrypted.

[0045] In a third aspect, an embodiment of the present application provides a computer device, including a processor and a memory, the memory stores machine readable instructions executable by the processor, when the computer device is running, the processor executes the machine readable instructions to perform the steps of the layout and routing method of the chip in the first aspect.

[0046] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, when the computer program is run by a processor, the steps of the layout and routing of the chip in the first aspect are executed.

[0047] The chip layout and routing method, device, computer device and readable storage medium provided by the embodiments of the present application can, in the chip layout and routing stage, determine a plurality of to-be-encrypted units meeting the preset voltage drop prevention unit attribute information, and encrypt the bottom layer Powermesh of the plurality of to-be-encrypted units according to the positions of the to-be-encrypted units after determining the positions of the to-be-encrypted units. The to-be-encrypted units are determined by using the voltage drop prevention unit attribute information, which can ensure the accuracy of the determined to-be-encrypted units. Meanwhile, the bottom layer Powermesh is encrypted according to the positions of the to-be-encrypted units, which can ensure that the unit Powermesh coverage is improved after encryption without affecting other routing in the chip. In addition, the to-be-encrypted units are identified and encrypted in the chip layout and routing stage, which can solve the voltage drop problem in advance and avoid the problems of affecting timing and low efficiency caused by solving the voltage drop problem after the layout and routing stage. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0049] Figure 1 The flowchart of the chip layout and routing method provided by the embodiments of the present application is shown in FIG. 1.

[0050] Figure 2 Another flowchart of the chip layout and routing method provided by the embodiments of the present application is shown in FIG. 2.

[0051] Figure 3 The position diagram of the plurality of to-be-encrypted units on the chip is shown in FIG. 3.

[0052] Figure 4 Another flowchart of the chip layout and routing method provided by the embodiments of the present application is shown in FIG. 4.

[0053] Figure 5 The module structure diagram of the chip layout and routing device provided by the embodiments of the present application is shown in FIG. 5.

[0054] Figure 6 The structure diagram of the computer device 60 provided by the embodiments of the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0055] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowcharts used in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowcharts or one or more operations can be removed from the flowcharts under the guidance of the content of the present application.

[0056] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0057] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0058] Currently, the problem of voltage drop is mainly solved after the PR stage. However, due to the process characteristics, the more bottom layer metal, the greater the resistance, and the power line is also the same, so the proportion of voltage drop of the bottom layer power mesh is higher. After the PR stage, most of the bottom layer routing resources are occupied by signal lines and the like, and if the problem of voltage drop is solved at this stage, the original position of the signal line needs to be deleted, and the power line needs to be strengthened. This way needs to make a large adjustment to the bottom layer routing resources laid out in the PR stage, so it may cause a large impact on the timing. At the same time, this method needs to be executed multiple times to effectively solve the problem of voltage drop, resulting in low design efficiency.

[0059] Based on the above problems, the embodiments of the present application propose a chip layout and routing method, which screens units that need to prevent voltage drop in the layout and routing stage of the chip, and encrypts according to the positions of these units, so that the problem of voltage drop can be solved in advance, avoiding the problems of affecting timing and low efficiency caused by solving the problem of voltage drop after the layout and routing stage.

[0060] The embodiments of the present application can be applied to a chip layout and routing scene. The layout and routing of a chip is an important part of a chip design process. In the layout and routing stage of a chip, the placement positions of units in the chip and the routing manner of the connections between the units can be determined. Specifically, the present application can be implemented after clock tree synthesis (CTS) and before routing. Alternatively, the technical solutions of the embodiments of the present application can be implemented in combination with an existing layout and routing scheme. For example, an initial layout and routing result can be obtained by using the existing layout and routing scheme after CTS and before routing, and then the encryption of units is performed based on the initial layout and routing result by using the technical solutions of the embodiments of the present application to solve the voltage drop problem.

[0061] In the following, the chip layout and routing method of the present application is described in detail through multiple embodiments.

[0062] Figure 1 A flowchart of the chip layout and routing method provided by the embodiments of the present application is shown in the figure. The execution subject of the method can be any computer device with computing processing capability. As shown in the figure, the method comprises the following steps. Figure 1

[0063] S101, determining a plurality of units to be encrypted according to preset voltage drop prevention unit attribute information. The voltage drop prevention unit attribute information comprises at least one of the following: the unit type is a master clock gate, the fan-out of the unit is greater than a preset fan-out value, and the drive of the unit is greater than a preset drive value.

[0064] In the layout and routing stage of a chip, a plurality of units to be encrypted can be determined according to the voltage drop prevention unit attribute information.

[0065] ​Optionally, the above preventive voltage drop cell attribute information can be obtained in advance according to the characteristics of the cells that affect the voltage drop. For example, the master clock gating type cell is in the always-on state in actual operation, has a high flip rate, and has a large dynamic voltage drop, and thus the master clock gating type cell can be taken as an encryption object. Thus, the attribute of "cell type is master clock gating" can be taken as a preventive voltage drop cell attribute information, and when a cell satisfies the attribute, the cell can be taken as a to-be-encrypted cell. In this way, each master clock gating type cell in the chip can be taken as a to-be-encrypted cell. For another example, when the fan-out of a cell is greater, the load is greater, and the voltage drop is greater, and thus the attribute of "fan-out of cell is greater than a preset fan-out value" can be taken as a preventive voltage drop cell attribute information, and when a cell satisfies the attribute, the cell can be taken as a to-be-encrypted cell. For another example, when the drive of a cell is greater, the power consumption of the cell is greater, the leakage current is greater, and the static voltage drop is greater, and thus the attribute of "drive of cell is greater than a preset drive value" can be taken as a preventive voltage drop cell attribute information, and when a cell satisfies the attribute, the cell can be taken as a to-be-encrypted cell.

[0066] Optionally, on the basis of obtaining the above preventive voltage drop cell attribute information, each cell of the chip can be traversed, and if a cell that is traversed satisfies any one of the above preventive voltage drop cell attribute information, the cell can be taken as a to-be-encrypted cell. After the traversal is completed, each to-be-encrypted cell in the chip can be obtained.

[0067] S102, respectively determine the positions of each to-be-encrypted cell.

[0068] Optionally, the position of the to-be-encrypted cell can refer to the position coordinates of the to-be-encrypted cell in the chip.

[0069] As an example, the position coordinates of the to-be-encrypted cell in the chip can be obtained by calling the innovus command as follows.

[0070] dbGet[dbGet top.insts.name $list-p].box

[0071] wherein, $list is a list composed of each to-be-encrypted cell.

[0072] S103, according to the positions of each to-be-encrypted cell, encrypt the bottom Powermesh of the plurality of to-be-encrypted cells to obtain the encrypted positions of each to-be-encrypted cell.

[0073] Optionally, based on the positions of the units to be encrypted, the underlying Powermesh of each unit to be encrypted can be encrypted to increase the coverage of the underlying Powermesh of each unit to be encrypted. For example, there are three units to be encrypted in a chip, namely unit A, unit B and unit C. Assuming that the underlying powermesh coverage of unit A, unit B and unit C is M before encryption, after encryption, the underlying powermesh coverage of unit A, unit B and unit C will be greater than M, so that the power resistance of unit A, unit B and unit C is reduced, thereby preventing IR_drop. At the same time, before encrypting the units to be encrypted, the signal lines in the area where the units to be encrypted are located can be cleaned to ensure that there is enough space for the units to be encrypted to encrypt the underlying Powermesh.

[0074] In this embodiment, during the layout and routing stage of the chip, according to the preset voltage drop prevention unit attribute information, a plurality of units to be encrypted satisfying the attribute information can be determined, and after the positions of the units to be encrypted are determined, the underlying Powermesh of the plurality of units to be encrypted can be encrypted according to the positions of the units to be encrypted. Determining the units to be encrypted by using the voltage drop prevention unit attribute information can ensure the accuracy of the determined units to be encrypted, and encrypting the underlying Powermesh according to the positions of the units to be encrypted can ensure that the unit Powermesh coverage is improved after encryption without affecting other routing in the chip. In addition, by identifying the units to be encrypted and encrypting the units to be encrypted during the layout and routing stage of the chip, the voltage drop problem can be solved in advance, and the problems of affecting timing and low efficiency that occur when the voltage drop problem is solved after the layout and routing stage can be avoided.

[0075] As an optional implementation, in the step S103, the encryption can be performed only on M1.

[0076] Specifically, the M1 layer Powermesh of the plurality of units to be encrypted can be encrypted according to the positions of the units to be encrypted to obtain the positions of the units to be encrypted after encryption.

[0077] Optionally, among the chip layers, layer M0 is the internal routing layer of the cell, and there is no extra routing space in this layer. Therefore, encryption is not performed on layer M0 in this embodiment. Layer M2 has a horizontal global layout and is parallel to the power supply of layer M0 of the cell itself. If encryption is continued, it will affect the routing of signal lines. Therefore, encryption is not performed on layer M2 in this embodiment. In addition, the upper layer power supply resistance of the chip is small, and the voltage drop ratio is low. The difference in voltage drop between encryption and encryption is small. Therefore, this embodiment performs M1 layer Powermesh encryption on multiple cells to be encrypted, which can ensure that the cell density is increased after encryption without affecting other wiring in the chip.

[0078] Optionally, when performing M1 layer Powermesh encryption on multiple units to be encrypted based on the location of each unit to be encrypted, the process can be executed as follows.

[0079] Figure 2 Another schematic diagram of the chip placement and routing method provided in the embodiments of this application is shown below. Figure 2 As shown, the process of performing M1 layer Powermesh encryption on multiple units to be encrypted based on the position of each unit includes:

[0080] S201. Delete the signal lines in the target area of ​​layer M1.

[0081] Optionally, the target area mentioned above may refer to the area on the chip where the aforementioned multiple units to be encrypted are located. For example, Figure 3 This is a schematic diagram showing the locations of multiple units to be encrypted on the chip, such as... Figure 3 In the example, if there are three units to be encrypted on the chip, namely unit A, unit B, and unit C, then the target region is the area encompassing the outermost boundaries of units A, B, and C. For example, the target region could be... Figure 3 The area enclosed by the dashed line. In practice, the target area can be the region formed along the outermost boundary of multiple units to be encrypted, or it can be a rectangle that includes all multiple units to be encrypted, which can be flexibly selected according to actual needs.

[0082] Optionally, after deleting the signal line in the target area, the signal line can be restored by winding it around outside the target area, thereby avoiding any impact on functionality and timing.

[0083] S202. Based on preset encryption parameters, encrypt the M1 layer Powermesh at the location of each unit to be encrypted to obtain the encrypted location of each unit in the target area.

[0084] Optionally, the M1 layer Powermesh encryption of the region of each unit to be encrypted can be performed by calling the innovus command for encrypting Powermesh. Specifically, the preset encryption parameters and the position of the unit to be encrypted are taken as the input parameters of the innovus command, and the innovus command is called, so that the M1 layer Powermesh encryption of the unit to be encrypted is implemented, and the position of the unit to be encrypted in the target region after encryption is obtained.

[0085] In the implementation process, the innovus command for encrypting Powermesh can be called for each unit to be encrypted.

[0086] Optionally, the encryption parameters can include, for example, the adjusted width, the adjusted distance, and the adjusted direction, etc. Different encryption parameters can be generated in advance for different types of units to be encrypted, or the same encryption parameters can be used for different types of units to be encrypted.

[0087] The following is an example of the innovus command for encrypting Powermesh.

[0088] addStripe-layer M1-width 0.02

[0089] -spacing 0.001-set_to_set_distance 0.1

[0090] -direction vertical-nets{VSS VDD}

[0091] -area“x1 y1 x2 y2”

[0092] In the above example, the parameters after -area are the position of the unit to be encrypted, specifically the position coordinates of the unit to be encrypted on the chip, and the remaining parameters are the encryption parameters described above. By taking the encryption parameters and the position of the unit to be encrypted as the input parameters of the innovus command and calling the innovus command, the Powermesh of the unit to be encrypted can be encrypted in the manner indicated by the encryption parameters.

[0093] As an optional implementation, after the plurality of units to be encrypted are encrypted in the M1 layer, the method further includes:

[0094] According to the position of each unit to be encrypted after encryption, a hole is added between the M1 layer and the adjacent layer of the M1 layer.

[0095] Optionally, the adjacent layer of the M1 layer includes the M0 layer and the M2 layer.

[0096] Optionally, after obtaining the encrypted position of the unit to be encrypted, if the position of the unit to be encrypted changes, holes can be added between layers M1 and M0, and between layers M1 and M2, based on the encrypted position of the unit to be encrypted. For example, holes can be drilled from the center coordinate point of the unit to be encrypted into layers M0 and M2.

[0097] In this embodiment, after encrypting the Powermesh of the cell region to be encrypted, adding holes between adjacent layers of M1 can ensure the effectiveness of solving the voltage drop problem.

[0098] As an optional implementation, after encrypting the multiple units to be encrypted as described above, the following process can be performed to further ensure the effectiveness of solving the voltage drop problem.

[0099] Optionally, the movement attribute of each unit to be encrypted can be adjusted to be immovable.

[0100] For example, the movement attribute of the unit to be encrypted can be adjusted to non-movable by calling the following innovus command.

[0101] dbSet selected.pStatus fixed

[0102] After setting the movement attribute of the cell to be encrypted to immovable, its position will not change during subsequent placement and routing. Since the encrypted position is the expected location that can solve the voltage drop problem, setting the movement attribute of the cell to immovable avoids re-adjusting its position during subsequent placement and routing, thus ensuring that the voltage drop effect is not affected.

[0103] Optionally, after adjusting the movement attribute of each unit to be encrypted to be immovable, the following processing procedure can be performed to further ensure the effectiveness of solving the voltage drop problem.

[0104] Optionally, a hardplacement blockage area can be added to the unit to be encrypted. The hardplacement blockage area is centered on the encrypted position of the unit to be encrypted, and the area of ​​the hardplacement blockage area is a preset range.

[0105] Optionally, the purpose of a hard-place blocking region is to prevent the placement of any cells other than the cell to be encrypted within this region. Therefore, by adding a hard-place blocking region to the cell to be encrypted, the cells surrounding it can be forcibly dispersed. After dispersion, the number of cells at the cell to be encrypted decreases, and the current decreases accordingly, thereby further addressing the voltage drop issue.

[0106] It is worth mentioning that in the implementation process, the preset range can be a smaller range such as 5um x 5um, so that the problem of voltage drop can be solved without affecting the cells to be dispersed.

[0107] The following describes an optional manner of determining the plurality of to-be-encrypted cells according to the preset prevention voltage drop cell attribute information in the foregoing step S101.

[0108] Figure 4 Another flowchart of the chip layout and routing method provided by the embodiment of the present application is shown in FIG. 4. Figure 4 As shown in FIG. 4, the step S101 can include:

[0109] S401, determining the cells belonging to the main clock gating in the chip, and taking each of the cells belonging to the main clock gating as a to-be-encrypted cell.

[0110] For example, the cells belonging to the main clock gating in the chip can be captured by calling the innovus command as follows.

[0111] filter_collection[get_cell[all_fanou-fromcoreclk-flat-only_cells-levels 6]]“is_clock_gating_check==true”

[0112] After calling the innovus command, the command can return the cells belonging to the main clock gating in the chip, and then each of the cells belonging to the main clock gating can be taken as a to-be-encrypted cell.

[0113] S402, determining the cells with a fanout value greater than the preset fanout value in the chip, and taking each of the cells with a fanout value greater than the preset fanout value as a to-be-encrypted cell.

[0114] For example, the fanout values of the cells in the chip can be obtained by calling the innovus command as follows.

[0115] sizeof_collection[all_fanout-from xxx / Z-only_cells-flat]

[0116] After obtaining the fanout values of the cells, the fanout values of the cells are respectively judged, and if the fanout value of a cell is greater than the preset fanout value, the cell is taken as a to-be-encrypted cell.

[0117] As an example, the preset fanout value can be 24.

[0118] S403, determining the unit in the chip whose drive value is greater than the preset drive value, and regarding each unit whose drive value is greater than the preset drive value as a to-be-encrypted unit.

[0119] As an example, the unit in the chip whose drive value is greater than the preset drive value can be captured by calling an innovus command as follows.

[0120] dbGet[dbGet top.inst.cell.name*V20*-p2].name

[0121] As an example, the preset drive value can be 16.

[0122] It should be noted that the execution order of the steps S401-S403 can not be in sequence, and can be independently executed.

[0123] Based on the same inventive concept, the chip layout and wiring method in the embodiments of the present application also provides a chip layout and wiring device corresponding to the chip layout and wiring method. Since the principle of solving problems in the device in the embodiments of the present application is similar to the above-mentioned chip layout and wiring method, the implementation of the device can be referred to the implementation of the method, and the repeated parts will not be described here.

[0124] Figure 5 The module structure diagram of the chip layout and wiring device provided in the embodiments of the present application is shown in Figure 5 The device comprises:

[0125] A first determining module 501 is configured to determine a plurality of to-be-encrypted units according to preset voltage drop prevention unit attribute information, wherein the voltage drop prevention unit attribute information comprises at least one of the following: a unit type is a master clock gate, a fanout of a unit is greater than a preset fanout value, and a drive of the unit is greater than a preset drive value.

[0126] A second determining module 502 is configured to determine a position of each to-be-encrypted unit.

[0127] An encryption module 503 is configured to perform encryption processing on a bottom Powermesh of the plurality of to-be-encrypted units according to the position of each to-be-encrypted unit, to obtain an encrypted position of each to-be-encrypted unit.

[0128] As an optional implementation, the encryption module 503 is specifically configured to:

[0129] perform encryption processing on an M1 layer Powermesh of the plurality of to-be-encrypted units according to the position of each to-be-encrypted unit, to obtain the encrypted position of each to-be-encrypted unit.

[0130] As an optional implementation, the encryption module 503 is specifically configured to:

[0131] deleting the signal line in the target region of the M1 layer.

[0132] encrypting the M1 layer Powermesh at the position of each of the to-be-encrypted units based on the preset encryption parameter, to obtain an encrypted position of each of the to-be-encrypted units in the target region.

[0133] As an optional implementation, the encryption module 503 is further configured to:

[0134] adding a hole between the M1 layer and an adjacent layer of the M1 layer according to the encrypted position of each of the to-be-encrypted units.

[0135] As an optional implementation, the encryption module 503 is further configured to:

[0136] adjusting a mobile attribute of each of the to-be-encrypted units to be non-movable.

[0137] As an optional implementation, the encryption module 503 is further configured to:

[0138] adding a hard placement blocking region to each of the to-be-encrypted units, the hard placement blocking region being centered at the encrypted position of each of the to-be-encrypted units, and a region range of the hard placement blocking region being a preset range.

[0139] As an optional implementation, the first determination module 501 is specifically configured to:

[0140] determining units in the chip that belong to the main clock gating, and taking each of the units that belong to the main clock gating as one of the to-be-encrypted units.

[0141] determining units in the chip that have a fan-out value greater than the preset fan-out value, and taking each of the units that have a fan-out value greater than the preset fan-out value as one of the to-be-encrypted units.

[0142] determining units in the chip that have a drive value greater than the preset drive value, and taking each of the units that have a drive value greater than the preset drive value as one of the to-be-encrypted units.

[0143] The embodiment of the present application further provides a computer device 60, as shown in Figure 6 FIG. 6 is a structural schematic diagram of the computer device 60 provided by the embodiment of the present application, which comprises a processor 61, a memory 62, and a bus 63. The memory 62 stores machine readable instructions (for example, a computer program) executable by the processor 61. Figure 5The first determining module 501, the second determining module 502 and the encryption module 503 in the device in the foregoing embodiments can be implemented by using a computer device 60. The computer device 60 includes a processor 61 and a memory 62. The memory 62 stores machine readable instructions. The processor 61 is configured to execute the machine readable instructions. The machine readable instructions include instructions for implementing the first determining module 501, the second determining module 502 and the encryption module 503. When the computer device 60 is running, the processor 61 communicates with the memory 62 through a bus 63. The machine readable instructions are executed by the processor 61 to perform the method steps in the foregoing method embodiments.

[0144] The computer readable storage medium stores a computer program. The computer program is run by a processor to perform the steps of the module layout method of the chip.

[0145] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiments, which will not be described herein. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented by other means. The device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. In actual implementation, another division mode can be used. For example, a plurality of modules or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed elements can be indirect coupling or communication connection through some communication interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0146] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0147] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A chip layout and routing method, characterized in that, include: Based on the preset voltage drop prevention unit attribute information, multiple units to be encrypted are determined, wherein the voltage drop prevention unit attribute information includes at least one of the following: the unit type is master clock gating, the unit's fan-out is greater than a preset fan-out value, and the unit's drive is greater than a preset drive value. The position of each of the units to be encrypted is determined respectively; Based on the location of each unit to be encrypted, the underlying power network Powermesh of the plurality of units to be encrypted is encrypted to obtain the encrypted location of each unit to be encrypted. The step of encrypting the underlying power mesh of the plurality of units to be encrypted according to their positions, to obtain the encrypted positions of the units to be encrypted, includes: Based on the position of each unit to be encrypted, the M1 layer power network of the multiple units to be encrypted is encrypted to obtain the encrypted position of each unit.

2. The method according to claim 1, characterized in that, The step of encrypting the plurality of units to be encrypted using the M1 layer power network based on the position of each unit to be encrypted, to obtain the encrypted position of each unit to be encrypted, includes: Delete the signal lines in the target area of ​​layer M1; Based on preset encryption parameters, the M1 layer power network at the location of each unit to be encrypted is encrypted to obtain the encrypted location of each unit in the target area.

3. The method according to claim 1, characterized in that, After performing M1 layer power network encryption on the plurality of units to be encrypted according to their positions to obtain the encrypted positions of each unit to be encrypted, the method further includes: Based on the encrypted position of each of the units to be encrypted, holes are added between adjacent layers of layer M1.

4. The method according to claim 1, characterized in that, After encrypting the underlying powermesh of the plurality of units to be encrypted according to their positions to obtain the encrypted positions of the units to be encrypted, the method further includes: The movement attribute of each of the units to be encrypted is adjusted to be immovable.

5. The method according to claim 4, characterized in that, The method further includes: A hard-place blocking region is added to the unit to be encrypted. The hard-place blocking region is centered on the encrypted position of the unit to be encrypted, and the area of ​​the hard-place blocking region is a preset range.

6. The method according to any one of claims 1-5, characterized in that, The step involves determining multiple units to be encrypted based on preset voltage drop prevention unit attribute information, including: Identify the units in the chip that belong to the master clock gating, and treat each unit belonging to the master clock gating as a unit to be encrypted; Identify the units in the chip whose fan-out value is greater than the preset fan-out value, and assign each unit whose fan-out value is greater than the preset fan-out value as a unit to be encrypted; The units in the chip whose driving values ​​are greater than the preset driving value are identified, and each unit whose driving value is greater than the preset driving value is taken as a unit to be encrypted.

7. A chip layout and wiring apparatus, characterized in that, include: The first determining module is used to determine multiple units to be encrypted based on preset voltage drop prevention unit attribute information, wherein the voltage drop prevention unit attribute information includes at least one of the following: the unit type is master clock gating, the unit's fan-out is greater than a preset fan-out value, and the unit's drive is greater than a preset drive value. The second determining module is used to determine the position of each of the units to be encrypted; An encryption module is used to encrypt the underlying power network Powermesh of the plurality of units to be encrypted according to the position of each unit to be encrypted, so as to obtain the encrypted position of each unit to be encrypted. The encryption module is specifically used for: Based on the position of each unit to be encrypted, the multiple units to be encrypted are subjected to M1 layer Powermesh encryption processing to obtain the encrypted position of each unit to be encrypted.

8. A computer device, characterized in that, include: A processor and a memory, the memory storing machine-readable instructions executable by the processor, which, when the computer device is running, are executed by the processor to perform the steps of the chip placement and routing method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the chip placement and routing method as described in any one of claims 1 to 6.

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