Convolution accelerator, convolution processing method, chip and electronic device

Abstract

The disclosure provides a convolution accelerator, a convolution processing method, a chip and an electronic device. The convolution accelerator with parallelism M includes: P convolution kernel operation modules; M latch groups, each latch group including N latches, each latch including a plurality of latch units; P read address decoding circuit groups, each read address decoding circuit group corresponding to one convolution kernel operation module; each latch unit is configured to store weight data; the P read address decoding circuit groups are respectively configured to obtain the weight data from the latch units and send the weight data to the corresponding convolution kernel operation modules; and the P convolution kernel operation modules are respectively configured to obtain graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit groups. The weight data is stored in the latch, which reduces the difficulty of layout and wiring of the back end, and the power consumption of reading the latch is much lower than that of reading the SRAM, thereby reducing the power consumption of the convolution processing process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a convolution accelerator, a convolution processing method, a chip and an electronic device. BACKGROUND

[0002] Convolution neural networks have great potential in artificial intelligence applications. When applying such algorithms, great computational processing requirements need to be overcome, which requires the convolution accelerator performing convolution operations to have high parallelism. The weight data supply in a high-parallelism convolution accelerator requires a large bit width.

[0003] In a convolution accelerator of the related art, a weight buffer for weight data supply is usually implemented using SRAM (Static Random Access Memory). In order to implement a large bit width supply, multiple SRAMs need to be spliced, which will result in great difficulty in back-end layout and routing, and great power consumption in reading the SRAM, causing the power consumption of the convolution processing process to be relatively large. SUMMARY

[0004] The present disclosure aims to at least partially solve one of the technical problems in the related art.

[0005] The present disclosure proposes a convolution accelerator to solve the problem of great difficulty in back-end layout and routing of the convolution accelerator in the related art, and the problem of relatively large power consumption of the convolution processing process.

[0006] According to a first aspect of the present disclosure, a convolution accelerator is provided, the parallelism of the convolution accelerator being M, the convolution accelerator comprising: P convolution kernel operation modules; M latch groups, each of the latch groups comprising N latches, each of the latches comprising a plurality of latch units; P read address decoding circuit groups, each of the read address decoding circuit groups corresponding to one of the convolution kernel operation modules; M, N and P being integers greater than or equal to 1; wherein: each of the latch units is configured to store weight data; the P read address decoding circuit groups are respectively configured to obtain the weight data from each of the latch units and send the weight data to the corresponding convolution kernel operation module; and the P convolution kernel operation modules are respectively configured to obtain graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit group.

[0007] As a first possible embodiment of this disclosure, each read address decoding circuit group includes M*N read address decoding circuits, and each read address decoding circuit in each read address decoding circuit group corresponds to one latch; each read address decoding circuit is used to obtain the weight data from the latch unit included in the corresponding latch, and send the obtained weight data to the corresponding convolution kernel operation module.

[0008] As a second possible embodiment of this disclosure, each convolution kernel operation module includes a read address register and a read data register; the read address register of each convolution kernel operation module is used to send a read address to the read address decoding circuit of the corresponding read address decoding circuit group; each read address decoding circuit is specifically used to decode the acquired read address to obtain a decoding result, determine a target latch unit from each latch unit of the corresponding latch according to the decoding result, read the weight data in the target latch unit, and send the read weight data to the read data register of the corresponding convolution kernel operation module; the read data register of each convolution kernel operation module is used to store the weight data sent by the read address decoding circuit of the corresponding read address decoding circuit group.

[0009] As a third possible embodiment of this disclosure, the path between each latch unit in the latch corresponding to the read address decoding circuit and the read data register in the corresponding convolution kernel operation module is a path of Q clock cycles, where Q is an integer greater than 1; the P groups of read address decoding circuits are respectively used to obtain the weight data from each latch unit after loading each latch for at least Q+1 clock cycles.

[0010] As a fourth possible scenario in this disclosure, when P is an integer greater than 1, the graph data obtained by different convolution kernel operation modules are different sub-feature maps after the same feature map is divided into multiple sub-feature maps.

[0011] According to a second aspect of the present disclosure, a convolution processing method is provided, applied to a convolution accelerator with a parallelism of M. The convolution accelerator includes: P convolution kernel operation modules; M latch groups, each latch group including N latches, each latch including multiple latch units; and P read address decoding circuit groups, each read address decoding circuit group corresponding to one of the convolution kernel operation modules; M, N, and P are integers greater than or equal to 1. The method includes: using the P read address decoding circuit groups to obtain stored weight data from each of the latch units respectively, and sending the weight data to the corresponding convolution kernel operation module; using the P convolution kernel operation modules to obtain graph data respectively, and performing operations on the graph data and the weight data sent by the corresponding read address decoding circuit groups.

[0012] As a first possible embodiment of this disclosure, each read address decoding circuit group includes M*N read address decoding circuits, and each read address decoding circuit in each read address decoding circuit group corresponds to one latch; the step of using P read address decoding circuit groups to obtain the stored weight data from each latch unit includes: using each read address decoding circuit to obtain the weight data from the latch unit included in the corresponding latch.

[0013] As a second possible embodiment of this disclosure, each convolution kernel operation module includes a read address register and a read data register; the step of obtaining the weight data from the latch unit included in the corresponding latch using each read address decoding circuit includes: decoding the read address sent by the read address register included in the corresponding convolution kernel operation module using each read address decoding circuit to obtain a decoding result, and determining a target latch unit from each latch unit included in the corresponding latch based on the decoding result, and reading the weight data in the target latch unit; after obtaining the weight data from the latch unit included in the corresponding latch using each read address decoding circuit, the step further includes: sending the read weight data to the read data register included in the corresponding convolution kernel operation module using each read address decoding circuit, so that the read data register stores the weight data.

[0014] As a third possible embodiment of this disclosure, the path between each latch unit in the latch corresponding to each read address decoding circuit and the read data register in the corresponding convolution kernel operation module is a path of Q clock cycles, where Q is an integer greater than 1; the step of using P groups of read address decoding circuits to obtain the stored weight data from each latch unit includes: using P groups of read address decoding circuits to obtain the weight data from each latch unit after loading each latch for at least Q+1 clock cycles.

[0015] As a fourth possible embodiment of this disclosure, P is an integer greater than 1, and the step of using P convolution kernel operation modules to obtain graph data includes: using different convolution kernel operation modules to obtain different sub-feature maps obtained after dividing the same feature map into multiple sub-feature maps.

[0016] According to a third aspect of this disclosure, a chip is provided that includes the convolution accelerator proposed in the embodiments of the first aspect of this disclosure.

[0017] According to a fourth aspect of this disclosure, an electronic device is provided, including the convolution accelerator proposed in the embodiments of the first aspect of this disclosure.

[0018] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 This is a schematic diagram of the structure of a convolution accelerator according to an exemplary embodiment;

[0021] Figure 2 This is a schematic diagram of the structure of a convolution accelerator according to another exemplary embodiment;

[0022] Figure 3 This is a schematic diagram illustrating a read latch process in a convolution accelerator according to another exemplary embodiment;

[0023] Figure 4 This is a flowchart illustrating a convolution processing method according to an exemplary embodiment;

[0024] Figure 5 This is a block diagram of a chip according to an exemplary embodiment;

[0025] Figure 6This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0026] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0027] In convolution accelerators of related technologies, the weight buffer used to supply weight data is usually implemented using SRAM. In order to achieve a large bit width of data supply, multiple SRAMs need to be spliced ​​together, which makes the back-end layout and routing difficult and the power consumption of reading SRAM is large, resulting in high power consumption in the convolution process.

[0028] To address the aforementioned problems, this disclosure proposes a convolution accelerator, a convolution acceleration method, a chip, and an electronic device. The convolution accelerator has a parallelism of M and includes: P convolution kernel operation modules; M latch groups, each latch group including N latches, and each latch including multiple latch units; and P read address decoding circuit groups, each read address decoding circuit group corresponding to one convolution kernel operation module. M, N, and P are integers greater than or equal to 1. Each latch unit is used to store weight data; the P read address decoding circuit groups are used to retrieve weight data from each latch unit and send the weight data to the corresponding convolution kernel operation module; and the P convolution kernel operation modules are used to retrieve graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit groups. Therefore, by using latches to implement the weight buffers used to supply weight data in the convolution accelerator, i.e., using latches to store weight data, the difficulty of back-end layout and routing is reduced, and the power consumption of reading the latches is much lower than that of reading SRAM, thereby reducing the power consumption of the convolution process.

[0029] The convolution accelerator, convolution processing method, chip, and electronic device provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the structure of a convolution accelerator according to an exemplary embodiment.

[0031] like Figure 1As shown, the convolution accelerator 100 includes: P convolution kernel operation modules 101; M latch groups 102, each latch group 102 including N latches, each latch including multiple latch units; and P read address decoding circuit groups 103, each read address decoding circuit group 103 corresponding to one convolution kernel operation module 101; M, N, and P are integers greater than or equal to 1. It should be noted that... Figure 1 The convolution accelerator 100 includes a convolution kernel operation module 101 with a number P of 2, a latch group 102 with a number M of 4, and each latch group 102 includes a latch with a number N of 4 (i.e., Figure 1 The following is an illustration of the number of latch0, latch1, latch2 and latch3, and the number of read address decoding circuit groups 103, P, is 2.

[0032] Each latch unit is used to store weight data;

[0033] The P read address decoding circuit groups 103 are used to obtain weight data from each latch unit and send the weight data to the corresponding convolution kernel operation module 101;

[0034] P convolution kernel operation modules 101 are used to acquire graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit group 103.

[0035] The number of latch groups 102 is the same as the parallelism of the convolution accelerator 100; that is, when the parallelism of the convolution accelerator 100 is M, the number of latch groups 102 is M. The number N of latches included in each latch group 102 can be arbitrarily set as needed, for example, according to the difficulty of the logic design of the convolution accelerator 100 and the needs of back-end layout and routing. This disclosure does not impose any restrictions on this. The number of latch units included in each latch can be set as needed, and this disclosure does not impose any restrictions on this.

[0036] The number of convolution kernel operation modules 101 can be set as needed, and this disclosure does not impose any limitation on it. When there is only one convolution kernel operation module 101, that module independently obtains weight data from each latch unit. When there are multiple convolution kernel operation modules 101, they share the weight data in each latch unit. When there are multiple convolution kernel operation modules 101, each module has the same structure, meaning that its operation units, processing units, etc., are identical.

[0037] The number of read address decoding circuit groups 103 is the same as the number of convolution kernel operation modules 101, with each read address decoding circuit group 103 corresponding to one convolution kernel operation module 101. Each read address decoding circuit group 103 can obtain weight data from each latch unit and send the weight data to the corresponding convolution kernel operation module 101. Each read address decoding circuit group 103 may include one or more read address decoding circuits.

[0038] The graph data can be image-related data such as pixels of each pixel in the image or the corresponding feature map, and this disclosure does not impose any restrictions on it. The graph data acquired by different convolution kernel operation modules 101 can be the same or different, and this disclosure does not impose any restrictions on it.

[0039] The weight buffer in the convolution accelerator 100 may include M latch groups 102 and P read address decoding circuit groups 103.

[0040] In the embodiments of this disclosure, all weight data required by the convolution kernel operation module 101 to perform convolution operations can be loaded into the latch units of each latch. Each latch unit stores a portion of the weight data, so that each read address decoding circuit group 103 can obtain all the weight data from each latch unit and send all the weight data to the corresponding convolution kernel operation module 101. Thus, each convolution kernel operation module 101 can perform operations on the obtained graph data and all the weight data sent by the corresponding read address decoding circuit group 103.

[0041] Therefore, the weight buffer used for feeding weight data in the convolution accelerator 100 can be implemented using latches. Since all storage cells of SRAM need to be tightly arranged during back-end placement and routing, the placement and routing of the back-end becomes quite difficult when a large bit width of data feeding is required. However, the latch cells of the latch can be distributed during back-end placement and routing. Therefore, using latches to store weight data provides a very large parallel data feeding bit width while reducing the difficulty of back-end placement and routing. Moreover, the power consumption of reading the latch is much lower than that of reading SRAM, thereby reducing the power consumption of the convolution processing.

[0042] In summary, the convolution accelerator with parallelism M provided in this embodiment includes: P convolution kernel operation modules; M latch groups, each latch group including N latches, each latch including multiple latch units; P read address decoding circuit groups, each read address decoding circuit group corresponding to one convolution kernel operation module; M, N, and P are integers greater than or equal to 1; wherein: each latch unit is used to store weight data; the P read address decoding circuit groups are respectively used to obtain weight data from each latch unit and send the weight data to the corresponding convolution kernel operation module; the P convolution kernel operation modules are respectively used to obtain graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit groups. Therefore, by using latches to implement the weight buffer for supplying weight data in the convolution accelerator, i.e., using latches to store weight data, the difficulty of backend layout and routing is reduced, and the power consumption of reading latches is much lower than that of reading SRAM, thereby reducing the power consumption of the convolution processing.

[0043] Furthermore, the weight buffers in related technologies employ a ping-pong prefetch structure, resulting in a large capacity for the weight buffers. Also, a single set of weight buffers composed of ping-pong prefetch structures corresponds to only a single convolutional kernel operation module. When multiple convolutional kernel operation modules collaborate to complete a convolutional layer, multiple sets of weight buffers are required, leading to a larger chip area. However, in the convolutional accelerator 100 provided in this disclosure, the weight buffers can also employ a ping-pong prefetch structure. When multiple convolutional kernel operation modules collaborate to complete a convolutional layer, since multiple convolutional kernel operation modules can share the weight data stored in the same weight buffer, and multiple read address decoding circuit groups can independently and collaboratively complete a convolutional layer, the number of weight buffers is reduced, thus reducing the chip area.

[0044] The following is combined Figure 2 The convolution accelerator provided in the embodiments of this disclosure will be further described.

[0045] Figure 2 This is a schematic diagram of the structure of a convolution accelerator according to another exemplary embodiment.

[0046] like Figure 2 As shown, in Figure 1 Based on the convolution accelerator 100 shown, each read address decoding circuit group 103 includes M*N read address decoding circuits. Figure 2 In the Read_mux), each read address decoding circuit group 103 includes a read address decoding circuit corresponding to a latch; each read address decoding circuit is used to obtain weight data from the latch unit included in the corresponding latch and send the obtained weight data to the corresponding convolution kernel operation module 101.

[0047] in,Figure 2 The convolution accelerator 100 includes 2 convolution kernel operation modules P, 4 latch groups 102, and 4 latches N in each latch group 102 (i.e., Figure 2 The following is an illustration of the number of latch0, latch1, latch2 and latch3, and the number of read address decoding circuit groups 103, P, is 2.

[0048] The read address decoding circuit is a data selector on the latch path.

[0049] In the embodiments of this disclosure, all weight data required by the convolution kernel operation module 101 to perform convolution operations can be loaded into the latch units of each latch. Each latch unit stores a portion of the weight data. Each read address decoding circuit corresponds to one latch. Each read address decoding circuit can obtain the weight data stored in the latch unit of the corresponding latch and send the obtained weight data to the corresponding convolution kernel operation module 101.

[0050] Further reference Figure 2 Each convolution kernel operation module 101 may include a read address register ( Figure 2 (not shown in the image) and read data register ( Figure 2 The number of read address registers and read data registers included in each convolution kernel operation module 101 can be set as needed, and this disclosure does not impose any restrictions on this. For example, the number of read address registers and read data registers included in each convolution kernel operation module 101 can be the same as the number of read address decoding circuits in the convolution accelerator 100, or the same as the number of latch groups 102 in the convolution accelerator 100. This disclosure embodiment illustrates the example where the number of read address registers and read data registers included in each convolution kernel operation module 101 is the same as the number of latch groups 102 in the convolution accelerator 100.

[0051] In the embodiments of this disclosure, each convolution kernel operation module 101 includes a read address register, which is used to send a read address to the read address decoding circuit included in the corresponding read address decoding circuit group 103; each read address decoding circuit is specifically used to decode the acquired read address to obtain a decoding result, and determine the target latch unit from each latch unit included in the corresponding latch according to the decoding result, and read the weight data in the target latch unit, and send the read weight data to the read data register included in the corresponding convolution kernel operation module 101; each convolution kernel operation module 101 includes a read data register, which is used to store the weight data sent by the read address decoding circuit included in the corresponding read address decoding circuit group 103.

[0052] The read address is used to read the weight data in the latch cell of the latch.

[0053] Among them, such as Figure 2 As shown, when the number of read address registers and read data registers included in each convolution kernel operation module 101 is the same as the number of latch groups 102 in the convolution accelerator 100, each read address register corresponds to N read address decoding circuits and one latch group 102, and each read data register corresponds to N read address decoding circuits and one latch group 102. Therefore, each read address register can send a read address to the corresponding N read address decoding circuits. Each read address decoding circuit can decode the obtained read address to obtain a decoding result, determine the target latch unit from the latch units included in the corresponding latch based on the decoding result, read the weight data in the target latch unit, and send the read weight data to the read data register corresponding to the read address decoding circuit included in the corresponding convolution kernel operation module 101.

[0054] The following is combined Figure 3 Taking a certain read address decoding circuit and a certain read data register and read address register included in the corresponding convolution kernel operation module 101 as examples, the process of reading weight data from the latch through the read address decoding circuit is explained. Figure 3 The latch includes 16 latching units (i.e. Figure 3 The following is an illustration using Cell0-Cell15 as an example.

[0055] refer to Figure 3 Within one clock cycle, read the address register ( Figure 3 The `Raddr_reg` in the code can be used to read the address decoding circuit ( Figure 3 The Read_mux module sends the read address corresponding to the latch unit to be read. The read address decoding circuit decodes the obtained read address to obtain the decoding result. Based on the decoding result, it determines the target latch unit from the latch units included in the corresponding latch, reads the weight data in the target latch unit, and sends the read weight data to the read data register (corresponding to the read address decoding circuit) included in the corresponding convolution kernel operation module 101. Figure 3 The data read register (Rdata_reg) can then store the weight data for the convolution kernel operation module 101 to perform convolution operations.

[0056] Understandably, before the convolution operation begins, a preloading process for the weight data occurs, loading all the weight data into the weight buffer. Therefore, each latch unit in the latch exhibits a write-before-read characteristic, and no write operation occurs during a read operation. Consequently, the input terminals of each latch unit in the latch to the read data register are essentially static.

[0057] In the embodiments of this disclosure, the path between each latch unit in the latch corresponding to the read address decoding circuit and the read data register in the corresponding convolution kernel operation module 101 can be set as a path of Q clock cycles, where Q is an integer greater than 1.

[0058] Accordingly, the first read weight buffer operation is only initiated after at least Q+1 clock cycles. That is, the P read address decoding circuit groups 103 are used to obtain weight data from each latch unit after loading each latch for at least Q+1 clock cycles.

[0059] This reduces timing pressure and is beneficial for backend layout and routing, as well as timing convergence.

[0060] In addition, in this embodiment of the present disclosure, when there are multiple convolution kernel operation modules 101, the graph data obtained by different convolution kernel operation modules 101 can be different sub-feature maps after the same feature map is divided into multiple sub-feature maps.

[0061] Accordingly, in this embodiment, after loading all weight data into the latches of the weight buffer, the operation processes of each convolution kernel operation module 101 can be started simultaneously. After loading the latches for at least Q+1 clock cycles, different convolution kernel operation modules 101 can obtain all weight data from the same weight buffer through their corresponding read address decoding circuit groups 103, and perform operations on different sub-feature maps and all weight data. Since different convolution kernel operation modules correspond to independent read address decoding circuit groups, different convolution kernel operation modules can obtain weight data corresponding to different addresses at the same time.

[0062] The weight data acquired by different convolution kernel operation modules 101 are stored in their own read data registers. The convolution kernel operation module 101 may also include a multiply-accumulate module. The multiply-accumulate module in different convolution kernel operation modules 101 can perform convolution operations based on different sub-feature maps and the weight data stored in its own read data register.

[0063] Based on the convolution accelerator provided in the above embodiments, this disclosure also provides a convolution processing method.

[0064] Figure 4This is a flowchart illustrating a convolution processing method according to an exemplary embodiment. It should be noted that this convolution processing method can be applied to a convolution accelerator. The convolution accelerator has a parallelism of M and includes: P convolution kernel operation modules; M latch groups, each latch group including N latches, and each latch including multiple latch units; P read address decoding circuit groups, each read address decoding circuit group corresponding to one convolution kernel operation module; M, N, and P are integers greater than or equal to 1.

[0065] like Figure 4 As shown, the convolution processing method includes the following steps:

[0066] Step 401: P read address decoding circuits are used to obtain the stored weight data from each latch unit and send the weight data to the corresponding convolution kernel operation module.

[0067] Step 402: P convolutional kernel operation modules are used to obtain graph data respectively, and the graph data and the weight data sent by the corresponding read address decoding circuit group are operated.

[0068] The specific implementation process and principle of steps 401-402 can be found in the descriptions of other embodiments, and will not be repeated here.

[0069] In one possible implementation, each read address decoding circuit group includes M*N read address decoding circuits, and each read address decoding circuit in each read address decoding circuit group corresponds to a latch. Accordingly, step 401, which uses P read address decoding circuit groups to obtain the stored weight data from each latch unit, may include:

[0070] Each read address decoding circuit is used to obtain weight data from the latching cells included in the corresponding latch.

[0071] As one possible implementation, each convolution kernel operation module may include a read address register and a read data register. Correspondingly, each read address decoding circuit retrieves weight data from the latch units included in the corresponding latch, which may include:

[0072] Each read address decoding circuit is used to decode the read address sent by the read address register of the corresponding convolution kernel operation module to obtain the decoding result. Based on the decoding result, the target latch unit is determined from each latch unit of the corresponding latch, and the weight data in the target latch unit is read.

[0073] Furthermore, after obtaining the weight data from the latching units included in the corresponding latches using each read address decoding circuit, it may also include:

[0074] Each read address decoding circuit is used to send the read weight data to the read data register included in the corresponding convolution kernel operation module, so that the read data register stores the weight data.

[0075] As one possible implementation, the path between each latch unit in the latch corresponding to each read address decoding circuit and the read data register in the corresponding convolution kernel operation module is a path of Q clock cycles, where Q is an integer greater than 1;

[0076] Accordingly, step 401, which uses P read address decoding circuits to retrieve the stored weight data from each latch unit, may include:

[0077] A group of P read address decoding circuits is used to obtain weight data from each latch cell after loading each latch for at least Q+1 clock cycles.

[0078] As one possible implementation, where P is an integer greater than 1, step 402, which uses P convolutional kernel modules to acquire graph data respectively, may include:

[0079] Different convolution kernel operation modules are used to obtain different sub-feature maps obtained after the same feature map is divided into multiple sub-feature maps.

[0080] In summary, the convolution processing method provided in this embodiment employs P read address decoding circuit groups to obtain stored weight data from each latch unit and sends the weight data to the corresponding convolution kernel operation module. P convolution kernel operation modules then obtain graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit groups. By implementing the weight buffer used for weight data supply in the convolution accelerator using a latch, i.e., using a latch to store the weight data, the difficulty of backend layout and routing is reduced. Furthermore, the power consumption of the read latch is much lower than that of reading SRAM, thereby reducing the power consumption of the convolution processing process.

[0081] Based on the above embodiments, this disclosure also proposes a chip.

[0082] like Figure 5 As shown, chip 500 includes the convolution accelerator 100 from the aforementioned embodiments.

[0083] The specific descriptions of the convolution accelerators in the foregoing embodiments also apply to the chips in the embodiments of this disclosure, and will not be repeated here.

[0084] The chip in this embodiment reduces the difficulty of back-end layout and routing by implementing the weight buffer used for weight data supply in the convolution accelerator of the chip using a latch. Moreover, the power consumption of reading the latch is much lower than that of reading SRAM, thereby reducing the power consumption of the convolution processing.

[0085] Based on the above embodiments, this disclosure also proposes an electronic device including the convolution accelerator in the foregoing embodiments.

[0086] like Figure 6 As shown, the electronic device 600 includes the convolution accelerator 100 from the aforementioned embodiments.

[0087] The specific descriptions of the convolution accelerators in the foregoing embodiments also apply to the electronic devices in the embodiments of this disclosure, and will not be repeated here.

[0088] The electronic device in this embodiment reduces the difficulty of back-end layout and routing by implementing the weight buffer for weight data supply in the convolution accelerator of the electronic device using a latch, and the power consumption of reading the latch is much lower than that of reading SRAM, thereby reducing the power consumption of the convolution processing.

[0089] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0090] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A convolution accelerator, comprising: The parallelism of the convolution accelerator is M, and the convolution accelerator comprises: P convolution kernel operation modules; M latch groups, each of which comprises N latches, each of which comprises a plurality of latch units; P read address decoding circuit groups, each of which corresponds to one of the convolution kernel operation modules; M, N, and P are integers greater than or equal to 1; wherein: Each of the latch units is configured to store weight data; P read address decoding circuit groups are respectively configured to obtain the weight data from each of the latch units and send the weight data to the corresponding convolution kernel operation module; P convolution kernel operation modules are respectively configured to obtain graph data and perform operations on the graph data and the weight data sent by the corresponding read address decoding circuit group; wherein each of the convolution kernel operation modules comprises a read address register and a read data register; The read address register is configured to send a read address to a read address decoding circuit included in the corresponding read address decoding circuit group; Each of the read address decoding circuits is specifically configured to decode the read address to obtain a decoding result, determine a target latch unit from the corresponding latch units according to the decoding result, read weight data in the target latch unit, and send the weight data to the corresponding read data register; The read data register is configured to store the weight data sent by the corresponding read address decoding circuit.

2. The convolution accelerator of claim 1, wherein, Each of the read address decoding circuit groups comprises M*N read address decoding circuits, and each of the read address decoding circuits included in each of the read address decoding circuit groups corresponds to one of the latches.

3. The convolution accelerator of claim 2, wherein, The path between each of the latch units in the latch corresponding to the read address decoding circuit and the read data register in the corresponding convolution kernel operation module is a path of Q clock cycles, where Q is an integer greater than 1; P read address decoding circuit groups are respectively configured to obtain the weight data from each of the latch units after loading each of the latches for at least Q+1 clock cycles.

4. The convolution accelerator of any one of claims 1-3, wherein, In the case where P is an integer greater than 1, the graph data obtained by different convolution kernel operation modules is different sub-feature maps after the same feature map is divided into multiple sub-feature maps.

5. A method of convolution processing, characterized by, The method is applied to a convolution accelerator with a parallelism of M, and the convolution accelerator comprises: P convolution kernel operation modules; M latch groups, each of which comprises N latches, each of which comprises a plurality of latch units; P read address decoding circuit groups, each of which corresponds to one of the convolution kernel operation modules; M, N, and P are integers greater than or equal to 1; the method comprises: P read address decoding circuit groups are respectively configured to obtain the weight data from each of the latch units and send the weight data to the corresponding convolution kernel operation module; Each of the read address decoding circuit groups comprises M*N read address decoding circuits, and each of the read address decoding circuits in each of the read address decoding circuit groups corresponds to one of the latches.

6. The method of claim 5, wherein, The path between each of the latching units in the corresponding latch and the read data register in the corresponding convolution kernel operation module is a path of Q clock cycles, where Q is an integer greater than 1.

7. The method of claim 5, wherein, The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises:

8. The method according to any one of claims 5-7, characterized in that, The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises:

9. A chip, characterized by The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises:

10. An electronic device, comprising: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1, and the P convolution kernel operation modules respectively acquiring graph data comprises: The P is an integer greater than 1,

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