Image processing method, device, equipment and medium

Abstract

This application discloses an image processing method, apparatus, device, and medium. When image processing is required, a processing operation corresponding to the image to be processed is obtained. This processing operation includes at least first processing information and second processing information. A first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information are obtained. That is, the processing regions corresponding to different processing information in the image to be processed are determined. Based on the first and second processing regions, the image to be processed is processed on a target frame buffer using an on-chip cache to obtain the image processing result. In other words, according to the positional relationship between the first and second processing regions, the image to be processed is processed using an on-chip cache, eliminating the need to store it in other frame buffers, thereby reducing switching between different frame buffers and thus reducing power consumption caused by switching.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an image processing method, apparatus, device, and medium. Background Technology

[0002] Image processing refers to the technology of using computers to analyze images to achieve desired results. To meet the needs of different users, various image processing technologies have emerged, such as beautification and makeup enhancement. Current image processing technologies are relatively rigid. For example, in the makeup enhancement pipeline, makeup effects are rendered sequentially. To ensure that the previous makeup effect can be rendered on the next, at least two frame buffers are needed for switching, resulting in very high power consumption. Summary of the Invention

[0003] In view of this, embodiments of this application provide an image processing method, apparatus, device, and medium to enable processing of different processing regions by utilizing on-chip buffers without switching frame buffers, thereby reducing processing power consumption.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] In a first aspect of this application, an image processing method is provided, the method comprising:

[0006] Obtain at least one processing information operation corresponding to the image to be processed, the processing operation including first processing information and second processing information;

[0007] Obtain the first processing region corresponding to the first processing information and the second processing region corresponding to the second processing information;

[0008] Based on the first processing region and the second processing region, the image to be processed is processed on the target frame buffer using on-chip buffer to obtain the image processing result.

[0009] In a second aspect of this application, an image processing apparatus is provided, the apparatus comprising:

[0010] The first acquisition unit is used to acquire at least one processing information operation corresponding to the image to be processed, the processing operation including first processing information and second processing information.

[0011] The second acquisition unit is used to acquire the first processing area corresponding to the first processing information and the second processing area corresponding to the second processing information.

[0012] The processing unit is configured to process the image to be processed on the target frame buffer using an on-chip cache based on the first processing region and the second processing region, and obtain the image processing result.

[0013] In a third aspect of this application, an electronic device is provided, the device comprising: a processor and a memory;

[0014] The memory is used to store instructions or computer programs;

[0015] The processor is configured to execute the instructions or computer program in the memory to cause the electronic device to perform the method described in the first aspect.

[0016] In a fourth aspect of this application, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a device, cause the device to perform the method described in the first aspect.

[0017] In a fifth aspect of this application, a computer program product is provided, the computer program product comprising a computer program / instructions that, when executed by a processor, implement the method described in the first aspect.

[0018] Therefore, this application has the following beneficial effects:

[0019] In this application, when image processing is required, the processing operation corresponding to the image to be processed is obtained. This processing operation includes at least first processing information and second processing information. A first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information are obtained. That is, the processing regions corresponding to different processing information in the image to be processed are determined. Based on the first and second processing regions, the image to be processed is processed using an on-chip cache on the target frame buffer to obtain the image processing result. That is, according to the positional relationship between the first and second processing regions, the image to be processed is processed using an on-chip cache to obtain the image processing result. In other words, through the technical solution provided by this application, image processing can be performed on an on-chip cache of the frame buffer without storing data in other frame buffers, thereby reducing switching between different frame buffers and thus reducing power consumption caused by switching. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a rendering of a traditional beauty makeup style.

[0022] Figure 2 A flowchart of an image processing method provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of a makeup rendering framework provided in an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of an image processing device structure provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0027] Currently, common image processing techniques employ sequential processing. For example, in a makeup rendering pipeline, rendering occurs one by one in sequence. To ensure that the previous makeup look can be rendered onto the next, two frame buffers are needed for switching. However, on mobile devices, this rendering method does not conform to the architecture of tile-based rendering (TBR), resulting in very high power consumption of the graphics processing unit (GPU). The frame buffer is also known as the video memory.

[0028] TBR (Transform-by-Frame) is a process that subdivides a computer graphics image into a regular grid in optical space and renders each part of the grid or tile separately. The advantage of this rendering method is that it reduces memory and bandwidth consumption compared to rendering systems that immediately draw the entire frame. In other words, TBR does not directly draw the entire screen; instead, it divides the screen into tiles, and the graphics processing unit (GPU) draws one tile at a time, writing the result to system memory only after completion.

[0029] For ease of understanding, see [link to relevant documentation]. Figure 1 The diagram shown illustrates a traditional makeup rendering process, using an example of six makeup effects. The rendering workflow includes the following:

[0030] 1. Detect key points in user images;

[0031] 2. Switch to frame buffer 1 to process the lipstick. Build a mesh for the lips using key points, render the lipstick, and store the rendering result in frame buffer 2.

[0032] 3. Switch to frame buffer 2, process the pupil, construct the mesh of the pupil part by key points, render the pupil of the eye, and store the rendering result on frame buffer 1;

[0033] 4. Switch to frame buffer 1, process the eyebrows, construct the mesh of the eye area through key points, render the eye and eyebrow parts, and store the rendering result on frame buffer 2;

[0034] 5. Switch to frame buffer 2 to process the eyeshadow. Construct a mesh for the eye area using key points, render the eyeshadow, and store the rendering result in frame buffer 1.

[0035] 6. Switch to frame buffer 1 to process blush. Build a full-face mesh using key points, render the blush on the face, and store the rendering result in frame buffer 2.

[0036] 7. Switch to frame buffer 2 to process the contouring. Construct a mesh for the entire face using key points, render the facial contouring, and obtain the final makeup result.

[0037] In other words, as can be seen from the above rendering chain, in order to complete the rendering, it is necessary to switch back and forth between two different frame buffers. Switching between frame buffers will generate a lot of power consumption, resulting in high GPU power consumption.

[0038] Based on this, this application provides a beauty makeup rendering method that generally uses the on-chip buffer in the GPU to reduce the power consumption caused by frame buffer switching. That is, the GPU can perform rendering on the same frame buffer without switching between two different frame buffers.

[0039] It is understood that before using the technical solutions of the various embodiments in this disclosure, users should be informed of the type, scope of use, and usage scenarios of the personal information involved in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0040] For example, upon receiving a user's active request, a prompt message is sent to the user to clearly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to choose, based on the prompt message, whether to provide personal information to the software or hardware such as electronic devices, applications, servers, or storage media performing the operations of this disclosed technical solution. Where synthetic services may cause public confusion or misinterpretation, they should be prominently marked in a reasonable location and area of ​​the generated or edited information content.

[0041] As an optional but not limited implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0042] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0043] To facilitate understanding of the technical solutions provided in the embodiments of this application, the following description will be provided in conjunction with the accompanying drawings.

[0044] See Figure 2 This figure is a flowchart of a makeup rendering method provided in an embodiment of this application. This method can be executed by an image processing client, which can be installed on an electronic device. The electronic device can include mobile phones, tablets, laptops, desktop computers, in-vehicle terminals, wearable electronic devices, all-in-one machines, smart home devices, and other devices with communication functions, or it can be a device simulated by a virtual machine or simulator. Figure 2 As shown, the method may include the following steps:

[0045] S201: Obtain a processing operation for the image to be processed, the processing operation including first processing information and second processing information.

[0046] In this embodiment, an image to be processed is acquired, and the corresponding processing operation is determined. The processing operation includes first processing information and second processing information. Different processing information refers to performing different processing operations on the image to be processed. For example, in the beauty industry, both the first and second processing information are beauty information; the first processing information could be blush information, and the second processing information could be contouring information; or, the first processing information could be lipstick information, and the second processing information could be eyeshadow information.

[0047] It should be noted that the processing operation may include more processing information. This embodiment uses the first processing information and the second processing information included in the processing operation as examples for illustration. Specifically, when performing makeup or beautification processing on the image to be processed, the image to be processed includes a face portion. The processing operation for the face portion is obtained, and the first processing information and the second processing information are different processing information for the face portion, respectively.

[0048] In some implementations, the first processing information and the second processing information can be obtained in the following ways:

[0049] One approach involves the user selecting a target processing template before uploading the image to be processed via the client, and then using the target processing template to process the image. The target processing template includes first processing information and second processing information.

[0050] Another approach is for users to first upload the image to be processed via the client. After the image is uploaded, multiple processing templates can be displayed to the user. In response to the user's selection action, the selected processing template is determined as the target processing template, and then the image to be processed is processed using the target processing template.

[0051] S202: Obtain the first processing area corresponding to the first processing information and the second processing area corresponding to the second processing information.

[0052] After obtaining the first processing information and the second processing information for the image to be processed, a first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information are determined. The first processing region and the second processing region refer to the corresponding processing regions on the image to be processed; they can be the same processing region or different processing regions. For example, when the first processing information is eyelash processing information and the second processing information is eyeshadow processing information, both the first and second processing regions are the eye region; when the first processing information is lipstick processing information and the second processing information is eyelash processing information, the first processing region is the lip region and the second processing region is the eye region.

[0053] In some implementations, the processing regions corresponding to different processing information can be determined by: obtaining key points to be processed from the image to be processed; constructing a mesh to be processed based on the key points to be processed; and determining a first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information based on the mesh to be processed. That is, in this embodiment, the obtained key points to be processed are used as vertices of the mesh to construct the mesh, and different processing regions are divided based on the constructed mesh.

[0054] For example, when performing makeup processing on an image, after acquiring the image, the face portion is identified and facial key points are extracted. These facial key points can include key points of facial features and contours such as cheeks, eyebrows, eyes, mouth, and nose. Since the algorithms for extracting facial key points are relatively mature, they will not be elaborated upon in this embodiment. The facial key points can form a facial mesh. To distinguish different areas, the mesh is divided into: a full-face mesh – covering the entire face area, where blush and contouring information is used for rendering; an eye mesh – covering the eyes and surrounding area, including the eyelashes and eyeshadow area, where eyelash and eyeshadow information is used for rendering; and a lip mesh – covering the mouth area, where lipstick information is used for rendering, etc.

[0055] S203: Based on the first processing region and the second processing region, the on-chip cache is used to process the image to be processed on the target frame buffer to obtain the image processing result.

[0056] In this embodiment, after determining the first processing region corresponding to the first processing information and the second processing region corresponding to the second processing information, the image to be processed is processed on the target frame buffer using an on-chip cache based on the positional relationship between the first and second processing regions to obtain the image processing result. The positional relationship between the first and second processing regions can be one where there is overlap or one where there is no overlap.

[0057] In some implementations, based on the positional relationship between the first processing region and the second processing region, processing the image to be processed on the target frame buffer using an on-chip cache may include the following processing steps:

[0058] (1) Determine whether the first processing area and the second processing area overlap. If there is no overlap, execute (2); otherwise, execute (3).

[0059] In this embodiment, it is first determined whether there is an overlapping area between the first processing area and the second processing area, and then different processing is performed according to the determination result.

[0060] The determination of whether the first processing region and the second processing region overlap includes: obtaining the first processing mesh corresponding to the first processing region and the second processing mesh corresponding to the second processing region; and determining whether the first processing region and the second processing region overlap based on the vertices included in the first processing mesh and the second processing mesh. That is, whether the processing regions corresponding to different processing meshes overlap is determined by whether there are overlapping vertices included in the vertices of different processing meshes. Specifically, if there are overlapping vertices included in the first processing mesh and the second processing mesh, then the first processing region and the second processing region overlap; if there are no overlapping vertices included in the first processing mesh and the second processing mesh, then the first processing region and the second processing region do not overlap. For example, if the first processing mesh includes vertices A, B, and C, and the second processing mesh includes vertices A, C, and D, then the first processing region and the second processing region overlap.

[0061] (2) Based on the first processing information, the first on-chip cache on the target frame cache is used to process the image to be processed to obtain a first processing result; and based on the second processing information, the second on-chip cache on the target frame cache is used to process the image to be processed to obtain a second processing result; the first processing result and the second processing result are fused to obtain an image processing result.

[0062] If there is no overlap between the first and second processing regions, the first and second processing information can be executed in parallel using different on-chip caches. Specifically, on the first on-chip cache in the target frame cache, the image to be processed is processed using the first processing information to obtain the first processing result; simultaneously, on the second on-chip cache in the target frame cache, the image to be processed is processed using the second processing information to obtain the second processing result. Finally, the first and second processing results are merged to obtain the final image processing result. The first on-chip cache corresponds to the first processing region, and the second on-chip cache corresponds to the second processing region. That is, different processing regions can correspond to different on-chip caches, thereby enabling parallel processing of non-overlapping processing regions and improving processing efficiency.

[0063] (3) Based on the first processing information and the processing priority of the second processing, the image to be processed is processed on the target frame buffer using on-chip buffer to obtain the image processing result.

[0064] If there is an overlapping area between the first processing region and the second processing region, the image to be processed will be processed on the target frame buffer using the on-chip buffer according to the processing priority of the first processing information and the second processing information to obtain the image processing result. That is, when there is an overlapping area, it will be processed serially according to the processing priority to satisfy the processing order.

[0065] Specifically, the image to be processed is processed using the third on-chip buffer of the target frame buffer based on the processing information with the highest processing priority, to obtain the third processing result; the third processing result is then processed using the fourth on-chip buffer of the target frame buffer based on the processing information with the second highest processing priority, to obtain the image processing result. In other words, the image to be processed is processed first using the processing information with the highest processing priority to obtain the third processing result, and then the third processing result is processed using the processing information with the second highest processing priority to obtain the image processing result.

[0066] The relationship between the third and fourth on-chip caches is related to the degree of overlap. If the first and second processing regions completely overlap (i.e., they are the same processing region), then the third and fourth on-chip caches are the same on-chip cache. If the first and second processing regions partially overlap, then the third and fourth on-chip caches are different on-chip caches, thus satisfying the requirement that different processing regions correspond to different on-chip caches.

[0067] For example, if the processing priority of the first processing information is higher than that of the second processing information, and the first processing region and the second processing region partially overlap, then the on-chip cache 1 on the target frame buffer is used to process the image to be processed to obtain processing result 1; on-chip cache 2 retrieves processing result 1 from on-chip cache 1 and uses the second processing information to process processing result 1 again to obtain the final image processing result. Here, on-chip cache 1 is the on-chip cache corresponding to the first processing region, and on-chip cache 2 is the on-chip cache corresponding to the second processing region.

[0068] As can be seen, when image processing is required, the processing operation corresponding to the image to be processed is obtained, and the processing operation includes at least first processing information and second processing information. A first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information are obtained. That is, the processing regions corresponding to different processing information in the image to be processed are determined. Based on the first and second processing regions, the image to be processed is processed using an on-chip cache on the target frame buffer to obtain the image processing result. That is, according to the positional relationship between the first and second processing regions, the image to be processed is processed using an on-chip cache to obtain the image processing result. In other words, through the technical solution provided in this application, image processing can be performed on an on-chip cache of the frame buffer without storing data in other frame buffers, thereby reducing switching between different frame buffers and thus reducing power consumption caused by switching.

[0069] For a better understanding of the specific implementation of the embodiments of this application, please refer to... Figure 3 Another makeup rendering framework diagram is shown below. Figure 3 In the application scenario shown, makeup looks with the same mesh will be merged and rendered. The specific rendering process includes:

[0070] 1. Detect facial landmarks in user images;

[0071] 2. Using on-chip cache 1 on the frame buffer, construct a mesh for the lips based on facial key points, process the lipstick in the lip area, and store the processing result 1 on on-chip cache 1;

[0072] 3. Using the on-chip cache 2 on frame buffer 1, construct a grid of pupils through facial key points, process the pupil region, and store the processing result 2 on the on-chip cache 2;

[0073] 4. Using the on-chip cache 3 on frame buffer 1, construct the eye mesh through facial key points, process the eye shadow area, and store the processing result 3 on the on-chip cache;

[0074] 5. The on-chip buffer 4 on frame buffer 1 retrieves processing result 1, processing result 2, and processing result 3, and fuses them to obtain the fused processing result.

[0075] 6. On-chip cache 4 constructs a full-face mesh using facial key mapping, performs blush and contouring processing, and obtains the final processing result.

[0076] Based on the above method embodiments, this application provides an image processing apparatus and an electronic device, which will be described below with reference to the accompanying drawings.

[0077] See Figure 4 This figure is a schematic diagram of an image processing device provided in an embodiment of this application, such as... Figure 4 As shown, the device 400 may include: a first acquisition unit 401, a second acquisition unit 402 and a third acquisition unit 403.

[0078] The first acquisition unit 401 is used to acquire processing operations for the image to be processed, the processing operations including first processing information and second processing information.

[0079] The second acquisition unit 402 is used to acquire the first processing area corresponding to the first processing information and the second processing area corresponding to the second processing information.

[0080] The processing unit is configured to process the image to be processed on the target frame buffer using an on-chip cache based on the first processing region and the second processing region, and obtain the image processing result.

[0081] In some implementations, the second acquisition unit 402 is specifically used to acquire key points to be processed from the image to be processed; construct a grid to be processed based on the key points; and determine a first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information based on the grid to be processed.

[0082] In some implementations, the processing unit 403 includes a determining subunit and a processing subunit;

[0083] The determining subunit is used to determine whether there is an overlapping area between the first processing area and the second processing area;

[0084] The processing subunit is configured to: if there is no overlapping region, process the image to be processed using a first on-chip cache on the target frame buffer based on the first processing information to obtain a first processing result; and process the image to be processed using a second on-chip cache on the target frame buffer based on the second processing information to obtain a second processing result; fuse the first processing result and the second processing result to obtain the image processing result; and if there is an overlapping region, process the image to be processed using an on-chip cache on the target frame buffer based on the first processing information and the processing priority of the second processing to obtain the image processing result.

[0085] In some embodiments, the determining subunit is used to obtain a first processing grid corresponding to the first processing region and a second processing grid corresponding to the second processing region; and to determine whether there is an overlapping region between the first processing region and the second processing region based on the vertices included in the first processing grid and the vertices included in the second processing grid.

[0086] In some implementations, the processing subunit is specifically used to process the image to be processed using a third on-chip buffer on the target frame buffer based on the processing information with the highest processing priority, to obtain a third processing result; and to process the third processing result using a fourth on-chip buffer on the target frame buffer based on the processing information with the second highest processing priority, to obtain an image processing result.

[0087] In some embodiments, the image to be processed includes a face region, and the first processing information and the second processing information are different processing information for the face region.

[0088] In some embodiments, the apparatus further includes: a determining unit;

[0089] The determining unit is used to confirm the target processing template in response to the selection operation triggered by the user on the client, wherein the target processing template includes the first processing information and the second processing information.

[0090] It should be noted that the specific implementation of each unit in this embodiment can be found in the relevant descriptions in the above method embodiments. The division of units in this application embodiment is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. The functional units in this application embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. For example, in the above embodiments, the processing unit and the sending unit can be the same unit or different units. The integrated unit can be implemented in hardware or as a software functional unit.

[0091] See Figure 5 The diagram illustrates a structural schematic of an electronic device 500 suitable for implementing embodiments of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0092] like Figure 5As shown, the electronic device 500 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the electronic device 500. The processing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0093] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device 500 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0094] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by the processing device 501, it performs the functions defined in the methods of embodiments of this disclosure.

[0095] The electronic device provided in this embodiment belongs to the same inventive concept as the method provided in the above embodiments. Technical details not described in detail in this embodiment can be found in the above embodiments, and this embodiment has the same beneficial effects as the above embodiments.

[0096] This disclosure provides a computer storage medium storing a computer program that, when executed by a processor, implements the methods provided in the above embodiments.

[0097] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0098] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0099] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0100] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, enable the electronic device to perform the aforementioned methods.

[0101] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the first user's computer, partially on the first user's computer, as a standalone software package, partially on the first user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the first user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0103] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units / modules do not necessarily limit the specific unit itself.

[0104] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0105] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0106] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems or apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0107] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0108] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0109] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0110] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An image processing method, characterized in that, The method includes: Obtain processing operations for the image to be processed, the processing operations including first processing information and second processing information; Obtain the first processing region corresponding to the first processing information and the second processing region corresponding to the second processing information; Determine whether there is an overlapping area between the first processing area and the second processing area; If there is no overlapping area, the image to be processed is processed using the first on-chip cache on the target frame buffer based on the first processing information to obtain a first processing result; and the image to be processed is processed using the second on-chip cache on the target frame buffer based on the second processing information to obtain a second processing result; the first processing result and the second processing result are fused to obtain the image processing result. If there are overlapping areas, the image to be processed is processed on the target frame buffer using an on-chip cache based on the first processing information and the processing priority of the second processing to obtain the image processing result.

2. The method according to claim 1, characterized in that, The step of obtaining the first processing region corresponding to the first processing information and the second processing region corresponding to the second processing information includes: Obtain the key points to be processed from the image to be processed; A grid to be processed is constructed based on the key points, and a first processing region corresponding to the first processing information and a second processing region corresponding to the second processing information are determined based on the grid to be processed.

3. The method according to claim 1, characterized in that, Determining whether the first processing region and the second processing region overlap includes: Obtain the first processing grid corresponding to the first processing region and the second processing grid corresponding to the second processing region; Based on the vertices included in the first processing grid and the vertices included in the second processing grid, determine whether there is an overlapping region between the first processing region and the second processing region.

4. The method according to claim 1, characterized in that, The step of processing the image to be processed using an on-chip cache on the target frame buffer based on the first processing information and the processing priority of the second processing to obtain the image processing result includes: Based on the processing information with the highest processing priority, the image to be processed is processed using the third on-chip buffer on the target frame buffer to obtain the third processing result; Based on the processing information with the second highest processing priority, the third processing result is processed using the fourth on-chip buffer on the target frame buffer to obtain the image processing result.

5. The method according to claim 1, characterized in that, The image to be processed includes a face region, and the first processing information and the second processing information are different processing information for the face region.

6. The method according to claim 1, characterized in that, The method further includes: In response to a selection operation triggered by the user on the client, a target processing template is confirmed, wherein the target processing template includes the first processing information and the second processing information.

7. An image processing apparatus, characterized in that, The device includes: The first acquisition unit is used to acquire at least one processing operation corresponding to the image to be processed, the processing operation including first processing information and second processing information. The second acquisition unit is used to acquire the first processing area corresponding to the first processing information and the second processing area corresponding to the second processing information. The processing unit is configured to determine whether there is an overlapping region between the first processing region and the second processing region; if there is no overlapping region, process the image to be processed using a first on-chip cache on the target frame buffer based on the first processing information to obtain a first processing result; and process the image to be processed using a second on-chip cache on the target frame buffer based on the second processing information to obtain a second processing result; merge the first processing result and the second processing result to obtain the image processing result; if there is an overlapping region, process the image to be processed using an on-chip cache on the target frame buffer based on the first processing information and the processing priority of the second processing to obtain the image processing result.

8. An electronic device, characterized in that, The device includes: a processor and a memory; The memory is used to store instructions or computer programs; The processor is configured to execute the instructions or computer program in the memory to cause the electronic device to perform the method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on the device, cause the device to perform the method according to any one of claims 1-6.

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