Electroluminescent display device

Abstract

An electroluminescent display device includes: pixels present in a minimal region in which all colors can be represented by a plurality of sub-pixels; a plurality of power lines for providing power voltages to the plurality of sub-pixels; data lines for providing data signals to the plurality of sub-pixels; a plurality of gate lines for providing gate signals to the plurality of sub-pixels; and reference node lines for connecting a plurality of reference nodes included in the plurality of sub-pixels, wherein, in the plurality of sub-pixels of a pixel, some sub-pixels include two compensation transistors connected to reference nodes for receiving reference voltages, and the two compensation transistors are connected to different gate lines and are turned on at different timings.

Description

[0001] This application is a divisional application of the invention patent application filed on November 29, 2019, with application number 201911201647.X and title "Electronic Light Emitting Display Device". Technical Field

[0002] This disclosure relates to electroluminescent display devices, and more specifically, to electroluminescent display devices including subpixel driving circuitry capable of compensating for voltage drops. Background Technology

[0003] With the advancement of information technology, the market for display devices, which serve as a connection medium between users and information, has grown. Consequently, the use of various types of display devices, such as electroluminescent displays, liquid crystal displays (LCDs), and quantum dot LEDs, has increased.

[0004] The display device includes: a display panel comprising a plurality of sub-pixels; a driver for driving the display panel; and a power supply unit for providing power to the display panel. The driver includes a gate driver for providing gate signals to the display panel and a data driver for providing data signals to the display panel.

[0005] For example, if gate signals and data signals are provided to a sub-pixel, the electroluminescent display device can display an image when the light-emitting diode (LED) of the sub-pixel emits light. The LED can be implemented based on organic or inorganic materials.

[0006] Since electroluminescent display devices display images based on light generated from light-emitting diodes within sub-pixels, they offer various advantages, thus requiring precision in the sub-pixel driving circuitry used to control the emission of light from the sub-pixels. For example, the precision of the sub-pixel driving circuitry can be improved by compensating for the time-varying characteristics (or variations over time) of the threshold voltage changes of the transistors included in the sub-pixel driving circuitry.

[0007] Various methods exist for compensating for the time-varying characteristics of electroluminescent display devices. However, some commonly suggested compensation methods can cause image quality problems, such as vertical brightness inhomogeneity or crosstalk on the display panel, because they do not take into account the drop in voltage applied to the subpixels.

[0008] Therefore, a design method for a subpixel driving circuit that enables subpixels to emit light with uniform brightness has been studied. Summary of the Invention

[0009] Therefore, this disclosure relates to an electroluminescent display device using a subpixel driving circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0010] This disclosure was made in view of the above problems, and the purpose of this disclosure is to provide an electroluminescent display device in which image quality problems such as vertical brightness inhomogeneity or crosstalk on the display panel are solved by compensating for time-varying characteristics while taking into account the voltage drop of the voltage application line.

[0011] Another object of this disclosure is to provide an electroluminescent display device in which the subpixel driving circuit of each subpixel is designed to include circuitry for effectively providing a reference voltage, and thus generating a driving current that excludes a high potential voltage that could generate a voltage drop across the voltage application line.

[0012] Additional features and aspects will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practicing the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures particularly pointed out in the written description or those derived therefrom, as well as by the claims and drawings thereof.

[0013] To achieve these and other aspects embodied and broadly described in this disclosure, an electroluminescent display device is provided, comprising: a pixel including a plurality of sub-pixels; a plurality of power lines for providing power voltages to the plurality of sub-pixels; a data line for providing data signals to the plurality of sub-pixels; a plurality of gate lines for providing gate signals to the plurality of sub-pixels; and a reference node line for connecting a plurality of reference nodes included in the plurality of sub-pixels. Each sub-pixel includes a light-emitting diode and a sub-pixel driving circuit for emitting light from the light-emitting diode, the sub-pixel driving circuit providing a drive current to the light-emitting diode excluding high-potential voltages due to a reference voltage applied from one of the power lines to the reference nodes included in the sub-pixel, and a portion of the plurality of sub-pixels including a compensation transistor connected to the reference node for receiving the reference voltage. Therefore, since a reference voltage is applied to the reference node of the sub-pixel connected via the reference node line, the reference voltage provided to the reference node through the compensation transistor included in a portion of the sub-pixel can solve the image quality problem of the electroluminescent display device by providing a drive current to the light-emitting diode unaffected by high-potential voltages.

[0014] On the other hand, an electroluminescent display device is provided, comprising a unit pixel in a minimal region where all colors can be represented by a combination of the three primary colors. The unit pixel includes at least one sub-pixel including a first compensation transistor and at least one sub-pixel including a second compensation transistor. The at least one sub-pixel includes a reference node for providing a reference voltage transmitted through a light-emitting diode, a driving transistor, a switching transistor, a capacitor, and either the first or second compensation transistor. Reference node lines for connecting the reference nodes are arranged within the unit pixel. Therefore, since a reference voltage is applied to the reference nodes of the sub-pixels included in the unit pixel through the compensation transistor, and to the reference nodes of other sub-pixels within the unit pixel through the reference node lines, a driving current unaffected by high potential voltages can be provided to the light-emitting diode, thereby solving the image quality problem of the electroluminescent display device.

[0015] Details of other implementation methods are included in the detailed embodiments and accompanying drawings.

[0016] According to embodiments of this disclosure, since the sub-pixel driving circuit included in a portion of the sub-pixel includes a compensation transistor for transmitting a reference voltage, a driving current that does not include a high potential voltage capable of generating a voltage drop through the line can be provided to the light-emitting diode, thereby solving image quality problems such as vertical brightness non-uniformity or crosstalk in electroluminescent display devices.

[0017] According to an embodiment of the present disclosure, during the time period when the (n-1)th scan signal and the nth scan signal correspond to the gate on-voltage, a reference voltage is provided to the sub-pixel through a reference node line connected to the reference node, thereby enabling the sub-pixel driving circuit included in the sub-pixel to compensate for time-varying characteristics while taking into account the voltage drop of the high potential voltage.

[0018] According to an embodiment of this disclosure, a unit pixel includes: a sub-pixel including a first compensation transistor, the first compensation transistor being turned on by the (n-1)th scan signal and configured to apply a reference voltage to a reference node; and a sub-pixel including a second compensation transistor, the second compensation transistor being turned on by the nth scan signal and configured to apply a reference voltage to a reference node, thereby the sub-pixels included in the unit pixel can emit light by driving current taking into account the voltage drop of the high potential voltage.

[0019] Other systems, methods, features, and advantages will be apparent or will become apparent to those skilled in the art upon studying the following figures and detailed embodiments. All such additional systems, methods, features, and advantages are intended to be included within this specification, falling within the scope of this disclosure, and protected by the appended claims. This portion should not be construed as limiting these claims. Other aspects and advantages are discussed below in conjunction with embodiments of this disclosure. It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0020] The accompanying drawings may be included to provide a further understanding of the disclosure, and the drawings are incorporated into and form part of this specification. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the various principles of the disclosure.

[0021] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0022] Figure 2 This is a sub-pixel driving circuit according to an exemplary embodiment of the present disclosure.

[0023] Figure 3 It is shown Figure 2 The waveform diagram shows the driving characteristics of the sub-pixel driving circuit.

[0024] Figure 4 and Figure 5 It is a sub-pixel driving circuit included in a unit pixel according to an exemplary embodiment of the present disclosure.

[0025] Figure 6 It is a unit pixel image according to an exemplary embodiment of the present disclosure.

[0026] Figure 7 It is a unit pixel image according to an exemplary embodiment of the present disclosure.

[0027] Throughout the accompanying drawings and detailed embodiments, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and depictions of these elements may be enlarged. Detailed Implementation

[0028] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where such obscurity would unnecessarily obscure the gist of the disclosure. The progression of the described processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to the order described herein, except that they must occur in a specific order, and may be varied as is known in the art. The same reference numerals denote the same elements throughout. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0029] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] The term "at least one" should be understood to include any one and all combinations of one or more of the listed related items. For example, "at least one of the first, second and third items" means a combination of all items derived from two or more of the first, second and third items, as well as the first, second or third item.

[0031] When describing embodiments, if a structure is described as being "above" or "below" another structure, this description should be interpreted to include cases where these structures are in contact with each other and cases where a third structure is arranged between them. The dimensions and thicknesses of each element shown in the accompanying drawings are given merely for ease of description, and embodiments of this disclosure are not limited thereto.

[0032] The terms “first horizontal axis direction,” “second horizontal axis direction,” and “vertical axis direction” should not be interpreted solely based on the geometric relationship that the directions are perpendicular to each other, but may refer to directions that have a broader directional nature within the scope of the functional operability of the components of this disclosure.

[0033] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may cooperate with each other and be technically driven in various ways. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0034] In this disclosure, the gate driver on the substrate of the display panel can be implemented using an N-type transistor or a P-type transistor. For example, the transistor can be implemented using a transistor with a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. The transistor can be a three-electrode device, including a gate, a source, and a drain. The source can provide charge carriers to the transistor. In the transistor, charge carriers can begin to move from the source. The drain can be an electrode through which charge carriers can move from the transistor to the outside.

[0035] For example, in a transistor, charge carriers can move from the source to the drain. In an N-type transistor, because the charge carriers are electrons, the voltage at the source is lower than the voltage at the drain, causing electrons to move from the source to the drain. In an N-type transistor, because electrons move from the source to the drain, current moves from the drain to the source. In a P-type transistor, because the charge carriers are holes, the voltage at the source is higher than the voltage at the drain, causing holes to move from the source to the drain. In a P-type transistor, because holes move from the source to the drain, current moves from the source to the drain. The source and drain of a transistor can be non-fixed and can switch according to the applied voltage.

[0036] In the following text, the gate on-voltage can be a voltage of a gate signal used to turn on the transistor. The gate off-voltage can be a voltage used to turn off the transistor. For example, in a P-type transistor, the gate on-voltage can be a logic low voltage VL, while the gate off-voltage can be a logic high voltage VH. In an N-type transistor, the gate on-voltage can be a logic high voltage, while the gate off-voltage can be a logic low voltage. The inventors of this disclosure have recognized the above-mentioned problems and have invented a display device for reducing the voltage drop of a voltage application line.

[0037] In the following description, a sub-pixel driving circuit and an electroluminescent display device including the sub-pixel driving circuit according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0038] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0039] Reference Figure 1 The electroluminescent display device 100 includes an image processor 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply unit 180.

[0040] The image processor 110 outputs drive signals for driving various devices along with externally provided image data. The drive signals output from the image processor 110 may include data enable signals, vertical synchronization signals, horizontal synchronization signals, and clock signals.

[0041] The timing controller 120 receives image data and drive signals from the image processor 110. Based on the drive signals, the timing controller 120 outputs a gate timing control signal GDC for controlling the operating timing of the gate driver 130 and a data timing control signal DDC for controlling the operating timing of the data driver 140.

[0042] Gate driver 130 outputs a gate signal in response to a gate timing control signal GDC provided from timing controller 120. Gate driver 130 outputs the gate signal through gate lines GL(1) to GL(n). Gate driver 130 may be provided as an IC (integrated circuit) or as a gate-in-panel (GIP) built into display panel 150. Gate driver 130 may be located on each of the left and right sides of display panel 150, or on one of the left and right sides, but the implementation is not limited to these sides. Gate driver 130 includes multiple stages. For example, the first stage of gate driver 130 outputs a first gate signal for driving the first gate line of display panel 150.

[0043] Data driver 140 outputs a data signal in response to a data timing control signal DDC provided from timing controller 120. Data driver 140 samples and latches the digital data signal DATA provided from timing controller 120, and converts the digital data signal DATA into an analog data signal based on a gamma reference voltage. Data driver 140 outputs the data signal to display panel 150 via data lines DL(1) to DL(m). Data driver 140 can be disposed on display panel 150 in the form of an IC (integrated circuit) or in the form of a chip-on-film (COF).

[0044] Power supply unit 180 outputs a high-potential voltage VDD, a low-potential voltage VSS, and a reference voltage VREF. These voltages are supplied to display panel 150. The high-potential voltage VDD is supplied to display panel 150 via a high-potential voltage line, and the low-potential voltage VSS is supplied to display panel 150 via a low-potential voltage line. The voltages output from power supply unit 180 can be used by gate driver 130 or data driver 140.

[0045] The display panel 150 displays an image in response to gate signals and data signals provided from the gate driver 130 and the data driver 140, respectively, and a power source provided from the power supply unit 180. The display panel 150 includes pixels P for displaying the image.

[0046] The display panel 150 includes a display area DA in which pixels P are arranged in rows and columns, and a non-display area NDA in which various signal lines or pads are formed outside the display area DA. Since the display area DA is the area where images are displayed, pixels P are located in the display area DA. Since the non-display area NDA is the area where images are not displayed, dummy pixels are located in the non-display area NDA, but pixels P are not located there.

[0047] Pixel P comprises multiple subpixels, and the image is displayed based on the grayscale displayed by each subpixel. Each subpixel is connected to a data line arranged along a column line (or column direction) and to a gate line (or pixel line) arranged along a row line (or row direction). Subpixels on the same pixel line are driven simultaneously and share the same gate line. When a subpixel arranged in the first pixel line is defined as the "first subpixel" and a subpixel arranged in the nth pixel line is defined as the "nth subpixel," the first subpixel to the nth subpixel are driven sequentially.

[0048] The pixels of the display panel 150 are arranged in a matrix to form a pixel array, but the implementation is not limited to this. For example, in addition to a matrix arrangement, the pixels can be arranged in various other forms, such as stripes and diamonds. When the smallest area that can represent all colors through a combination of the three primary colors of red, green, and blue is defined as a unit pixel, the size and shape of the unit pixel can be changed depending on the arrangement of the pixels. Depending on the situation, in addition to red, green, and blue, subpixels may include white and yellow.

[0049] Pixel P may include two or more of red, green, and blue sub-pixels; may include two or more of white, red, green, and blue sub-pixels; or may include two or more of red, green, blue, and yellow sub-pixels. A sub-pixel may have one or more different light-emitting regions depending on its light-emitting characteristics. For example, a pixel including red, green, and blue sub-pixels can constitute a unit pixel. Additionally, a pixel including red and green sub-pixels and a pixel including blue and green sub-pixels can constitute a unit pixel. Furthermore, a pixel including red and green sub-pixels and a pixel including blue and white sub-pixels can constitute a unit pixel. Additionally, a pixel including red, green, and blue sub-pixels, a pixel including any two of red, green, and blue sub-pixels and a white sub-pixel, or a pixel including red, green, blue, and white sub-pixels can constitute a unit pixel.

[0050] Figure 2 This is a sub-pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 3 It is shown Figure 2 The waveform diagram shows the driving characteristics of the sub-pixel driving circuit. (Refer to...) Figure 2 To describe the sub-pixel SP in the nth row and mth column.

[0051] The display panel 150 includes a display area DA in which an image is displayed based on subpixels SP and a non-display area NDA in which signal lines or drive circuits are arranged and no image is displayed.

[0052] The electroluminescent display device 100 displays an image based on light generated from light-emitting diodes (ELs) included in the sub-pixels SP. However, since the electroluminescent display device 100 has time-varying characteristics (or changes over time) of the threshold voltage of the elements (driving transistors, etc.) included in the sub-pixels SP, threshold voltage compensation is required.

[0053] Therefore, a sub-pixel driving circuit for solving image quality problems such as vertical brightness inhomogeneity or crosstalk in an electroluminescent display device 100 according to an embodiment of the present disclosure will be described. The sub-pixel driving circuit, described later, includes, for example, P-type transistors, but the embodiment is not limited to, for example, P-type transistors. The sub-pixel driving circuit according to an embodiment of the present disclosure can be applied to N-type transistors.

[0054] like Figure 2 and Figure 3 As shown, in the electroluminescent display device 100 according to the example embodiment, a reference voltage VREF is applied externally to the reference node Nref to reduce the voltage drop of the high potential voltage VDD applied to the sub-pixel SP. The nth scan signal Scan(n) and the nth emission control signal Em(n) are provided to the sub-pixel SP. In this case, the externally applied voltage refers to the voltage applied from the non-display area NDA, which corresponds to the outside of the display area DA. The reference voltage VREF can be provided from a power supply unit separately packaged in the display panel 150, or the nth scan signal Scan(n) and the nth emission control signal Em(n) can be provided from the gate driver 130 arranged in the non-display area NDA.

[0055] The reference voltage VREF, applied via the reference voltage line, is transmitted to the reference node Nref of the sub-pixel SP within a specific time period. The reference voltage VREF can have a voltage level between the high potential voltage VDD and the low potential voltage VSS, or a voltage level equal to the high potential voltage VDD. For example, the high potential voltage can be 4.6V, and the reference voltage can be 4.0V.

[0056] Gate driver 130 includes a scan driver and an emitter driver that provide scan signals and emission control signals to sub-pixels SP arranged along pixel lines. Each of the scan driver and the emitter driver includes multiple stages. The nth stage of each of the scan driver and the emitter driver outputs an nth scan signal Scan(n) and an nth emission signal Em(n) to drive the nth sub-pixel SP.

[0057] The sub-pixel SP according to embodiments of this disclosure includes a sub-pixel driving circuit and a light-emitting diode EL, and the sub-pixel driving circuit includes a first transistor T1 to a seventh transistor T7, a driving transistor DT, and a capacitor Cst. In the embodiments shown in this disclosure, the sub-pixel SP is implemented based on a total of eight transistors and one capacitor. However, embodiments of this disclosure are not limited to the embodiments shown. The configuration and connection relationships of the nth sub-pixel SP will be described below.

[0058] Reference Figure 2 and Figure 3 The driving transistor DT includes a gate, a source, and a drain connected to the gate node DGT. The source of the driving transistor DT is the first electrode of the driving transistor DT, and the drain of the driving transistor DT is the second electrode of the driving transistor DT.

[0059] The gate of the first transistor T1 is connected to the nth scan line, the first electrode of the first transistor T1 is connected to the mth data line DL(m), and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 and the first electrode of the driving transistor DT. The first transistor T1 is turned on to correspond to the nth scan signal Scan(n) applied through the logic low voltage VL of the nth scan line. If the first transistor T1 is turned on, the data voltage Vdata(m) applied through the mth data line DL(m) is applied to the second electrode of the first transistor T1.

[0060] The gate of the second transistor T2 is connected to the nth light-emitting control signal line, the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 is connected to the high-potential power line and the first electrode of the seventh transistor T7. The second transistor T2 is turned on to correspond to the nth light-emitting control signal Em(n) applied through the logic low voltage VL via the nth light-emitting control signal line. When the second transistor T2 is turned on, the data voltage Vdata(m) charged in the second electrode of the first transistor T1 is transmitted to one end of the capacitor Cst through the second transistor T2 and the seventh transistor T7.

[0061] The gate of the third transistor T3 is connected to the nth scan line, the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor DT, and the second electrode of the third transistor T3 is connected to the gate of the driving transistor DT. The third transistor T3 is turned on to correspond to the nth scan signal Scan(n) applied through the logic low voltage VL of the nth scan line. If the third transistor T3 is turned on, the driving transistor DT becomes diode-connected because the gate and second electrode of the driving transistor DT are turned on.

[0062] The gate of the fourth transistor T4 is connected to the (n-1)th scan line, the first electrode of the fourth transistor T4 is connected to the initialization voltage line, and the second electrode of the fourth transistor T4 is connected to the other end of the capacitor Cst, the second electrode of the third transistor T3, and the gate of the driving transistor DT. The fourth transistor T4 is turned on to correspond to the (n-1)th scan signal Scan(n-1) applied through the logic low voltage VL of the (n-1)th scan line. If the fourth transistor T4 is turned on, the gate node DTG of the driving transistor DT is initialized based on the initialization voltage Vini. In this case, the gate node DTG of the driving transistor DT is connected to the gate of the driving transistor DT.

[0063] The gate of the fifth transistor T5 is connected to the nth light-emitting control signal line, the first electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor DT, and the second electrode of the fifth transistor T5 is connected to the anode of the light-emitting diode EL. The fifth transistor T5 is turned on to correspond to the nth light-emitting control signal Em(n) applied through the logic low voltage VL of the nth light-emitting control signal line. If the fifth transistor T5 is turned on, the light-emitting diode EL emits light in response to the drive current provided by the driving transistor DT.

[0064] The gate of the sixth transistor T6 is connected to the nth scan line, the first electrode of the sixth transistor T6 is connected to the initialization voltage line, and the second electrode of the sixth transistor T6 is connected to the second electrode of the fifth transistor T5 and the anode of the light-emitting diode EL. The sixth transistor T6 is turned on to correspond to the nth scan signal Scan(n) applied through the logic low voltage VL of the nth scan line. If the sixth transistor T6 is turned on, the anode of the light-emitting diode EL is initialized based on the initialization voltage Vini.

[0065] The gate of the seventh transistor T7 is connected to the nth light-emitting control signal line. The first electrode of the seventh transistor T7 is connected to the high-potential power line and the second electrode of the second transistor T2. The second electrode of the seventh transistor T7 is connected to one end of the capacitor Cst. The seventh transistor T7 is turned on to correspond to the nth light-emitting control signal Em(n) applied through the logic low voltage VL via the nth light-emitting control signal line. When the seventh transistor T7 is turned on, the data voltage Vdata(m) charged in the second electrode of the first transistor T1 is transmitted to one end of the capacitor Cst through the second transistor T2.

[0066] One end of capacitor Cst is connected to the second electrode of the seventh transistor T7, and the other end of capacitor Cst is connected to the second electrode of the fourth transistor T4. The node connected to the second electrode of the seventh transistor T7 and one end of capacitor Cst is defined as the reference node Nref to which the reference voltage VREF is transmitted. The anode of light-emitting diode EL is connected to the second electrode of the fifth transistor T5, and the cathode of light-emitting diode EL is connected to the low-potential power line. The low-potential voltage VSS is applied to the cathode through the low-potential power line.

[0067] Reference Figure 3 According to embodiments of this disclosure, the sub-pixel SP operates in the following order: a first initialization period INI, a sampling and second initialization period SAM, a hold period HLD, and an emission period EMI. The first initialization period INI is the period for initializing the gate node DTG of the driving transistor DT. The sampling and second initialization period SAM is the period for initializing the light-emitting diode EL while sampling the threshold voltage of the driving transistor DT. The hold period HLD is the period for holding the data voltage Vdata(m) applied through the m-th data line DL(m) at a specific node. The emission period EMI is the period that allows the light-emitting diode EL to emit light through the drive current generated based on the data voltage Vdata(m).

[0068] Since the sub-pixel SP according to the embodiments of this disclosure has a first initialization period INI and a sampling and second initialization period SAM during the period when the nth emission control signal Em(n) is not applied (the period when the logic voltage VH is maintained high), compensation based on internal circuitry is performed. The operating characteristics of these periods are as follows. As an example, during a horizontal period (1H), the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) are applied as a logic low voltage VL. Furthermore, during a horizontal period (1H), each of the first initialization period INI and the sampling and second initialization period SAM is performed.

[0069] During the first initialization period INI, the fourth transistor T4 is turned on to correspond to the (n-1)th scan signal Scan(n-1) applied via the logic low voltage VL through the (n-1)th scan line. In this case, an initialization voltage Vini, lower than the high-potential voltage VDD applied via the high-potential power line, is applied to the initialization voltage line. Through this operation, the gate node DTG of the driving transistor DT is initialized based on the initialization voltage Vini. A reference voltage VREF is applied to the reference node Nref to initialize one end of the capacitor Cst as the reference voltage.

[0070] During the sampling and second initialization period (SAM), the first transistor T1, the third transistor T3, and the sixth transistor T6 are turned on to correspond to the nth scan signal Scan(n) applied via the logic low voltage VL through the nth scan line. The reference voltage VREF is continuously applied to the reference node Nref. The data voltage Vdata(m) applied via the mth data line DL(m) through the turn-on operation of the first transistor T1 is applied to the first electrode of the driving transistor DT. Since the driving transistor DT becomes diode-connected through the turn-on operation of the third transistor T3, the threshold voltage of the driving transistor DT is sampled. The data voltage Vdata(m) applied to the first electrode of the driving transistor DT charges the gate node DTG of the driving transistor DT. Furthermore, the light-emitting diode EL is initialized based on the initialization voltage Vini through the turn-on operation of the sixth transistor T6.

[0071] The hold period HLD varies depending on the duration of the clock signal for the light-emitting driver that outputs the nth light-emitting control signal Em(n) and the duration of the clock signal for the scan driver that outputs the nth scan signal Scan(n). For example, the hold period HLD can be a horizontal period 1H or more. During the hold period HLD, the capacitor Cst charges and holds the data voltage based on the voltage difference between its terminals. When the nth scan signal Scan(n) transitions from logic low voltage VL to logic high voltage VH during the hold period HLD, the voltage at the gate node DTG of the driving transistor DT can be slightly varied by the parasitic capacitor.

[0072] During the EMI emission period, the second transistor T2, the seventh transistor T7, and the fifth transistor T5 are turned on to correspond to the nth emission control signal Em(n) applied via the logic low voltage VL through the nth emission control signal line. The high-potential voltage VDD applied via the high-potential power line through the turn-on operation of the second transistor T2 is applied to the first electrode of the driving transistor DT. The high-potential voltage VDD applied via the high-potential power line through the turn-on operation of the seventh transistor T7 is applied to the reference node Nref, which serves as one end of the capacitor Cst. In this case, the voltage of the gate node DTG of the driving transistor DT, which serves as the other end of the capacitor Cst, is changed by coupling to be as much as the voltage of the reference node Nref, which changes from the reference voltage VREF to the high-potential voltage VDD.

[0073] Since the reference voltage VREF is provided to the reference node Nref during the first initialization period INI and the sampling and second initialization period SAM to account for the voltage drop of the high potential voltage VDD, the sub-pixel SP according to the embodiment of this disclosure is compensated. Therefore, the current of the compensated sub-pixel SP is expressed by the following equation.

[0074] Ioled=K(Vsg–|Vth|)2=K{(VDD-(Vdata(m)-|Vth|+VDD-VREF)-|Vth|}2=K(VREF-Vdata(m))2

[0075] In the above equations, Ioled represents the current flowing through the light-emitting diode EL, K represents a constant, Vsg represents the voltage between the source and gate of the driving transistor DT, Vth represents the threshold voltage of the driving transistor DT, VDD represents the high-potential voltage applied through the high-potential power line, VREF represents the reference voltage applied through the reference voltage line, and Vdata(m) represents the data voltage applied through the m-th data line DL(m).

[0076] As shown in the equation above, Ioled is determined by the difference between the reference voltage VREF and the data voltage Vdata(m). According to this equation, it can be noted from the nth sub-pixel SP according to the embodiment of this disclosure that the voltage drop of the high-potential voltage VDD applied through the high-potential power line can be compensated by the reference voltage VREF applied during the first initialization period INI and the sampling and second initialization period SAM.

[0077] The following describes a sub-pixel driving circuit for providing the reference voltage VREF to the reference node Nref during the first initialization period INI and the sampling and second initialization period SAM.

[0078] Figure 4 and Figure 5 This refers to a sub-pixel driving circuit included in a unit pixel according to an exemplary embodiment of this disclosure. From... Figure 2 The sub-pixel driving circuit of the example implementation Figure 4 and Figure 5 The sub-pixel driving circuit is modified, and the connection relationships between transistors T1 to T6 and the capacitors, except for the seventh transistor T7, are also applicable. Figure 4 and Figure 5 The sub-pixel driving circuit. Therefore, a brief description of the sub-pixel driving circuit will be omitted or omitted. Figure 2 Repeated description.

[0079] Reference Figure 4 The sub-pixel driving circuit includes transistor T7-1 to replace... Figure 2 The seventh transistor T7. The gate of the 7-1 transistor T7-1 is connected to the (n-1)th scan line, the first electrode of the 7-1 transistor T7-1 is connected to the reference voltage line, and the second electrode of the 7-1 transistor T7-1 is connected to the reference node Nref, which is one end of the capacitor Cst. The 7-1 transistor T7-1 is turned on to correspond to the (n-1)th scan signal Scan(n-1) applied through the logic low voltage VL of the (n-1)th scan line. If the 7-1 transistor T7-1 is turned on, the reference voltage VREF provided through the reference voltage line is transmitted to the reference node Nref, which is one end of the capacitor Cst. According to the example embodiment, the reference node Nref is connected to the reference node of the adjacent sub-pixel through a reference node line. The reference node line used to connect the reference node Nref of the sub-pixel in the nth pixel line is defined as the nth reference node line NrefL(n). Figure 6 and Figure 7 To describe the reference node line.

[0080] Reference Figure 5 The sub-pixel driving circuit includes a 7-2nd transistor T7-2 replacing the 7th transistor T7. The gate of the 7-2nd transistor T7-2 is connected to the nth scan line, the first electrode of the 7-2nd transistor T7-2 is connected to a reference voltage line, and the second electrode of the 7-2nd transistor T7-2 is connected to a reference node Nref, which serves as one end of a capacitor Cst. The 7-2nd transistor T7-2 is turned on to correspond to the nth scan signal Scan(n) applied via the logic low voltage VL through the nth scan line. When the 7-2nd transistor T7-2 is turned on, the reference voltage VREF provided through the reference voltage line is transmitted to the reference node Nref, which serves as one end of the capacitor Cst.

[0081] exist Figure 4In the sub-pixel driving circuit, during the period when the (n-1)th scan signal Scan(n-1) corresponds to the gate on-voltage, the reference voltage VREF is applied to the reference node Nref. Figure 5 In the sub-pixel driving circuit, during the period when the nth scan signal Scan(n) corresponds to the gate turn-on voltage, the reference voltage VREF is applied to the reference node Nref.

[0082] During the periods when the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) correspond to the gate on-voltage, the reference voltage VREF should be applied to the reference node Nref, thereby allowing each sub-pixel driving circuit to compensate for time-varying characteristics by taking into account the voltage drop at high potential voltages. Therefore, in Figure 4 and Figure 5 In this configuration, each unit pixel includes at least one sub-pixel driving circuit. In this case, transistor T7-1, used to apply the reference voltage VREF to the reference node Nref according to the compensation timing, can be defined as the first compensation transistor, and transistor T7-2, used as the second compensation transistor, can be defined as the second compensation transistor. The first and second compensation transistors can be collectively referred to as compensation transistors.

[0083] The shape of the unit pixel and the arrangement of the sub-pixel driving circuitry will be described below.

[0084] Figure 6 It is a unit pixel image according to an exemplary embodiment of the present disclosure.

[0085] According to an example embodiment of this disclosure, a unit pixel UP includes three sub-pixels SP1(n), SP2(n), and SP3(n) connected to the nth pixel line. The (n-1)th gate line GL(n-1), the nth gate line GL(n), a reference voltage line VREFL, a high-potential voltage line VDDL for applying a high-potential voltage VDD, a low-potential voltage line VSSL for applying a low-potential voltage VSS, and an initialization voltage line VINL for applying an initialization voltage VINI are connected to each of the three sub-pixels SP1(n), SP2(n), and SP3(n). The first nth sub-pixel SP1(n) is connected to the (m-2)th data line DL(m-2), the second nth sub-pixel SP2(n) is connected to the (m-1)th data line DL(m-1), and the third nth sub-pixel SP3(n) is connected to the mth data line DL(m). In this case, the (n-1)th gate line GL(n-1) may be the (n-1)th scan line, and the nth gate line GL(n) may include both the nth scan line and the nth emitter line. The high-potential voltage line VDDL, the reference voltage line VREFL, the low-potential voltage line VSSL, and the initialization voltage line VINL can be collectively referred to as power lines.

[0086] As described above, in a unit pixel UP, since a reference voltage VREF should be applied to the reference node Nref during the periods when the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) correspond to the gate on-state voltage, the first nth sub-pixel SP1(n) and the second nth sub-pixel SP2(n) included in the unit pixel UP according to the example embodiment of this disclosure are connected to the reference voltage line VREFL for providing the reference voltage VREF. During the period when the (n-1)th scan signal Scan(n-1) corresponds to the gate on-state voltage, the reference voltage VREF is applied to the reference node Nref through the sub-pixel driving circuit of the first nth sub-pixel SP1(n), and during the period when the nth scan signal Scan(n) corresponds to the gate on-state voltage, the reference voltage VREF is applied to the reference node Nref through the sub-pixel driving circuit of the second nth sub-pixel SP2(n).

[0087] The reference node Nref included in each of the three sub-pixels SP1(n), SP2(n), and SP3(n) in the nth pixel line is connected to the nth reference node line NrefL(n). Therefore, during the periods when the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) correspond to the gate on-voltage, a reference voltage VREF is applied to the reference node Nref of the sub-pixel driving circuits included in the three sub-pixels SP1(n), SP2(n), and SP3(n) of the nth pixel line. The nth reference node line NrefL(n) may have a structure in which all the reference nodes Nref of the nth sub-pixel in the nth pixel line are connected, or it may have a structure in which the reference nodes Nref of the nth sub-pixel included in a unit pixel UP are connected per unit pixel UP. In the latter case, the reference node line NrefL(n) is separated from the reference node lines of adjacent unit pixels UP, and only the reference nodes Nref included in the unit pixel UP share the voltage.

[0088] Since the reference voltage VREF is applied to the reference node Nref of the third nth sub-pixel SP3(n) through the first nth sub-pixel SP1(n) and the second nth sub-pixel SP2(n), the sub-pixel driving circuit has a reference node Nref but does not include a separate circuit for providing the reference voltage VREF to the reference node Nref.

[0089] Therefore, the sub-pixel driving circuit of the first nth sub-pixel SP1(n) according to the exemplary embodiment of this disclosure can be Figure 4 This includes the sub-pixel driving circuit of transistor T7-1 (7-1), and the sub-pixel driving circuit of the second nth sub-pixel SP2(n) can be... Figure 5This includes a sub-pixel driving circuit containing the 7-2nd transistor T7-2, and the sub-pixel driving circuit for the third nth sub-pixel SP3(n) can be... Figure 2 Sub-pixel driving circuit.

[0090] The connection relationship between the sub-pixels included in the unit pixel UP and the reference voltage line VREFL in the exemplary embodiments of this disclosure is not limited to... Figure 6 The implementation method is as follows. However, any one of the sub-pixels SP1(n), SP2(n), and SP3(n) included in the unit pixel UP includes a sub-pixel driving circuit in which a reference voltage can be applied to the reference node Nref according to the timing of the (n-1)th scan signal Scan(n-1), and the other one of the sub-pixels SP1(n), SP2(n), and SP3(n) includes a sub-pixel driving circuit in which a reference voltage can be applied to the reference node Nref according to the timing of the nth scan signal Scan(n).

[0091] Therefore, since the reference voltage VREF is applied to the reference node Nref included in the sub-pixel driving circuit, the sub-pixel driving circuit included in the unit pixel UP can solve image quality problems such as vertical brightness inhomogeneity or crosstalk on the display panel by providing a driving current to the light-emitting diode EL that does not include a high potential voltage, where a high potential voltage can cause a voltage drop in the voltage application line.

[0092] Figure 7 It is a unit pixel image according to an exemplary embodiment of the present disclosure.

[0093] A unit pixel UP according to an exemplary embodiment of this disclosure includes two sub-pixels SP1(n-1) and SP2(n-1) connected to the (n-1)th pixel line and two sub-pixels SP1(n) and SP2(n) connected to the nth pixel line. A (n-2)th gate line GL(n-2), a (n-1)th gate line GL(n-1), a high-potential voltage line VDDL for applying a high-potential voltage VDD, and a low-potential voltage line VSSL for applying a low-potential voltage VSS are connected to each of the two sub-pixels SP1(n-1) and SP2(n-1) connected to the (n-1)th pixel line. The first (n-1)th sub-pixel SP1(n-1) and the first nth sub-pixel SP1(n) are connected to the (m-1)th data line DL(m-1), and the second (n-1)th sub-pixel SP2(n-1) and the second nth sub-pixel SP2(n) are connected to the mth data line DL(m). In this configuration, the (n-2)th gate line GL(n-2) can be the (n-2)th scan line, and each of the (n-1)th gate line GL(n-1) and the nth gate line GL(n) can include the (n-1)th scan line, the (n-1)th emitter line, the nth scan line, and the nth emitter line. The initialization voltage line VINL is located between the sub-pixel connected to the (m-1)th data line DL(m-1) and the sub-pixel connected to the mth data line DL(m), thereby providing an initialization voltage VINI from the same initialization voltage line VINL to both the sub-pixel connected to the (m-1)th data line DL(m-1) and the sub-pixel connected to the mth data line DL(m). The high-potential voltage line VDDL, the reference voltage line VREFL, the low-potential voltage line VSSL, and the initialization voltage line VINL can be collectively referred to as the power line.

[0094] As described above, in a unit pixel UP, since a reference voltage VREF should be applied to reference nodes Nref(n-1) and Nref(n) during the periods when the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) correspond to the gate on-voltage, the reference voltage line VREFL for providing the reference voltage VREF is connected to the first (n-1)th sub-pixel SP1(n-1) and the first nth sub-pixel SP1(n) in the unit pixel UP according to the example embodiment of this disclosure. Since the first (n-1)th sub-pixel SP1(n-1) and the first nth sub-pixel SP1(n) are along a row, the first (n-1)th sub-pixel SP1(n-1) and the first nth sub-pixel SP1(n) are connected to the same reference voltage line VREFL. During the period when the (n-1)th scan signal Scan(n-1) corresponds to the gate on-voltage, the reference voltage VREF is applied to the reference node Nref(n-1) through the sub-pixel driving circuit of the first (n-1)th sub-pixel SP1(n-1), and during the period when the nth scan signal Scan(n) corresponds to the gate on-voltage, the reference voltage VREF is applied to the reference node Nref(n) through the sub-pixel driving circuit of the first nth sub-pixel SP1(n).

[0095] To share the reference voltage VREF applied to the reference node Nref(n-1) of the first (n-1)th sub-pixel SP1(n-1), the reference nodes Nref(n-1) of the first (n-1)th sub-pixel SP1(n-1) and Nref(n-1) of the second (n-1)th sub-pixel SP2(n-1) are connected to the (n-1)th reference node line NrefL(n-1). To share the reference voltage VREF applied to the reference node Nref(n) of the first nth sub-pixel SP1(n), the reference node Nref(n) of the second nth sub-pixel SP2(n) is connected to the nth reference node line NrefL(n).

[0096] In this case, in the first (n-1)th sub-pixel SP1(n-1) and the second (n-1)th sub-pixel SP2(n-1), a reference voltage VREF is applied to the reference node Nref(n-1) during the time period corresponding to the gate on-state voltage of the (n-1)th scan signal. In the first nth sub-pixel SP1(n) and the second nth sub-pixel SP2(n), a reference voltage VREF is applied to the reference node Nref(n) during the time period corresponding to the gate on-state voltage of the nth scan signal. Since the reference voltage VREF should be provided to each of the sub-pixels SP1(n-1), SP2(n-1), SP1(n), and SP2(n) included in the unit pixel UP during the time period corresponding to the gate on-state voltage of the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n), the sub-pixels are implemented to be provided with a reference voltage VREF from the gate on-state voltage of the (n-1)th scan signal Scan(n-1). Figure 7 The time period during which the reference voltage VREF is applied to the parallel unit pixels UP shown.

[0097] According to the second embodiment of this disclosure, a unit pixel arranged parallel to and adjacent to the unit pixel UP can be implemented as a sub-pixel driving circuit as follows: wherein, during the period when the nth scan signal Scan(n) corresponds to the gate on-state voltage, the first (n-1)th sub-pixel SP1(n-1) among the sub-pixels included in the unit pixel UP according to the example embodiment of this disclosure can receive the reference voltage VREF, and during the period when the (n-1)th scan signal Scan(n-1) corresponds to the gate on-state voltage, the first nth sub-pixel SP1(n) can receive the reference voltage VREF.

[0098] Therefore, in order to apply a reference voltage VREF to the reference node Nref(n) of the sub-pixel driving circuit included in the four sub-pixels of the two unit pixels and the reference node Nref(n) of the sub-pixel driving circuit included in the four sub-pixels of the two unit pixels during the period when the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) correspond to the gate turn-on voltage, the (n-1)th reference node line NrefL(n-1) and the nth reference node line NrefL(n) are connected to the unit pixel UP and the (n-1)th reference node and the nth reference node of the unit pixel adjacent to the unit pixel UP.

[0099] More specifically, the (n-1)th reference node line NrefL(n-1) can have a structure in which all the (n-1)th reference nodes Nref(n-1) of the (n-1)th sub-pixel in the (n-1)th pixel line are connected, or it can have a structure in which the (n-1)th reference nodes Nref(n-1) of the (n-1)th sub-pixel included in the (n-1)th unit pixel UP included in the two unit pixels arranged parallel to both sides of the (n-1)th pixel line are connected. Similarly, the nth reference node line NrefL(n) can have a structure in which all the reference nodes Nref(n) of the nth sub-pixel arranged in the nth pixel line are connected, or it can have a structure in which the reference nodes Nref(n) of the nth sub-pixel included in the two unit pixels UP arranged parallel to both sides of the nth pixel line are connected. In the latter case of each of the methods for connecting reference node lines, the (n-1)th reference node line NrefL(n-1) and the nth reference node line NrefL(n) are arranged in the cells of two pixels that are adjacent to each other and connected to the sub-pixels included in the two adjacent unit pixels, so that the reference nodes included only in the two unit pixels share the voltage.

[0100] Since the reference voltage VREF is applied to the reference nodes Nref(n-1) and Nref(n) of the second (n-1)th sub-pixel SP2(n-1) and the second nth sub-pixel SP2(n) through the first (n-1)th sub-pixel SP1(n-1) and the first nth sub-pixel SP1(n), the sub-pixel driving circuit has reference nodes Nref(n-1) and Nref(n), but does not include a separate circuit for providing the reference voltage VREF to the reference nodes Nref(n-1) and Nref(n).

[0101] Therefore, the sub-pixel driving circuit of the first (n-1)th sub-pixel SP1(n-1) of the unit pixel UP according to the example embodiment of this disclosure can be Figure 4 This includes a sub-pixel driving circuit with transistor T7-1 (7-1), and the sub-pixel driving circuit for the first nth sub-pixel SP1(n) can be... Figure 5 This includes a sub-pixel driving circuit containing the 7-2nd transistor T7-2, and the sub-pixel driving circuits for the second (n-1)th sub-pixel SP2(n-1) and the second nth sub-pixel SP2(n) can be... Figure 2 Sub-pixel driving circuit.

[0102] The connection relationship between the sub-pixels included in the unit pixel UP and the reference voltage line VREFL in the exemplary embodiments of this disclosure is not limited to... Figure 7The implementation method is as follows. However, any one of the sub-pixels SP1(n-1), SP2(n-1), SP1(n), and SP2(n) included in the unit pixel UP includes a sub-pixel driving circuit that can apply a reference voltage VREF to the reference node according to the timing of the (n-1)th scan signal Scan(n-1), and another one of the sub-pixels SP1(n-1), SP2(n-1), SP1(n), and SP2(n) includes a sub-pixel driving circuit that can apply a reference voltage VREF to the reference node according to the timing of the nth scan signal Scan(n). However, in order to avoid unnecessary arrangement of the reference voltage line VREFL, the sub-pixels including the sub-pixel driving circuit for applying the reference voltage VREF to the reference node according to the timing of the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) can be arranged in the same column.

[0103] Therefore, when a reference voltage VREF is applied to the reference node Nref included in the sub-pixel driving circuit, the sub-pixel driving circuit included in the unit pixel UP can solve image quality problems such as vertical brightness non-uniformity or crosstalk on the display panel by providing a driving current to the light-emitting diode EL that does not include a high potential voltage, where a high potential voltage may cause a voltage drop in the voltage application line.

[0104] The sub-pixel driving circuit and electroluminescent display device according to embodiments of the present disclosure can be described as follows.

[0105] According to embodiments of this disclosure, an electroluminescent display device includes: a pixel comprising a plurality of sub-pixels; a plurality of power lines for providing power voltage to the plurality of sub-pixels; a data line for providing data signals to the plurality of sub-pixels; a plurality of gate lines for providing gate signals to the plurality of sub-pixels; and a reference node line for connecting a plurality of reference nodes included in the plurality of sub-pixels. Each sub-pixel includes a light-emitting diode (LED) and a sub-pixel driving circuit for controlling the light emission of the LED. The sub-pixel driving circuit provides a driving current to the LED, excluding high-potential voltages, due to a reference voltage applied from one of the power lines to the reference node included in the sub-pixel. A portion of the sub-pixels includes a compensation transistor connected to the reference node for receiving the reference voltage. Therefore, since a reference voltage is applied to the reference node of the sub-pixel connected via the reference node line, the reference voltage provided to the reference node through the compensation transistor included in a portion of the sub-pixel can solve the image quality problem of the electroluminescent display device by providing a driving current to the LED that is unaffected by high-potential voltages.

[0106] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a plurality of sub-pixels may be located at the intersection of a plurality of gate lines in the row direction and a data line in the column direction, and a reference node line may be connected to a plurality of reference nodes included in a plurality of sub-pixels arranged in the row direction.

[0107] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the power lines may include a high-potential voltage line for providing a high-potential voltage, a reference voltage line for providing a reference voltage, and an initialization voltage line for providing initialization voltages to a plurality of sub-pixels, and a compensation transistor may be connected to a reference node and a reference voltage line.

[0108] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the plurality of gate lines may include scan lines for providing scan signals and emitter lines for providing emitter signals.

[0109] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a plurality of sub-pixels may be arranged in the nth row and may receive the (n-1)th scan signal and the nth scan signal respectively through the (n-1)th scan line and the nth scan line.

[0110] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a sub-pixel may include: a sub-pixel including a first compensation transistor, the first compensation transistor being controlled by an (n-1)th scan signal and connected to a reference voltage line for providing a reference voltage; and a sub-pixel including a second compensation transistor, the second compensation transistor being controlled by an nth scan signal and connected to the reference voltage line.

[0111] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a pixel may be the smallest unit capable of representing all colors, a plurality of subpixels included in a pixel may be arranged in a direction in which a plurality of gate lines are arranged, and a subpixel driving circuit for at least two subpixels may include a compensation transistor.

[0112] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a pixel may be the smallest unit capable of representing all colors, a plurality of sub-pixels included in a pixel may be arranged in a direction having at least two gate lines and at least two data lines, and the sub-pixel driving circuit of the sub-pixel in the sub-pixel in the at least one data line may include a compensation transistor.

[0113] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a sub-pixel driving circuit includes a driving transistor for uniformly providing a driving current to a light-emitting diode. The sub-pixel driving circuit includes a first initialization period for initializing the gate node of the driving transistor, a sampling and second initialization period for sampling a threshold voltage of the driving transistor and initializing the light-emitting diode, a holding period for holding a data voltage applied through a data line, and a light-emitting period for allowing the light-emitting diode to emit light through a driving current generated based on the data voltage. A reference voltage may be applied to a reference node during the first initialization period and the sampling and second initialization periods.

[0114] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the sub-pixel driving circuit may include a capacitor for charging a data voltage, and one end of the capacitor may be connected to a reference node and the other end of the capacitor may be connected to the gate node of a driving transistor.

[0115] According to embodiments of this disclosure, an electroluminescent display device includes a unit pixel in a minimal region where all colors can be represented by a combination of the three primary colors. The unit pixel includes at least one sub-pixel including a first compensation transistor and at least one sub-pixel including a second compensation transistor. Each sub-pixel includes a reference node for providing a reference voltage transmitted through a light-emitting diode, a driving transistor, a switching transistor, a capacitor, and either the first or second compensation transistor. Reference node lines for connecting the reference nodes are arranged within the unit pixel. Therefore, since a reference voltage is applied to the reference nodes of the sub-pixels included in the unit pixel through the compensation transistors, and to the reference nodes of other sub-pixels within the unit pixel through the reference node lines, a driving current unaffected by high-potential voltages can be provided to the light-emitting diodes, thereby solving the image quality problem of the electroluminescent display device.

[0116] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the light-emitting diode may include an anode to which a driving current is applied to allow the light-emitting diode to emit light, and a cathode to which a low potential voltage is applied. The gate of the driving transistor may be connected to one end of a capacitor. A high potential voltage and a data voltage may be applied to the source of the driving transistor through a switching transistor, and the other end of the capacitor may be connected to a reference node.

[0117] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the reference voltage may be a voltage value between a high potential voltage and a low potential voltage.

[0118] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a unit pixel may include at least three sub-pixels for emitting red light, blue light, and green light.

[0119] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the first compensation transistor and the second compensation transistor may be connected to different gate lines and thus turn on at different timings.

[0120] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a reference node of a sub-pixel that does not include the first compensation transistor and the second compensation transistor in a unit pixel can be connected to a reference node line, thereby allowing a reference voltage to be applied to the reference node.

[0121] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a unit pixel may include a sub-pixel arranged in the nth pixel line, the gate of the first compensation transistor and the gate of the second compensation transistor may be connected to the (n-1)th scan line and the nth scan line, respectively, and the first electrode of the first compensation transistor and the first electrode of the second compensation transistor may be connected to different reference voltage lines for applying reference voltages, respectively.

[0122] For example, in an electroluminescent display device according to an embodiment of the present disclosure, reference node lines can be arranged per unit pixel, and thus can be separated from reference node lines of adjacent unit pixels.

[0123] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a unit pixel may include a sub-pixel arranged in the (n-1)th pixel line and the nth pixel line, and the gate of the first compensation transistor and the gate of the second compensation transistor may be connected to the (n-1)th scan line and the nth scan line, respectively, and the first electrode of the first compensation transistor and the first electrode of the second compensation transistor may be connected to a reference voltage line for applying a reference voltage.

[0124] For example, in an electroluminescent display device according to an embodiment of the present disclosure, reference node lines can connect unit pixels arranged to be adjacent to each other.

[0125] For example, in an electroluminescent display device according to an embodiment of the present disclosure, at least one sub-pixel may include a light-emitting diode and a sub-pixel driving circuit for controlling the light emission of the light-emitting diode.

[0126] For example, in an electroluminescent display device according to an embodiment of the present disclosure, the sub-pixel driving circuit can provide a driving current to the light-emitting diode without the high potential voltage due to the reference voltage.

[0127] For example, in an electroluminescent display device according to an embodiment of the present disclosure, at least one sub-pixel may be arranged in the nth row and receive the (n-1)th scan signal and the nth scan signal through the (n-1)th scan line and the nth scan line, respectively.

[0128] For example, in an electroluminescent display device according to an embodiment of the present disclosure, a first compensation transistor may be controlled by an (n-1)th scan signal and provided with a reference voltage, and a second compensation transistor may be controlled by an nth scan signal.

[0129] Furthermore, the technology disclosed herein can provide the following configuration:

[0130] 1. An electroluminescent display device, comprising:

[0131] A pixel, which includes multiple sub-pixels;

[0132] Multiple power lines are used to provide power voltage to the multiple sub-pixels;

[0133] A data line, used to provide data signals to the plurality of sub-pixels;

[0134] Multiple gate lines for providing gate signals to the multiple sub-pixels; and

[0135] Reference node lines are used to connect multiple reference nodes included in the plurality of sub-pixels.

[0136] Each sub-pixel includes a light-emitting diode (LED) and a sub-pixel driving circuit for controlling the light emission of the LED. The sub-pixel driving circuit provides a driving current to the LED, excluding high-potential voltages, due to a reference voltage applied from one of the plurality of power lines to a reference node included in the sub-pixel.

[0137] Some of the sub-pixels include a compensation transistor connected to the reference node for receiving a reference voltage.

[0138] 2. The electroluminescent display device according to configuration 1, wherein the plurality of sub-pixels are located at the intersection of the plurality of gate lines in the row direction and the data lines in the column direction, and the reference node lines are connected to the plurality of reference nodes included in the plurality of sub-pixels arranged in the row direction.

[0139] 3. The electroluminescent display device according to configuration 1, wherein the power lines comprise:

[0140] High-potential voltage lines are used to provide high-potential voltages;

[0141] A reference voltage line, which is used to provide a reference voltage; and

[0142] An initialization voltage line is used to provide an initialization voltage to the plurality of sub-pixels.

[0143] The compensation transistor is connected to the reference node and the reference voltage line.

[0144] 4. The electroluminescent display device according to configuration 1, wherein the plurality of gate lines include scan lines for providing scan signals and emitter lines for providing emitter signals.

[0145] 5. The electroluminescent display device according to configuration 4, wherein the plurality of sub-pixels are arranged in the nth row and receive the (n-1)th scan signal and the nth scan signal respectively through the (n-1)th scan line and the nth scan line.

[0146] 6. The electroluminescent display device according to configuration 5, wherein the sub-pixel comprises:

[0147] A sub-pixel including a first compensation transistor, the first compensation transistor being controlled by the (n-1)th scan signal and connected to a reference voltage line for providing a reference voltage; and

[0148] The sub-pixel includes a second compensation transistor, which is controlled by the nth scan signal and connected to the reference voltage line.

[0149] 7. The electroluminescent display device according to configuration 1, wherein the pixel is the smallest unit capable of representing all colors, and the plurality of sub-pixels included in the pixel are arranged in a direction in which the plurality of gate lines are arranged, and

[0150] The sub-pixel driving circuit of at least two sub-pixels in the sub-pixel includes the compensation transistor.

[0151] 8. The electroluminescent display device according to configuration 1, wherein the pixel is the smallest unit capable of representing all colors, and the plurality of sub-pixels included in the pixel are arranged in a direction having at least two gate lines and at least two data lines, and

[0152] The sub-pixel driving circuit of the sub-pixels in at least one data line includes the compensation transistor.

[0153] 9. The electroluminescent display device according to configuration 1, wherein the sub-pixel driving circuit includes a driving transistor for uniformly providing the driving current to the light-emitting diode.

[0154] The sub-pixel driving circuit includes:

[0155] The first initialization period is used to initialize the gate node of the driving transistor;

[0156] The sampling and second initialization period is used to sample the threshold voltage of the driving transistor and initialize the light-emitting diode;

[0157] A hold period for maintaining the data voltage applied through the data line; and a light emission period for allowing the light-emitting diode to emit light through a drive current generated based on the data voltage.

[0158] The reference voltage is applied to the reference node during the first initialization period and during the sampling and second initialization periods.

[0159] 10. The electroluminescent display device according to configuration 9, wherein the sub-pixel driving circuit includes a capacitor for charging the data voltage, and one end of the capacitor is connected to the reference node and the other end of the capacitor is connected to the gate node of the driving transistor.

[0160] 11. An electroluminescent display device, comprising:

[0161] The unit pixel is the smallest region within which all colors can be represented by a combination of the three primary colors.

[0162] The unit pixel includes: at least one sub-pixel including a first compensation transistor and at least one sub-pixel including a second compensation transistor.

[0163] The at least one sub-pixel includes a reference node for providing a reference voltage transmitted through a light-emitting diode, a driving transistor, a switching transistor, a capacitor, and a first compensation transistor or a second compensation transistor, and

[0164] Reference node lines for connecting the reference nodes are arranged in the unit pixel.

[0165] 12. The electroluminescent display device according to configuration 11, wherein the light-emitting diode includes an anode to which a driving current is applied to allow the light-emitting diode to emit light, and a cathode to which a low potential voltage is applied.

[0166] 13. The electroluminescent display device according to configuration 11, wherein the gate of the driving transistor is connected to one end of the capacitor, a high potential voltage and a data voltage are applied to the source of the driving transistor through the switching transistor, and the other end of the capacitor is connected to the reference node.

[0167] 14. The electroluminescent display device according to configuration 11, wherein the reference voltage is a voltage value between a high potential voltage and a low potential voltage.

[0168] 15. The electroluminescent display device according to configuration 11, wherein the unit pixel includes at least three sub-pixels for emitting red light, blue light and green light.

[0169] 16. The electroluminescent display device according to configuration 11, wherein the first compensation transistor and the second compensation transistor are connected to different gate lines and are therefore turned on at different timings.

[0170] 17. The electroluminescent display device according to configuration 11, wherein the at least one sub-pixel includes: the light-emitting diode; and a sub-pixel driving circuit for controlling the light emission of the light-emitting diode.

[0171] 18. The electroluminescent display device according to configuration 17, wherein the sub-pixel driving circuit provides a driving current to the light-emitting diode excluding a high-potential voltage due to the reference voltage.

[0172] 19. The electroluminescent display device according to configuration 11, wherein the at least one sub-pixel is arranged in the nth row and receives the (n-1)th scan signal and the nth scan signal through the (n-1)th scan line and the nth scan line, respectively.

[0173] 20. The electroluminescent display device according to configuration 19, wherein the first compensation transistor is controlled by the (n-1)th scan signal and provides the reference voltage, and the second compensation transistor is controlled by the nth scan signal.

[0174] It will be apparent to those skilled in the art that the present disclosure is not limited to the described embodiments and drawings, and that various substitutions, modifications, and alterations may be made within the present disclosure without departing from its spirit or scope. Therefore, the scope of the present disclosure is defined by the appended claims, and all modifications or variations derived from the meaning, scope, and equivalents of the claims are intended to fall within the scope of the present disclosure.

[0175] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications cited in and / or listed in the application data sheets are incorporated herein by reference. If it is necessary to employ concepts from various patents, applications, and publications to provide other embodiments, aspects of this embodiment may be modified. These and other changes may be made to this embodiment based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents granted by such claims. Therefore, the claims are not limited by the disclosure.

Claims

1. An electroluminescent display device, comprising: The pixels that exist in the smallest region where all colors can be represented by multiple sub-pixels; Multiple power lines are used to provide power voltage to the multiple sub-pixels; A data line, used to provide data signals to the plurality of sub-pixels; Multiple gate lines are used to provide gate signals to the multiple sub-pixels; as well as Reference node lines are used to connect multiple reference nodes included in the plurality of sub-pixels. Among the plurality of sub-pixels of a pixel, some sub-pixels include: A sub-pixel including a first compensation transistor, the first compensation transistor being connected to a reference node for receiving a reference voltage, and A sub-pixel including a second compensation transistor, the second compensation transistor being connected to a reference node for receiving a reference voltage; and The first compensation transistor and the second compensation transistor are connected to different gate lines and are turned on at different times.

2. The electroluminescent display device according to claim 1, wherein, Each of the sub-pixels includes a light-emitting diode and a sub-pixel driving circuit for controlling the light emission of the light-emitting diode.

3. The electroluminescent display device according to claim 1, wherein, The plurality of sub-pixels are located at the intersection of the plurality of gate lines in the row direction and the data lines in the column direction, and the reference node lines are connected to the plurality of reference nodes included in the plurality of sub-pixels arranged in the row direction.

4. The electroluminescent display device according to claim 1, wherein, The power lines include: High-potential voltage lines are used to provide high-potential voltages; A reference voltage line, which is used to provide a reference voltage; and An initialization voltage line is used to provide an initialization voltage to the plurality of sub-pixels. The first compensation transistor and the second compensation transistor are each connected to a corresponding reference node and a corresponding reference voltage line.

5. The electroluminescent display device according to claim 1, wherein, The plurality of gate lines include scan lines for providing scan signals and transmit lines for providing transmit signals.

6. The electroluminescent display device according to claim 5, wherein, The plurality of sub-pixels are arranged in the nth row and receive the (n-1)th scan signal and the nth scan signal respectively through the (n-1)th scan line and the nth scan line.

7. The electroluminescent display device according to claim 6, wherein, The power lines include reference voltage lines for providing a reference voltage. The first compensation transistor is controlled by the (n-1)th scan signal and connected to the reference voltage line; and The second compensation transistor is controlled by the nth scan signal and connected to the reference voltage line.

8. The electroluminescent display device according to claim 2, wherein, The plurality of sub-pixels included in the pixel are arranged in the direction in which the plurality of gate lines are arranged, and The sub-pixels include at least two sub-pixels.

9. The electroluminescent display device according to claim 2, wherein, The plurality of sub-pixels included in the pixel are arranged in a direction in which at least two gate lines and at least two data lines are arranged, and The sub-pixels include multiple sub-pixels in at least one data line.

10. The electroluminescent display device according to claim 2, wherein, The sub-pixel driving circuit includes a driving transistor for uniformly providing driving current to the light-emitting diode. The sub-pixel driving circuit includes: The first initialization period is used to initialize the gate node of the driving transistor; The sampling and second initialization period is used to sample the threshold voltage of the driving transistor and initialize the light-emitting diode; A hold period is used to maintain the data voltage applied through the data line; and The light-emitting period is used to allow the light-emitting diode to emit light through a drive current generated based on the data voltage, and The reference voltage is applied to the reference node during the first initialization period and during the sampling and second initialization periods.

11. The electroluminescent display device according to claim 10, wherein, The sub-pixel driving circuit includes a capacitor for charging the data voltage, with one end of the capacitor connected to the reference node and the other end of the capacitor connected to the gate node of the driving transistor.

12. The electroluminescent display device according to claim 2, wherein, The light-emitting diode includes an anode to which a driving current is applied to allow the light-emitting diode to emit light, and a cathode to which a low potential voltage is applied.

13. The electroluminescent display device according to claim 11, wherein, The gate of the driving transistor is connected to one end of the capacitor, a high potential voltage and a data voltage are applied to the source of the driving transistor through a switching transistor, and the other end of the capacitor is connected to the reference node.

14. The electroluminescent display device according to claim 1, wherein, The reference voltage is the voltage value between the high potential voltage and the low potential voltage.

15. The electroluminescent display device according to claim 1, wherein, The plurality of sub-pixels further includes: at least one sub-pixel excluding a compensation transistor, the at least one sub-pixel including a reference node for providing a reference voltage transmitted through a reference node line, a light-emitting diode, a driving transistor, a switching transistor, and a capacitor.

16. The electroluminescent display device according to claim 15, wherein, The partial sub-pixels and the at least one sub-pixel include sub-pixels for emitting red, blue, and green light.

17. The electroluminescent display device according to claim 2, wherein, The sub-pixel driving circuit provides the light-emitting diode with a driving current excluding high-potential voltages due to the reference voltage.

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