Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, which are applied to the technical field of display. The display panel comprises an FDC area, the FDC area comprises N pixel circuit queues distributed longitudinally, N is a positive integer; wherein: the anode reset voltages of each pixel circuit in each pixel circuit queue are the same, and the value of the anode reset voltage of each pixel circuit is inversely proportional to the horizontal distance between the pixel circuit queue and the axis in the FDC area. Through the scheme, the picture quality uniformity of the FDC area can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] FDC (Full Display with Camera) technology achieves a true full-screen display by hiding the camera under the screen.

[0003] For display panels using FDC (Film Direct Conversion) technology, there is a significant loading between the anode and pixel in the pixel circuitry within the FDC area (the area where the camera is hidden in the display panel). The closer a pixel circuit is to the central axis of the FDC area, the greater the loading between its anode and pixel. This results in poor image quality uniformity in the FDC area under low brightness conditions. Figure 1 As shown, the image quality uniformity of the FDC area is poor, specifically manifested in the fact that the brightness of the FDC aperture area decreases from both sides to the middle, and there is a dark bar in the middle of the FDC aperture area.

[0004] Therefore, how to improve the image quality uniformity in the FDC region is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel and display device to improve the image quality uniformity in the FDC (Free Concentration Control) area. The specific technical solution is as follows:

[0006] In a first aspect, embodiments of the present invention provide a display panel, the display panel including an FDC region, the FDC region including N vertically distributed pixel circuit queues, where N is a positive integer; wherein:

[0007] The anode reset voltage of each pixel circuit in each pixel circuit queue is the same, and the magnitude of the anode reset voltage of each pixel circuit is inversely proportional to the horizontal distance between the pixel circuit queue and the axis of the FDC region.

[0008] Optionally, each pixel circuit includes an anode reset switch device, and each pixel circuit queue is provided with an anode reset line for providing the anode reset voltage.

[0009] The anode reset line of each pixel circuit queue is electrically connected to the input terminal of the anode reset switch device of each pixel circuit in that pixel circuit queue.

[0010] Optionally, the display panel further includes a voltage divider having M output terminals with different output voltages, where M is a positive integer greater than or equal to N / 2; where:

[0011] For each pixel circuit queue in the N pixel circuit queues, the input terminal of the anode reset line of the pixel circuit queue is electrically connected to the output terminal corresponding to the pixel circuit queue among the M output terminals; wherein, the smaller the horizontal distance between the pixel circuit queue and the axis in the FDC region, the smaller the maximum voltage difference of the output terminal. The maximum voltage difference of each output terminal is the difference between the maximum voltage output by the M output terminals and the voltage output by the output terminal.

[0012] Optionally, the input terminals of the anode reset lines of the two pixel circuit queues symmetrically distributed around the central axis within the FDC region are electrically connected to the same output terminal of the voltage divider.

[0013] Optionally, the voltage divider is disposed within the display chip of the display panel; the output terminal of the voltage divider is connected to the output pin of the display chip;

[0014] For each pixel circuit queue in the N pixel circuit queues, the input terminal of the anode reset line of the pixel circuit queue is connected to the output pin of the corresponding output terminal of the pixel circuit queue.

[0015] Optionally, the display chip further includes: a voltage conversion unit; the voltage conversion unit is used to convert the input voltage of the display chip into a preset voltage output, wherein:

[0016] The output of the voltage conversion unit is connected to the input of the voltage divider.

[0017] Optionally, the voltage conversion unit is a charge pump.

[0018] Optionally, the voltage output by each output terminal of the voltage divider is greater than or equal to -3V and less than or equal to -1.8V.

[0019] Optionally, the voltage divider is a resistive voltage divider.

[0020] Optionally, the anode reset switch for each pixel circuit is an anode reset transistor; wherein:

[0021] The first terminal of the anode reset transistor of each pixel circuit is electrically connected to the anode reset line of the pixel circuit queue.

[0022] The second terminal of the anode reset transistor of each pixel circuit is connected to the anode of that pixel circuit;

[0023] The control electrode input of the anode reset transistor in each pixel circuit is the anode reset control signal that controls the anode reset.

[0024] In a second aspect, embodiments of the present invention provide a display device, including a display panel as described in the first aspect.

[0025] Beneficial effects of the embodiments of the present invention:

[0026] This invention provides a display panel and display device. The display panel includes a Field-Controlled Display (FDC) region, which comprises N vertically distributed pixel circuit queues. Each pixel circuit in each queue has the same anode reset voltage, and the magnitude of the anode reset voltage is inversely proportional to the horizontal distance between the pixel circuit queue and the axis of the FDC region. Since pixel circuits closer to the axis of the FDC region have a greater load between their anode and pixel, and in this invention, the same anode reset voltage for each pixel circuit in the display panel's pixel circuit queue, with the anode reset voltage inversely proportional to the horizontal distance between the pixel circuit queue and the axis of the FDC region, means that pixel circuits closer to the axis of the FDC region have a greater anode reset voltage. In other words, pixel circuits with greater load between their anode and pixel have a greater anode reset voltage, thus allowing pixel circuits with different loads between their anode and pixel to achieve the same display effect. Therefore, this invention can improve the image quality uniformity of the FDC region.

[0027] Of course, implementing any product or method of the present invention does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0029] Figure 1 This is a schematic diagram illustrating uneven image quality in an FDC (Image Capability Distortion) region.

[0030] Figure 2 A schematic diagram of the load between the anode and the pixel in a pixel circuit within an FDC region, provided as an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a first type of display panel provided in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of the first type of FDC region provided in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the second type of FDC region provided in an embodiment of the present invention;

[0034] Figure 6A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0035] Figure 7 A schematic diagram of the third type of FDC region provided in an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of the structure of a second type of display panel provided in an embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of a voltage divider provided in an embodiment of the present invention;

[0038] Figure 10 This is a schematic diagram of the connection between the first type of FDC region and the voltage divider provided in an embodiment of the present invention;

[0039] Figure 11 This is a schematic diagram of the connection between the second type of FDC region and the voltage divider provided in an embodiment of the present invention;

[0040] Figure 12 This is a schematic diagram of the structure of a third type of display panel provided in an embodiment of the present invention;

[0041] Figure 13 This is a schematic diagram showing the connection of various components of a display panel according to an embodiment of the present invention;

[0042] Figure 14 A display chip output architecture diagram provided in an embodiment of the present invention;

[0043] Figure 15 This is a schematic diagram of the structure of a fourth type of display panel provided in an embodiment of the present invention;

[0044] Figure 16 This is a schematic diagram of the connection structure between a charge pump and a pressure divider provided in an embodiment of the present invention;

[0045] Figure 17 This is a schematic diagram of the structure of a fifth type of display panel provided in an embodiment of the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on the present invention are within the scope of protection of the present invention.

[0047] FDC (Full Display with Camera) technology achieves a true full-screen display by hiding the camera under the screen. In existing technologies, the FDC area exhibits good image quality uniformity when displaying high-brightness images, but poor uniformity when displaying low-brightness or low-grayscale images. The reason for the poor image quality uniformity in the FDC area is that there is a significant load between the anode and the pixel (i.e., the display) in the pixel circuit within the FDC area. Furthermore, the load between the anode and the pixel varies with the horizontal distance between the pixel circuit and the central axis of the FDC area.

[0048] like Figure 2 As shown in the figure, this embodiment of the invention provides a schematic diagram of the load between the anode and the pixel in a pixel circuit within an FDC region. Figure 2 The circular area in the middle represents the FDC (Fixed Directional Control) region. The dashed line within the circular area is the central axis of the FDC region. The enlarged area on the left is a magnified view of the rectangular frame within the FDC region. Each square in the enlarged area represents the pixel circuitry of each pixel within the FDC region. R1, R2…, R6 within the square represent the load between the anode of the pixel circuitry and the pixel. Figure 2 It can be seen that the load between the anode and the pixel is the same for each pixel circuit in the same column. For example, in the magnified area, the load between the anode and the pixel of each pixel circuit in the first column on the left is R6, and the load between the anode and the pixel of each pixel circuit in the first column on the right is R1. Since the pixel circuits are outside the FDC area, and according to the display panel (Panel) traces, the closer the pixel circuit is to the central axis, the greater the load between its anode and the pixel, and vice versa. Therefore, in the above magnified area, R1 > R2 > R3 > R4 > R5 > R6.

[0049] It should be noted that, for the FDC region, the pixel circuit queues are symmetrically distributed along the central axis. This means that, in the left half of the FDC region, the load between the anode and the pixel increases from left to right, while in the right half, the load increases from right to left. Since the pixel circuit queues in the left and right halves of the FDC region are symmetrically distributed, for every pixel circuit queue in the left half, there is at least one other pixel circuit queue in the right half with the same load between its anode and pixel, and the two pixel circuit queues are symmetrically distributed along the central axis.

[0050] To improve the image quality uniformity in the FDC region, such as Figure 3As shown in the diagram, this embodiment of the invention provides a structural schematic of a display panel 300. The display panel 300 includes an FDC region 301, which includes N vertically distributed pixel circuit queues, where N is a positive integer; wherein:

[0051] The anode reset voltage of each pixel circuit in each pixel circuit queue is the same, and the magnitude of the anode reset voltage of each pixel circuit is inversely proportional to the horizontal distance between the pixel circuit queue and the axis of the FDC region.

[0052] like Figure 4 As shown, when N is an even number, this embodiment of the invention provides a schematic diagram of an FDC region. In this example, the pixel circuit queues from column 1 to column N / 2 are located in the left half of the FDC region, and the load between the anode and the pixel increases sequentially from left to right. The load between the anode and the pixel is the largest in each pixel circuit in column N / 2. The pixel circuit queues from column N / 2+1 to column N are located in the right half of the FDC region, and the load between the anode and the pixel increases sequentially from right to left. The load between the anode and the pixel is the largest in each pixel circuit in column N / 2+1. Since the pixel circuit queues in the left and right halves of the FDC region are symmetrically distributed, for each pixel circuit queue in the left half of the FDC region, there is at least one other pixel circuit queue in the right half with the same load between its anode and pixel, and the two pixel circuit queues are symmetrically distributed along the central axis. For example... Figure 4 The first and Nth column pixel circuit queues, the second and N-1th column pixel circuit queues, the third and N-2th column pixel circuit queues, and the N / 2th and N / 2+1th column pixel circuit queues.

[0053] like Figure 5 As shown, when N is an odd number, this embodiment of the invention provides a schematic diagram of an FDC region. In this example, the (N+1) / 2th column of pixel circuits is located on the central axis of the FDC region, the 1st to (N+1) / 2-1st columns of pixel circuits are located in the left half of the FDC region, and the (N+1) / 2+1st to Nth columns of pixel circuits are located in the right half of the FDC region. Among the N vertically distributed pixel circuit columns, the pixel circuits in the (N+1) / 2th column of pixel circuits have the largest load between the anode and the pixel, and the load decreases sequentially towards both sides. Similarly, except for the (N+1) / 2th column of pixel circuits located on the central axis, for each pixel circuit column in the left half of the FDC region, there is at least one other pixel circuit column in the right half with the same load between its anode and the pixel, and the two pixel circuit columns are symmetrically distributed along the central axis. For example... Figure 5The first and Nth column pixel circuit queues, the second and N-1th column pixel circuit queues, and the third and N-2th column pixel circuit queues are in the same array.

[0054] Within the FDC region, the smaller the horizontal distance between a pixel circuit queue and the central axis of the FDC region, the greater the load between the anode and the pixel of each pixel circuit, resulting in poor image quality uniformity in the FDC region. To improve image quality uniformity in the FDC region, in this invention, the anode reset voltage of each pixel circuit in each pixel circuit queue is the same, and the magnitude of the anode reset voltage value of each pixel circuit is inversely proportional to the horizontal distance between the pixel circuit queue and the central axis of the FDC region.

[0055] The aforementioned anode reset voltage is the voltage after anode reset in the pixel circuit, such as... Figure 6 The diagram shows a schematic of a pixel circuit. Vinit2 represents the anode reset voltage of the pixel circuit within the FDC region. After the pixel circuit is reset, the voltage at node N4 becomes the anode reset voltage. VDD represents the first power supply signal, VSS represents the second power supply signal, T1-T7 represent thin-film transistors, Cst represents a capacitor, Reset represents the capacitor reset signal, Vinit1 represents the capacitor reset voltage, Gate represents the gate control signals for thin-film transistors T2 and T4, EM represents the light emission control signal, Vdata represents the data signal, and N1-N4 represent nodes.

[0056] Since the load between the anode and the pixel is the same in each pixel circuit within the same pixel circuit queue, the anode reset voltage of each pixel circuit in the same pixel circuit queue is set to be the same in order to ensure the uniformity of image quality distribution in the vertical direction. Simultaneously, since the horizontal distance between a pixel circuit queue and the central axis of the FDC region is smaller, the load between the anode and the pixel of each pixel circuit within it is larger. A larger load results in lower brightness when displaying low-brightness or low-grayscale images. To ensure the uniformity of image quality distribution in the horizontal direction, pixel circuits with larger loads require larger anode reset voltages. Therefore, in this embodiment, the anode reset voltage of each pixel circuit is set to be inversely proportional to the horizontal distance between the pixel circuit queue and the central axis of the FDC region. That is, the anode reset voltage of each pixel circuit in a pixel circuit queue with a smaller horizontal distance from the central axis of the FDC region is larger, and the anode reset voltage of each pixel circuit in a pixel circuit queue with a larger horizontal distance from the central axis of the FDC region is smaller. This ensures that pixel circuits with larger loads have larger anode reset voltages, thereby effectively improving the image quality uniformity in the FDC region.

[0057] For example, its above Figure 4 The example shown illustrates this. Figure 4In the N / 2 column pixel circuit queue, compared to the N / 2-1 column, the horizontal distance between the N / 2 column pixel circuit queue and the axis of the FDC region is smaller. Therefore, the load between the anode and the pixel in the N / 2 column pixel circuit queue is larger. At the same time, due to the smaller horizontal distance between the anode and the axis of the FDC region, the anode reset voltage is larger. Therefore, although the load between the anode and the pixel in the N / 2 column pixel circuit queue is greater than that in the N / 2-1 column pixel circuit queue, the anode reset voltage in the N / 2 column pixel circuit queue is also greater than that in the N / 2-1 column pixel circuit queue. This makes the display effect of the pixels in the N / 2 column pixel circuit queue basically the same as that in the N / 2-1 column pixel circuit queue, thus greatly improving the image quality uniformity in the FDC region.

[0058] To ensure that the anode reset voltage of all pixel circuits in each pixel circuit queue is the same, one implementation method involves individually controlling each pixel circuit in each pixel circuit queue to achieve the same anode reset voltage. Furthermore, considering the complexity of individually controlling each pixel circuit, this embodiment of the invention also provides another implementation method, such as... Figure 7 As shown, this embodiment of the invention also provides a schematic diagram of an FDC region. Each pixel circuit queue in the FDC region is provided with an anode reset line for providing the anode reset voltage. For example... Figure 7 The V1-VN anode reset lines shown correspond to one anode reset line for each pixel circuit queue. The anode reset line for each pixel circuit queue provides the anode reset voltage for each pixel circuit within that queue.

[0059] Optionally, in one implementation, each pixel circuit includes an anode reset switch device. In this case, the anode reset line of each pixel circuit queue is electrically connected to the input terminal of the anode reset switch device of each pixel circuit in the pixel circuit queue.

[0060] The aforementioned anode reset switch is a switch device for controlling the pixel circuit to perform anode reset. In one implementation, the anode reset switch can be an anode reset transistor, which can be a thin-film transistor (TFT), as described above. Figure 6 T7 is shown. Optionally, the first terminal of the anode reset transistor of each pixel circuit is electrically connected to the anode reset line of the pixel circuit queue. When the anode reset transistor is a thin-film transistor, the aforementioned first terminal can be the source terminal of the thin-film transistor, such as... Figure 6The source input of T7 is Vinit2. The second terminal of the anode reset transistor of each pixel circuit is connected to the anode of that pixel circuit. When the anode reset transistor is a thin-film transistor, the aforementioned second terminal can be the drain of the thin-film transistor, such as... Figure 6 The drain of T7 is connected to node N4, where the anode is located. The gate of the anode reset transistor in each pixel circuit receives the anode reset control signal. When the anode reset transistor is a thin-film transistor (TFT), the aforementioned control electrode can be the gate of the TFT. This anode reset control signal is as follows: Figure 6 The gate signal Gate-1 controls the conduction and cutoff of T7. During an anode reset, Gate-1 controls T7 to conduct, and the anode reset voltage Vinit2 is written to node N4, completing the anode reset of the pixel circuit. When an anode reset is not required, Gate-1 controls T7 to cut off. In this embodiment, when each pixel circuit includes an anode reset switch, the anode reset line of each pixel circuit queue is electrically connected to the input terminals of the anode reset switches of each pixel circuit in that queue. That is, the input terminals of the anode reset switches of each pixel circuit in each queue are connected to the anode reset line of that queue, thereby ensuring that the anode reset voltage of each pixel circuit in the same queue is the same.

[0061] like Figure 8 As shown in the figure, the present invention also provides a schematic diagram of the structure of a display panel. The display panel 300 further includes a voltage divider 302, wherein the voltage divider has M output terminals with different output voltages, and M is a positive integer greater than or equal to N / 2. Figure 8 In the middle, voltage divider 302 includes O1-O M There are M output terminals in total, and the voltage output by each of the M output terminals is different, for example, V. O1 >V O2 >…>V OM , or V O1 <V O2 <...<V OM , where V Oi This is the voltage output by the i-th output terminal.

[0062] In one implementation, when the anode reset voltage of the pixel circuit is negative, the voltage output by each output terminal of the aforementioned voltage divider can be greater than or equal to -3V and less than or equal to -1.8V. At this time, in V... O1 <V O2 <...<V OM In the case of V O1 Greater than or equal to -3V, V OM Greater than or equal to -1.8V.

[0063] The voltage divider described above can be of any type. Optionally, in one implementation, to simplify the process, the voltage divider can be a resistive voltage divider. For example... Figure 9 As shown in the figure, an embodiment of the present invention provides a schematic diagram of a voltage divider. The voltage divider in the figure includes R1-R connected in series. M-1 There are a total of M-1 resistors, each with two output terminals, serving as the output terminals of the voltage divider. In one implementation, since the load difference between the anode and pixel of every two pixel driving circuits on the left and right sides of the FDC region is almost constant, in order to further reduce the process complexity, the above R1=R2=…=R M-1 .

[0064] It should be noted that a voltage divider having M output terminals with different output voltages does not mean that the voltage divider only contains M output terminals. For example, in addition to M output terminals with different output voltages, a voltage divider can also have multiple output terminals with the same output voltage. Figure 8 The voltage divider shown contains O1-O M Output terminals, each with multiple output terminals, such as including 2 O1 output terminals, 2 O... M Output terminals, etc.

[0065] To ensure that each pixel circuit queue within the FDC region receives a satisfactory anode reset voltage, M is a positive integer greater than or equal to N / 2. As previously stated, since the pixel circuit queues within the FDC region are symmetrically distributed along their central axis, and the load between the anode and pixel is the same in both symmetrically distributed queues, the required anode reset voltage can also be the same for both queues. Therefore, to ensure that each pixel circuit queue within the FDC region receives a satisfactory anode reset voltage, the number of output terminals with different voltages from the voltage divider should be a positive integer greater than or equal to N / 2. For example, when N is 1000, M needs to be greater than or equal to 500; when N is 1001, M needs to be greater than or equal to 501.

[0066] For each of the N pixel circuit queues, the input terminal of the anode reset line of that pixel circuit queue is electrically connected to the output terminal corresponding to that pixel circuit queue among the M output terminals. The pixel circuit queue with the smaller horizontal distance from the axis of the FDC region corresponds to the smaller the maximum voltage difference at its output terminal. The maximum voltage difference at each output terminal is the difference between the maximum voltage output by the M output terminals and the voltage output by that output terminal.

[0067] Among them, the smaller the horizontal distance between the pixel circuit queue and the central axis in the FDC region, the smaller the maximum voltage difference at the output terminal. This means that the output voltage of the pixel circuit queue with the smaller horizontal distance between it and the central axis in the FDC region is greater.

[0068] For example, as mentioned above Figure 4 The example shown illustrates this. The left half of the FDC region includes the pixel circuit queues from column 1 to column N / 2. The horizontal distance between these queues and the axis of the FDC region gradually decreases. This means that the required output voltage of the output terminals corresponding to the pixel circuit queues from column 1 to column N / 2 gradually increases. Specifically, the output voltage of the output terminal corresponding to column 1 is less than that of column 2, and so on, until the output voltage of column N / 2-1 is less than that of column N / 2. Let M take the minimum value N / 2, and V... O1 <V O2 <...<V OM To explain, as follows Figure 10 As shown, the output terminal corresponding to the first column of the pixel circuit queue is O1, the output terminal corresponding to the second column of the pixel circuit queue is O2, and so on, with the output terminal corresponding to the N / 2th column of the pixel circuit queue being O1. M Furthermore, the right half of the FDC region includes the pixel circuit queues from column N / 2+1 to column N, whose horizontal distance from the axis of the FDC region gradually decreases, resulting in the output terminal corresponding to column N / 2+1 being O. M The output terminal O corresponding to the N / 2+2th column of the pixel circuit queue M-1 (Not shown in the figure), and so on, the output terminal corresponding to the Nth column of the pixel circuit queue is O1.

[0069] To give another example, using the above... Figure 5 For illustration, the left half of the FDC region includes the pixel circuit queues from column 1 to column (N+1) / 2-1. The horizontal distance between these queues and the axis of the FDC region gradually decreases. This means that the output voltage required by the output terminals corresponding to the pixel circuit queues from column 1 to column (N+1) / 2-1 gradually increases, and the output voltage required by the output terminal corresponding to the pixel circuit queue located on the central axis (N+1) / 2 is the largest. Let M take the minimum value (N+1) / 2, and V... O1 <V O2 <...<V OM To explain, as follows Figure 11As shown, the output terminal corresponding to the first column of the pixel circuit queue is O1, the output terminal corresponding to the second column of the pixel circuit queue is O2, and so on, the output terminal corresponding to the (N+1) / 2-1th column of the pixel circuit queue is O2. M-1 The output terminal corresponding to the (N+1) / 2th column of the pixel circuit queue is O. M Furthermore, the right half of the FDC region includes the pixel circuit queues from column (N+1) / 2+1 to column N, whose horizontal distance from the axis of the FDC region gradually decreases, resulting in the output terminal corresponding to column (N+1) / 2+1 being O. M-1 The output terminal corresponding to the (N+1) / 2+2th column of the pixel circuit queue is O. M-2 (Not shown in the figure), and so on, the output terminal corresponding to the Nth column of the pixel circuit queue is O1.

[0070] In one implementation, to reduce process complexity, the input terminals of the anode reset lines of two pixel circuit queues symmetrically distributed along the central axis within the FDC region are electrically connected to the same output terminal of the voltage divider, such as... Figure 10 , Figure 11 In the diagram, the first column of pixel circuits and the Nth column of pixel circuits are symmetrically distributed about the central axis. Therefore, the input terminals of the anode reset lines of the first column of pixel circuits and the Nth column of pixel circuits are both connected to the output terminal O1 of the voltage divider.

[0071] Optional, such as Figure 12 As shown in the diagram, this embodiment of the invention also provides a schematic diagram of a display panel structure. The voltage divider 302 can be disposed within the display chip 303 of the display panel; the output terminal of the voltage divider 302 is connected to the output pin of the display chip 303. Figure 12 As shown, the display chip 303 includes M output pins P1-P1 for connecting to the display chip 303. M .

[0072] In this case, for each pixel circuit queue in the N pixel circuit queues, the input terminal of the anode reset line of that pixel circuit queue is connected to the output pin connected to the corresponding output terminal of that pixel circuit queue. For example, as shown... Figure 13 As shown in the diagram, this embodiment of the invention provides a connection diagram of the various components of a display panel. For each pixel circuit queue, the input terminal of the anode reset line of the pixel circuit queue is connected to the output pin connected to the corresponding output terminal of the pixel circuit queue.

[0073] In one implementation, the output pin of the display chip 303 connected to the output terminal of the voltage divider 302 can be a dummy pin (virtual pin) among the pins included in a display chip in the related art. This dummy pin is an unused pin among the pins included in the display chip. Simply put, existing DICs (Display Chips) contain three or four rows of output pins, symmetrically distributed from right to left as GOUT (gate signal output) pin, Vinit (reset voltage) pin, Source (power supply) pin, and dummy pin. Since the dummy pin is an unused pin, the display chip contains a relatively large number of usable output pins. Therefore, in this application, by setting a voltage divider 302 in the display chip 303 and connecting the input terminal of the voltage divider 302 to each dummy pin, the complexity of the manufacturing process can be minimized. Figure 14 The diagram shown is an output architecture diagram of a display chip provided by an embodiment of the present invention. In the diagram, P1-P in the middle of the top row are... M The area is the region where the output pin of the display chip 303 is connected to the output terminal of the voltage divider 302. Figure 14 In the diagram, GOA (Gate Driver on Array) is the gate signal output pin area of ​​the array substrate, and its output gate signal is used to control the control switches in the display panel. Vinit is the reset control signal output pin area, and its output reset control signal is used to control the pixel circuit to reset. SOURCE is the data signal output area, MEMORY is the storage unit, LOGIC is the logic unit, INTERFACE is the protocol unit, and ANALOG is the digital unit.

[0074] Optional, such as Figure 15 As shown in the figure, the present invention also provides a schematic diagram of the structure of a display panel. The display chip 303 further includes a voltage conversion unit 304. The voltage conversion unit 304 is used to convert the input voltage of the display chip 303 into a preset voltage output, wherein the output terminal of the voltage conversion unit 304 is connected to the input terminal of the voltage divider 302.

[0075] In one implementation, when the anode reset voltage of the anode in the pixel circuit is negative, the voltage conversion unit 304 needs to convert the positive voltage input to the input terminal of the display chip 303 into a negative voltage. In this case, the voltage conversion unit can be a charge pump, which can increase or decrease the input voltage and can also be used to generate a negative voltage.

[0076] For a display chip to function properly, it requires three or four voltage inputs: VDDI (1.8V), VCI (3.1V), DVDD (1.2V) (optional), and AVDD (7.6V). These four input voltages are used internally by an LDO (Low Drop Out) unit and a charge pump to generate the various voltages required by the display panel. When the anode reset voltage in the pixel circuit is negative, the charge pump needs to convert the input power supply, such as VCI, to a negative voltage, which is then input to the voltage divider 302.

[0077] In the voltage divider Figure 9 In the case of the resistor divider shown, such as Figure 16 As shown in the diagram, this embodiment of the invention provides a schematic diagram of the connection structure between a charge pump and a voltage divider. The charge pump converts the input voltage VCI into a negative voltage VCIN, which is then transmitted through the voltage divider via its output terminals O1-O1. M The input voltage is the voltage of the voltage divider.

[0078] like Figure 17 As shown in the diagram, this embodiment of the invention also provides a schematic diagram of a display panel structure, in which the anode reset line of each column of pixel circuits within the FDC region is directly connected to the display chip (i.e., the DIC in the figure). Optionally, the source line of each column of pixel circuits within the FDC region can also be directly connected to the display chip. In this case, each column of pixel circuits has a source line and an anode reset line directly connected to the display chip. In this embodiment, a basis for accurately controlling the anode reset voltage of each column of pixel circuits within the FDC region can be provided.

[0079] In another embodiment of the present invention, a display device is also provided, including the display panel provided in the embodiments of the present invention.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the display device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a Field Controlled Pixel Array (FDC) region, which comprises N vertically distributed pixel circuit queues, where N is a positive integer. Within the FDC region, the pixel circuit closer to the axis of the FDC region has a greater load between its anode and the pixel. Wherein: The anode reset voltage of each pixel circuit in each pixel circuit queue is the same, and the magnitude of the anode reset voltage of each pixel circuit is inversely proportional to the horizontal distance between the pixel circuit queue and the axis of the FDC region.

2. The display panel according to claim 1, characterized in that, Each pixel circuit includes an anode reset switch device, and each pixel circuit queue is provided with an anode reset line for providing the anode reset voltage. The anode reset line of each pixel circuit queue is electrically connected to the input terminal of the anode reset switch device of each pixel circuit in that pixel circuit queue.

3. The display panel according to claim 2, characterized in that, The display panel also includes a voltage divider, which has M output terminals with different output voltages, where M is a positive integer greater than or equal to N / 2; where: For each pixel circuit queue in the N pixel circuit queues, the input terminal of the anode reset line of the pixel circuit queue is electrically connected to the output terminal corresponding to the pixel circuit queue among the M output terminals; wherein, the smaller the horizontal distance between the pixel circuit queue and the axis in the FDC region, the smaller the maximum voltage difference of the output terminal. The maximum voltage difference of each output terminal is the difference between the maximum voltage output by the M output terminals and the voltage output by the output terminal.

4. The display panel according to claim 3, characterized in that, The input terminals of the anode reset lines of the two pixel circuit queues symmetrically distributed around the central axis within the FDC region are electrically connected to the same output terminal of the voltage divider.

5. The display panel according to claim 3, characterized in that, The voltage divider is disposed within the display chip of the display panel; the output terminal of the voltage divider is connected to the output pin of the display chip; For each pixel circuit queue in the N pixel circuit queues, the input terminal of the anode reset line of the pixel circuit queue is connected to the output pin of the corresponding output terminal of the pixel circuit queue.

6. The display panel according to claim 5, characterized in that, The display chip further includes: a voltage conversion unit; the voltage conversion unit is used to convert the input voltage of the display chip into a preset voltage output, wherein: The output of the voltage conversion unit is connected to the input of the voltage divider.

7. The display panel according to claim 6, characterized in that, The voltage conversion unit is a charge pump.

8. The display panel according to claim 3, characterized in that, The voltage output from each output terminal of the voltage divider is greater than or equal to -3V and less than or equal to -1.8V.

9. The display panel according to claim 3, characterized in that, The voltage divider is a resistive voltage divider.

10. The display panel according to claim 2, characterized in that, The anode reset switch for each pixel circuit is an anode reset transistor; where: The first terminal of the anode reset transistor of each pixel circuit is electrically connected to the anode reset line of the pixel circuit queue. The second terminal of the anode reset transistor of each pixel circuit is connected to the anode of that pixel circuit; The control electrode input of the anode reset transistor in each pixel circuit is the anode reset control signal that controls the anode reset.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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