A gate drive circuit and driving method thereof, and a display panel

Abstract

The present invention provides a gate drive circuit, a driving method thereof, and a display panel. The gate drive circuit includes a plurality of cascaded shift registers. In the shift register, a first light-emitting control signal output module is configured to transmit a first-level voltage signal provided by a first-level voltage terminal to a first output terminal of the shift register in response to a conduction level of a control terminal of the first light-emitting control signal output module. In a first target mode, during at least a portion of the period when the control terminal of the first light-emitting control signal output module is at a conduction level, a switch module is turned on, and a scan signal output module transmits an enable level of a scan clock signal provided by a first scan clock signal terminal to a second output terminal of the shift register in response to the conduction level of the control terminal of the first light-emitting control signal output module. According to the present invention, the bezel width of the display screen can be effectively reduced, thereby fully realizing a narrow-bezel design for the display screen.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and in particular relates to a gate drive circuit and a driving method thereof, and a display panel. Background Art

[0002] In the field of display panel technology, narrow bezels on displays have always been a sought-after feature in screen design, and they are also popular with users. Therefore, how to achieve narrow bezels is always a hot design topic. Currently, achieving narrow bezels has always been a non-circuit-based improvement design. For example, narrow bezels are achieved by compressing the package width and changing the packaging method; or by compressing the bezel trace width and adjusting the circuit wiring space. In this type of solution, the circuit component composition does not actually change during the process of achieving narrow bezels. However, with the rapid development of display technology, the width of displays has basically been compressed to near the limit under these non-circuit-based narrow bezel improvement design solutions. It is no longer possible to further compress the bezel using this type of solution.

[0003] Based on this, how to further compress the display frame to meet users' demand for narrow display frame design to the greatest extent is still a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0004] The embodiments of the present application provide a gate drive circuit and a driving method thereof, and a display panel, which can effectively reduce the width of the display screen frame, thereby fully realizing the narrow frame design of the display screen.

[0005] In a first aspect, an embodiment of the present application provides a gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, the shift register including a scanning signal output module, a switch module, and a first light-emitting control signal output module;

[0006] a first terminal of the first light-emitting control signal output module electrically connected to the first level voltage terminal, and a second terminal of the first light-emitting control signal output module electrically connected to the first output terminal of the shift register, for transmitting the first level voltage signal provided by the first level voltage terminal to the first output terminal of the shift register in response to the conduction level of the control terminal of the first light-emitting control signal output module;

[0007] A first end of the switch module is electrically connected to the control end of the first light-emitting control signal output module, and a second end of the switch module is electrically connected to the control end of the scan signal output module;

[0008] The first end of the scan signal output module is electrically connected to the first scan clock signal end, and the second end of the scan signal output module is electrically connected to the second output end of the shift register;

[0009] In the first target mode, in at least part of the stage when the control end of the first light-emitting control signal output module is at the on-level, the switch module is turned on, and the scan signal output module transmits the enable level of the scan clock signal provided by the first scan clock signal end to the second output end of the shift register in response to the on-level provided by the first node.

[0010] In a possible implementation of the first aspect, the switch module includes a first control signal terminal and a second control signal terminal. The switch module is specifically configured to be turned on in response to the on-level provided by the first control signal terminal and the on-level provided by the second control signal terminal during at least a partial stage when the control terminal of the first light-emitting control signal output module is at the on-level, and transmit the on-level of the control terminal of the first light-emitting control signal output module to the control terminal of the scanning signal output module, thereby facilitating a more reasonable implementation of on or off control of the above-mentioned switch module.

[0011] In one possible implementation of the first aspect, the switch module includes a first switch unit and a second switch unit; the control end of the first switch unit is electrically connected to the first control signal end, the first end of the first switch unit is electrically connected to the control end of the first light-emitting control signal output module, and the second end of the first switch unit is electrically connected to the first end of the second switch unit, for transmitting the potential of the control end of the first light-emitting control signal output module to the first end of the second switch unit in response to the conduction level provided by the first control signal end; the control end of the second switch unit is electrically connected to the second control signal end, and the second end of the second switch unit is electrically connected to the second output end of the shift register, for transmitting the potential of the first end of the second switch unit to the second output end of the shift register in response to the conduction level provided by the second control signal end. In this way, reasonable conduction control of the above-mentioned switch module can be further achieved based on the first control signal end and the second control signal end.

[0012] In one possible implementation of the first aspect, taking into account the actual operating scenarios of the multi-stage shift registers in the gate drive circuit, to further reduce the bezel width, it is possible to multiplex the output signals of the first output terminals of the corresponding row shift registers and provide them to the first control signal terminal and the second control signal terminal. Based on this, one of the first control signal terminal and the second control signal terminal connected to any N-stage shift register in the gate drive circuit is electrically connected to the first output terminal of the N-2-stage shift register, and the other is electrically connected to the first output terminal of the N+1-stage shift register, where N is a positive integer greater than 2. In this way, by rationally multiplexing the signals of the cascaded shift registers, the realization of a narrow bezel on the display screen is further facilitated.

[0013] In a possible implementation of the first aspect, the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal of the N-th stage shift register is separated from the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal of the N+1-th stage shift register by a first time duration, the duration for the first scan clock signal terminal to provide the enable level of the first scan clock signal is a second time duration, and the first time duration is greater than or equal to the second time duration.

[0014] In a possible implementation of the first aspect, the first duration is half of a duration during which the first output terminal of the first-stage shift register provides a non-enable level of the light-emitting control signal.

[0015] In a possible implementation of the first aspect, in the first target mode, the end moment of the non-enable level of the light-emitting control signal provided by the first output end of the N-2-stage shift register is before the start moment of the non-enable level of the light-emitting control signal provided by the first output end of the N+1-stage shift register, and the time interval is greater than or equal to the time length of the enable level of the first scan clock signal provided by the first scan clock signal end; in at least part of the stage between the end moment of the non-enable level of the light-emitting control signal provided by the first output end of the N-2-stage shift register and the start moment of the non-enable level of the light-emitting control signal provided by the first output end of the N+1-stage shift register, the light-emitting control signal provided by the first output end of the N-stage shift register is the non-enable level, the control end of the first light-emitting control signal output module in the N-stage shift register is the on level, the switch module is turned on, and the scan signal output module transmits the enable level of the scan clock signal provided by the first scan clock signal end to the second output end of the shift register in response to the on level of the control end of the first light-emitting control signal output module.

[0016] In a possible implementation of the first aspect, in the second target mode, a phase of a disabling level of the light-emitting control signal provided by the first output terminal of the N-2-th stage shift register overlaps with a phase of a disabling level of the light-emitting control signal provided by the first output terminal of the N+1-th stage shift register, a switch module in the N-th stage shift register is always cut off, and the scan signal output module does not output the scan clock signal provided by the first scan clock signal terminal;

[0017] In a possible implementation of the first aspect, in a display frame, the first target mode is located before the second target mode.

[0018] In a possible implementation of the first aspect, a duration of a non-enable level of a trigger signal input to an input end of the shift register in the second target mode is greater than a duration of a non-enable level of a trigger signal input to an input end of the shift register in the first target mode.

[0019] In a possible implementation of the first aspect, the first-level voltage signal provided by the first-level voltage terminal is transmitted to the first output terminal of the shift register as a non-enable level of the light-emitting control signal.

[0020] In a possible implementation of the first aspect, one of the first scan clock signal terminals of the shift registers of two adjacent stages is electrically connected to the first scan clock signal line, and the other is electrically connected to the second scan clock signal line; the phase of the scan clock signal output by the first scan clock signal line differs from the phase of the scan clock signal provided by the second scan clock signal line by a first time length, and the first time length is half of the time length during which the first output terminal of the first-stage shift register provides a non-enable level of the light-emitting control signal.

[0021] In a possible implementation of the first aspect, the shift register further includes a first light-emitting clock signal terminal and a second light-emitting clock signal terminal; the first light-emitting clock signal terminal of the 3M+1-level shift register is electrically connected to the first light-emitting clock signal line, and the second light-emitting clock signal terminal of the 3M+1-level shift register is electrically connected to the second light-emitting clock signal line; the first light-emitting clock signal terminal of the 3M+2-level shift register is electrically connected to the second light-emitting clock signal line, and the second light-emitting clock signal terminal of the 3M+2-level shift register is electrically connected to the third light-emitting clock signal line; the first light-emitting clock signal terminal of the 3M+3-level shift register is electrically connected to the third light-emitting clock signal line, and the second light-emitting clock signal terminal of the 3M+3-level shift register is electrically connected to the first light-emitting clock signal line, and M is an integer greater than or equal to 0.

[0022] In a possible implementation of the first aspect, the periods of the first light-emitting clock signal provided by the first light-emitting clock signal line, the second light-emitting clock signal provided by the second light-emitting clock signal line, and the third light-emitting clock signal provided by the third light-emitting clock signal line are all target light-emitting clock signal periods, and the phases between the first light-emitting clock signal, the second light-emitting clock signal, and the third light-emitting clock signal lag behind 1 / 3 of the target light-emitting clock signal period respectively.

[0023] In a possible implementation of the first aspect, the phase difference between the signal input to the input end of the shift register and the light-emitting control signal output from the first output end of the shift register is a first duration, and the first duration is half of the duration of the non-enabling level of the light-emitting control signal provided by the first output end of the first-stage shift register.

[0024] In a possible implementation of the first aspect, the input end of the 1st-stage shift register is electrically connected to the trigger signal end, the input end of the Kth-stage shift register is electrically connected to the first output end of the K-1th-stage shift register, and K is a positive integer greater than or equal to 2.

[0025] In a possible implementation of the first aspect, the shift register further includes a first luminous clock signal terminal and a second luminous clock signal terminal; in the second target mode, a trigger signal is input into the input terminal of the shift register, and in the non-enable level stage of the trigger signal, the target luminous clock signal provided by the target luminous clock signal terminal contains at least two enable levels, the switch module is always cut off, and the scan signal output module does not output the scan clock signal; wherein, the target luminous clock signal terminal is the first luminous clock signal terminal or the second luminous clock signal terminal.

[0026] In a possible implementation of the first aspect, the shift register further includes a light-emitting control signal shift control module, the light-emitting control signal shift control module includes a first light-emitting clock signal terminal, a second light-emitting clock signal terminal and an input terminal of the shift register, the first output terminal of the light-emitting control signal shift control module is electrically connected to the control terminal of the first light-emitting control signal output module, and the second output terminal of the light-emitting control signal shift control module is electrically connected to the control terminal of the second light-emitting control signal output module; the light-emitting control signal shift control module is configured to output a conduction level or a cut-off level from the first output terminal of the light-emitting control signal shift control module, and output a conduction level or a cut-off level from the second output terminal of the light-emitting control signal shift control module, under the control of the first light-emitting clock signal terminal, the second light-emitting clock signal terminal and the input terminal of the shift register.

[0027] In a possible implementation of the first aspect, the shift register further includes a bootstrap module; a first end of the bootstrap module is electrically connected to a second end of the scan signal output module, and the second end of the bootstrap module is electrically connected to a control end of the scan signal output module.

[0028] In a possible implementation of the first aspect, the bootstrap module includes a bootstrap capacitor, a first electrode of the bootstrap capacitor is electrically connected to the second end of the scan signal output module, and a second electrode of the bootstrap capacitor is electrically connected to the control end of the scan signal output module.

[0029] In a possible implementation of the first aspect, the shift register further includes a second light-emitting control signal output module; the first end of the second light-emitting control signal output module is electrically connected to the second level voltage end, and the second end of the second light-emitting control signal output module is electrically connected to the first output end of the shift register, and is used to transmit the second level voltage signal provided by the second level voltage end to the first output end of the shift register in response to the conduction level of the control end of the second light-emitting control signal output module.

[0030] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a driving method for a gate driving circuit. The driving method for a gate driving circuit is applied to the gate driving circuit provided in any of the aforementioned embodiments of the first aspect of the present application. The driving method for a gate driving circuit includes:

[0031] In the first target mode, in at least part of the stage when the control end of the first light-emitting control signal output module is at the on-level, the control switch module is turned on, so that the scan signal output module responds to the on-level of the control end of the first light-emitting control signal output module and transmits the enable level of the scan clock signal provided by the first scan clock signal end to the second output end of the shift register.

[0032] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a shift register, the shift register including a scan signal output module, a switch module, and a first light-emitting control signal output module;

[0033] a first terminal of the first light-emitting control signal output module electrically connected to the first level voltage terminal, and a second terminal of the first light-emitting control signal output module electrically connected to the first output terminal of the shift register, for transmitting the first level voltage signal provided by the first level voltage terminal to the first output terminal of the shift register in response to the conduction level of the control terminal of the first light-emitting control signal output module;

[0034] A first end of the switch module is electrically connected to the control end of the first light-emitting control signal output module, and a second end of the switch module is electrically connected to the control end of the scan signal output module;

[0035] The first end of the scan signal output module is electrically connected to the first scan clock signal end, and the second end of the scan signal output module is electrically connected to the second output end of the shift register;

[0036] In at least part of the stage when the first node is at the on-level, the switch module is turned on, and the scan signal output module transmits the scan clock signal provided by the first scan clock signal terminal to the second output terminal of the shift register in response to the on-level of the control terminal of the first light-emitting control signal output module.

[0037] Based on the same inventive concept, in a fourth aspect, an embodiment of the present application provides a display panel, which includes a gate driving circuit provided by any of the aforementioned embodiments of the first aspect of the present application.

[0038] Based on the same inventive concept, in a fifth aspect, an embodiment of the present application provides a display device, which includes a display panel provided in the embodiment of the fourth aspect of the present application.

[0039] The embodiments of the present application provide a gate drive circuit, a driving method thereof, and a display panel. A switch module and a scan signal output module are added to a conventional shift register. The first end of the switch module is electrically connected to the control end of the first light-emitting control signal output module. Thus, when the control end of the first light-emitting control signal output module is at an on-level, the first light-emitting control signal output module is turned on, transmitting the first-level voltage signal provided by the first-level voltage end to the first output end of the shift register. Furthermore, during at least a portion of the period when the control end of the first light-emitting control signal output module is at an on-level, the switch module is turned on, and the scan signal output module transmits the scan clock signal provided by the first scan clock signal end to the second output end of the shift register in response to the on-level of the control end of the first light-emitting control signal output module. The embodiments of the present application provide a gate drive circuit, a driving method thereof, and a display panel. By utilizing the characteristic that the scan drive signal only takes effect when the light-emitting control signal outputs a non-enable level, the gate signal of the non-enable level output transistor in the shift register is used as the gate of the scan drive signal output transistor, thereby merging the existing Scan circuit and EM circuit, greatly reducing the number of components and thereby fully achieving the effect of reducing the width of the display screen border. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0042] Figure 2 This is a schematic structural diagram of a shift register provided in an embodiment of the present application;

[0043] Figure 3 is a structural diagram of another shift register provided in an embodiment of the present application;

[0044] Figure 4 This is a structural diagram of another shift register provided in an embodiment of the present application;

[0045] Figure 5 is a structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0046] Figure 6 This is a timing diagram of a gate drive circuit provided in an embodiment of the present application;

[0047] Figure 7 is a structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0048] Figure 8 This is a timing diagram of a gate drive circuit provided in an embodiment of the present application;

[0049] Figure 9 is a structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0050] Figure 10 A timing diagram of a gate drive circuit provided in an embodiment of the application;

[0051] Figure 11 1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0052] Figure 12 This is a timing diagram of a gate drive circuit provided in an embodiment of the present application;

[0053] Figure 13 1 is a timing diagram of a gate drive circuit in a second target mode provided by an embodiment of the present application;

[0054] Figure 14 1 is a schematic diagram of a simulated output waveform of a gate drive circuit in a first target mode provided by an embodiment of the present application;

[0055] Figure 15 1 is a schematic diagram of a simulated output waveform of a gate drive circuit in a second target mode provided by an embodiment of the present application;

[0056] Figure 16 This is a structural diagram of another shift register provided in an embodiment of the present application;

[0057] Figure 17 This is a structural diagram of another shift register provided in an embodiment of the present application;

[0058] Figure 18 This is a structural diagram of another shift register provided in an embodiment of the present application;

[0059] Figure 19 This is a structural diagram of another shift register provided in an embodiment of the present application;

[0060] Figure 20 This is a structural diagram of another shift register provided in an embodiment of the present application;

[0061] Figure 21 1 is a flow chart of a driving method of a gate driving circuit provided in an embodiment of the present application;

[0062] Figure 22 This is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0063] Figure 23 This is a structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0065] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "include..." do not exclude the presence of additional identical elements in the process, method, article, or device that includes the elements.

[0066] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0067] It should be noted that the transistors in the embodiments of the present application can be either N-type transistors or P-type transistors. For N-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second electrodes are conductive, and when the gate of the N-type transistor is at a low level, the first and second electrodes are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the gate of the P-type transistor is at a low level, the first and second electrodes are conductive, and when the gate of the P-type transistor is at a high level, the first and second electrodes are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and depending on the signal of the gate of each transistor and its type, the first electrode can serve as the source and the second electrode as the drain, or the first electrode can serve as the drain and the second electrode as the source, without distinction being made herein. In addition, the on-level and off-level in the embodiments of the present invention are both general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0068] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0069] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0070] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0071] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0072] As mentioned above, the inventors of this application have discovered that the current methods used to achieve narrow bezel design: for example, by compressing the package width, changing the package, or by compressing the bezel trace width, adjusting the circuit wiring space, etc., have compressed the display width to near the limit. Such solutions can no longer further compress the bezel, so it is possible to consider further compressing the bezel by changing the circuit structure.

[0073] Based on this, the inventors of this application have carefully studied and discovered that the GIP (Gate in Panel) in a display panel typically includes a Scan circuit and an EM circuit. The former is used to control the writing and resetting of data in the pixel circuit, and the latter is used to gate drive the light-emitting control tube in the pixel circuit. In actual operation, the Scan circuit will only output an enable level when the EM circuit outputs a non-enable level. Therefore, it is possible to consider utilizing this feature and reuse the gate signal of the non-enable level output tube in the EM circuit as the gate signal of its output tube, thereby reducing the number of border components and thus achieving the purpose of reducing the border width.

[0074] In view of the above research findings of the inventors, in order to solve the problems of the prior art, the embodiments of the present application provide a gate driving circuit and a driving method thereof, and a display panel. It should be noted that the embodiments provided in this application are not intended to limit the scope of the disclosure of this application.

[0075] The following first introduces the gate drive circuit provided in the embodiment of the present application.

[0076] Figure 1 1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application. The gate drive circuit 10 includes a plurality of cascaded shift registers 1 .

[0077] The shift register 1 included in the gate drive circuit 10 is described in detail below. Figure 2 , Figure 2 Schematic diagram of the structure of a shift register provided by an embodiment of the present application. Figure 2 As shown, for any shift register 1 in the above-mentioned gate driving circuit 10 , the shift register 1 includes a scanning signal output module 101 , a switch module 102 , and a first light-emitting control signal output module 103 .

[0078] Specifically, the control end of the above-mentioned first light-emitting control signal output module 103 is electrically connected to the first node N1, the first end of the first light-emitting control signal output module 103 is electrically connected to the first level voltage end VGH, and the second end of the first light-emitting control signal output module 103 is electrically connected to the first output end EM of the shift register 1.

[0079] The first light-emitting control signal output module 103 is specifically configured to be turned on under the control of the conduction level provided by the first node N1, and transmit the first level voltage signal provided by the first level voltage terminal VGH to the first output terminal EM of the shift register 1 as the non-enable level of the light-emitting control signal.

[0080] A first end of the switch module 102 is electrically connected to the first node N1, and a second end of the switch module 102 is electrically connected to the control end of the scan signal output module 101. A first end of the scan signal output module 101 is electrically connected to the first scan clock signal end sck, and a second end of the scan signal output module 101 is electrically connected to the second output end SN of the shift register 1.

[0081] In the first target mode, during at least a portion of the time when the first node N1 is at the on-level, the switch module 102 is turned on, and the on-level of the first node N1 is transmitted to the control terminal of the scan signal output module 101 via the turned-on switch module 102. Controlled by the on-level provided by the first node N1, the scan signal output module 101 is turned on, transmitting the enable level of the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1. The disable level and the enable level can be opposite in level. For example, the disable level can be a high level, and the enable level can be a low level.

[0082] It should be understood that the above-mentioned first target mode is specifically an operating mode that allows the shift register 1 in the gate drive circuit 10 to transmit the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1 in at least part of the stage when the first node N1 is at the on level.

[0083] An embodiment of the present application provides a gate drive circuit 10 that adds the aforementioned switch module 102 and scan signal output module 101 to a conventional shift register. The first terminal of the switch module 102 is electrically connected to the first node N1. Thus, when the first node N1 is at an on-level, the first light-emitting control signal output module 103 in the EM circuit is turned on, transmitting the first-level voltage signal provided by the first-level voltage terminal VGH to the first output terminal of the shift register 1. Furthermore, during at least a portion of the period when the first node N1 is at an on-level, the switch module 102 is turned on, and the scan signal output module 103, in response to the on-level provided by the first node, transmits the enable level of the scan clock signal provided by the first scan clock signal terminal to the second output terminal of the shift register 1.

[0084] A gate drive circuit 10 in an embodiment of the present application utilizes the characteristic that a scan drive signal takes effect only when a light-emitting control signal outputs a non-enable level, and uses the gate signal of the non-enable level output tube in the shift register 1 as the gate of the scan drive signal output tube to merge the existing Scan circuit and EM circuit, thereby greatly reducing the number of components and fully achieving the effect of reducing the width of the display screen border.

[0085] See below Figure 3 , Figure 3 Schematic diagram of another structure of a shift register provided by an embodiment of the present application. Figure 3 As shown, in some more specific embodiments, in order to more reasonably implement on-off control of the switch module 102 , optionally, the control end of the switch module 102 may include a first control signal end G1 and a second control signal end G2 .

[0086] The above-mentioned switch module 102 can be specifically used to be turned on in response to the on-level provided by the first control signal terminal G1 and the on-level provided by the second control signal terminal G2 during at least part of the stage when the first node N1 is at the on-level, and transmit the on-level of the first node N1 to the control terminal of the scan signal output module 101.

[0087] See below Figure 4 , Figure 4 This is a structural diagram of another shift register provided by an embodiment of the present application. Figure 4 As shown, in some more specific embodiments, in order to further achieve reasonable conduction control of the above-mentioned switch module 102 based on the first control signal terminal G1 and the second control signal terminal G2, optionally, the above-mentioned switch module 102 may specifically include a first switch unit 1021 and a second switch unit 1022.

[0088] The control terminal of the first switch unit 1021 is electrically connected to the first control signal terminal G1, the first terminal of the first switch unit 1021 is electrically connected to the first node N1, and the second terminal of the first switch unit 1021 is electrically connected to the first terminal of the second switch unit 1022. The first switch unit 1021 can be configured to transmit the node potential of the first node N1 to the first terminal of the second switch unit 1022 in response to the conduction level provided by the first control signal terminal G1.

[0089] The control terminal of the second switch unit 1022 is electrically connected to the second control signal terminal G2, and the second terminal of the second switch unit 1022 is electrically connected to the second output terminal SN of the shift register 1. The control terminal of the second switch unit 1022 can be used to transmit the conduction level of the first terminal of the second switch unit 1022 to the second output terminal SN of the shift register 1 in response to the conduction level provided by the second control signal terminal G2.

[0090] It should be understood that Figure 4 The figure only shows one possible embodiment in which the first switch unit 1021 is electrically connected to the first control signal terminal G1, and the control terminal of the second switch unit 1022 is electrically connected to the second control signal terminal G2. In other embodiments, the first switch unit 1021 may also be electrically connected to the second control signal terminal G2, and the second switch unit 1022 may also be electrically connected to the first control signal terminal G1. This application does not impose any specific limitations on this.

[0091] It should be noted that both the first switch unit 1021 and the second switch unit 1022 may be transistors, and the control terminals of the first switch unit 1021 and the second switch unit 1022 may be gates of the transistors.

[0092] See below Figure 5 , Figure 5 Schematic diagram of a gate drive circuit provided in an embodiment of the present application. Figure 5 As shown, in some more specific embodiments, in combination with the actual working scenario of the multi-stage shift register 1 in the gate drive circuit 10, in order to further achieve the purpose of reducing the border width, it can be considered to multiplex the output signal of the first output terminal EM of the corresponding row shift register 1 and provide it to the first control signal terminal G1 and the second control signal terminal G2. Based on this, one of the first control signal terminal G1 and the second control signal terminal G2 connected to any N-stage shift register 1 in the gate drive circuit 10 is electrically connected to the first output terminal EM of the shift register 1 before the N-stage shift register 1 (which can be called the x-stage shift register 1), and the other is electrically connected to the first output terminal EM of the shift register 1 after the N-stage shift register 1 (which can be called the Y-stage shift register 1). The end time of the disable level of the first output terminal EM of the x-th stage shift register 1 is before the start time of the disable level of the first output terminal EM of the Y-th stage shift register 1, and the time interval between the end time of the disable level of the first output terminal EM of the x-th stage shift register 1 and the start time of the disable level of the first output terminal EM of the Y-th stage shift register 1 is greater than or equal to the duration of the enable level of the first scan clock signal provided by the first scan clock signal terminal sck. Such a configuration can ensure that, in the first target mode, during at least a portion of the period between the end time of the disabling level of the light-emitting control signal provided at the first output terminal of the X-stage shift register and the start time of the disabling level of the light-emitting control signal provided at the first output terminal of the Y-stage shift register, the levels of the first control signal terminal and the second control signal terminal output by the X-stage shift register and the Y-stage shift register to the switch module in the N-stage shift register are both enable levels, the light-emitting control signal provided by the first output terminal of the N-stage shift register is the disabling level, the control terminal of the first light-emitting control signal output module of the N-stage shift register is the on level, the enable levels of the first control signal terminal and the second control signal terminal output by the X-stage shift register and the Y-stage shift register to the N-stage shift register turn on the switch module of the N-stage shift register, and the scan signal output module of the N-stage shift register turns on in response to the on level of the control terminal of the first light-emitting control signal output module, and transmits the enable level of the scan clock signal provided by the first scan clock signal terminal to the second output terminal of the shift register.

[0093] Figure 5 In the gate drive circuit 10 shown in FIG, one of the first control signal terminal G1 and the second control signal terminal G2 connected to any N-th stage shift register 1 is electrically connected to the first output terminal EM of the N-2-th stage shift register 1, and the other is electrically connected to the first output terminal EM of the N+1-th stage shift register 1, where N is a positive integer greater than 2. Exemplarily, the first control signal terminal G1 connected to any N-th stage shift register 1 is electrically connected to the first output terminal EM of the N-2-th stage shift register 1, and the second control signal terminal G2 connected to any N-th stage shift register 1 is electrically connected to the first output terminal EM of the N+1-th stage shift register 1. Exemplarily, the first control signal terminal G1 connected to the N+2-th stage shift register 1 is electrically connected to the first output terminal EM of the N-th stage shift register 1, and the second control signal terminal G2 connected to any N-th stage shift register 1 is electrically connected to the first output terminal EM of the N+3-th stage shift register 1.

[0094] Combine Figure 5 In terms of Figure 5 The first control signal terminal G1 of the Nth stage shift register 1 <n>Actual and EM <n-2>electrically connected to the first output terminal EM of the N-2 stage shift register 1; the second control signal terminal G2 <n>Actual and EM<N+1> Electrically connected, that is, electrically connected to the first output terminal EM of the (N+1)th stage shift register 1.

[0095] Figure 5 The first control signal terminal G1 of the N+1th stage shift register 1<N+1> Actual and EM <n-1>electrically connected to the first output terminal EM of the N-1th stage shift register 1; the second control signal terminal G2<N+1> Actual and EM<N+2> Electrically connected, that is, electrically connected to the first output terminal EM of the (N+2)th stage shift register 1.

[0096] By analogy, Figure 5 G1 in<N+2> Actual and EM <n>Electrical connection, G2<N+2> Actual and EM<N+3> Electrical connection, G1<N+3> Actual and EM<N+1> Electrical connection, G2<N+3> Actual and EM<N+4> The electrical connection is not described in detail in this application.

[0097] It should be understood that the first control signal terminal G1 connected to any N-th stage shift register 1 can also be electrically connected to the first output terminal EM of the N+1-th stage shift register 1, and accordingly, the second control signal terminal G2 connected to any N-th stage shift register 1 is electrically connected to the first output terminal EM of the N-2-th stage shift register 1. This application does not impose any specific restrictions on this.

[0098] See below Figure 6 , Figure 6 1 is a timing diagram of a gate drive circuit provided by an embodiment of the present application. Figure 6 As shown, in some more specific embodiments, optionally, in combination with the signal multiplexing of the first output terminal EM of the cascaded shift register 1 by the aforementioned first control signal terminal G1 and the second control signal terminal G2, in order to more reasonably realize the cascading and signal multiplexing of multiple rows of shift registers in the gate drive circuit 10, in the gate drive circuit 10 of the present application, the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal EM of the N-th stage shift register 1 and the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal EM of the N+1-th stage shift register 1 are separated by a first time length t1, and the time length for the first scan clock signal terminal sck to provide the enable level of the first scan clock signal is a second time length t2, and the first time length t1 is greater than or equal to the second time length t2.

[0099] For example, Figure 6 Signal EM in <1> 、S <1> It can be the first output terminal EM of the Nth stage shift register 1 <n>The output light control signal and the second output terminal SN <n>Output scanning signal. Figure 6 Signal EM in <2> 、S <2> It can be the first output terminal EM of the N+1th stage shift register 1<N+1> The output light control signal and the second output terminal SN<N+1> Output scanning signal. Figure 6 Signal EM in <3> 、S <3> It can be the first output terminal EM of the N+2 stage shift register 1<N+2> The output light control signal and the second output terminal SN<N+2> Output scanning signal. Figure 6 Signal EM in <4> 、S <4> It can be the first output terminal EM of the N+3th stage shift register 1<N+3> The output light control signal and the second output terminal SN<N+3> Output scanning signal.

[0100] Please continue to see Figure 6 In some more specific implementations, optionally, the first duration t1 may be half of the duration during which the first output terminal EM of the first-stage shift register 1 provides the non-enable level of the light-emitting control signal.

[0101] In this embodiment, taking into account the specific implementation scenario, the output signals of the first output terminals EM of the two adjacent shift registers 1 are set to differ by half the duration of the non-enable level of the light-emitting control signal (in this embodiment, half the EM high level time). In this way, combined with the above example, it can be achieved that when the second output terminal SN of the shift register 1 of the current stage outputs the enable level, the first output terminal EM of the shift register 1 of the next stage outputs the non-enable level. In the stage where the first output terminals EM of the shift register 1 of the current stage and the first output terminals EM of the shift register 1 of the next stage both output the non-enable level, the second output terminal SN of the shift register 1 of the next stage outputs the enable level, which is conducive to providing the corresponding row pixel circuit with the corresponding scanning signal in the non-light-emitting stage. The pixel circuit may include a driving transistor, a data writing transistor, a gate initialization transistor, a light-emitting control transistor, an anode initialization transistor, a threshold compensation transistor, etc. The light-emitting control signal output by the first output terminal EM of the shift register 1 of the current stage can be used as the light-emitting control signal of the light-emitting control transistor in the pixel circuit of the current row. For example, the scanning signal output by the second output terminal SN of the shift register 1 at this level can be used as a scanning signal of the gate initialization transistor of the pixel circuit in this row to control the conduction or off-state of the gate initialization transistor of the pixel circuit in this row, and can also be used as a scanning signal of the data writing transistor of the pixel circuit in the previous row to control the conduction or off-state of the data writing transistor of the pixel circuit in the previous row.

[0102] In some more specific embodiments, in the first target mode, the end moment of the non-enable level of the light-emitting control signal provided by the first output terminal of the N-2 stage shift register is before the start moment of the non-enable level of the light-emitting control signal provided by the first output terminal of the N+1 stage shift register, and the time interval is greater than or equal to the time length of the enable level of the first scan clock signal provided by the first scan clock signal terminal.

[0103] In some more specific embodiments, in the first target mode (equivalent to the refresh stage), in at least part of the stage between the end time of the non-enable level of the light-emitting control signal provided at the first output end of the N-2-stage shift register and the start time of the non-enable level of the light-emitting control signal provided at the first output end of the N+1-stage shift register, it is equivalent to the levels of the first control signal end and the second control signal end output by the N-2-stage shift register and the N+1-stage shift register to the switch module in the N-stage shift register being enable levels, the switch module in the N-stage shift register is turned on, the light-emitting control signal provided at the first output end of the N-stage shift register is the non-enable level, the control end of the first light-emitting control signal output module in the N-stage shift register is the on level, and the scan signal output module in the N-stage shift register transmits the enable level of the scan clock signal provided by the first scan clock signal end to the second output end of the shift register in response to the on level of the control end of the first light-emitting control signal output module.

[0104] In some more specific embodiments, in the second target mode (equivalent to the black insertion stage), the stage of the non-enable level of the light-emitting control signal provided by the first output end of the N-2-stage shift register overlaps with the stage of the non-enable level of the light-emitting control signal provided at the first output end of the N+1-stage shift register, which is equivalent to the levels of the first control signal end and the second control signal end of the switch module in the N-stage shift register output by the N-2-stage shift register and the N+1-stage shift register are both non-enable levels, the switch module in the N-stage shift register is always cut off, and the scan signal output module does not output the scan clock signal provided by the first scan clock signal end.

[0105] In some more specific implementations, considering actual display scenarios, in a display frame, the first target mode may be located before the second target mode.

[0106] In some more specific embodiments, when the clock signals in the second target mode are consistent with the clock signals in the first target mode, the duration of the non-enable level of the trigger signal input to the input end of the shift register in the second target mode can be greater than the duration of the non-enable level of the trigger signal input to the input end of the shift register in the first target mode.

[0107] See below Figure 7 , Figure 7 Schematic diagram of another gate drive circuit provided by an embodiment of the present application. Figure 7 As shown, in some more specific embodiments, the gate drive circuit 10 optionally includes a first scan clock signal line SCK1 and a second scan clock signal line SCK2. One of the first scan clock signal terminals sck of the shift registers 1 of two adjacent stages is electrically connected to the first scan clock signal line SCK1, and the other is electrically connected to the second scan clock signal line SCK2. In other words, the first scan clock signal line SCK1 and the second scan clock signal line SCK2 appear alternately in the cascaded shift registers 1, thereby achieving reasonable multiplexing of the first scan clock signal line SCK1 and the second scan clock signal line SCK2 by multiple rows of shift registers 1 in the gate drive circuit 10. The first scan clock signal line SCK1 and the second scan clock signal line SCK2 can have the same frequency.

[0108] In this embodiment, taking into account specific implementation scenarios, when the first output terminal EM of each stage of the shift register 1 outputs a non-enable level, the two SCK signals provided by the first scan clock signal line SCK1 and the second scan clock signal line SCK2 are output to the second output terminal SN of the shift register 1 according to odd and even rows. The second output terminals SN of the shift registers 1 of two adjacent stages can be electrically connected to corresponding scan signal terminals in the pixel circuit, respectively, to provide corresponding scan signals for the pixel circuit in operating stages such as reset and charging in the non-light-emitting stage.

[0109] Furthermore, considering that the first scan clock signal line SCK1 and the second scan clock signal line SCK2 appear alternately in the cascaded shift register 1, the timing between the first scan clock signal line SCK1 and the second scan clock signal line SCK2 also needs to be set alternately accordingly.

[0110] Based on this, the following can be specifically combined Figure 8 , Figure 8 This is a timing diagram of another gate drive circuit provided by an embodiment of the present application. Figure 8 As shown, the phase of the scanning clock signal output by the above-mentioned first scanning clock signal line SCK1 and the phase of the scanning clock signal provided by the second scanning clock signal line SCK2 differ by a first time length t1. The first time length t1 can be half of the time length of the non-enabling level of the luminous control signal provided to the first output terminal EM of the first-stage shift register 1.

[0111] See Figure 9 , Figure 9 This is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Figure 9 As shown, in some more specific embodiments, the gate drive circuit 10 optionally uses three emission clock signal lines, namely: a first emission clock signal line ECK1, a second emission clock signal line ECK2, and a third emission clock signal line ECK3, which may have the same frequency. The shift register 1 may also include a first emission clock signal terminal and a second emission clock signal terminal.

[0112] For details about the cascade multiplexing relationship between the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2 and the third light-emitting clock signal line ECK3, please continue to refer to Figure 9 . Figure 9 As can be seen in FIG, when the multi-row shift register 1 in the gate drive circuit 10 is working, the first light-emitting clock signal terminal of the 3M+1-stage shift register 1 can be electrically connected to the first light-emitting clock signal line ECK1, and the second light-emitting clock signal terminal of the 3M+1-stage shift register 1 can be electrically connected to the second light-emitting clock signal line ECK2, where M is an integer greater than or equal to 0. For example, Figure 9 The Nth stage shift register 1 in.

[0113] In the gate driving circuit 10, the first light-emitting clock signal terminal of the 3M+2-stage shift register 1 can be electrically connected to the second light-emitting clock signal line ECK2, and the second light-emitting clock signal terminal of the 3M+2-stage shift register 1 can be electrically connected to the third light-emitting clock signal line ECK3. Figure 9 The N+1th stage shift register 1 in .

[0114] The first light-emitting clock signal terminal of the 3M+3-stage shift register 1 can be electrically connected to the third light-emitting clock signal line ECK3, and the second light-emitting clock signal terminal of the 3M+3-stage shift register 1 can be electrically connected to the first light-emitting clock signal line ECK1. Figure 9 The N+2th stage shift register 1 in .

[0115] The multiple shift registers 1 are divided into multiple groups, with every three adjacent shift registers 1 as a group, which are cyclically and alternately connected to three light-emitting clock signal lines, and each shift register 1 is connected to two or three light-emitting clock signal lines.

[0116] In some more specific embodiments, in order to further realize the reasonable multiplexing of the signals of the cascaded shift registers 1 in the gate drive circuit 10, so as to effectively reduce the number of components and thus fully realize the narrow frame design of the display screen, optionally, the input end of the first stage shift register 1 is electrically connected to the trigger signal end, and the input end of the Kth stage shift register 1 is electrically connected to the first output end EM of the K-1th stage shift register 1, where K is a positive integer greater than or equal to 2. For example, as shown in FIG.

[0117] See below Figure 10 , Figure 10 This is another timing diagram of a gate drive circuit provided by an embodiment of the present application. In some more specific implementations, in combination with the cascade multiplexing method of the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2 and the third light-emitting clock signal line ECK3, in order to more reasonably realize the clock control of the shift registers 1 of different rows in the gate drive circuit 10, it is optional, such as Figure 10 As shown, the periods of the first light-emitting clock signal provided by the first light-emitting clock signal line ECK1, the second light-emitting clock signal provided by the second light-emitting clock signal line ECK2, and the third light-emitting clock signal provided by the third light-emitting clock signal line ECK3 are all target light-emitting clock signal periods, and the phases between the first light-emitting clock signal, the second light-emitting clock signal and the third light-emitting clock signal lag behind 1 / 3 of the target light-emitting clock signal period respectively.

[0118] Please continue to see Figure 10 In some more specific embodiments, optionally, the phase difference between the signal input to the input terminal of the shift register 1 and the light-emitting control signal output from the first output terminal EM of the shift register 1 is a first duration t1. The first duration t1 may be half the duration of the non-enable level of the light-emitting control signal provided to the first output terminal EM of the first-stage shift register 1.

[0119] In order to more intuitively reflect the timing setting of the gate drive circuit 10 and the cascade structure and signal multiplexing design of the shift register 1 in this application, please refer to the following Figure 11 and Figure 12 , Figure 11 is a schematic structural diagram of a complete gate drive circuit provided by an embodiment of the present application, and, Figure 12 This is a timing diagram of a complete gate drive circuit provided by an embodiment of the present application. Figure 11 and Figure 12 Corresponding.

[0120] In this embodiment, by providing the above-mentioned cascade multiplexing structure in the gate driving circuit 1 , the number of frame components can be reduced to a great extent, thereby reducing the frame size of the display screen.

[0121] like Figure 12 As shown, the cascade multiplexing structure in the aforementioned gate driving circuit 1 is designed to match the corresponding timing.

[0122] Specifically, the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal EM of the Nth stage shift register 1 is separated from the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal EM of the N+1th stage shift register 1 by a first time length t1, and the time length for the first scan clock signal terminal sck to provide the enable level of the first scan clock signal is a second time length t2, and the first time length t1 can be greater than or equal to the second time length t2.

[0123] The phase of the scan clock signal output by the first scan clock signal line SCK1 differs from the phase of the scan clock signal provided by the second scan clock signal line SCK2 by a first time duration t1. The periods of the first light-emitting clock signal provided by the first light-emitting clock signal line ECK1, the second light-emitting clock signal provided by the second light-emitting clock signal line ECK2, and the third light-emitting clock signal provided by the third light-emitting clock signal line ECK3 are all target light-emitting clock signal periods, and the phases of the first light-emitting clock signal, the second light-emitting clock signal, and the third light-emitting clock signal lag behind one-third of the target light-emitting clock signal period, respectively.

[0124] The phase difference between the signal input to the input terminal of the shift register 1 and the light-emitting control signal output from the first output terminal EM of the shift register 1 is a first duration t1. The first duration t1 is half of the duration during which the first output terminal EM of the first-stage shift register 1 provides the non-enable level of the light-emitting control signal.

[0125] To more intuitively understand the timing design in this embodiment, the following describes each signal in detail using the target emission clock signal period as a standard. The target emission clock signal period is the period of the first emission clock signal provided by the first emission clock signal line ECK1, the second emission clock signal provided by the second emission clock signal line ECK2, and the third emission clock signal provided by the third emission clock signal line ECK3, hereinafter referred to as the ECK period.

[0126] The phases of the first light-emitting clock signal, the second light-emitting clock signal and the third light-emitting clock signal provided by the above-mentioned ECK1, ECK2 and ECK3 respectively lag behind by 1 / 3 ECK cycle respectively, the width / duration of the non-enable level of the signal input to the input end of the shift register 1 is 2 / 3 ECK cycle, the periods of the scanning clock signals provided by SCK1 and SCK2 are both 2 / 3 ECK cycle, and the phase difference between the scanning clock signals provided by SCK1 and SCK2 is 1 / 3 ECK cycle.

[0127] In this embodiment, by performing corresponding timing matching design on the cascade multiplexing structure in the aforementioned gate driving circuit 1, the aforementioned cascade multiplexing structure can be more reasonably implemented, thereby greatly reducing the number of border components and further reducing the border size of the display screen.

[0128] See below Figure 13 , Figure 13 This is a timing diagram of a gate drive circuit in a second target mode provided by an embodiment of the present application. In some more specific embodiments, in actual application, in order to facilitate the unified control of the output of the scanning clock signal of multiple rows of shift registers in the gate drive circuit, the above-mentioned shift register 1 may optionally further include a first light-emitting clock signal terminal and a second light-emitting clock signal terminal. Figure 13 As shown, in the second target mode, a trigger signal is input to the input terminal of the shift register 1. When the trigger signal is at a non-enable level, the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains at least two enable levels, the switch module 102 is always cut off, and the scan signal output module 101 does not output the scan clock signal. The target light-emitting clock signal terminal is either the first light-emitting clock signal terminal or the second light-emitting clock signal terminal.

[0129] In some more specific embodiments, relatively, in the first target mode, a trigger signal is input to the input end of the shift register 1, and in the non-enable level stage of the trigger signal, the target light-emitting clock signal provided by the target light-emitting clock signal end contains an enable level.

[0130] In contrast to the first target mode, when the gate drive circuit 1 is in the second target mode, the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains at least two enable levels, and the above-mentioned switch module 102 is always cut off, so that in the stage where the first output terminal EM of the shift register 1 outputs a non-enable level, the scan signal output module 101 is always unable to receive the conduction level of the first node N1 to be turned on, and thus cannot transmit the scan clock signal provided by the above-mentioned first scan clock signal terminal sck to the second output terminal SN of the shift register 1. Finally, the scan signal output module 101 does not output a scan clock signal at this stage.

[0131] Specifically, when the gate drive circuit 1 is in the second target mode, the target light emitting clock signal provided by the target light emitting clock signal terminal contains at least two enable levels. <n>In the stage of outputting the non-enable level, the first output terminal EM of the N-2 stage shift register 1 <n-2>and the first output terminal EM of the N+1th stage shift register 1<N+1> In this case, since the first control signal terminal G1 connected to the Nth stage shift register 1 is <n>and the second control signal terminal G2 <n>It is impossible to receive the conduction level at the same time. Therefore, the above-mentioned switch module 102 will always be cut off at this stage, resulting in the scanning signal output module 101 always being unable to receive the conduction level of the first node N1 through the turned-on switch module 102 to be turned on, and thus unable to transmit the scanning clock signal provided by the above-mentioned first scanning clock signal terminal sck to the second output terminal SN of the shift register 1. Finally, at this stage, the scanning signal output module 101 does not output the scanning clock signal.

[0132] In this embodiment, when the clock signals in the second target mode are consistent with the clock signals in the first target mode, by changing the length of the non-enable level of the trigger signal input to the output end of the first-stage shift register 1 (controlling the EIN non-enable phase to cross at least two enable levels of any ECK of the current row shift register), full-row black insertion control of multiple rows of shift registers 1 in the gate drive circuit 10 can be achieved.

[0133] Specifically, combined with the specific examples, Figure 14 This is a schematic diagram of a simulated output waveform of a gate drive circuit in a first target mode provided in an embodiment of the present application. Figure 14 , in FIG. 3 , waveforms of the first output terminal EM of the shift register for three consecutive rows and waveforms of the second output terminal SN of the shift register 1 for three consecutive rows in the first target mode are shown.

[0134] from Figure 14 It can be seen from FIG that when the gate drive circuit is in the first target mode, the shift register 1 of each row outputs the EM non-enable level ( Figure 14 At least part of the phase (high level), each row shift register simultaneously outputs the SN enable level ( Figure 14 (low level in the middle).

[0135] Figure 15 This is a schematic diagram of a simulated output waveform of a gate drive circuit in a second target mode provided in an embodiment of the present application. Figure 15 , the waveforms of the first output terminal EM and the second output terminal SN of the shift register 1 of three consecutive stages in the second target mode are shown. The output of the second output terminal SN of the shift register 1 does not follow the output of the first output terminal EM of the shift register 1.

[0136] from Figure 15 It can be seen from FIG that when the gate drive circuit is in the second target mode, the shift registers of each row output EM non-enable level ( Figure 15 During at least part of the phase (where the SN level is high), each row shift register does not output the SN enable level.

[0137] See below Figure 16 , Figure 16 is a schematic diagram of the structure of another shift register provided in an embodiment of the present application. In some more specific embodiments, to further enable the above-mentioned scan signal output module 101 to effectively output the above-mentioned scan clock signal, the shift register 1 may optionally further include a bootstrap module 104. The first end of the above-mentioned bootstrap module 104 is electrically connected to the second end of the scan signal output module 101, and the second end of the bootstrap module 104 is electrically connected to the control end of the scan signal output module 101.

[0138] In some more specific embodiments, the bootstrap module 104 may include a bootstrap capacitor, a first electrode of the bootstrap capacitor is electrically connected to the second end of the scan signal output module 101 , and a second electrode of the bootstrap capacitor is electrically connected to the control end of the scan signal output module 101 .

[0139] In specific operation, for example, when the scan signal output module 101 is turned on in response to the conduction level (low level in this example) transmitted by the first node N1, the scan signal output module 101 transmits the scan clock signal (low level in this example) provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1, and the potential of the second output terminal SN of the shift register 1 jumps to low. At this time, the bootstrap module 104 uses its own coupling function to further lower the potential of the control terminal of the scan signal output module 101, thereby ensuring that the scan signal output module 101 is fully turned on as much as possible, which is conducive to maintaining the normal output of the scan clock signal.

[0140] See below Figure 17 , Figure 17 is a schematic diagram of the structure of another shift register provided in an embodiment of the present application. In some more specific embodiments, the shift register 1 may optionally further include a second light-emitting control signal output module 105. The control terminal of the second light-emitting control signal output module 105 is electrically connected to the second node N2, the first terminal of the second light-emitting control signal output module 105 is electrically connected to the second level voltage terminal VGL, and the second terminal of the second light-emitting control signal output module 105 is electrically connected to the first output terminal EM of the shift register 1.

[0141] Specifically, the second light emitting control signal output module 105 may be turned on under the control of the on-level provided by the second node N2 , and transmit the second-level voltage signal provided by the second-level voltage terminal VGL to the first output terminal EM of the shift register 1 .

[0142] Optionally, the first-level voltage signal provided by the first-level voltage terminal VGH may be a high level. Optionally, the second-level voltage signal provided by the second-level voltage terminal VGL may be a low level.

[0143] See below Figure 18 , Figure 18 : This is a structural diagram of another shift register provided in an embodiment of the present application. In some more specific embodiments, optionally, the shift register 1 further includes a light-emitting control signal shift control module 106. The light-emitting control signal shift control module 106 includes a first light-emitting clock signal terminal eck1, a second light-emitting clock signal terminal eck2, and an input terminal EIN of the shift register 1. The first output terminal of the light-emitting control signal shift control module 106 is electrically connected to the control terminal of the first light-emitting control signal output module 103, and the second output terminal of the light-emitting control signal shift control module 106 is electrically connected to the control terminal of the second light-emitting control signal output module 105. The light-emitting control signal shift control module 106 is configured to output a conduction level or an off-level from the first output terminal of the light-emitting control signal shift control module 106, and output a conduction level or an off-level from the second output terminal of the light-emitting control signal shift control module 106, under the control of the first light-emitting clock signal terminal eck1, the second light-emitting clock signal terminal eck2, and the shift register input terminal EIN.

[0144] To facilitate understanding of the shift register 1 in the gate driving circuit 10 provided in the present application, some specific application embodiments are described below.

[0145] See below Figure 19 , Figure 19 This is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Figure 19 As shown, according to some embodiments of the present application, optionally, in the gate drive circuit 10 provided in this embodiment, the above-mentioned scan signal output module 101 can be specifically the sixteenth transistor T16, the above-mentioned switch module can be specifically composed of the fourteenth transistor T14 and the fifteenth transistor T15, the above-mentioned first light-emitting control signal output module 103 can be specifically the ninth transistor T9, the above-mentioned second light-emitting control signal output module 105 can be specifically the tenth transistor T10, and the above-mentioned bootstrap module 104 can be specifically the bootstrap capacitor C4. In addition, the above-mentioned transistors involved in this embodiment are all P-type drive transistors. It should be noted that in some other embodiments, the channel type of each of the above-mentioned transistors can also be flexibly adjusted according to actual conditions, and this application does not impose strict restrictions on this.

[0146] The control terminal of the ninth transistor T9 is electrically connected to the first node N1, the first terminal of the ninth transistor T9 is electrically connected to the first level voltage terminal VGH, and the second terminal of the ninth transistor T9 is electrically connected to the first output terminal EM of the shift register 1. The control terminal of the fourteenth transistor T14 is electrically connected to the first control signal terminal G1, the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1, and the second terminal of the fourteenth transistor T14 is electrically connected to the first terminal of the fifteenth transistor T15. The control terminal of the fifteenth transistor T15 is electrically connected to the second control signal terminal G2, and the second terminal of the fifteenth transistor T15 is electrically connected to the second output terminal SN of the shift register 1. The first terminal of the sixteenth transistor T16 is electrically connected to the first scan clock signal terminal sck, and the second terminal of the sixteenth transistor T16 is electrically connected to the second output terminal SN of the shift register 1. The first terminal of the bootstrap capacitor C4 is electrically connected to the second terminal of the sixteenth transistor T16, and the second terminal of the bootstrap capacitor C4 is electrically connected to the control terminal of the sixteenth transistor T16. The control terminal of the tenth transistor T10 is electrically connected to the second node N2 , the first terminal of the tenth transistor T10 is electrically connected to the second level voltage terminal VGL, and the second terminal of the tenth transistor T10 is electrically connected to the first output terminal EM of the shift register 1 .

[0147] During specific operation, when the gate drive circuit is in the first target mode, in the shift register 1, in at least part of the stage when the first node N1 is at the on-level, the ninth transistor T9 is turned on under the control of the on-level provided by the first node N1, and transmits the first-level voltage signal provided by the first-level voltage terminal VGH to the first output terminal EM of the shift register 1.

[0148] The fourteenth transistor T14 is turned on in response to the on-level provided by the first control signal terminal G1, and transmits the node potential of the first node N1 to the first terminal of the fifteenth transistor T15. The control terminal of the fifteenth transistor T15 can be used to transmit the on-level of the first terminal of the fifteenth transistor T15 to the second output terminal SN of the shift register 1 in response to the on-level provided by the second control signal terminal G2. At this time, the sixteenth transistor T16 transmits the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1 in response to the on-level provided by the first node N1.

[0149] In this stage, the second node N2 is at the cut-off level, the tenth transistor is cut off in response to the cut-off level provided by the second node N2, and the second level voltage signal provided by the second level voltage terminal VGL is not transmitted to the first output terminal EM of the shift register 1.

[0150] It should be noted that, in addition to the transistors listed above, the gate driving circuit 10 may also include other transistors, which together constitute various types of gate driving circuits, and this application does not impose any specific restrictions on this.

[0151] See below Figure 20 , Figure 20 This is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Figure 20 As shown, according to some embodiments of the present application, optionally, Figure 20 Zhongzai Figure 19 On the basis of the EM circuit, the gate signal generating circuit of the front-stage EM output tube is added, which together with the output tubes T9 and T10 of the back-stage constitutes the existing 13T3C shift register. The specific device composition and the connection relationship between the devices can be shown as follows. Figure 20 As shown, the light emitting control signal shift control module 106 specifically includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, a second capacitor 2, and a third capacitor C3. In this embodiment, the first transistor T1 to the sixteenth transistor can all be P-type transistors. However, it should be understood that in some other possible implementations, the transistors can also be of other channel types. When the channel types of some transistors are changed, their corresponding timings will also be adaptively adjusted accordingly, and this application does not impose strict restrictions on this.

[0152] The control terminal of the first transistor T1 is electrically connected to the first light-emitting clock signal terminal eck1, the first terminal of the first transistor is electrically connected to the input terminal EIN of the shift register 1, and the second terminal of the first transistor T1 is electrically connected to the third node N3. The control terminal of the second transistor T2 is electrically connected to the third node N3, the first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the first light-emitting clock signal terminal eck1. The control terminal of the third transistor T3 is electrically connected to the first light-emitting clock signal terminal eck1, and the first terminal of the third transistor T3 is electrically connected to the second level voltage terminal VGL. The control terminal of the fourth transistor T4 is electrically connected to the second terminal of the twelfth transistor T12, the first terminal of the fourth transistor T4 is electrically connected to the first level voltage terminal VGH, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to the second light-emitting clock signal terminal eck2, and the second terminal of the fifth transistor T5 is electrically connected to the third node N3. The control terminal of the sixth transistor T6 is electrically connected to the third node N3, the first terminal of the sixth transistor is electrically connected to the first node N1, and the second terminal of the sixth transistor T6 is electrically connected to the first voltage level terminal VGH. The control terminal of the seventh transistor T7 is electrically connected to the second light-emitting clock signal terminal eck2, the first terminal of the seventh transistor T7 is electrically connected to the second electrode of the first capacitor C1, and the second terminal of the seventh transistor T7 is electrically connected to the first node N1. The control terminal of the eighth transistor T8 is electrically connected to the first electrode of the first capacitor C1, the first terminal of the eighth transistor T8 is electrically connected to the second light-emitting clock signal terminal eck2, and the second terminal of the eighth transistor T8 is electrically connected to the second electrode of the first capacitor C1. The control terminal of the eleventh transistor T11 is electrically connected to the second voltage level terminal VGL, the first terminal of the eleventh transistor T11 is electrically connected to the third node N3, and the second terminal of the eleventh transistor T11 is electrically connected to the second node N2. The control terminal of the twelfth transistor T12 is electrically connected to the second voltage level terminal VGL, and the first terminal of the twelfth transistor T12 is electrically connected to the first electrode of the first capacitor C1.

[0153] The control terminal of the thirteenth transistor T13 and the control terminal of the twelfth transistor T12 are electrically connected to the second level voltage terminal VGL. The first terminal of the thirteenth transistor T13 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the thirteenth transistor T13 is electrically connected to the first terminal of the twelfth transistor T12. A first electrode of the second capacitor C2 is electrically connected to the second node N2, and a second electrode of the second capacitor C2 is electrically connected to the second light-emitting clock signal terminal eck2. A first electrode of the third capacitor C3 is electrically connected to the first level voltage terminal VGH, and a second electrode of the third capacitor C3 is electrically connected to the first node N1.

[0154] Based on the gate driving circuit provided in any of the above embodiments, accordingly, an embodiment of the present application further provides a driving method for a gate driving circuit, and the driving method for a gate driving circuit is applied to the gate driving circuit provided in any of the above embodiments of the present application.

[0155] See below Figure 21 , Figure 21 This is a flow chart of a driving method of a gate driving circuit provided in an embodiment of the present application.

[0156] like Figure 21 As shown, the driving method of the gate driving circuit includes:

[0157] S2110. In the first target mode, during at least part of the stage when the control end of the first light-emitting control signal output module is at the on-level, the control switch module is turned on so that the scanning signal output module transmits the enable level of the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register in response to the on-level of the control end of the first light-emitting control signal output module.

[0158] Specifically, in the first target mode, the switch module is controlled to be turned on during at least a portion of the period when the control terminal of the first light-emitting control signal output module is at an on-level. This allows the on-level of the control terminal of the first light-emitting control signal output module to be transmitted to the control terminal of the scan signal output module via the turned-on switch module.

[0159] In this way, the scan signal output module can be turned on in response to the on-level provided by the control terminal of the first light-emitting control signal output module. The enable level of the scan clock signal provided by the first scan clock signal terminal is ultimately transmitted to the second output terminal of the shift register through the turned-on scan signal output module, thereby achieving the output of the enable level of the scan clock signal during at least the portion of the period when the control terminal of the first light-emitting control signal output module is at the on-level.

[0160] A driving method for a gate drive circuit in an embodiment of the present application utilizes the characteristic that a scan drive signal takes effect only when a light-emitting control signal outputs a non-enable level, and uses the gate signal of the non-enable level output tube in the shift register as the gate of the scan drive signal output tube to merge the existing Scan circuit and EM circuit. Scan does not need to generate the potential of the control output tube gate by itself, which greatly reduces the number of components, thereby fully achieving the effect of reducing the width of the display screen border.

[0161] Optionally, the driving method of the gate drive circuit also includes: in the second target mode, a trigger signal is input into the input end of the shift register 1, and in the non-enable level stage of the trigger signal, the target light-emitting clock signal provided by the target light-emitting clock signal end contains at least two enable levels, the switch module 102 is always cut off, and the scan signal output module 101 does not output the scan clock signal.

[0162] Based on the gate driving circuit provided in any of the above embodiments, the present application also provides a display panel, including the gate driving circuit 10 provided in the present application. Figure 22 , Figure 22 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 22 As shown, the display panel 100 provided in the embodiment of the present application may include the gate driving circuit 10 of any of the above embodiments. Figure 22 The display panel shown may be an organic light-emitting diode (OLED) display panel.

[0163] Those skilled in the art should understand that in other implementations of the present application, the display panel may also be a micro light emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0164] The display panel provided in the embodiment of the present application has the beneficial effects of the gate drive circuit 10 provided in the embodiment of the present application. For details, please refer to the specific description of the gate drive circuit 10 in the above embodiments, and this embodiment will not be repeated here.

[0165] Based on the display panel provided in the above embodiment, the present application also provides a display device, including the display panel provided in the present application. Figure 23 , Figure 23 A schematic structural diagram of a display device provided in an embodiment of the present application. Figure 23 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 23 In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It is understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application. For details, please refer to the specific description of the display panel 100 in the above embodiments, and this embodiment will not be repeated here.

[0166] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other unless there is any contradiction.

[0167] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments of this application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to only specific embodiments. Obviously, based on the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of this application, so that those skilled in the art can make good use of this application and the modifications based on this application. This application is only limited by the claims and their full scope and equivalents.

[0168] Those skilled in the art should understand that the above embodiments are illustrative rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to identify names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The presence of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of cascaded shift registers, and the shift register includes a scanning signal output module, a switch module, and a first light-emitting control signal output module; A first terminal of the first light-emitting control signal output module is electrically connected to the first level voltage terminal, and a second terminal of the first light-emitting control signal output module is electrically connected to the first output terminal of the shift register, and is configured to transmit the first level voltage signal provided by the first level voltage terminal to the first output terminal of the shift register in response to the conduction level of the control terminal of the first light-emitting control signal output module; The first end of the switch module is electrically connected to the control end of the first light-emitting control signal output module, and the second end of the switch module is electrically connected to the control end of the scanning signal output module; The first end of the scan signal output module is electrically connected to the first scan clock signal end, and the second end of the scan signal output module is electrically connected to the second output end of the shift register; In the first target mode, during at least a portion of a phase in which the control terminal of the first light-emitting control signal output module is at an on-level, the switch module is turned on, and the scan signal output module transmits an enable level of the scan clock signal provided by the first scan clock signal terminal to the second output terminal of the shift register in response to the on-level of the control terminal of the first light-emitting control signal output module; The switch module includes a first control signal terminal and a second control signal terminal. The switch module is specifically configured to, in at least a portion of a stage in which the control terminal of the first light-emitting control signal output module is at a conduction level, transmit the conduction level of the control terminal of the first light-emitting control signal output module to the control terminal of the scanning signal output module in response to the conduction level provided by the first control signal terminal and the conduction level provided by the second control signal terminal; The switch module includes a first switch unit and a second switch unit.

2. The gate drive circuit according to claim 1, wherein: The control end of the first switch unit is electrically connected to the first control signal end, the first end of the first switch unit is electrically connected to the control end of the first light-emitting control signal output module, and the second end of the first switch unit is electrically connected to the first end of the second switch unit, and is configured to transmit the potential of the control end of the first light-emitting control signal output module to the first end of the second switch unit in response to the conduction level provided by the first control signal end; The control end of the second switch unit is electrically connected to the second control signal end, and the second end of the second switch unit is electrically connected to the second output end of the shift register, and is used to transmit the level of the first end of the second switch unit to the second output end of the shift register in response to the conduction level provided by the second control signal end.

3. The gate drive circuit according to claim 1 or 2, characterized in that: One of the first control signal terminal and the second control signal terminal of any N-th stage shift register in the gate drive circuit is electrically connected to the first output terminal of the N-2-th stage shift register, and the other is electrically connected to the first output terminal of the N+1-th stage shift register, where N is a positive integer greater than 2.

4. The gate driving circuit according to claim 3, wherein: The starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal of the Nth stage shift register is separated from the starting moment of the non-enable level of the light-emitting control signal provided by the first output terminal of the N+1th stage shift register by a first time length, and the time length for the first scan clock signal terminal to provide the enable level of the first scan clock signal is a second time length, and the first time length is greater than or equal to the second time length.

5. The gate driving circuit according to claim 4, wherein: The first duration is half of the duration during which the first output terminal of the first-stage shift register provides the non-enable level of the light-emitting control signal.

6. The gate driving circuit according to claim 3, wherein: In the first target mode, the end moment of the non-enable level of the light-emitting control signal provided by the first output end of the N-2-stage shift register is before the start moment of the non-enable level of the light-emitting control signal provided by the first output end of the N+1-stage shift register, and the time interval is greater than or equal to the time length of the enable level of the first scan clock signal provided by the first scan clock signal end; in at least part of the stage between the end moment of the non-enable level of the light-emitting control signal provided by the first output end of the N-2-stage shift register and the start moment of the non-enable level of the light-emitting control signal provided by the first output end of the N+1-stage shift register, the light-emitting control signal provided by the first output end in the N-stage shift register is the non-enable level, the control end of the first light-emitting control signal output module in the N-stage shift register is the on level, the switch module is turned on, and the scan signal output module transmits the enable level of the scan clock signal provided by the first scan clock signal end to the second output end of the shift register in response to the on level of the control end of the first light-emitting control signal output module.

7. The gate driving circuit according to claim 3, wherein: In the second target mode, a phase of a non-enable level of the light-emitting control signal provided by the first output terminal of the N-2-th stage shift register overlaps with a phase of a non-enable level of the light-emitting control signal provided by the first output terminal of the N+1-th stage shift register, the switch module in the N-th stage shift register is always cut off, and the scan signal output module does not output the scan clock signal provided by the first scan clock signal terminal; In a display frame, the first target mode precedes the second target mode.

8. The gate driving circuit according to claim 7, wherein: The duration of the non-enable level of the trigger signal input to the input end of the shift register in the second target mode is longer than the duration of the non-enable level of the trigger signal input to the input end of the shift register in the first target mode.

9. The gate driving circuit according to claim 1, wherein: The first-level voltage signal provided by the first-level voltage terminal is transmitted to the first output terminal of the shift register as a non-enable level of the light emitting control signal.

10. The gate driving circuit according to claim 1, wherein: One of the first scanning clock signal terminals of the shift registers of two adjacent stages is electrically connected to the first scanning clock signal line, and the other is electrically connected to the second scanning clock signal line; The phase of the scanning clock signal output by the first scanning clock signal line differs from the phase of the scanning clock signal provided by the second scanning clock signal line by a first duration, and the first duration is half of the duration of the non-enabling level of the light-emitting control signal provided by the first output end of the first-stage shift register.

11. The gate driving circuit according to claim 1, wherein: The shift register further includes a first light-emitting clock signal terminal and a second light-emitting clock signal terminal; The first light-emitting clock signal terminal of the 3M+1-stage shift register is electrically connected to the first light-emitting clock signal line, and the second light-emitting clock signal terminal of the 3M+1-stage shift register is electrically connected to the second light-emitting clock signal line, where M is an integer greater than or equal to 0; The first light-emitting clock signal terminal of the 3M+2-stage shift register is electrically connected to the second light-emitting clock signal line, and the second light-emitting clock signal terminal of the 3M+2-stage shift register is electrically connected to the third light-emitting clock signal line; The first light-emitting clock signal terminal of the 3M+3-stage shift register is electrically connected to the third light-emitting clock signal line, and the second light-emitting clock signal terminal of the 3M+3-stage shift register is electrically connected to the first light-emitting clock signal line.

12. The gate driving circuit according to claim 11, wherein: The periods of the first light-emitting clock signal provided by the first light-emitting clock signal line, the second light-emitting clock signal provided by the second light-emitting clock signal line, and the third light-emitting clock signal provided by the third light-emitting clock signal line are all target light-emitting clock signal periods, and the phases between the first light-emitting clock signal, the second light-emitting clock signal and the third light-emitting clock signal lag behind by 1 / 3 of the target light-emitting clock signal period respectively.

13. The gate driving circuit according to claim 1, wherein: The phase difference between the signal input to the input end of the shift register and the light-emitting control signal output from the first output end of the shift register is a first duration, and the first duration is half of the duration of the non-enabling level of the light-emitting control signal provided by the first output end of the shift register.

14. The gate driving circuit according to claim 1, wherein: The input end of the first stage shift register is electrically connected to the trigger signal end, the input end of the Kth stage shift register is electrically connected to the first output end of the K-1th stage shift register, and K is a positive integer greater than or equal to 2.

15. The gate driving circuit according to claim 1, wherein: The shift register further includes a first light-emitting clock signal terminal and a second light-emitting clock signal terminal; In the second target mode, a trigger signal is input to the input terminal of the shift register. When the trigger signal is at a non-enable level, the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains at least two enable levels. The switch module is always cut off, and the scan signal output module does not output the scan clock signal. The target light-emitting clock signal terminal is the first light-emitting clock signal terminal or the second light-emitting clock signal terminal.

16. The gate driving circuit according to claim 15, wherein: In the first target mode, a trigger signal is input to the input terminal of the shift register, and in a non-enable level stage of the trigger signal, the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains an enable level.

17. The gate driving circuit according to claim 1, wherein: The shift register further includes a bootstrap module; The first end of the bootstrap module is electrically connected to the second end of the scan signal output module, and the second end of the bootstrap module is electrically connected to the control end of the scan signal output module.

18. The gate driving circuit according to claim 17, wherein: The bootstrap module includes a bootstrap capacitor, a first electrode of the bootstrap capacitor is electrically connected to the second end of the scan signal output module, and a second electrode of the bootstrap capacitor is electrically connected to the control end of the scan signal output module.

19. The gate driving circuit according to claim 1, wherein: The shift register further includes a second light emitting control signal output module; The first end of the second light-emitting control signal output module is electrically connected to the second level voltage end, and the second end of the second light-emitting control signal output module is electrically connected to the first output end of the shift register, and is used to transmit the second level voltage signal provided by the second level voltage end to the first output end of the shift register in response to the conduction level of the control end of the second light-emitting control signal output module.

20. The gate driving circuit according to claim 19, wherein: The shift register further includes a light-emitting control signal shift control module, which includes a first light-emitting clock signal terminal, a second light-emitting clock signal terminal, and an input terminal of the shift register, a first output terminal of the light-emitting control signal shift control module being electrically connected to the control terminal of the first light-emitting control signal output module, and a second output terminal of the light-emitting control signal shift control module being electrically connected to the control terminal of the second light-emitting control signal output module; The light-emitting control signal shift control module is used to output a conduction level or an off-level from the first output end of the light-emitting control signal shift control module, and to output a conduction level or an off-level from the second output end of the light-emitting control signal shift control module under the control of the first light-emitting clock signal end, the second light-emitting clock signal end and the shift register input end.

21. A driving method for a gate driving circuit, characterized in that: Applied to the gate drive circuit according to any one of claims 1 to 20, the method comprising: In the first target mode, in at least part of the stage when the control end of the first light-emitting control signal output module is at the on-level, the control switch module is turned on, so that the scan signal output module responds to the on-level of the control end of the first light-emitting control signal output module and transmits the enable level of the scan clock signal provided by the first scan clock signal end to the second output end of the shift register.

22. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit as claimed in any one of claims 1 to 20.

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