A 9T1C storage circuit, multiplication and accumulation circuit, in-memory operation circuit, and chip

Abstract

The present invention belongs to the field of integrated circuit technology, specifically relating to a 9T1C storage-calculation circuit, a multiplication-accumulation circuit, an in-memory arithmetic circuit, and a chip. The 9T1C storage-calculation circuit has data read / write retention functions and multiplication operations. The 9T1C storage-calculation circuit is composed of six NMOS transistors N0 to N5, three PMOS transistors P0 to P2, and one capacitor C0. P0, N0, P1, and N1 in the circuit form a cross-coupling structure for latching data. N2 and N3 serve as transmission transistors, located on the left and right sides of the cross-coupling structure, respectively, as two storage node write paths. N4 and P2 form a transmission gate. N5 serves as a calculation control terminal, and C0 serves as a capacitor for transmitting voltage differences. The multiplication-accumulation arithmetic circuit includes an arithmetic array composed of 9T1C storage-calculation circuits arranged in columns, a word line group, a bit line group, an input signal line IL, an output signal line OL, a column switch S, and a quantization circuit. Furthermore, the in-memory arithmetic circuit is formed. Compared with existing solutions, the present invention improves the performance of the storage-calculation circuit in terms of power consumption, stability, accuracy, and computational efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a 9T1C storage-calculation circuit, a multiplication-accumulation circuit designed using the 9T1C storage-calculation circuit, an in-memory calculation circuit based on 9T1C-SRAM, and a CIM chip based on 9T1C-SRAM. Background Art

[0002] With the continuous development of information technology, big data has become integrated into every aspect of human life, greatly improving productivity and bringing convenience to people. Informatization and large-scale data processing tasks rely on the computing power of various integrated circuits. In recent years, the rapid iteration of integrated circuit manufacturing processes and technologies has proven Moore's Law, leading to continuous improvements in chip performance and exponential growth in chip data processing capabilities. However, as chip manufacturing processes reach below 10 nanometers, significant improvements in the computing performance of a single chip are becoming increasingly difficult, limiting the computing performance of integrated circuits. Furthermore, computer systems based on the von Neumann architecture require separate processing and storage of data in the processor and memory, with data transmission between the two. This architecture has become another factor limiting the growth of computing power. With no major breakthroughs in chip manufacturing processes expected in the near future, scientists in the computer and big data fields are increasingly focusing their efforts on research projects focused on breakthroughs in the von Neumann architecture.

[0003] Computing in memory (CIM) has attracted widespread attention as an effective strategy to break through the von Neumann architecture. CIM combines memory and computing modules into one, significantly reducing data movement and, in turn, saving time and energy. Currently, scientists from universities and research teams at major companies around the world are actively pursuing this area, resulting in a flourishing research landscape.

[0004] SRAM, due to its high speed, low power consumption, and good logic circuit compatibility, is widely used for high-speed caches closest to computing units. Current research on SRAM-based in-memory computing focuses primarily on the voltage, current, and charge domains. Standard SRAM cells implement data storage operations based on voltage-domain signals, while current-domain computing cells primarily benefit from simplicity and compatibility with standard SRAM cells. However, due to inherent nonlinearities and process variations in access transistors, both devices suffer from relatively low computational accuracy. Charge-domain intermetallic compounds (IMCs) offer improved computational accuracy and higher parallelism. Computations are performed on capacitors, whose current variations are much smaller than those of the smallest access transistors. Furthermore, charge-sharing-based operations are unaffected by the active area of ​​transistors, allowing more capacitors to be simultaneously active, resulting in higher throughput and efficiency gains. However, the design of storage arithmetic circuits based on charge-domain SRAM is more complex and challenging, resulting in fewer circuit designs compared to the previous two approaches. These designs often fail to simultaneously meet user requirements for power consumption, data storage stability and accuracy, and logic performance. Summary of the Invention

[0005] In order to solve the problem that the existing SRAM-based storage and calculation circuits cannot achieve comprehensive improvement in power consumption, stability, accuracy and calculation efficiency, the present invention provides a 9T1C storage and calculation circuit, a multiplication and accumulation calculation circuit, an in-memory calculation circuit, and a chip.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] A 9T1C storage circuit has data read / write retention and multiplication functions. The 9T1C storage circuit consists of six NMOS transistors N0 to N5, three PMOS transistors P0 to P2, and one capacitor C0. The circuit connection relationship is as follows:

[0008] The gate of P1, the gate of N1, the drain of P0, the drain of N0, the drain of N2, and the gate of N4 are connected and serve as storage node Q. The gate of P0, the gate of N0, the drain of N1, the drain of P1, the drain of N3, and the gate of P2 are connected and serve as inverted storage node QB. The sources of P0 and P1 are connected and connected to VDD. The sources of N0 and N1 are connected and connected to VSS. The gates of N2 and N3 are connected to word line WWL; the gate of N5 is connected to word line WLR. The source of N2 is connected to bit line BL; the sources of N3 and N5 are connected to bit line BLB. The drain of N4 is connected to the source of P2 and to bit line IL. The source of N4, the drain of P2, and the drain of N5 are connected and connected to the right plate of capacitor C0, and the left plate of capacitor C0 is connected to bit line OL.

[0009] In the circuit structure of the 9T1C storage and calculation circuit provided by the present invention, P0 and N0 constitute an inverter, and P1 and N1 constitute another inverter; the two inverters form a cross-coupling structure, thereby forming two storage nodes Q and QB for storing and maintaining data; N2 and N3 serve as transmission tubes, respectively located on the left and right sides of the cross-coupling structure as two storage node write paths; N4 and P2 constitute a transmission gate; N5 serves as a calculation control terminal, and C0 serves as a capacitor for transmitting the voltage difference.

[0010] Based on the above circuit connection state, the 9T1C memory-calculation circuit provided by the present invention supports single-ended bidirectional access during the data read phase. Furthermore, when performing multiplication operations, the 9T1C unit can perform multiplication between single-bit numbers or between single-bit numbers and multi-bit numbers.

[0011] As a further improvement of the present invention, the operation logic of the 9T1C storage and calculation circuit for performing data read and write retention is as follows:

[0012] 1. Data write operation

[0013] The word line WLR is set to a low level, and the word line WWL is set to a high level; then, the data to be stored is written into the storage nodes Q and QB through the bit lines BL and BLB.

[0014] In the data write operation state, the bit lines IL and OL can also be set to a high level to keep the voltage across the capacitor at a high level, thereby eliminating the voltage difference across the capacitor, reducing charge transfer, and thus reducing device power consumption.

[0015] 2. Data retention operation

[0016] The word lines WLR and WLL are set to a low level, and the bit lines BL, BLB, IL and OL are set to a high level; at this time, N2 and N3 are turned off, and the storage nodes Q and QB are connected to the gates of N4 and P2 respectively.

[0017] Analysis of the circuit reveals that in the data hold state, NMOS transistors N2 and N3 are both off, and storage nodes Q and QB are connected to the gates of NMOS transistor N4 and PMOS transistor P2, respectively. Therefore, bit lines BL, BLB, OL, and IL have no effect on storage nodes Q or QB. The latch structure formed by PMOS transistors P0, NMOS transistor N0, PMOS transistor P1, and NMOS transistor N1 can stably latch the data at storage nodes Q and QB.

[0018] 3. Data Read Operation

[0019] The 9T1C memory-calculation circuit provided by the present invention is a device with single-ended bidirectional access capabilities, that is, it supports two different methods for reading data from storage nodes. Specifically, the data read operations supported by the 9T1C memory-calculation circuit provided by the present invention are divided into the following column read mode and row read mode:

[0020] 1. In column read mode, the word line WWL is set to a low level, the word line WLR is set to a high level, the bit lines BL, BLB and OL are set to a high level, and the bit line IL is set to a low level. The read operation result of the QB node is reflected on the bit line BLB:

[0021] (1) If the bit line BLB can maintain a high level, it means that the data stored in the node QB is 1 and the data stored in the node Q is 0.

[0022] (2) If the voltage of the bit line BLB drops, it means that the data stored in the node QB is 0 and the data stored in the node Q is 1.

[0023] 2. In row read mode, the word line WWL is set to a low level, the word line WLR is set to a high level, the bit lines BL, BLB and OL are set to a high level, and the bit line IL is set to a low level. The read operation result of the Q node is reflected on the bit line IL:

[0024] (1) If the bit line IL can maintain a low level, it means that the data stored in the node Q is 0, and correspondingly, the data stored in the node QB is 1.

[0025] (2) If the voltage of the bit line IL increases, it means that the data stored in the node Q is 1, and correspondingly, the data stored in the node QB is 0.

[0026] As a further improvement of the present invention, the 9T1C storage-calculation circuit performs multiplication operations in two modes: single-multiplication-single mode and single-multiplication-multiple mode. The specific operation logic is as follows:

[0027] (1) In the data write mode, the first operand is written to the storage node Q of the 9T1C storage circuit.

[0028] Furthermore, it should be emphasized that writing the first operand is not mandatory. Because each 9T1C storage circuit already has data stored in its storage node Q or QB after power-up, the present invention can directly select the corresponding 9T1C storage circuit to perform the multiplication task of this solution, eliminating the need for additional data writing.

[0029] (2) Precharge each signal line, including: setting the bit line OL to a high level, IL to a low level, WLR to a high level, WWL to a low level, and BLB to a low level.

[0030] (3) The second operand is input into the 9T1C storage circuit through the bit line IL.

[0031] In the single-by-single mode, the second operand input is the high or low level representing the binary number 1 or 0. In the single-by-multiple mode, the second operand is the corresponding voltage value V obtained by performing digital-to-analog conversion on the multi-bit binary number according to the preset rules. DAC .

[0032] (4) The bit line OL is suspended, and then the current voltage of the bit line OL after the charge in C0 is redistributed is obtained and quantized as the product result.

[0033] In the single-multiplication-single mode, when the voltage of the bit line OL is VDD, the multiplication result is 0, and when the voltage of the bit line OL is 0, the multiplication result is 1. In the single-multiplication-multiple mode, when the first operand is 0, the voltage of the bit line OL is VDD, that is, the multiplication result is 0; when the first operand is 1, the voltage of the bit line OL is VDD-V DAC ;VDD-V DAC After the numbers are converted according to the preset rules, a multi-digit binary number is obtained, which is the product.

[0034] As a further improvement of the present invention, the 9T1C storage circuit should perform a reset operation in the non-operation phase to reduce the power consumption of the circuit; the operation logic of the reset operation is as follows:

[0035] Set the word line WWL to a low level, the word line WLR to a high level, the bit lines BL, BLB, OL, and IL to a high level, and charge the left plate of capacitor C0 through BLB via N5, so that the voltage difference across capacitor C0 is cleared.

[0036] In the above-mentioned 9T1C storage-calculation circuit, the present invention further provides a multiplication-accumulation circuit, which includes: an operation array, a word line group, a bit line group, an input signal line IL, an output signal line OL, a column switch S and a quantization circuit.

[0037] The operation array is composed of N aforementioned 9T1C memory circuits arranged in columns. The word line group includes N word lines WLL and N word lines WLR. Each 9T1C memory circuit in the operation array is connected to an independent set of word lines WLL and WLR; word lines WLL and WLR are used to select the 9T1C memory circuit in each row before a multiplication-accumulation operation to write the first operand of the multiplication-accumulation operation. The bit line group includes one bit line BL and one bit line BLB; all 9T1C memory circuits in the same column are connected to the same bit lines BL and BLB, which are used to write the first operand of the multiplication-accumulation operation into each 9T1C memory circuit.

[0038] There are N input signal lines IL. Each 9T1C memory / calculation circuit in the computation array is connected to an independent input signal line IL, which serves as the input for the second operand in its respective computation. There is one output signal line OL. All 9T1C memory / calculation circuits in the same column are connected to this output signal line OL, which serves as the output terminal for the multiplication-accumulation result. A column switch S is connected between the output signal line OL and the power supply VDD to control the connection between the output signal line OL and the power supply VDD.

[0039] The quantization circuit is connected to the output signal line OL and is used to convert the voltage value on the output signal line OL into a digital value representing the result of the multiplication and accumulation operation.

[0040] As a further improvement of the present invention, the operation logic of the multiplication-accumulation-addition circuit performing the multiplication-accumulation-addition operation is as follows:

[0041] (1) Preparation stage:

[0042] A reset operation is performed on all 9T1C storage circuits in the operation array to ensure that the initial states of all capacitors C0 in the operation array are the same, that is, the right plate voltage Vc of the capacitor C0 remains consistent.

[0043] (2) Pre-storage stage:

[0044] The word lines WLR and WWL of each row are sequentially set to low level and high level, and the first operands of the respective storage nodes in the 9T1C memory circuits of each row are written through the bit lines BL and BLB.

[0045] (3) Pre-charge stage:

[0046] Close the column switch S, connect the output signal line OL to VDD, so that the left plate of each capacitor C0 is precharged to VDD; set WLR to a high level, and BLB to a low level, so that the right plate of each capacitor C0 is precharged to "0"; and the bit line IL is precharged to a low level.

[0047] (4) Product operation stage

[0048] The input voltage V after digital-to-analog conversion is input to each 9T1C storage circuit through the input signal line IL DAC At this time, WLR is set to a low level, the column switch S is still closed, and the voltage difference across the capacitor C0 in each 9T1C storage circuit changes as follows according to the Q value of the storage cell:

[0049] a. When Q = "1", the transmission gate is open, and the input value is input to the right plate of capacitor C0 through the transmission gate. The voltage of the left plate of capacitor C0 remains at VDD, and the voltage of the right plate of capacitor C0 remains at V DAC ; At this time, the voltage difference between the two ends of capacitor C0 is VDD-VDAC .

[0050] b. When Q = "0", the transmission gate is closed; the voltage on the left plate of capacitor C0 remains at VDD, and the voltage on the right plate of capacitor C0 is 0; at this time, the voltage difference between the two ends of capacitor C0 remains at VDD.

[0051] It can be seen from this that the multiplication results of each 9T1C storage circuit are accumulated on the right plate of each capacitor C0.

[0052] (5) Accumulation operation stage:

[0053] Open the column switch S, leaving the output signal line OL floating, that is, the left plate of the capacitor floating. Then, set WLR to a high level and the bit line IL to a low level, so that the voltage on the left plate of capacitor C0 in each row changes as follows according to the Q value of the memory cell:

[0054] a. When Q = "1", the transmission gate is open, and the voltage value of the right plate of capacitor C0 is pulled down to 0 by the bit line IL. At this time, the voltage difference between the two ends of capacitor C0 cannot change suddenly, and the voltage difference of capacitor C0 during the multiplication phase is VDD-V DAC , so the voltage value of the left plate of capacitor C0 becomes VDD-V DAC .

[0055] b. When Q = "0", the transmission gate is closed and the voltage difference across capacitor C0 remains at VDD, so the voltage on the left plate of capacitor C0 remains at VDD.

[0056] At this time, the multiplication result of each 9T1C storage circuit is reflected as the value of the power supply voltage VDD minus the voltage of the left plate of capacitor C0; because the bit line OL of a column is shared, the charge of the left plate of capacitor C0 in each 9T1C storage circuit is shared, and the analog value corresponding to the final multiplication and accumulation result is obtained on the bit line OL.

[0057] (6) Quantized output

[0058] The voltage value of OL is converted into the corresponding digital value according to the preset analog-to-digital conversion rules, which is the final multiplication and accumulation operation result.

[0059] The present invention also includes an in-memory arithmetic circuit based on 9T1C-SRAM, which has data read / write retention functions, multiplication functions, and multiplication-accumulation functions. It supports single-ended bidirectional access during the data read phase; the multiplication and multiplication-accumulation functions supported by the circuit include single-bit multiplication and multi-bit multiplication. Specifically, based on functional division, the in-memory arithmetic circuit based on 9T1C-SRAM provided by the present invention includes: a memory arithmetic array, a word line group, a bit line group, an input signal line group, an output signal line group, a word line driver, a decoder, a precharge circuit, a timing control module, a mode switch, a read / write control circuit, a switch control circuit, an input module, and a quantized output circuit.

[0060] The memory and arithmetic array is composed of N×M aforementioned 9T1C memory and arithmetic circuits arranged in an array of N rows and M columns. The word line group includes N word lines WLL and N word lines WLR. All 9T1C memory and arithmetic circuits in a row of the memory and arithmetic array are connected to the same set of word lines WLL and WLR. The bit line group includes M bit lines BL and M bit lines BLB. All 9T1C memory and arithmetic circuits in the same column of the memory and arithmetic array are connected to the same bit lines BL and BLB. The input signal line group includes N input signal lines IL. All 9T1C memory and arithmetic circuits in a row of the memory and arithmetic array are connected to a single input signal line IL. The output signal line group includes M output signal lines OL. All 9T1C memory and arithmetic circuits in the same column of the memory and arithmetic array are connected to a single output signal line OL.

[0061] The wordline driver controls the activation of each wordline (WLR) and wordline (WWL). A decoder is connected to the wordline driver, decoding the address signal and transmitting it to the wordline driver. The precharge circuit precharges the bitlines (BL, BLB) and output signal line (OL). The timing control module generates the clock signals required to perform data storage tasks or multiplication and multiply-accumulate operations. The mode switch switches the operating mode of the in-memory arithmetic circuit, which includes data storage mode and logic operation mode. The read / write control circuit controls the data read and write operations performed by the in-memory arithmetic circuit.

[0062] The switch control circuit includes M column switches S, each connected between one of the output signal lines OL and the power supply VDD, controlling the connectivity between that line and VDD. During the multiplication or multiply-accumulate operation phase, the input module performs digital-to-analog conversion on the second operand and then inputs the result to the corresponding 9T1C storage circuit via the input signal line IL.

[0063] The quantized output circuit is connected to the output signal line OL, the bit line BLB, and the input signal line IL. It includes a data read section and an arithmetic output section. The data read section outputs the stored data of each storage node. The arithmetic output section performs analog-to-digital conversion on the voltage at OL and outputs the corresponding multiplication result or multiply-accumulate result.

[0064] As a further improvement of the present invention, in a memory-calculation array, each 9T1C memory-calculation circuit serves as a basic unit for implementing data storage and multiplication operations. All 9T1C memory-calculation circuits in the same column, along with column switches S, form a basic unit for performing multiplication-accumulation operations. The 9T1C memory-calculation circuits in each column of this 9T1C-SRAM-based in-memory arithmetic circuit support parallel execution of multiplication-accumulation operations.

[0065] The present invention also includes a 9T1C-SRAM-based CIM chip, which is encapsulated by the aforementioned 9T1C-SRAM-based in-memory arithmetic circuit.

[0066] The technical solution provided by the present invention has the following beneficial effects:

[0067] The 9T1C-SRAM device designed in the present invention is a charge domain SRAM device that has conventional data read, write and retention performance, and can also implement single-bit and multi-bit multiplication operations. It is a CIM circuit with better performance and broader application prospects.

[0068] In the circuit provided by the present invention, the calculation process is performed on capacitors, and the current change of capacitors is much smaller than that of the smallest connected transistors. At the same time, the charge-sharing-based operation is not affected by the transistor's operating area, and more capacitors can be turned on simultaneously, thereby achieving higher throughput and efficiency gains, significantly improving the efficiency and accuracy of multiplication and accumulation operations.

[0069] The device provided by the present invention utilizes the characteristic that the voltage across a capacitor cannot change suddenly to perform multiplication and addition calculations, thereby improving linearity and computational accuracy. The device can perform single-sided calculations and support lossless equal division of multi-bit inputs, thus achieving higher computational accuracy and parallelism.

[0070] From the perspective of data storage, the 9T1C-SRAM provided by the present invention has a simple circuit structure and low power consumption. Furthermore, due to the use of read decoupling, it can effectively solve the problem of read corruption and improve the security and stability of data stored in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0072] Figure 1 This is a circuit diagram of a 9T1C storage and calculation circuit provided in Example 1 of the present invention.

[0073] Figure 2 for Figure 1 The working principle diagram of the circuit when the data read node adopts the column read mode.

[0074] Figure 3 for Figure 1 The working principle diagram of the circuit when the data read node adopts the row read mode.

[0075] Figure 4 for Figure 1 The signal state diagram when the circuit completes the single-bit multiplication operation of 0×0=0.

[0076] Figure 5 for Figure 1 The signal state diagram when the circuit completes the single-bit multiplication operation of 0×1=0.

[0077] Figure 6 for Figure 1 The signal state diagram when the circuit completes the single-bit multiplication operation of 1×0=0.

[0078] Figure 7 for Figure 1 The signal state diagram when the circuit completes the single-bit multiplication operation of 1×1=1.

[0079] Figure 8 for Figure 1 The circuit in FIG1 is an operation timing diagram of different stages when performing multi-bit multiplication.

[0080] Figure 9 for Figure 1 The signal state diagram when the circuit completes the multi-bit multiplication operation of 0×V=0.

[0081] Figure 10 for Figure 1 The signal state diagram when the circuit completes the multi-bit multiplication operation of 1×V=V.

[0082] Figure 11 for Figure 8 Figure 2 shows the waveforms of the signals during the execution of two different multi-bit multiplication operations.

[0083] Figure 12 This is a module diagram of a multiplication-accumulation circuit provided in Example 2 of the present invention.

[0084] Figure 13 This is a state diagram of a 4×1 multiplication-accumulation operation array executing an operation task in embodiment 2 of the present invention.

[0085] Figure 14 An architectural diagram of an in-memory arithmetic circuit based on 9T1C-SRAM provided in Example 3 of the present invention.

[0086] Figure 15 This is a state diagram of a parallel multiplication-accumulation operation task performed using a 4×4 multiplication-accumulation operation array in embodiment 3 of the present invention.

[0087] Figure 16 for Figure 15 The waveform diagram of each signal during the execution phase of the corresponding computing task. DETAILED DESCRIPTION

[0088] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0089] Example 1

[0090] This embodiment provides a 9T1C storage circuit, which has data read and write retention functions and multiplication functions. Figure 1 As shown, the 9T1C storage and calculation circuit provided in this embodiment is composed of 6 NMOS transistors N0 to N5, 3 PMOS transistors P0 to P2 and 1 capacitor C0. The circuit connection relationship is as follows:

[0091] The gate of P1, the gate of N1, the drain of P0, the drain of N0, the drain of N2, and the gate of N4 are connected and serve as storage node Q. The gate of P0, the gate of N0, the drain of N1, the drain of P1, the drain of N3, and the gate of P2 are connected and serve as inverted storage node QB. The sources of P0 and P1 are connected and connected to VDD. The sources of N0 and N1 are connected and connected to VSS. The gates of N2 and N3 are connected to word line WWL; the gate of N5 is connected to word line WLR. The source of N2 is connected to bit line BL; the sources of N3 and N5 are connected to bit line BLB. The drain of N4 is connected to the source of P2 and to bit line IL. The source of N4, the drain of P2, and the drain of N5 are connected and connected to the right plate of capacitor C0, and the left plate of capacitor C0 is connected to bit line OL.

[0092] In the circuit structure of the 9T1C storage-calculation circuit provided in this embodiment, P0 and N0 form an inverter, and P1 and N1 form another inverter. The two inverters form a cross-coupling structure, which in turn forms two storage nodes, Q and QB, for storing and retaining data. N2 and N3 act as transmission transistors, located on the left and right sides of the cross-coupling structure, and serve as write paths for the two storage nodes. N4 and P2 form a transmission gate; N5 serves as the calculation control terminal, and C0 acts as a capacitor to transmit the voltage difference.

[0093] Based on the above circuit connection state, the 9T1C memory-calculation circuit provided in this embodiment supports single-ended bidirectional access during the data read phase. Moreover, when performing multiplication operations, the 9T1C unit can perform multiplication between single-bit numbers or between single-bit numbers and multi-bit numbers.

[0094] The 9T1C storage circuit performs the following operation logic for data read, write, and hold:

[0095] 1. Data write operation

[0096] The word line WLR is set to a low level, and the word line WWL is set to a high level; then, the data to be stored is written into the storage nodes Q and QB through the bit lines BL and BLB.

[0097] In the data write operation state, the bit lines IL and OL can also be set to a high level to keep the voltage across the capacitor at a high level, thereby eliminating the voltage difference across the capacitor, reducing charge transfer, and thus reducing device power consumption.

[0098] 2. Data retention operation

[0099] The word lines WLR and WLL are set to a low level, and the bit lines BL, BLB, IL and OL are set to a high level; at this time, N2 and N3 are turned off, and the storage nodes Q and QB are connected to the gates of N4 and P2 respectively.

[0100] Analysis of the circuit reveals that in the data hold state, NMOS transistors N2 and N3 are both off, and storage nodes Q and QB are connected to the gates of NMOS transistor N4 and PMOS transistor P2, respectively. Therefore, bit lines BL, BLB, OL, and IL have no effect on storage nodes Q or QB. The latch structure formed by PMOS transistors P0, NMOS transistor N0, PMOS transistor P1, and NMOS transistor N1 can stably latch the data at storage nodes Q and QB.

[0101] 3. Data Read Operation

[0102] The 9T1C memory-calculation circuit provided in this embodiment is a device with single-ended bidirectional access capabilities, that is, it supports two different methods for reading data from storage nodes. Specifically, the data read operations supported by the 9T1C memory-calculation circuit provided by the present invention are divided into the following column read mode and row read mode:

[0103] 1. In column read mode, the word line WWL is set to a low level, the word line WLR is set to a high level, the bit lines BL, BLB and OL are set to a high level, and the bit line IL is set to a low level. The read operation result of the QB node is reflected on the bit line BLB:

[0104] (1) If the bit line BLB can maintain a high level, it means that the data stored in the node QB is 1 and the data stored in the node Q is 0.

[0105] (2) If the voltage of the bit line BLB drops, it means that the data stored in the node QB is 0 and the data stored in the node Q is 1.

[0106] The following combination Figure 2 The column read mode is further explained. Figure 2 In the 9T1C memory-calculation circuit, the data stored in storage node Q is "1," meaning storage node Q is high and QB is low. At the start of a column read operation, bit lines BL and BLB are precharged high, word line WWL is set low, word line WLR is set high, and NMOS transistors N4 and N5 and PMOS transistor P2 are turned on. Bit line BLB then discharges to bit line IL through transfer transistor N5 and transfer gates N4 and P2. At this point, the voltage on bit line BLB drops, and after amplification by the analog-to-digital converter (ADC), the readout result is "0." In other words, the data stored in storage node QB, read by BLB, is "0," and correspondingly, the data stored in storage node Q is "1." This matches the data actually stored in the storage node.

[0107] Conversely, if the data stored in the storage node Q of the memory cell is "0" before the column read operation, that is, Q is low and QB is high, then transmission gates N4 and P2 will not be turned on, BLB will remain high, and the output result will be QB's value being "1" and the corresponding Q's value being "0".

[0108] 2. In row read mode, the word line WWL is set to a low level, the word line WLR is set to a high level, the bit lines BL, BLB and OL are set to a high level, and the bit line IL is set to a low level. The read operation result of the Q node is reflected on the bit line IL:

[0109] (1) If the bit line IL can maintain a low level, it means that the data stored in the node Q is 0, and correspondingly, the data stored in the node QB is 1.

[0110] (2) If the voltage of the bit line IL increases, it means that the data stored in the node Q is 1, and correspondingly, the data stored in the node QB is 0.

[0111] The following combination Figure 3 The column read mode is further explained. Figure 3In the 9T1C memory-calculation circuit, the data stored in storage node Q is "1," meaning that storage node Q is high and QB is low. At the start of a row read operation, bit lines BL and BLB are precharged high, word line WWL is set low, and word line WLR is set high. NMOS transistors N4 and N5, and PMOS transistor P2 are turned on. BLB charges IL through transfer transistor N5 and transfer gates N4 and P2, pulling the voltage on bit line IL high. After amplification by the analog-to-digital converter (ADC), the data stored in storage node Q is read as "1," and accordingly, the value of storage node QB becomes "0."

[0112] On the contrary, if the data stored in the storage node Q of the memory cell is "0" before the row read operation, that is, Q is low and QB is high, then the transmission gates N4 and P2 will not be turned on, IL will still remain low, and the output result will be Q's value "0" and the corresponding QB's value "1".

[0113] 4. Multiplication

[0114] The 9T1C memory circuit provided in this embodiment has the function of performing multiplication operations. In particular, the multiplication operations supported by this type of 9T1C memory circuit include single-multiplication single mode and single-multiplication multiple mode. The specific operation logic is as follows:

[0115] (1) In the data write mode, the first operand is written to the storage node Q of the 9T1C storage circuit.

[0116] Furthermore, it should be emphasized that writing the first operand is not mandatory. Because each 9T1C storage circuit already has data stored in storage node Q or QB when powered on, the present invention can directly select the corresponding 9T1C storage circuit to perform the multiplication task of this solution, eliminating the need for additional data writing.

[0117] (2) Precharge each signal line, including: setting the bit line OL to a high level, IL to a low level, WLR to a high level, WWL to a low level, and BLB to a low level.

[0118] (3) The second operand is input into the 9T1C storage circuit through the bit line IL.

[0119] In the single-by-single mode, the second operand input is the high or low level representing the binary number 1 or 0. In the single-by-multiple mode, the second operand is the corresponding voltage value V obtained by performing digital-to-analog conversion on the multi-bit binary number according to the preset rules. DAC .

[0120] (4) The bit line OL is suspended, and then the current voltage of the bit line OL after the charge in C0 is redistributed is obtained and quantized as the product result.

[0121] In the single-multiplication-single mode, when the voltage of the bit line OL is VDD, the multiplication result is 0, and when the voltage of the bit line OL is 0, the multiplication result is 1. In the single-multiplication-multiple mode, when the first operand is 0, the voltage of the bit line OL is VDD, that is, the multiplication result is 0; when the first operand is 1, the voltage of the bit line OL is VDD-V DAC ;VDD-V DAC After the numbers are converted according to the preset rules, a multi-digit binary number is obtained, which is the product.

[0122] The following uses single-bit multiplication and multi-bit multiplication as examples to explain the process of performing multiplication operations by the 9T1C storage-calculation circuit of this embodiment:

[0123] In this embodiment, the four states of the 9T1C storage circuit performing multiplication operations between single-bit numbers are as follows: Figure 4-7 shown.

[0124] exist Figure 4 In the 9T1C storage-calculation circuit, the first operand has already been pre-stored, that is, Q = 0. In this state, if the input of bit line IL is low, it indicates that the second operand is 0. Before the operation begins, OL is pre-charged to a high level, and then OL is left floating during the operation phase. At this time, because Q = 0, transmission gates N4 and P2 are not conducting, and OL ultimately remains at the high level VDD. The high level state of OL is defined as 0, and the product result is 0, and the multiplication operation implemented is 0 × 0 = 0.

[0125] exist Figure 5 In the 9T1C storage-calculation circuit, the first operand has already been pre-stored, i.e., Q = 0. In this state, if the input to bit line IL is at a high level (VDD), the second operand is 1. Before the operation begins, OL is pre-charged to a high level, and then remains floating during the operation phase. At this time, since Q = 0, transmission gates N4 and P2 are not conducting, and OL ultimately remains at a high level (VDD). The high level state of OL is defined as 0, and the product is 0, achieving the multiplication operation of 0 × 1 = 0.

[0126] exist Figure 6In the 9T1C storage circuit, the first operand has already been pre-stored, i.e., Q = 1. In this state, if the input to bit line IL is low, the second operand is 0. Before the operation begins, OL is pre-charged to a high level, and then OL is left floating during the operation phase. At this time, because Q = 1, transmission gates N4 and P2 are turned on, connecting bit line IL to the right plate of the capacitor, keeping the voltage on the right plate low. OL ultimately remains at a high level, VDD. The high level state of OL is defined as 0, and the product is 0, achieving the multiplication operation of 1 × 0 = 0.

[0127] exist Figure 7 In the example, the 9T1C storage circuit has already pre-stored the first operand, i.e., Q = 1. In this state, if the input to bit line IL is at a high level (VDD), the second operand is 1. Before the operation begins, OL is pre-charged to a high level, and then remains floating during the operation phase. At this time, because Q = 1, transmission gates N4 and P2 are turned on, connecting bit line IL to the right plate of the capacitor, causing the voltage on the right plate to reach a high level. This causes OL to discharge to a low level. The low level state of OL is defined as 1, and the product is 1, achieving a multiplication operation of 1 × 1 = 1.

[0128] In summary: Figure 1 The truth table of the 9T1C storage circuit in performing single-bit multiplication is shown in the following table:

[0129] Table 1: Single-bit multiplication truth table of the 9T1C storage circuit in this embodiment

[0130]

[0131] In this embodiment, the operation process of the 9T1C storage circuit performing the multiplication operation between single-bit numbers and multi-bit numbers can be combined with Figure 8 To explain, Figure 8 The left part of the middle part is the 1-bit digital "1" as the first operand, V DAC (the analog value corresponding to the multi-bit number) is the second operand of the multiplication operation. The right part is the 1-bit digital "0" as the first operand, V DAC The operation process is roughly divided into three stages: the pre-charge stage closes the column switch S to pre-charge OL to a high level; the input stage closes V DAC It is input to the 9T1C storage and calculation circuit through the input signal line IL; in the calculation stage, IL is reset to a low level and the column switch S is disconnected.

[0132] Specifically, the operation process of multiplying 0 by a multi-bit number can be combined with Figure 8 The right part and Figure 9 .exist Figure 9 In the example, the 9T1C storage circuit has already completed the pre-storage of the first operand, that is, Q = 0. Then, any multi-bit binary number can be converted into a corresponding analog potential V according to a specific encoding rule. DAC ; Then the analog potential V DAC The second operand is input to the 9T1C storage circuit via bit line IL. Before the operation begins, OL is precharged to a high level, and then left floating during the operation phase. At this point, since Q = 0 and transmission gates N4 and P2 are not conducting, OL remains at a high level, VDD. Defining the low-high VDD state of OL as 0 indicates a product of 0, resulting in a multiplication operation of 0 × V = 0. Here, "V" represents any multi-bit binary number. That is, when the first operand is 0, the product is 0 regardless of the value of the second operand.

[0133] Specifically, the operation process of multiplying 1 by a multi-bit number can be combined with Figure 8 The left part and Figure 10 .exist Figure 10 In the example, the 9T1C storage circuit has already completed the pre-storage of the first operand, that is, Q = 1. Then, for any multi-bit binary number, it can be converted into a corresponding analog potential V according to a specific encoding rule. DAC ; Then the analog potential V DAC The bit line IL is input to the 9T1C storage circuit as the second operand. Before the operation begins, OL is precharged to a high level, and then OL is kept floating during the operation phase. At this time, since Q = 1, the transmission gates N4 and P2 are turned on, connecting the bit line IL to the right plate of the capacitor, thereby causing the voltage on the right plate of the capacitor to rise to V DAC , the potential of OL will drop to VDD-V according to the value of input IL DAC At this time, through a special analog-to-digital conversion rule, VDD-V DAC Converts the digital value that is the same as the second operand input. This implements the multiplication operation 1×V=V, that is, when the first operand is 1, the product is the second operand regardless of the second operand's value.

[0134] in, Figure 8 The signal timing diagrams of the two different single-bit multiplication operations are as follows: Figure 11 shown.

[0135] In summary: Figure 1 The truth table of the 9T1C storage circuit in performing multi-bit multiplication is shown in the following table:

[0136] Table 2: Truth table of multi-bit multiplication operation of the 9T1C storage circuit in this embodiment

[0137]

[0138] Thus, it can be found that the 9T1C storage-calculation circuit provided in this embodiment has a complete data storage function and can perform full-function multiplication operations, including single-bit multiplication and multi-bit multiplication.

[0139] In addition, in the 9T1C storage circuit provided in this embodiment, if there is spontaneous charge transfer between the two plates of capacitor C0 during non-operation operation, it will cause the power consumption of the device to increase. Therefore, in the non-operation phase, the 9T1C storage circuit should actively perform a zeroing operation to reduce the power consumption of the circuit. The operation logic of the zeroing operation is as follows:

[0140] Set the word line WWL to a low level, the word line WLR to a high level, the bit lines BL, BLB, OL, and IL to a high level, and charge the left plate of capacitor C0 through BLB via N5, so that the voltage difference across capacitor C0 is cleared.

[0141] Example 2

[0142] Based on the 9T1C storage circuit provided in Example 1, this embodiment further provides a multiplication and accumulation circuit. Figure 12 As shown, according to functional modules, the multiplication and accumulation circuit of this embodiment includes: an operation array, a word line group, a bit line group, an input signal line IL, an output signal line OL, a column switch S and a quantization circuit.

[0143] The operation array is composed of N 9T1C memory circuits, such as those described in Example 1, arranged in columns. A word line group includes N word lines WLL and N word lines WLR. Each 9T1C memory circuit in the operation array is connected to an independent set of word lines WLL and WLR; word lines WLL and WLR are used to select the 9T1C memory circuits in each row before a multiplication-accumulation operation to write the first operand of the multiplication-accumulation operation. A bit line group includes one bit line BL and one bit line BLB; all 9T1C memory circuits in the same column are connected to the same bit lines BL and BLB, which are used to write the first operand of the multiplication-accumulation operation into each 9T1C memory circuit.

[0144] There are N input signal lines IL. Each 9T1C memory / calculation circuit in the computation array is connected to an independent input signal line IL, which serves as the input for the second operand in its respective computation. There is one output signal line OL. All 9T1C memory / calculation circuits in the same column are connected to this output signal line OL, which serves as the output terminal for the multiplication-accumulation result. A column switch S is connected between the output signal line OL and the power supply VDD to control the connection between the output signal line OL and the power supply VDD.

[0145] The quantization circuit is connected to the output signal line OL and is used to convert the voltage value on the output signal line OL into a digital value representing the result of the multiplication and accumulation operation.

[0146] The operation logic of this type of multiplication and accumulation circuit to perform multiplication and accumulation operations is as follows:

[0147] (1) Preparation stage:

[0148] A reset operation is performed on all 9T1C storage circuits in the operation array to ensure that the initial states of all capacitors C0 in the operation array are the same, that is, the right plate voltage Vc of the capacitor C0 remains consistent.

[0149] (2) Pre-storage stage:

[0150] The word lines WLR and WWL of each row are sequentially set to low level and high level, and the first operands of the respective storage nodes in the 9T1C memory circuits of each row are written through the bit lines BL and BLB.

[0151] (3) Pre-charge stage:

[0152] Close the column switch S, connect the output signal line OL to VDD, so that the left plate of each capacitor C0 is precharged to VDD; set WLR to a high level, and BLB to a low level, so that the right plate of each capacitor C0 is precharged to "0"; and the bit line IL is precharged to a low level.

[0153] (4) Product operation stage

[0154] The input voltage V after digital-to-analog conversion is input to each 9T1C storage circuit through the input signal line IL DAC At this time, WLR is set to a low level, the column switch S is still closed, and the voltage difference across the capacitor C0 in each 9T1C storage circuit changes as follows according to the Q value of the storage cell:

[0155] a. When Q = "1", the transmission gate is open, and the input value is input to the right plate of capacitor C0 through the transmission gate. The voltage of the left plate of capacitor C0 remains at VDD, and the voltage of the right plate of capacitor C0 remains at V DAC ; At this time, the voltage difference between the two ends of capacitor C0 is VDD-V DAC .

[0156] b. When Q = "0", the transmission gate is closed, the left plate voltage of capacitor C0 remains at VDD, and the right plate voltage of capacitor C0 is 0; at this time, the voltage difference between the two ends of capacitor C0 remains at VDD.

[0157] It can be seen from this that the multiplication results of each 9T1C storage circuit are accumulated on the right plate of each capacitor C0.

[0158] (5) Accumulation operation stage:

[0159] Open the column switch S, leaving the output signal line OL floating, that is, the left plate of the capacitor floating. Then, set WLR to a high level and the bit line IL to a low level, so that the voltage on the left plate of capacitor C0 in each row changes as follows according to the Q value of the memory cell:

[0160] a. When Q = "1", the transmission gate is open, and the voltage value of the right plate of capacitor C0 is pulled down to 0 by the bit line IL. At this time, the voltage difference between the two ends of capacitor C0 cannot change suddenly, and the voltage difference of capacitor C0 during the multiplication phase is VDD-V DAC , so the voltage value of the left plate of capacitor C0 becomes VDD-V DAC .

[0161] b. When Q = "0", the transmission gate is closed and the voltage difference across capacitor C0 remains at VDD, so the voltage on the left plate of capacitor C0 remains at VDD.

[0162] At this time, the multiplication result of each 9T1C storage circuit is reflected as the value of the power supply voltage VDD minus the voltage of the left plate of capacitor C0; because the bit line OL of a column is shared, the charge of the left plate of capacitor C0 in each 9T1C storage circuit is shared, and the analog value corresponding to the final multiplication and accumulation result is obtained on the bit line OL.

[0163] (6) Quantized output

[0164] The voltage value of OL is converted into the corresponding digital value according to the preset analog-to-digital conversion rules, which is the final multiplication and accumulation operation result.

[0165] In order to verify the operation performance of the multiplication and accumulation circuit provided by this embodiment, the following Figure 13 A 4×1 array composed of four 9T1C storage and calculation circuits is used to illustrate the specific operation effect of the multiplication and accumulation circuit. Figure 13 In the figure, the storage values ​​(first operands) of the four 9T1C storage circuits from top to bottom are 1, 0, 0, 0 respectively; the second operands input to each 9T1C storage circuit are 1.2V, 0.8V, 0.8V, 0V respectively.

[0166] Therefore, the ideal calculation result of this input is 1.2×1+0.8×0+0.8×0+0×0=1.2V.

[0167] In the actual budget stage, the storage unit value of the first row is 1, IL <0> is 1.2V, so the accumulated voltage value of the left plate of the unit capacitor is VCL <0> VDD-VDAC=1.2V-1.2V=0V. The storage cell value of the second row is 0, so the accumulated voltage value of the left plate of the cell capacitor is VCL. <1> VDD = 1.2V. Similarly, the accumulated voltage value VCL of the left plate of the unit capacitor in the third row is obtained. <2> VDD = 1.2V. The accumulated voltage value VCL of the left plate of the unit capacitor in the fourth row <3> Also VDD=1.2V.

[0168] Therefore, OL=(VCL <0> +VCL <0> +VCL <2> +VCL <3> ) / 4=0.9V.

[0169] Based on the principle of the multiplication-accumulation circuit in this embodiment, it can be seen that the voltage OL of the output signal line should satisfy the following formula during the operation process:

[0170]

[0171] Therefore, the actual multiplication and accumulation result calculated by the circuit is:

[0172]

[0173] Substituting VDD = 1.2V, OL = 0.8V, we can calculate:

[0174]

[0175] That is, the actual calculation result is 1.2V. Therefore, the actual calculation result is consistent with the ideal result. The result of this multiplication and accumulation operation is completely correct.

[0176] Example 3

[0177] Based on the solutions of Example 1 and Example 2, this embodiment further provides an in-memory operation circuit based on 9T1C-SRAM, which has data read and write retention functions, multiplication operation functions, and multiplication-accumulation operation functions. It also supports single-ended bidirectional access during the data read phase; and the multiplication and multiplication-accumulation operation functions supported by the circuit include single-bit multiplication and multi-bit multiplication. Specifically, Figure 14 As shown, according to the functional division, the in-memory operation circuit based on 9T1C-SRAM provided in this embodiment includes: a memory operation array, a word line group, a bit line group, an input signal line group, an output signal line group, a word line driver, a decoder, a precharge circuit, a timing control module, a mode switch, a read-write control circuit, a switch control circuit, an input module, and a quantization output circuit.

[0178] The memory and arithmetic array is composed of N×M aforementioned 9T1C memory and arithmetic circuits arranged in an array of N rows and M columns. The word line group includes N word lines WLL and N word lines WLR. All 9T1C memory and arithmetic circuits in a row of the memory and arithmetic array are connected to the same set of word lines WLL and WLR. The bit line group includes M bit lines BL and M bit lines BLB. All 9T1C memory and arithmetic circuits in the same column of the memory and arithmetic array are connected to the same bit lines BL and BLB. The input signal line group includes N input signal lines IL. All 9T1C memory and arithmetic circuits in a row of the memory and arithmetic array are connected to a single input signal line IL. The output signal line group includes M output signal lines OL. All 9T1C memory and arithmetic circuits in the same column of the memory and arithmetic array are connected to a single output signal line OL.

[0179] The wordline driver controls the activation of each wordline (WLR) and wordline (WWL). A decoder is connected to the wordline driver, decoding the address signal and transmitting it to the wordline driver. The precharge circuit precharges the bitlines (BL, BLB) and output signal line (OL). The timing control module generates the clock signals required to perform data storage tasks or multiplication and multiply-accumulate operations. The mode switch switches the operating mode of the in-memory arithmetic circuit, which includes data storage mode and logic operation mode. The read / write control circuit controls the data read and write operations performed by the in-memory arithmetic circuit.

[0180] The switch control circuit includes M column switches S, each connected between one of the output signal lines OL and the power supply VDD, controlling the connectivity between that line and VDD. During the multiplication or multiply-accumulate operation phase, the input module performs digital-to-analog conversion on the second operand and then inputs the result to the corresponding 9T1C storage circuit via the input signal line IL.

[0181] The quantized output circuit is connected to the output signal line OL, the bit line BLB, and the input signal line IL. It includes a data read section and an arithmetic output section. The data read section outputs the stored data of each storage node. The arithmetic output section performs analog-to-digital conversion on the voltage at OL and outputs the corresponding multiplication result or multiply-accumulate result.

[0182] The 9T1C-SRAM-based in-memory arithmetic circuit in this embodiment is actually a large-scale integrated circuit composed of the basic unit circuits in Examples 1 and 2. Therefore, this circuit has the complete functionality of Examples 1 and 2. For example, in the memory-calculation array, each 9T1C memory-calculation circuit serves as a basic unit for implementing data storage and multiplication functions. All 9T1C memory-calculation circuits in the same column, together with the column switch S, form a basic unit for performing multiplication and accumulation operations.

[0183] In order to verify the parallel multiplication and accumulation performance of the memory array in the memory operation circuit based on 9T1C-SRAM, this embodiment uses Figure 15 For a 4×4 array, multiplication and addition operations are performed on four columns simultaneously, resulting in the sum of four 4-bit*1-bit multiplication results per column. The 4-bit input value is distinguished by the input voltage of the bit line IL, and the 1-bit weight is distinguished by the value of the storage cell. For example, if the input voltages are 1.2V, 0.8V, 0.8V, and 0V, and the storage cell values ​​are "0000, 1000, 0110, and 0111" in sequence, the multiplication and addition operation is performed as follows:

[0184] For the first column:

[0185] The theoretical calculation result should be: 1.2×0+0.8×0+0.8×0+0×0=0V

[0186] During the operation, because IL <0> The value of the storage unit is 0, so the accumulated voltage value of the left plate of the unit capacitor is VCL. <00> For VDD = 1.2V, VCL can be obtained by the same logic <10> 、VCL <20> 、VCL <30> Both are VDD.

[0187] So OL <0> =(VCL <00> +VCL <10> +VCL <20> +VCL <30> ) / 4=1.2V;

[0188] Further calculation shows that the result of the multiplication and accumulation operation is: 4×(1.2V-1.2V)=0.

[0189] For the second column:

[0190] The theoretical calculation result should be: 1.2×1+0.8×0+0.8×0+0×0=1.2V

[0191] During the operation, because IL <0> =1.2V, the value of the storage unit is 1, so the accumulated voltage value of the left plate of the unit capacitor is VCL <01> VDD-VDAC=1.2V-1.2V=0V. IL <1> =0.8V, the value of the storage unit is 0, so the accumulated voltage value of the left plate of the unit capacitor is VCL <11> VDD = 1.2V. IL <2> =0.8V, the value of the storage unit is 0, so the accumulated voltage value of the left plate of the unit capacitor is VCL <21> VDD = 1.2V. IL <3> =0V, the value of the storage unit is 0, so the accumulated voltage value of the left plate of the unit capacitor is VCL <31> VDD=1.2V.

[0192] So OL <1> =(VCL <01> +VCL <11> +VCL <21> +VCL <31> ) / 4=0.9V.

[0193] Further calculation shows that the result of the multiplication and accumulation operation is: 4×(1.2V-0.9V)=1.2V.

[0194] For the third column:

[0195] The theoretical calculation result should be: 1.2×0+0.8×1+0.8×1+0×0=1.6V

[0196] During the operation, because IL <0> =1.2V, the value of the storage unit is 0, so the accumulated voltage value of the left plate of the unit capacitor is VCL <02> VDD = 1.2V. IL <1> =0.8V, the value of the storage unit is 1, so the accumulated voltage value of the left plate of the unit capacitor is VCL <12> VDD-VDAC=1.2V-0.8V=0.4V. IL <2> =0.8V, the value of the storage unit is 1, so the accumulated voltage value of the left plate of the unit capacitor is VCL <22> VDD-VDAC=1.2V-0.8V=0.4V. IL <3> =0V, the value of the storage unit is 0, so the accumulated voltage value of the left plate of the unit capacitor is VCL <32> VDD=1.2V.

[0197] So OL <2> =(VCL <02> +VCL <12> +VCL <22> +VCL <32> ) / 4=0.8V;

[0198] Further calculation shows that the result of the multiplication and accumulation operation is: 4×(1.2V-0.8V)=1.6V.

[0199] For the fourth column:

[0200] The theoretical calculation result should be: 1.2×1+0.8×1+0.8×1+0×1=2.8V

[0201] During the operation, because IL <0> =1.2V, the value of the storage unit is 1, so the accumulated voltage value of the left plate of the unit capacitor is VCL <03> VDD-VDAC=1.2V-1.2V=0V;IL <1> =0.8V, the value of the storage unit is 1, so the accumulated voltage value of the left plate of the unit capacitor is VCL <13> VDD-VDAC=1.2V-0.8V=0.4V; IL <2> =0.8V, the value of the storage unit is 1, so the accumulated voltage value of the left plate of the unit capacitor is VCL <23> VDD-VDAC=1.2V-0.8V=0.4V; IL <3> =0V, the value of the storage unit is 1, so the voltage accumulated on the left plate of the unit capacitor is VCL <33> VDD-VDAC=1.2V-0V=1.2V; so OL <3> =(VCL <03> +VCL <13> +VCL <23> +VCL <33> ) / 4=0.5V.

[0202] Further calculation shows that the result of the multiplication and accumulation operation is: 4×(1.2V-0.5V)=2.8V.

[0203] In summary, the results of the four multiplication and accumulation operations completed in parallel in this embodiment are all completely correct. Figure 13 During the multiplication and accumulation operation of the array, the timing waveforms of each signal are as follows Figure 14 As shown by Figure 14 It can be seen that after three cycles, four groups of four rows of 4*1 multiplication-addition results can be obtained. These three cycles are the precharge cycle (precharging IL and OL to a preset level), the input cycle (inputting each second operand), and the calculation cycle (each array performs the calculation and reflects the result on OL). Therefore, it can be seen that the in-memory arithmetic circuit based on 9T1C-SRAM provided by this embodiment can achieve highly linear multi-bit multiplication-accumulation operations.

[0204] In addition, it should be noted that: in actual applications, the in-memory operation circuit based on 9T1C-SRAM in this embodiment can also be packaged into a CIM chip based on 9T1C-SRAM, and produced and sold as a chip.

[0205] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A 9T1C storage and calculation circuit, characterized in that: It has data read and write retention functions and multiplication functions; the 9T1C storage circuit consists of 6 NMOS transistors N0 to N5, 3 PMOS transistors P0 to P2 and 1 capacitor C0. The circuit connection relationship is as follows: The gates of P1, N1, and N4 are connected to the drains of P0, N0, and N2 and serve as storage node Q; the gates of P0, N0, and P2 are connected to the drains of N1, P1, and N3 and serve as inverted storage node QB; the sources of P0 and P1 are connected and connected to VDD; the sources of N0 and N1 are connected and connected to VSS; the gates of N2 and N3 are connected to word line WWL; the gate of N5 is connected to word line WLR; the source of N2 is connected to bit line BL; the sources of N3 and N5 are connected to bit line BLB; the drain of N4 is connected to the source of P2 and to bit line IL; the source of N4 is connected to the drains of P2 and N5 and to the right plate of capacitor C0, and the left plate of C0 is connected to bit line OL; The operation logic of multiplication is as follows: (1) In data write mode, the first operand is written to the storage node Q of the 9T1C storage circuit; (2) Precharge each signal line, including: setting the bit line OL to a high level, IL to a low level, WLR to a high level, WWL to a low level, and BLB to a low level; (3) Inputting the second operand into the 9T1C storage circuit via the bit line IL; (4) The bit line OL is suspended, and then the current voltage of the bit line OL after the charge in C0 is redistributed is obtained and quantized as the product result.

2. The 9T1C memory-calculation circuit according to claim 1, wherein: In the circuit, P0 and N0 form an inverter, and P1 and N1 form another inverter. The two inverters form a cross-coupled structure, forming two storage nodes Q and QB for storing and holding data. N2 and N3 act as transmission transistors, located on the left and right sides of the cross-coupled structure, respectively, as write paths for the two storage nodes. N4 and P2 form a transmission gate. N5 acts as a calculation control terminal, and C0 acts as a capacitor for transmitting the voltage difference. The 9T1C storage circuit supports single-ended bidirectional access during the data read phase; the multiplication operations supported by the 9T1C unit include multiplication between single-bit numbers and multiplication between single-bit numbers and multiplication between multi-bit numbers.

3. The 9T1C storage-calculation circuit according to claim 2, wherein: The operation logic of the 9T1C storage circuit for performing data read, write and hold is as follows: (1) Data write operation Set the word line WLR to a low level and the word line WWL to a high level; then, write the data to be stored into the storage nodes Q and QB through the bit lines BL and BLB; (2) Data hold operation Set word lines WLR and WLL to low level, and bit lines BL, BLB, IL, and OL to high level; at this time, N2 and N3 are turned off, and storage nodes Q and QB are connected to the gates of N4 and P2 respectively; (3) Data read operation The data read operations supported by the 9T1C memory-calculation circuit are divided into the following column read mode and row read mode: a. In column read mode, word line WWL is set to low level, word line WLR is set to high level, bit lines BL, BLB and OL are set to high level, bit line IL is set to low level, and the read operation result of QB node is reflected on bit line BLB; b. In row read mode, word line WWL is set to low level, word line WLR is set to high level, bit lines BL, BLB and OL are set to high level, bit line IL is set to low level, and the read operation result of Q node is reflected on bit line IL.

4. The 9T1C storage-calculation circuit according to claim 2, wherein: The multiplication operation supported by the 9T1C storage circuit includes two modes: single multiplication single mode and single multiplication multiple mode. In the multiplication operation step (3), in the single multiplication single mode, the second operand input is a high or low level representing a binary number 1 or 0; in the single multiplication multiple mode, the second operand is a corresponding voltage value V obtained by performing digital-to-analog conversion on a multi-bit binary number according to a preset rule. DAC ; In step (4), in the single-multiplication-single mode, when the voltage of the bit line OL is VDD, it means the multiplication result is 0, and when the voltage of the bit line OL is 0, it means the multiplication result is 1; in the single-multiplication-multiple mode, when the first operand is 1, the voltage of the bit line OL is VDD, that is, the multiplication result is 0; when the first operand is 0, the voltage of the bit line OL is VDD-V DAC ;VDD-V DAC After the numbers are converted according to the preset rules, a multi-digit binary number is obtained, which is the product.

5. The 9T1C storage-calculation circuit according to claim 2, wherein: The 9T1C storage circuit should be reset to zero during the non-operation phase to reduce power consumption. The logic of the reset to zero operation is as follows: Set the word line WWL to a low level, the word line WLR to a high level, the bit lines BL, BLB, OL, and IL to a high level, and charge the left plate of capacitor C0 through BLB via N5, so that the voltage difference across capacitor C0 is cleared.

6. A multiplication-accumulation circuit, characterized in that: It includes: An operation array, which is composed of N 9T1C storage and operation circuits according to any one of claims 1 to 5 arranged in columns; A word line group including N word lines WLL and N word lines WLR; each 9T1C memory circuit in the operation array is connected to an independent set of word lines WLL and WLR; the word lines WLL and WLR are used to select the 9T1C memory circuits in each row before a multiplication-accumulation operation to write the first operand of the multiplication-accumulation operation; A bit line group includes one bit line BL and one bit line BLB; all 9T1C memory circuits in the same column are connected to the same bit lines BL and BLB, and the bit lines BL and BLB are used to write the first operand of the multiplication and accumulation operation in each 9T1C memory circuit; Input signal lines IL, the number of which is N; each 9T1C storage and calculation circuit in the operation array is connected to an independent input signal line IL and serves as the input terminal of the second operand in the respective operation process; Output signal line OL: All 9T1C storage circuits in the same column are connected to the output signal line OL, which serves as the output terminal of the multiplication and accumulation operation result; a column switch S connected between the output signal line OL and the power supply VDD, for controlling the connection state between the output signal line OL and the power supply VDD; as well as The quantization circuit is connected to the output signal line OL and is used to convert the voltage value on the output signal line OL into a digital value representing the result of the multiplication and accumulation operation.

7. The multiplication-accumulation circuit according to claim 6, wherein: The operation logic for performing multiplication and accumulation operations is as follows: (1) Preparation stage: Performing a zeroing operation on all 9T1C storage circuits in the operation array to ensure that the initial states of all capacitors C0 in the operation array are the same, that is, the right plate voltage Vc of the capacitor C0 remains consistent; (2) Pre-storage stage: Sequentially set the word line WLR of each row to a low level and the word line WWL to a high level; then, write the first operand of each row into the storage node of the 9T1C storage circuit through the bit lines BL and BLB; (3) Pre-charge stage: Close the column switch S, connect the output signal line OL to VDD, and precharge the left plate of each capacitor C0 to VDD; set WLR to a high level, and precharge BLB to a low level, so that the right plate of each capacitor C0 is precharged to "0"; and precharge the bit line IL to a low level; (4) Product operation stage The input voltage V after digital-to-analog conversion is input to each 9T1C storage circuit through the input signal line IL DAC At this time, WLR is set to a low level, the column switch S is still closed, and the voltage difference across the capacitor C0 in each 9T1C storage circuit changes as follows according to the Q value of the storage cell: a. When Q = "1", the transmission gate is open, and the input value is input to the right plate of capacitor C0 through the transmission gate. The voltage of the left plate of capacitor C0 remains at VDD, and the voltage of the right plate of capacitor C0 remains at V DAC ; At this time, the voltage difference between the two ends of capacitor C0 is VDD-V DAC ; b. When Q = "0", the transmission gate is closed; the left plate voltage of capacitor C0 remains at VDD, and the right plate voltage of capacitor C0 is 0; at this time, the voltage difference between the two ends of capacitor C0 remains at VDD; From this we can see that the multiplication results of each 9T1C storage circuit are accumulated on the right plate of their respective capacitors C0; (5) Accumulation operation stage: The column switch S is turned off, leaving the output signal line OL floating, that is, the left plate of the capacitor floating; WLR is set to a high level and the bit line IL is set to a low level, so that the voltage of the left plate of the capacitor C0 in each row changes as follows according to the Q value of the memory cell; a. When Q = "1", the transmission gate is open, and the voltage value of the right plate of capacitor C0 is pulled down to 0 by the bit line IL. At this time, the voltage difference between the two ends of capacitor C0 cannot change suddenly, and the voltage difference of capacitor C0 during the multiplication phase is VDD-V DAC , so the voltage value of the left plate of capacitor C0 becomes VDD-V DAC ; b. When Q = "0", the transmission gate is closed and the voltage difference across capacitor C0 remains at VDD, so the voltage on the left plate of capacitor C0 remains at VDD; At this point, the multiplication result of each 9T1C memory circuit is represented by the power supply voltage VDD minus the voltage on the left plate of capacitor C0. Since the bit line OL of a column is shared, the charge on the left plate of capacitor C0 in each 9T1C memory circuit is shared, and the analog value corresponding to the final multiplication and accumulation result is obtained on the bit line OL. (6) Quantized output The voltage value of OL is converted into the corresponding digital value according to the preset analog-to-digital conversion rules, which is the final multiplication and accumulation operation result.

8. An in-memory operation circuit based on 9T1C-SRAM, characterized in that: It has data read and write hold functions, multiplication functions, and multiplication-accumulation functions, and supports single-ended bidirectional access during the data read phase; the multiplication and multiplication-accumulation functions include single-bit multiplication and multi-bit multiplication; the in-memory operation circuit based on 9T1C-SRAM includes: A storage and computation array, comprising N×M 9T1C storage and computation circuits as described in any one of claims 1 to 5 arranged in an array of N rows and M columns; A word line group, comprising N word lines WLL and N word lines WLR; each 9T1C memory circuit in a row of the memory array is connected to the same group of word lines WLL and WLR; A bit line group includes M bit lines BL and M bit lines BLB; all 9T1C memory circuits in the same column of the memory array are connected to the same bit lines BL and BLB; An input signal line group, comprising N input signal lines IL; all 9T1C memory-calculation circuits in a row of the memory-calculation array are connected to one input signal line IL; An output signal line group, comprising M output signal lines OL; all 9T1C memory-calculation circuits in the same column of the memory-calculation array are connected to one output signal line OL; A word line driver, which is used to control the opening of each word line WLR and WWL; A decoder connected to the word line driver, the decoder is used to decode the address signal and transmit it to the word line driver; A precharge circuit, which is used to precharge the bit lines BL, BLB and the output signal line OL; A timing control module, which is used to generate various clock signals required in executing data storage tasks or performing multiplication and multiplication-accumulation operations; a mode switching circuit, configured to switch an operating mode of the in-memory operation circuit, wherein the operating modes of the in-memory operation circuit include a data storage mode and a logic operation mode; A read / write control circuit is used to control the process of performing data read / write operations on the in-memory operation circuit; a switch control circuit comprising M column switches S, each column switch S being connected between one of the output signal lines OL and the power supply VDD, for controlling a connection state between the output signal line OL and the power supply VDD; An input module, which performs digital-to-analog conversion on the second operand during the multiplication operation or multiplication-accumulation operation phase, and then inputs the second operand into the corresponding 9T1C storage circuit via the input signal line IL; and A quantization output circuit is connected to the output signal line OL, the bit line BLB and / or the input signal line IL; the quantization output circuit includes a data read part and an operation output part, the data read part is used to output the storage data of each storage node, and the operation output part is used to perform analog-to-digital conversion on the voltage of OL and output the corresponding multiplication result or multiplication-accumulation result.

9. The in-memory operation circuit based on 9T1C-SRAM according to claim 8, characterized in that: In the storage and computing array, each 9T1C storage and computing circuit serves as a basic unit for realizing data storage function and multiplication operation function; all 9T1C storage and computing circuits in the same column and the column switch S together constitute a basic unit for performing multiplication and accumulation operations; the 9T1C storage and computing circuits in each column of the 9T1C-SRAM-based in-memory computing circuit support parallel execution of multiplication and accumulation operations.

10. A CIM chip based on 9T1C-SRAM, characterized by: It is encapsulated by the in-memory operation circuit based on 9T1C-SRAM as described in claim 8.

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