Shift register unit and driving method thereof, panel driving circuit, display device

Abstract

The present disclosure provides a shift register unit and a driving method thereof, a panel driving circuit and a display device, and belongs to the technical field of display. The shift register unit comprises an input circuit, an output circuit and a compensation circuit. The input circuit can charge a pull-up node based on an input signal provided by an input signal terminal. The output circuit can transmit a clock signal provided by a clock signal terminal to an output signal terminal based on the potential of the pull-up node. The compensation circuit can control the conduction between the output signal terminal and the input signal terminal based on the potential of the pull-up node and the clock signal, so as to compensate the input signal provided by the input signal terminal based on the clock signal transmitted to the output signal terminal. In this way, the voltage difference between the input signal terminal and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the self-boosting capacitor in the output circuit, that is, the source-drain voltage difference of the transistor in the input circuit is reduced. Further, the characteristic negative drift of the transistor in the input circuit can be avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register unit and a driving method thereof, a panel driving circuit and a display device. BACKGROUND

[0002] With the progress of display technology, the gate driver on array (GOA) technology is often used to integrate the gate driving circuit on the array substrate in the display device, so as to facilitate the narrow frame design of the display device. The gate driving circuit is also called GOA circuit.

[0003] In the related art, the GOA circuit generally includes a plurality of cascaded shift register units (also referred to as GOA units). The GOA unit includes an input circuit and an output circuit. The input circuit is coupled with an input signal end and a pull-up node respectively; the output circuit is coupled with the pull-up node, a clock signal end and an output signal end respectively. The input circuit is used to charge the pull-up node under the control of the input signal end. The output circuit is used to control the clock signal end to output the clock signal to the output signal end under the control of the potential of the pull-up node. Moreover, the output circuit can lift the potential of the pull-up node by the capacitor included therein, so as to facilitate the transmission of the clock signal to the output signal end.

[0004] However, on the basis of lifting the potential of the pull-up node, the source-drain voltage difference of the transistor in the input circuit is increased, and inevitable negative drift occurs. SUMMARY

[0005] A shift register unit and a driving method thereof, a panel driving circuit and a display device are provided, which can solve the problem that in the related art, on the basis of lifting the potential of the pull-up node, the source-drain voltage difference of the transistor in the input circuit is increased, and inevitable negative drift occurs. The technical solution is as follows:

[0006] In one aspect, a shift register unit is provided, which includes:

[0007] an input circuit coupled with an input signal end and a pull-up node respectively, and configured to control the on-off of the input signal end and the pull-up node based on an input signal provided by the input signal end;

[0008] an output circuit coupled with the pull-up node, a clock signal end and an output signal end respectively, and configured to control the on-off of the clock signal end and the output signal end based on the potential of the pull-up node;

[0009] A compensation circuit is coupled to the pull-up node, the clock signal terminal, the output signal terminal and the input signal terminal respectively, and is configured to control the on-off of the output signal terminal and the input signal terminal based on the potential of the pull-up node and a clock signal provided by the clock signal terminal.

[0010] Optionally, the compensation circuit comprises:

[0011] A first compensation sub-circuit is coupled to the pull-up node, the clock signal terminal and a control node respectively, and is configured to control the on-off of the clock signal terminal and the control node based on the potential of the pull-up node;

[0012] A second compensation sub-circuit is coupled to the control node, the output signal terminal and the input signal terminal respectively, and is configured to control the on-off of the output signal terminal and the input signal terminal based on the potential of the control node.

[0013] Optionally, the first compensation sub-circuit comprises a first transistor.

[0014] The gate of the first transistor is coupled to the pull-up node, the first pole of the first transistor is coupled to the clock signal terminal, and the second pole of the first transistor is coupled to the control node.

[0015] Optionally, the second compensation sub-circuit comprises a second transistor.

[0016] The gate of the second transistor is coupled to the control node, the first pole of the second transistor is coupled to the output signal terminal, and the second pole of the second transistor is coupled to the input signal terminal.

[0017] Optionally, the output signal terminal comprises a cascade output terminal and a driving output terminal, the cascade output terminal is configured to be coupled to a next stage of the shift register unit, and the driving output terminal is configured to be coupled to a pixel; the output circuit comprises:

[0018] A first output sub-circuit is coupled to the pull-up node, the clock signal terminal and the cascade output terminal respectively, and is configured to control the on-off of the clock signal terminal and the cascade output terminal based on the potential of the pull-up node;

[0019] A second output sub-circuit is coupled to the pull-up node, the clock signal terminal and the driving output terminal respectively, and is configured to control the on-off of the clock signal terminal and the driving output terminal based on the potential of the pull-up node;

[0020] Optionally, the compensation circuit is coupled to the cascade output terminal comprised in the output signal terminal, and is configured to control the on-off of the cascade output terminal and the input signal terminal based on the potential of the pull-up node and the clock signal.

[0021] Optionally, the first output sub-circuit comprises a third transistor, and the second output sub-circuit comprises a fourth transistor and a storage capacitor;

[0022] The gate of the third transistor is coupled with the pull-up node, the first pole of the third transistor is coupled with the clock signal end, and the second pole of the third transistor is coupled with the cascade output end.

[0023] The gate of the fourth transistor is coupled with the pull-up node, the first pole of the fourth transistor is coupled with the clock signal end, and the second pole of the fourth transistor is coupled with the driving output end.

[0024] One end of the storage capacitor is coupled with the pull-up node, and the other end of the storage capacitor is coupled with the driving output end.

[0025] Optionally, the shift register unit further comprises:

[0026] a reset circuit, which is coupled with a total reset signal end, a first reset signal end, a second reset signal end, a first pull-down power supply end, a second pull-down power supply end, the pull-up node and the driving output end, and is configured to control the on-off of the first pull-down power supply end and the pull-up node based on a total reset signal provided by the total reset signal end, control the on-off of the first pull-down power supply end and the pull-up node based on a first reset signal provided by the first reset signal end, and control the on-off of the second pull-down power supply end and the driving output end based on a second reset signal provided by the second reset signal end;

[0027] at least one pull-down control circuit, each of which is coupled with a pull-up power supply end, the input signal end, the pull-up node, the first pull-down power supply end and a pull-down node, and is configured to control the on-off of the pull-up power supply end and the pull-down node based on a pull-up power supply signal provided by the pull-up power supply end, control the on-off of the first pull-down power supply end and the pull-down node based on the input signal and the potential of the pull-up node;

[0028] at least one pull-down circuit corresponding to the at least one pull-down control circuit, each of which is coupled with the pull-down node, the first pull-down power supply end, the second pull-down power supply end, the pull-up node, the cascade output end and the driving output end, and is configured to control the on-off of the first pull-down power supply end and the pull-up node based on the potential of the pull-down node, control the on-off of the first pull-down power supply end and the cascade output end, and control the on-off of the second pull-down power supply end and the driving output end.

[0029] Optionally, the reset circuit comprises a fifth transistor, a sixth transistor and a seventh transistor; the pull-down control circuit comprises an eighth transistor, a ninth transistor and a tenth transistor; the pull-down circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor; the input circuit comprises a fourteenth transistor;

[0030] The gate of the fifth transistor is coupled with the total reset signal end, the first pole of the fifth transistor is coupled with the first pull-down power supply end, and the second pole of the fifth transistor is coupled with the pull-up node;

[0031] The gate of the sixth transistor is coupled with the first reset signal end, the first pole of the sixth transistor is coupled with the first pull-down power supply end, and the second pole of the sixth transistor is coupled with the pull-up node;

[0032] The gate of the seventh transistor is coupled with the second reset signal end, the first pole of the seventh transistor is coupled with the second pull-down power supply end, and the second pole of the seventh transistor is coupled with the driving output end;

[0033] The gate and the first pole of the eighth transistor are both coupled with the pull-up power supply end, and the second pole of the eighth transistor is coupled with the pull-down node;

[0034] The gate of the ninth transistor is coupled with the input signal end, the first pole of the ninth transistor is coupled with the first pull-down power supply end, and the second pole of the ninth transistor is coupled with the pull-down node;

[0035] The gate of the tenth transistor is coupled with the pull-up node, the first pole of the tenth transistor is coupled with the first pull-down power supply end, and the second pole of the tenth transistor is coupled with the pull-down node;

[0036] The gate of the eleventh transistor is coupled with the pull-down node, the first pole of the eleventh transistor is coupled with the first pull-down power supply end, and the second pole of the eleventh transistor is coupled with the pull-up node;

[0037] The gate of the twelfth transistor is coupled with the pull-down node, the first pole of the twelfth transistor is coupled with the first pull-down power supply end or the second pull-down power supply end, and the second pole of the twelfth transistor is coupled with the cascade output end;

[0038] The gate of the thirteenth transistor is coupled with the pull-down node, the first pole of the thirteenth transistor is coupled with the second pull-down power supply end, and the second pole of the thirteenth transistor is coupled with the driving output end;

[0039] The gate and the first electrode of the fourteenth transistor are coupled with the input signal terminal, and the second electrode of the fourteenth transistor is coupled with the pull-up node.

[0040] In another aspect, a driving method of a shift register unit is provided for driving the shift register unit according to any one of the preceding aspects, and the method comprises:

[0041] In the input stage, the input signal provided by the input signal terminal has a first potential, the clock signal provided by the clock signal terminal has a second potential, the input circuit controls the input signal terminal and the pull-up node to be conductive based on the input signal, the output circuit controls the clock signal terminal and the output signal terminal to be conductive based on the potential of the pull-up node, and the compensation circuit controls the output signal terminal and the input signal terminal to be decoupled based on the potential of the pull-up node and the clock signal.

[0042] In the output stage, the potential of the clock signal jumps from the second potential to the first potential, the potential of the pull-up node remains the first potential, the output circuit controls the clock signal terminal and the output signal terminal to be conductive based on the potential of the pull-up node, and the compensation circuit controls the output signal terminal and the input signal terminal to be conductive based on the potential of the pull-up node and the clock signal.

[0043] In yet another aspect, a panel driving circuit is provided, comprising at least two cascaded shift register units according to any one of the preceding aspects.

[0044] In still another aspect, a display device is provided, comprising a display panel and a panel driving circuit according to the yet another aspect.

[0045] The display panel comprises a plurality of pixels, and the panel driving circuit is coupled with the plurality of pixels and is configured to transmit light-emitting driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0046] In summary, the technical solutions provided by the embodiments of the present disclosure can bring at least the following beneficial effects:

[0047] Provided are a shift register unit and a driving method thereof, a panel driving circuit, and a display device. The shift register unit includes an input circuit, an output circuit, and a compensation circuit. The input circuit is configured to charge a pull-up node based on an input signal provided by an input signal terminal. The output circuit is configured to transmit a clock signal provided by a clock signal terminal to an output signal terminal based on a potential of the pull-up node. The compensation circuit is configured to control the output signal terminal and the input signal terminal to be conductive based on the potential of the pull-up node and the clock signal, so as to compensate the input signal provided by the input signal terminal based on the clock signal transmitted to the output signal terminal. In this way, the voltage difference between the input signal terminal and the pull-up node can be reduced in the stage in which the pull-up node is pulled up by the self bootstrap of the capacitor in the output circuit, that is, the source-drain voltage difference of the transistor in the input circuit is reduced. Thus, the characteristic negative shift of the transistor in the input circuit can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0049] Figure 1 is a structural schematic diagram of a shift register unit in the related art;

[0050] Figure 2 is a signal timing diagram of a shift register unit coupled on the basis of Figure 1

[0051] Figure 3 is a characteristic curve diagram of a transistor on the basis of Figure 1

[0052] Figure 4 is a structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0053] Figure 5 is a structural schematic diagram of another shift register unit provided by an embodiment of the present disclosure;

[0054] Figure 6 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present disclosure;

[0055] Figure 7 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present disclosure;

[0056] Figure 8 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present disclosure; ​​

[0057] Figure 9 is a driving method flowchart of a shift register unit provided by an embodiment of the present disclosure;

[0058] Figure 10 is a signal timing diagram of a shift register unit provided by an embodiment of the present disclosure;

[0059] Figure 11 is a structural schematic diagram of a panel driving circuit provided by an embodiment of the present disclosure;

[0060] Figure 12 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0062] The transistors adopted in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors adopted in the embodiments of the present disclosure are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor adopted here are symmetrical, the source and drain can be interchangeable. In the embodiments of the present disclosure, the source is referred to as the first pole and the drain is referred to as the second pole. According to the mode in the drawings, the middle end of the transistor is defined as the control pole, which can also be referred to as the gate, the signal input signal end is defined as the source, and the signal output end is defined as the drain. In addition, the switching transistor adopted in the embodiments of the present disclosure can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, the plurality of signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent two states of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0063] At present, referring to Figure 1 , the input circuit in the GOA unit can include an input transistor T1 connected by the gate-source (i.e., the gate g and the source s), the output circuit can include an output transistor T2 and a storage capacitor Cst. The gate g and the source s of the input transistor T1 can be coupled with the input signal end INPUT, and the drain can be coupled with the pull-up node PU. The gate g of the output transistor T2 can be coupled with the pull-up node PU, the source s can be coupled with the clock signal end CLK, and the drain d can be coupled with the output signal end OUT. The storage capacitor Cst is connected in series between the gate g and the drain d of the output transistor T2. In addition, Figure 1It is also shown that the GOA unit comprises two reset transistors T3 and T4, wherein the gates g of the reset transistors T3 and T4 are coupled with the reset signal end RST, the sources s of the reset transistors T3 and T4 are coupled with the pull-down power supply end VSS, and the drains d of the reset transistors T3 and T4 are respectively coupled with the pull-up node PU and the output signal end OUT.

[0064] And, taking the transistors as N-type transistors as an example, combining Figure 2 : First, in the input stage t1, the input signal end INPUT can provide an input signal of high potential VGH, so that the input transistor T1 is turned on, and the input signal end INPUT transmits the input signal of high potential VGH to the pull-up node PU to pre-charge the pull-up node PU. At this time, the clock signal end CLK can provide a clock signal of low potential VGL. Then, in the output stage t2, after the pull-up node PU is pre-charged, the output transistor T2 can be turned on. At this time, the input signal end INPUT can provide an input signal of low potential VGL, so that the input transistor T1 is turned off. And, the clock signal end CLK can provide a clock signal of high potential VGH, which can be transmitted to the output signal end OUT through the output transistor T2. In addition, in the output stage t2, the storage capacitor Cst can also further raise the potential of the pull-up node PU through the bootstrap action, which can be raised to about 2VGH, so that the output transistor T2 is fully turned on. Assuming that VGH is 32 volts (V), the potential of the pull-up node PU will be raised to about 64V by bootstrap. If the low potential VGL of the input signal is -10V, it can be seen that the source-drain voltage difference Vds of the input transistor T1 is as high as 74V (64-(-10)=74) in the stage of raising the potential of the pull-up node PU by bootstrap. In addition, Figure 2 It is also shown that the reset stage t3 after the output stage t2, in the reset stage t3, the reset signal end RST can provide a reset signal of high potential VGH, so that the reset transistors T3 and T4 are turned on, and the pull-down power supply end VSS can transmit a pull-down power signal of low potential VGL to the pull-up node PU and the output signal end OUT respectively, so as to reset the pull-up node PU and the output signal end OUT.

[0065] It is found in the test that in the high temperature and high humidity operation experiment, the invasion of water vapor plus the higher Vds pressure difference will cause the input transistor T1 in the input circuit to have a negative characteristic drift. For example Figure 3As shown, when the gate-source voltage difference Vgs of the input transistor T1 is 0V, the drain current of the input transistor T1 will exponentially increase, so that the input transistor T1 is conductorized. In turn, it will cause the pull-up node PU to leak, and the potential of the pull-up node PU cannot be maintained, so that the output transistor T2 cannot normally output the clock signal, the GOA unit fails to work, and the display device has an abnormal display (AD) defect problem. Figure 3 The abscissa is the gate-source voltage difference Vgs, and the unit is V; the ordinate is the drain current Id, and the unit is ampere (A).

[0066] In the related art, attempts are also made to reduce the source-drain voltage difference Vds of the input transistor T1 by reducing VGH and VGL, so as to improve the characteristic negative drift phenomenon of the input transistor T1, solve the AD defect problem, and improve the product life. However, reducing VGH will undoubtedly affect the charging rate. On the one hand, under certain large load (i.e., heavy load) pictures, mura defects are prone to occur; on the other hand, the limit or margin of the working life is also reduced. The embodiments of the present disclosure consider the above problems and propose a method for reducing the voltage difference Vds of the transistor in the input circuit without changing the settings of VGH and VGL, thereby improving the characteristic negative drift phenomenon of the transistor and ensuring that the display device can normally display the picture.

[0067] Figure 4 is a structural schematic diagram of a shift register unit provided by the embodiments of the present disclosure. As shown in the figure, Figure 4 The shift register unit includes an input circuit 01, an output circuit 02, and a compensation circuit 03.

[0068] The input circuit 01 is coupled to the input signal end INPUT and the pull-up node PU, respectively, and is used to control the on-off of the input signal end INPUT and the pull-up node PU based on the input signal provided by the input signal end INPUT.

[0069] For example, the input circuit 01 can control the input signal end INPUT and the pull-up node PU to be conductive when the potential of the input signal provided by the input signal end INPUT is the first potential. At this time, the input signal provided by the input signal end INPUT can be transmitted to the pull-up node PU. In addition, the input circuit 01 can control the input signal end INPUT and the pull-up node PU to be disconnected when the potential of the input signal provided by the input signal end INPUT is the second potential.

[0070] Optionally, in the embodiments of the present disclosure, the first potential can be an effective potential, and the second potential can be an ineffective potential. Moreover, the first potential can be a high potential, and the second potential can be a low potential, that is, the first potential is larger than the second potential. On the basis of the potential, the transistor in the corresponding circuit can be an N-type transistor. If the transistor in the circuit is a P-type transistor, the first potential can be a low potential, and the second potential can be a high potential, that is, the first potential is smaller than the second potential. The following embodiments will not be described again.

[0071] The output circuit 02 is coupled with the pull-up node PU, the clock signal end CLK, and the output signal end OUT, respectively. The output circuit 02 is configured to control the clock signal end CLK and the output signal end OUT based on the potential of the pull-up node PU.

[0072] For example, the output circuit 02 can control the clock signal end CLK and the output signal end OUT to be conductive when the potential of the pull-up node PU is the first potential. At this time, the clock signal provided by the clock signal end CLK can be transmitted to the output signal end OUT. Moreover, the output circuit 02 can control the clock signal end CLK and the output signal end OUT to be decoupled when the potential of the pull-up node PU is the second potential.

[0073] The compensation circuit 03 is coupled with the pull-up node PU, the clock signal end CLK, the output signal end OUT, and the input signal end INPUT, respectively. The compensation circuit 03 is configured to control the output signal end OUT and the input signal end INPUT based on the potential of the pull-up node PU and the clock signal provided by the clock signal end CLK.

[0074] For example, the compensation circuit 03 can control the output signal end OUT and the input signal end INPUT to be conductive when the potential of the pull-up node PU and the potential of the clock signal provided by the clock signal end CLK are both the first potential. At this time, the clock signal transmitted to the output signal end OUT by the output circuit 02 can be further fed back to the input signal end INPUT. Moreover, the compensation circuit 03 can control the output signal end OUT and the input signal end INPUT to be decoupled when the potential of the pull-up node PU and / or the potential of the clock signal provided by the clock signal end CLK is the second potential.

[0075] When the potential of the clock signal is the first potential (that is, the high potential VGH), as described in the above embodiments, the potential of the pull-up node PU will be boosted to close to 2VGH. At this time, by setting the compensation circuit 03 to feed back the clock signal of the high potential VGH to the input signal end INPUT, the potential of the input signal provided by the input signal end INPUT can be compensated to VGH. In this way, the source-drain voltage difference Vds of the transistor in the input circuit 01 can be reduced. In Figure 1Based on the structure shown, Vds can be reduced from 2VGH-VGL in the related art to 2VGH-VGH=VGH, that is, to only one VGH. Further, the characteristic negative drift of the transistor in the input circuit 01 can be improved, the leakage of the pull-up node PU is avoided, the potential stability of the pull-up node PU is ensured, and further, the clock signal required by the output circuit 02 based on the potential of the pull-up node PU can be reliably output to the output signal end OUT, and the AD bad phenomenon of the display device is improved.

[0076] In summary, the embodiment of the present disclosure provides a shift register unit. The shift register unit includes an input circuit, an output circuit, and a compensation circuit. Wherein, the input circuit can charge the pull-up node based on the input signal provided by the input signal end. The output circuit can transmit the clock signal provided by the clock signal end to the output signal end based on the potential of the pull-up node. The compensation circuit can control the conduction between the output signal end and the input signal end based on the potential of the pull-up node and the clock signal, so as to compensate the input signal provided by the input signal end based on the clock signal transmitted to the output signal end. In this way, the voltage difference between the input signal end and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the capacitor in the output circuit, that is, the source-drain voltage difference of the transistor in the input circuit is reduced. Further, the negative drift of the transistor in the input circuit can be avoided.

[0077] Based on avoiding the negative drift of the transistor in the input circuit, the leakage of the pull-up node can be avoided, and the potential of the pull-up node can be ensured to remain stable. Accordingly, the output circuit can reliably transmit the clock signal to the output signal end based on the potential of the pull-up node, and the display device can reliably display the picture.

[0078] Figure 5 is another structure diagram of a shift register unit provided by the embodiment of the present disclosure. As shown in Figure 5 The output signal end OUT can include a cascaded output end OUT_C and a driving output end OUT1.

[0079] The cascaded output end OUT_C can be used to be coupled with the next stage shift register unit. For example, the cascaded output end OUT_C of the current stage shift register unit can be coupled with the input signal end INPUT of the next stage shift register unit in cascade. Accordingly, the clock signal transmitted to the cascaded output end OUT_C can be used as the input signal of the next stage shift register unit to drive the next stage shift register unit to work. The cascaded output end OUT_C can also be called a shift output end.

[0080] The driving output terminal OUT1 can be used to couple with the pixel. For example, the driving output terminal OUT1 can be coupled with the pixel through the gate line Gate. Correspondingly, the clock signal transmitted to the driving output terminal OUT1 can be transmitted to the pixel as a gate driving signal to drive the pixel to emit light. The driving circuit including the shift register unit can be referred to as a gate driving circuit. Of course, in some embodiments, the driving output terminal OUT1 can also be coupled with the pixel through the light emitting control line EM, and on this basis, the clock signal transmitted to the driving output terminal OUT1 can be transmitted to the pixel as a light emitting control signal. The embodiments of the present disclosure do not limit the signal line connected with the pixel of the driving output terminal OUT1.

[0081] By dividing the output signal terminal OUT into the cascaded output terminal OUT C and the driving output terminal OUT1, the cascaded shift register unit and the pixel light emission driving can be performed respectively, so that the cascading and driving do not interfere with each other, which ensures reliable operation of the shift register unit and reliable driving of the pixel light emission.

[0082] In addition, on the basis that the output signal terminal OUT can include the cascaded output terminal OUT C and the driving output terminal OUT1, it is continued to refer to Figure 5 It can be seen that the output circuit 02 can include a first output sub-circuit 021 and a second output sub-circuit 022.

[0083] The first output sub-circuit 021 can be coupled with the pull-up node PU, the clock signal terminal CLK and the cascaded output terminal OUT C respectively. The first output sub-circuit 021 can be used to control the on-off of the clock signal terminal CLK and the cascaded output terminal OUT C based on the potential of the pull-up node PU.

[0084] For example, the first output sub-circuit 021 can control the clock signal terminal CLK and the cascaded output terminal OUT C to be conductive when the potential of the pull-up node PU is the first potential. At this time, the clock signal provided by the clock signal terminal CLK can be transmitted to the cascaded output terminal OUT C and then transmitted to the next stage of the cascaded shift register unit through the cascaded output terminal OUT C, which is used to drive the next stage of the shift register unit to work reliably. In addition, the first output sub-circuit 021 can control the clock signal terminal CLK and the cascaded output terminal OUT C to be decoupled when the potential of the pull-up node PU is the second potential.

[0085] The second output sub-circuit 022 can be coupled with the pull-up node PU, the clock signal terminal CLK and the driving output terminal OUT1 respectively. The second output sub-circuit 022 can be used to control the on-off of the clock signal terminal CLK and the driving output terminal OUT1 based on the potential of the pull-up node PU.

[0086] For example, the second output sub-circuit 022 can control the clock signal end CLK and the driving output end OUT1 to be conductive when the potential of the pull-up node PU is the first potential. At this time, the clock signal provided by the clock signal end CLK can be transmitted to the driving output end OUT1, and then transmitted to the pixel through the driving output end OUT1, for driving the pixel to emit light. In addition, the second output sub-circuit 022 can control the clock signal end CLK and the driving output end OUT1 to be decoupled when the potential of the pull-up node PU is the second potential.

[0087] In the above embodiment, it is continued to refer to Figure 5 It can be seen that the compensation circuit 03 disclosed in the embodiment of the present disclosure can be coupled with the cascade output end OUT_C included in the output signal end OUT. Correspondingly, the compensation circuit 03 can be used to control the on-off of the cascade output end OUT_C and the input signal end INPUT based on the potential of the pull-up node PU and the clock signal, so as to compensate the input signal provided by the input signal end INPUT based on the clock signal transmitted to the cascade output end OUT_C by the first output sub-circuit 021. In this way, the output of the previous cascade row driving output end OUT1 will not be affected. Of course, in some embodiments, the compensation circuit 03 can be coupled with the driving output end OUT1 included in the output signal end OUT, and control the on-off of the driving output end OUT1 and the input signal end INPUT based on the potential of the pull-up node PU and the clock signal.

[0088] Optionally, Figure 6 is another structure diagram of a shift register unit provided by the embodiment of the present disclosure. As shown in Figure 6 The compensation circuit 03 can include a first compensation sub-circuit 031 and a second compensation sub-circuit 032.

[0089] The first compensation sub-circuit 031 can be coupled with the pull-up node PU, the clock signal end CLK and the control node V1 respectively. The first compensation sub-circuit 031 can be used to control the on-off of the clock signal end CLK and the control node V1 based on the potential of the pull-up node PU.

[0090] For example, the first compensation sub-circuit 031 can control the clock signal end CLK and the control node V1 to be conductive when the potential of the pull-up node PU is the first potential, at this time, the clock signal provided by the clock signal end CLK can be transmitted to the control node V1. In addition, the first compensation sub-circuit 031 can control the clock signal end CLK and the control node V1 to be decoupled when the potential of the pull-up node PU is the second potential.

[0091] The second compensation sub-circuit 032 can be coupled to the control node V1, the output signal terminal OUT, and the input signal terminal INPUT, respectively. The second compensation sub-circuit 032 can be used to control the on / off state of the output signal terminal OUT and the input signal terminal INPUT based on the potential of the control node V1.

[0092] For example, the second control sub-circuit 032 can control the output signal terminal OUT to conduct with the input signal terminal INPUT when the potential of control node V1 is at the first potential. At this time, the signal transmitted from output circuit 02 to output signal terminal OUT can be fed back to input signal terminal INPUT. Since the first compensation sub-circuit 031 transmits the clock signal to control node V1, and the output circuit 02 also transmits the clock signal to output signal terminal OUT when the potential of pull-up node PU is at the first potential, the second control sub-circuit 032 actually transmits the clock signal at the first potential to input signal terminal INPUT when both the potential of pull-up node PU and the potential of the clock signal are at the first potential, thereby compensating for the potential of the input signal provided by input signal terminal INPUT. Furthermore, the second control sub-circuit 032 can control the output signal terminal OUT to disconnect from input signal terminal INPUT when the potential of control node V1 is at the second potential.

[0093] It should be noted that, in Figure 5 Based on the structure shown, combined with Figure 6 It can be seen that the second compensation sub-circuit 032 can be coupled to the cascaded output terminal OUT_C ​​of the output signal terminal OUT and the drive output terminal OUT1. Accordingly, the second compensation sub-circuit 032 can be used to control the on / off state of the cascaded output terminal OUT_C ​​and the input signal terminal INPUT based on the potential of the control node V1.

[0094] Optional, Figure 7 This is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. For example... Figure 7 As shown, the shift register unit may further include: a reset circuit 04, at least one pull-down control circuit 05, and at least one pull-down circuit 06 corresponding to the at least one pull-down control circuit 05.

[0095] The reset circuit 04 can be coupled with the total reset signal terminal TGOA_RST, the first reset signal terminal RST_1, the second reset signal terminal RST_2, the first pull-down power terminal LVGL, the second pull-down power terminal VGL, the pull-up node PU and the driving output terminal OUT1 respectively. The reset circuit 04 can be used to control the on-off of the first pull-down power terminal LVGL and the pull-up node PU based on the total reset signal provided by the total reset signal terminal TGOA_RST, control the on-off of the first pull-down power terminal LVGL and the pull-up node PU based on the first reset signal provided by the first reset signal terminal RST_1, and control the on-off of the second pull-down power terminal VGL and the driving output terminal OUT1 based on the second reset signal provided by the second reset signal terminal RST_2.

[0096] For example, the reset circuit 04 can control the first pull-down power terminal LVGL and the pull-up node PU to be conductive when the potential of the total reset signal provided by the total reset signal terminal TGOA_RST is the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL can be transmitted to the pull-up node PU to reset the pull-up node PU. In addition, the reset circuit 04 can control the first pull-down power terminal LVGL and the pull-up node PU to be decoupled when the potential of the total reset signal provided by the total reset signal terminal TGOA_RST is the second potential. Similarly, the reset circuit 04 can control the first pull-down power terminal LVGL and the pull-up node PU to be conductive when the potential of the first reset signal provided by the first reset signal terminal RST_1 is the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL can be transmitted to the pull-up node PU to reset the pull-up node PU. In addition, the reset circuit 04 can control the first pull-down power terminal LVGL and the pull-up node PU to be decoupled when the potential of the first reset signal provided by the first reset signal terminal RST_1 is the second potential. The reset circuit 04 can control the second pull-down power terminal VGL and the driving output terminal OUT1 to be conductive when the potential of the second reset signal provided by the second reset signal terminal RST_2 is the first potential. At this time, the second pull-down power signal provided by the second pull-down power terminal VGL can be transmitted to the driving output terminal OUT1 to reset the driving output terminal OUT1. In addition, the reset circuit 04 can control the second pull-down power terminal VGL and the driving output terminal OUT1 to be decoupled when the potential of the second reset signal provided by the second reset signal terminal RST_2 is the second potential.

[0097] Optionally, the potential of the first pull-down power signal and the potential of the second pull-down power signal can both be the second potential, and the potential of the first pull-down power signal can be less than the potential of the second pull-down power signal.

[0098] Each pull-down control circuit 05 can be coupled with the pull-up power supply end VDD, the input signal end INPUT, the pull-up node PU, the first pull-down power supply end LVGL and the pull-down node PD respectively. Each pull-down control circuit 05 can be configured to control the pull-up power supply end VDD and the pull-down node PD based on the pull-up power supply signal provided by the pull-up power supply end VDD, and control the first pull-down power supply end LVGL and the pull-down node PD based on the input signal and the potential of the pull-up node PU.

[0099] For example, each pull-down control circuit 05 can control the pull-up power supply end VDD and the pull-down node PD to be conductive when the potential of the pull-up power supply signal provided by the pull-up power supply end VDD is the first potential. At this time, the pull-up power supply signal provided by the pull-up power supply end VDD can be transmitted to the pull-down node PD. In addition, each pull-down control circuit 05 can control the pull-up power supply end VDD and the pull-down node PD to be decoupled when the potential of the pull-up power supply signal provided by the pull-up power supply end VDD is the second potential. Similarly, each pull-down control circuit 05 can control the first pull-down power supply end LVGL and the pull-down node PD to be conductive when the potential of the input signal is the first potential. At this time, the first pull-down power supply signal provided by the first pull-down power supply end LVGL can be transmitted to the pull-down node PD. In addition, each pull-down control circuit 05 can control the first pull-down power supply end LVGL and the pull-down node PD to be decoupled when the potential of the input signal is the second potential. Each pull-down control circuit 05 can control the first pull-down power supply end LVGL and the pull-down node PD to be conductive when the potential of the pull-up node PU is the first potential. At this time, the first pull-down power supply signal provided by the first pull-down power supply end LVGL can be transmitted to the pull-down node PD. In addition, each pull-down control circuit 05 can control the first pull-down power supply end LVGL and the pull-down node PD to be decoupled when the potential of the pull-up node PU is the second potential.

[0100] Each pull-down circuit 06 can be coupled with the pull-down node PD, the first pull-down power supply end LVGL, the second pull-down power supply end VGL, the pull-up node PU, the cascade output end OUT C and the driving output end OUT1 respectively. Each pull-down circuit 06 can be configured to control the first pull-down power supply end LVGL and the pull-up node PU, control the first pull-down power supply end LVGL and the cascade output end OUT C, and control the second pull-down power supply end VGL and the driving output end OUT1 based on the potential of the pull-down node PD.

[0101] For example, each pull-down circuit 06 can control the first pull-down power terminal LVGL to be conductive with the pull-up node PU, control the first pull-down power terminal LVGL to be conductive with the cascade output terminal OUT_C, and control the second pull-down power terminal VGL to be conductive with the driving output terminal OUT1 when the potential of the pull-down node PD is the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL can be transmitted to the pull-up node PU and the cascade output terminal OUT_C, and the second pull-down power signal provided by the second pull-down power terminal VGL can be transmitted to the driving output terminal OUT1. In addition, each pull-down circuit 06 can control the first pull-down power terminal LVGL to be decoupled from the pull-up node PU, control the first pull-down power terminal LVGL to be decoupled from the cascade output terminal OUT_C, and control the second pull-down power terminal VGL to be decoupled from the driving output terminal OUT1 when the potential of the pull-down node PD is the second potential.

[0102] Optionally, Figure 7 Two pull-down control circuits 05 and two pull-down circuits 06 are schematically shown in one-to-one correspondence. In addition, for distinction, the pull-up power terminals VDD coupled by the two pull-down control circuits 05 are respectively identified as VDD_A and VDD_B, and the pull-down nodes PD coupled by the two pull-down control circuits 05 are respectively identified as PD_A and PD_B. The pull-up power signal provided by the pull-up power terminal VDD_A and the pull-up power signal provided by the pull-up power terminal VDD_B can be exactly opposite, that is, the potentials are different at the same period. In this way, the respective pull-down control circuits 05 and the respective pull-down circuits 06 can be alternately operated in time periods, thereby ensuring a longer service life of the shift register unit.

[0103] Optionally, Figure 8 is another structural schematic diagram of a shift register unit provided by the embodiments of the present disclosure. As shown in Figure 8 The first compensation sub-circuit 031 can include a first transistor M1.

[0104] The gate of the first transistor M1 can be coupled with the pull-up node PU, the first pole of the first transistor M1 can be coupled with the clock signal terminal CLK, and the second pole of the first transistor M1 can be coupled with the control node V1.

[0105] Optionally, continuing to refer to Figure 8 It can be seen that the second compensation sub-circuit 032 can include a second transistor M2.

[0106] The gate of the second transistor M2 can be coupled with the control node V1, the first pole of the second transistor M2 can be coupled with the output signal terminal OUT, and the second pole of the second transistor M2 can be coupled with the input signal terminal INPUT. In combination with Figure 7 Here, the first pole of the second transistor M2 can be coupled with the cascade output terminal OUT_C included in the output signal terminal OUT.

[0107] Optionally, with reference to the foregoing Figure 8 It can be seen that the first output sub-circuit 021 can include a third transistor M3. The second output sub-circuit 022 can include a fourth transistor M4 and a storage capacitor C1.

[0108] The gate of the third transistor M3 can be coupled with the pull-up node PU, the first pole of the third transistor M3 can be coupled with the clock signal end CLK, and the second pole of the third transistor M3 can be coupled with the cascade output end OUT_C.

[0109] The gate of the fourth transistor M4 can be coupled with the pull-up node PU, the first pole of the fourth transistor M4 can be coupled with the clock signal end CLK, and the second pole of the fourth transistor M4 can be coupled with the driving output end OUT1.

[0110] One end of the storage capacitor C1 can be coupled with the pull-up node PU, and the other end of the storage capacitor C1 can be coupled with the driving output end OUT1.

[0111] Optionally, with reference to the foregoing Figure 8 It can be seen that the reset circuit 04 can include a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The pull-down control circuit 05 can include an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10. The pull-down circuit 06 can include an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13.

[0112] The gate of the fifth transistor M5 can be coupled with the total reset signal end TGOA_RST, the first pole of the fifth transistor M5 can be coupled with the first pull-down power supply end LVGL, and the second pole of the fifth transistor M5 can be coupled with the pull-up node PU.

[0113] The gate of the sixth transistor M6 can be coupled with the first reset signal end RST_1, the first pole of the sixth transistor M6 can be coupled with the first pull-down power supply end LVGL, and the second pole of the sixth transistor M6 can be coupled with the pull-up node PU.

[0114] The gate of the seventh transistor M7 can be coupled with the second reset signal end RST_2, the first pole of the seventh transistor M7 can be coupled with the second pull-down power supply end VGL, and the second pole of the seventh transistor M7 can be coupled with the driving output end OUT1.

[0115] The gate and the first pole of the eighth transistor M8 can be coupled with the pull-up power supply end VDD, and the second pole of the eighth transistor M8 can be coupled with the pull-down node PD.

[0116] The gate of the ninth transistor M9 can be coupled to the input signal terminal INPUT, the first terminal of the ninth transistor M9 can be coupled to the first pull-down power supply terminal LVGL, and the second terminal of the ninth transistor M9 can be coupled to the pull-down node PD.

[0117] The gate of the tenth transistor M10 can be coupled to the pull-up node PU, the first terminal of the tenth transistor M10 can be coupled to the first pull-down power supply terminal LVGL, and the second terminal of the tenth transistor M10 can be coupled to the pull-down node PD.

[0118] The gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first terminal of the eleventh transistor M11 is coupled to the first pull-down power supply terminal LVGL, and the second terminal of the eleventh transistor M11 is coupled to the pull-up node PU.

[0119] The gate of the twelfth transistor M12 can be coupled to the pull-down node PD. The first terminal of the twelfth transistor M12 can be coupled to the first pull-down power supply terminal LVGL or the second pull-down power supply terminal VGL. The second terminal of the twelfth transistor M12 can be coupled to the cascaded output terminal OUT_C.

[0120] For example, such as Figure 8 As shown, in one pull-down circuit 06, the first terminal of the twelfth transistor M12_A is coupled to the first pull-down power supply terminal LVGL; in another pull-down circuit 06, the first terminal of the twelfth transistor M12_B is coupled to the second pull-down power supply terminal VGL.

[0121] The gate of the thirteenth transistor M13 can be coupled to the pull-down node PD, the first terminal of the thirteenth transistor M13 can be coupled to the second pull-down power supply terminal VGL, and the second terminal of the thirteenth transistor M13 can be coupled to the drive output terminal OUT1.

[0122] Optional, continue to refer to Figure 8 It can be seen that the input circuit 01 may include: the fourteenth transistor M14.

[0123] The gate and first terminal of the fourteenth transistor M14 can both be coupled to the input signal terminal INPUT, and the second terminal of the fourteenth transistor M14 can be coupled to the pull-up node PU. Therefore, it can be seen that the transistors included in the input circuit 01 described in this embodiment are the gate-source connected transistors described in the above embodiments.

[0124] Figure 8To distinguish, in the two pull-down control circuits 05, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 included in one pull-down control circuit 05 are respectively identified as M8_A, M9_A and M10_A; the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 included in the other pull-down control circuit 05 are respectively identified as M8_B, M9_B and M10_B. In addition, in the two pull-down circuits 06, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 included in one pull-down circuit 06 are respectively identified as M11_A, M12_A and M13_A; the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 included in the other pull-down circuit 06 are respectively identified as M11_B, M12_B and M13_B.

[0125] Optionally, the shift register unit protected by the embodiment of the present disclosure can include transistors that are all N-type transistors. On this basis, as described in the above embodiment, the first potential (i.e., the effective potential) can be a high potential, and the second potential (i.e., the ineffective potential) can be a low potential. The embodiment of the present disclosure mainly lies in the setting of the first transistor M1 and the second transistor M2. In addition, it should be noted that, in addition to the 20T1C (i.e., 20 transistors and 1 capacitor) structure shown in the figure, the shift register unit described in the embodiment of the present disclosure can also be other structures, such as 14T1C, but on the premise that the fourteenth transistor M14, the first transistor M1 and the second transistor M2 are included. Figure 8

[0126] In summary, the embodiment of the present disclosure provides a shift register unit. The shift register unit includes an input circuit, an output circuit and a compensation circuit. The input circuit can charge the pull-up node based on the input signal provided by the input signal terminal. The output circuit can transmit the clock signal provided by the clock signal terminal to the output signal terminal based on the potential of the pull-up node. The compensation circuit can control the output signal terminal and the input signal terminal to be conductive based on the potential of the pull-up node and the clock signal, so as to compensate the input signal provided by the input signal terminal based on the clock signal transmitted to the output signal terminal. In this way, the voltage difference between the input signal terminal and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the self bootstrap of the capacitor in the output circuit, that is, the source-drain voltage difference of the transistor in the input circuit is reduced. Further, the negative drift of the transistor in the input circuit can be avoided.

[0127] On the basis of avoiding the negative drift of the transistor in the input circuit, the leakage of the pull-up node can be avoided, and the potential of the pull-up node can be kept stable. Correspondingly, the output circuit can reliably transmit the clock signal to the output signal terminal based on the potential of the pull-up node, and the display device can reliably display the picture.

[0128] Figure 9 ​This is a flowchart of a driving method for a shift register unit provided in an embodiment of this disclosure, which can be used to drive such... Figures 4 to 8 Any of the shift register units shown. For example... Figure 9 As shown, the method includes:

[0129] Step 901, Input Phase: The potential of the input signal provided by the input signal terminal is the first potential, and the potential of the clock signal provided by the clock signal terminal is the second potential. The input circuit controls the input signal terminal to conduct with the pull-up node based on the input signal. The output circuit controls the clock signal terminal to conduct with the output signal terminal based on the potential of the pull-up node. The compensation circuit controls the output signal terminal to disconnect from the input signal terminal based on the potential of the pull-up node and the clock signal.

[0130] Step 902, Output Stage: The clock signal potential jumps from the second potential to the first potential, the pull-up node potential remains at the first potential, the output circuit controls the clock signal terminal to conduct with the output signal terminal based on the pull-up node potential, and the compensation circuit controls the output signal terminal to conduct with the input signal terminal based on the pull-up node potential and the clock signal.

[0131] Optional, with Figure 8 Taking the structure shown, in which the transistors included are N-type transistors, with a first potential of high potential VGH and a second potential of low potential VGL as an example, the working principle of the shift register unit provided in this embodiment is explained as follows:

[0132] Figure 10 A timing diagram for a shift register unit is provided. For example... Figure 10 As shown, firstly, in the input phase t1, the input signal provided by the input signal terminal INPUT is at a high potential, while the clock signal provided by the clock signal terminal CLK is at a low potential. Accordingly, the fourteenth transistor M14 can be turned on. Then, the high-potential input signal can be transmitted to the pull-up node PU via the fourteenth transistor M14, pre-charging the pull-up node PU and also charging the storage capacitor C1. Accordingly, the third transistor M3, the fourth transistor M4, and the first transistor M1 are all turned on. The low-potential clock signal can be transmitted to the cascaded output terminal OUT_C ​​via the third transistor M3, to the drive output terminal OUT1 via the fourth transistor M4, and to the control node V1 via the first transistor M1. Accordingly, the second transistor M2 can be turned off.

[0133] Secondly, in the output stage t2 after the input stage t1, the potential of the clock signal provided by the clock signal terminal CLK can jump to a high potential. And, due to the bootstrap effect of the storage capacitor C1, the potential of the pull-up node PU can be further pulled up. As described in the above embodiment, the potential of the pull-up node PU can be pulled up to 2VGH. Correspondingly, the third transistor M3, the fourth transistor M4 and the first transistor M1 can all be further fully turned on. The clock signal of the high potential can be transmitted to the cascade output terminal OUT C through the third transistor M3, can be transmitted to the driving output terminal OUT1 through the fourth transistor M4, and can be transmitted to the control node V1 through the first transistor M1. Correspondingly, the second transistor M2 can be turned on. The clock signal of the high potential transmitted to the cascade output terminal OUT C can be transmitted to the input signal terminal INPUT through the second transistor M2, thereby realizing the compensation charging of the input signal terminal INPUT, so that the potentials of the gate and the source of the fourteenth transistor M14 are close to VGH. On this basis, even if the potential of the pull-up node PU is pulled up to 2VGH, that is, the potential of the drain of the fourteenth transistor M14 is 2VGH, the source-drain voltage difference Vds of the fourteenth transistor M14 can also be reduced to one VGH (that is, 2VGH-VGH=VGH). Compared with the related art, the source-drain voltage difference Vds of the transistor in the input circuit is 2VGH-VGL, which can greatly reduce the source-drain voltage difference Vds. Further, the characteristic negative drift phenomenon of the fourteenth transistor M14 can be improved, the potential leakage of the pull-up node PU is avoided, that is, the potential of the pull-up node PU is ensured to be stable.

[0134] In addition, in the input stage t1 and the output stage t2, the potential of the total reset signal provided by the total reset signal terminal TGOA_RST, the potential of the first reset signal provided by the first reset signal terminal RST_1 and the potential of the second reset signal provided by the second reset signal terminal RST_2 can all be low potentials, so that the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off, avoiding the transmission of the low potential first pull-down power signal from the first pull-down power supply terminal LVGL to the pull-up node PU, and avoiding the transmission of the low potential second pull-down power signal from the second pull-down power supply terminal VGL to the driving output terminal OUT1. And, because the potential of the pull-up node PU and the potential of the input signal are both high potentials, the ninth transistor M9 and the tenth transistor M10 can both be turned on, thereby making the first pull-down power supply terminal LVGL transmit the low potential first pull-down power signal to the pull-down node PD. Correspondingly, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 can all be turned off, avoiding the transmission of the low potential first pull-down power signal from the first pull-down power supply terminal LVGL to the pull-up node PU and the cascade output terminal OUT C, and avoiding the transmission of the low potential second pull-down power signal from the second pull-down power supply terminal VGL to the driving output terminal OUT1.

[0135] After the input stage t1 and the output stage t2, a reset stage can be further included. In the reset stage, first, the potential of the global reset signal provided by the global reset signal terminal TGOA_RST, the potential of the first reset signal provided by the first reset signal terminal RST_1 and the potential of the second reset signal provided by the second reset signal terminal RST_2 can all be high potentials, so that the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned on, so that the first pull-down power supply terminal LVGL transmits the low potential first pull-down power supply signal to the pull-up node PU, and the second pull-down power supply terminal VGL transmits the low potential second pull-down power supply signal to the driving output terminal OUT1. In addition, in the reset stage, the potential of the input signal provided by the input signal terminal INPUT can be a low potential, and in combination with the low potential of the pull-up node PU, the ninth transistor M9 and the tenth transistor M10 can be both turned off. Further, the high potential pull-down power supply signal provided by the pull-up power supply terminal VDD can be transmitted to the pull-down node PD through the turned-on eighth transistor M8. Correspondingly, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 can all be turned on, so that the first pull-down power supply terminal LVGL can transmit the low potential first pull-down power supply signal to the pull-up node PU and the cascade output terminal OUT_C, and the second pull-down power supply terminal VGL can transmit the low potential second pull-down power supply signal to the driving output terminal OUT1. Thus, the pull-up node PU, the cascade output terminal OUT_C and the driving output terminal OUT1 can be reliably reset.

[0136] In summary, the disclosed embodiment provides a driving method of a shift register unit. In the input stage, the input circuit can control the input signal terminal and the pull-up node to be conductive based on the input signal, the output circuit can control the clock signal terminal and the output signal terminal to be conductive based on the potential of the pull-up node, and the compensation circuit can control the output signal terminal and the input signal terminal to be decoupled based on the potential of the pull-up node and the clock signal. In the output stage, the output circuit can control the clock signal terminal and the output signal terminal to be conductive based on the potential of the pull-up node, and the compensation circuit can control the output signal terminal and the input signal terminal to be conductive based on the potential of the pull-up node and the clock signal. In this way, the voltage difference between the input signal terminal and the pull-up node can be reduced in the stage in which the pull-up node is pulled up by the capacitor in the output circuit, that is, the source-drain voltage difference of the transistor in the input circuit is reduced. Further, the negative drift of the transistor in the input circuit can be avoided.

[0137] On the basis of avoiding the negative drift of the transistor in the input circuit, the leakage of the pull-up node can be avoided, and the potential of the pull-up node can be kept stable. Correspondingly, the output circuit can reliably transmit the clock signal to the output signal terminal based on the potential of the pull-up node, and the display device can reliably display the picture.

[0138] Figure 11 is a structural schematic diagram of a panel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 11 , the panel driving circuit comprises at least two shift register units 00 as shown in any of Figures 4 to 8 .

[0139] Optionally, taking the structure as shown in Figure 8 , in the embodiment of the present disclosure, the cascade output end OUT C of the current stage shift register unit 00 can be cascaded with the input signal end INPUT of the next stage shift register unit 00; the driving output end OUT1 of the current stage shift register unit 00 can be coupled with the pixel. As for the first stage shift register unit 00, the input signal end INPUT thereof can be coupled with the start signal end STV to receive the start input signal provided by the start signal end STV, so as to realize the cascade output.

[0140] For example, as described in the above embodiment, the driving output end OUT1 of the current stage shift register unit 00 can be coupled with the gate line Gate to be indirectly coupled with the pixel through the gate line Gate. On this basis, the panel driving circuit can also be referred to as a gate driving circuit. Of course, in some other embodiments, the driving output end OUT1 of the current stage shift register unit 00 can also be coupled with the pixel through the light-emitting control line EM. On this basis, the panel driving circuit can also be referred to as a light-emitting driving circuit.

[0141] Figure 12 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in Figure 12 , the display device comprises a display panel 100 and a panel driving circuit 000 as shown in Figure 11 .

[0142] Among them, the display panel 100 comprises a plurality of pixels P1, and the panel driving circuit 000 can be coupled with the plurality of pixels P1 and used to transmit a light-emitting driving signal to the plurality of pixels P1 to drive the plurality of pixels P1 to emit light.

[0143] For example, assuming that the panel driving circuit 000 is a gate driving circuit as described in the above embodiment, the panel driving circuit 000 can be coupled with the plurality of pixels P1 through a plurality of gate lines Gate as shown in Figure 12 , and used to transmit a gate driving signal (which belongs to a light-emitting driving signal) to the plurality of pixels P1 to drive the plurality of pixels P1 to emit light.

[0144] Optionally, the display device can be any product or component with display function, such as an organic light-emitting diode (OLED) display device, electronic paper, mobile phone, tablet computer, television, display, notebook computer, or navigator.

[0145] It should be understood that the terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should be understood as having the common meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

[0146] As used in the specification and claims of the present patent application, the terms "first", "second", or "third" and similar terms, do not denote any order, quantity, or importance, but are used to distinguish one element from another.

[0147] Similarly, the terms "one" or "a" or similar terms do not denote a quantity restriction, but indicate the presence of at least one.

[0148] The terms "include" or "contain" or similar terms mean that the elements or objects appearing before the "include" or "contain" cover the elements or objects listed after the "include" or "contain" and their equivalents, and do not exclude other elements or objects.

[0149] "Up", "down", "left" or "right" and the like are used only to indicate relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0150] "Connection" or "coupling" means electrical connection. "And / or" means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally means that the associated objects before and after are in an "or" relationship.

[0151] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described gate drive circuit, shift register unit, each circuit and each sub-circuit can refer to the corresponding processes in the method embodiments, which will not be described here.

[0152] The above description is only optional embodiments of the present disclosure and does not limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A shift register unit characterized by comprising: The shift register unit comprises: an input circuit coupled to an input signal terminal and a pull-up node respectively, and configured to control the input signal terminal and the pull-up node based on an input signal provided by the input signal terminal; an output circuit coupled to the pull-up node, a clock signal terminal and an output signal terminal respectively, and configured to control the clock signal terminal and the output signal terminal based on a potential of the pull-up node; a compensation circuit coupled to the pull-up node, the clock signal terminal, the output signal terminal and the input signal terminal respectively, and configured to control the output signal terminal and the input signal terminal based on the potential of the pull-up node and a clock signal provided by the clock signal terminal; the compensation circuit comprises: a first compensation sub-circuit coupled to the pull-up node, the clock signal terminal and a control node respectively, and configured to control the clock signal terminal and the control node based on the potential of the pull-up node; a second compensation sub-circuit coupled to the control node, the output signal terminal and the input signal terminal respectively, and configured to control the output signal terminal and the input signal terminal based on the potential of the control node.

2. The shift register cell of claim 1, wherein, The first compensation sub-circuit comprises a first transistor; a gate of the first transistor is coupled to the pull-up node, a first pole of the first transistor is coupled to the clock signal terminal, and a second pole of the first transistor is coupled to the control node.

3. The shift register cell of claim 1, wherein, The second compensation sub-circuit comprises a second transistor; a gate of the second transistor is coupled to the control node, a first pole of the second transistor is coupled to the output signal terminal, and a second pole of the second transistor is coupled to the input signal terminal.

4. The shift register unit according to any one of claims 1 to 3, characterized in that, The output signal terminal comprises a cascade output terminal and a driving output terminal, the cascade output terminal is configured to be coupled to a next stage shift register unit, and the driving output terminal is configured to be coupled to a pixel; the output circuit comprises: a first output sub-circuit coupled to the pull-up node, the clock signal terminal and the cascade output terminal respectively, and configured to control the clock signal terminal and the cascade output terminal based on the potential of the pull-up node; a second output sub-circuit coupled to the pull-up node, the clock signal terminal and the driving output terminal respectively, and configured to control the clock signal terminal and the driving output terminal based on the potential of the pull-up node; the compensation circuit is coupled to the cascade output terminal comprised in the output signal terminal, and configured to control the cascade output terminal and the input signal terminal based on the potential of the pull-up node and the clock signal.

5. The shift register cell of claim 4, wherein, The first output sub-circuit comprises a third transistor, and the second output sub-circuit comprises a fourth transistor and a storage capacitor; a gate of the third transistor is coupled to the pull-up node, a first pole of the third transistor is coupled to the clock signal terminal, and a second pole of the third transistor is coupled to the cascade output terminal; a gate of the fourth transistor is coupled to the pull-up node, a first pole of the fourth transistor is coupled to the clock signal terminal, and a second pole of the fourth transistor is coupled to the driving output terminal; One end of the storage capacitor is coupled with the pull-up node, and the other end of the storage capacitor is coupled with the driving output end.

6. The shift register cell of claim 4, wherein, The shift register unit further comprises: a reset circuit coupled with a total reset signal end, a first reset signal end, a second reset signal end, a first pull-down power supply end, a second pull-down power supply end, the pull-up node and the driving output end, and configured to control the on-off of the first pull-down power supply end and the pull-up node based on a total reset signal provided by the total reset signal end, control the on-off of the first pull-down power supply end and the pull-up node based on a first reset signal provided by the first reset signal end, and control the on-off of the second pull-down power supply end and the driving output end based on a second reset signal provided by the second reset signal end; at least one pull-down control circuit, each coupled with a pull-up power supply end, the input signal end, the pull-up node, the first pull-down power supply end and a pull-down node, and configured to control the on-off of the pull-up power supply end and the pull-down node based on a pull-up power supply signal provided by the pull-up power supply end, control the on-off of the first pull-down power supply end and the pull-down node based on the input signal and the potential of the pull-up node; at least one pull-down circuit corresponding to the at least one pull-down control circuit, each coupled with the pull-down node, the first pull-down power supply end, the second pull-down power supply end, the pull-up node, the cascade output end and the driving output end, and configured to control the on-off of the first pull-down power supply end and the pull-up node based on the potential of the pull-down node, control the on-off of the first pull-down power supply end and the cascade output end, and control the on-off of the second pull-down power supply end and the driving output end.

7. The shift register cell of claim 6, wherein, The reset circuit comprises a fifth transistor, a sixth transistor and a seventh transistor; the pull-down control circuit comprises an eighth transistor, a ninth transistor and a tenth transistor; the pull-down circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor; and the input circuit comprises a fourteenth transistor. The gate of the fifth transistor is coupled with the total reset signal end, the first pole of the fifth transistor is coupled with the first pull-down power supply end, and the second pole of the fifth transistor is coupled with the pull-up node. The gate of the sixth transistor is coupled with the first reset signal end, the first pole of the sixth transistor is coupled with the first pull-down power supply end, and the second pole of the sixth transistor is coupled with the pull-up node. The gate of the seventh transistor is coupled with the second reset signal end, the first pole of the seventh transistor is coupled with the second pull-down power supply end, and the second pole of the seventh transistor is coupled with the driving output end. The gate and the first pole of the eighth transistor are both coupled with the pull-up power supply end, and the second pole of the eighth transistor is coupled with the pull-down node. The gate of the ninth transistor is coupled with the input signal end, the first pole of the ninth transistor is coupled with the first pull-down power supply end, and the second pole of the ninth transistor is coupled with the pull-down node. The gate of the tenth transistor is coupled with the pull-up node, the first pole of the tenth transistor is coupled with the first pull-down power supply end, and the second pole of the tenth transistor is coupled with the pull-down node. A gate of the tenth transistor is coupled with the pull-up node, a first pole of the tenth transistor is coupled with the first pull-down power terminal, and a second pole of the tenth transistor is coupled with the pull-down node; A gate of the eleventh transistor is coupled with the pull-down node, a first pole of the eleventh transistor is coupled with the first pull-down power terminal, and a second pole of the eleventh transistor is coupled with the pull-up node; A gate of the twelfth transistor is coupled with the pull-down node, a first pole of the twelfth transistor is coupled with the first pull-down power terminal or the second pull-down power terminal, and a second pole of the twelfth transistor is coupled with the cascade output terminal; A gate of the thirteenth transistor is coupled with the pull-down node, a first pole of the thirteenth transistor is coupled with the second pull-down power terminal, and a second pole of the thirteenth transistor is coupled with the driving output terminal; A gate and a first pole of the fourteenth transistor are coupled with the input signal terminal, and a second pole of the fourteenth transistor is coupled with the pull-up node.

8. A driving method of a shift register unit, characterized by, The method for driving the shift register unit as claimed in any one of claims 1 to 7 comprises: In an input stage, a potential of an input signal provided by the input signal terminal is a first potential, a potential of a clock signal provided by the clock signal terminal is a second potential, the input circuit controls the input signal terminal and the pull-up node to be conductive based on the input signal, the output circuit controls the clock signal terminal and the output signal terminal to be conductive based on a potential of the pull-up node, and the compensation circuit controls the output signal terminal and the input signal terminal to be decoupled based on the potential of the pull-up node and the clock signal; In an output stage, the potential of the clock signal jumps from the second potential to the first potential, the potential of the pull-up node remains the first potential, the output circuit controls the clock signal terminal and the output signal terminal to be conductive based on the potential of the pull-up node, and the compensation circuit controls the output signal terminal and the input signal terminal to be conductive based on the potential of the pull-up node and the clock signal.

9. A panel drive circuit, characterized by comprising: The panel driving circuit comprises at least two cascaded shift register units as claimed in any one of claims 1 to 7.

10. A display device, characterized by comprising: The display device comprises a display panel and a panel driving circuit as claimed in claim 9. The display panel comprises a plurality of pixels, the panel driving circuit is coupled with the plurality of pixels, and is used for transmitting light-emitting driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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