Shift register and driving method thereof, gate driving circuit and display panel

Abstract

Embodiments of the present application provide a shift register and a driving method thereof, a gate driving circuit and a display panel. The shift register comprises: a first output module, a control end of which is electrically connected with a first node, a first end of which is electrically connected with a first clock signal end, and a second end of which is electrically connected with an output end of the shift register; and a first node control module, which comprises a first switch unit and a second switch unit. The first switch unit is electrically connected with the first node, a first power voltage signal end and a second node. The second switch unit is electrically connected with the second node, the first power voltage signal end and the first node. In a low-level output stage, the first switch unit is turned on under the control of the first node, and a cutoff level of the first power voltage signal end is written into the second node. The second switch unit is turned off under the control of the second node. Embodiments of the present application can solve the problem of unstable output of the shift register.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a shift register and a driving method thereof, a gate drive circuit and a display panel. BACKGROUND

[0002] A display panel usually includes multiple rows of gate lines and multiple columns of data lines. For driving the gate lines, a gate drive circuit composed of multiple cascaded shift registers can be used to provide scanning driving signals for the multiple rows of gate lines, so as to control the multiple rows of gate lines to be opened in sequence.

[0003] However, the inventors of the present application have found that the shift register in the related art has the problem of unstable output when outputting a low-level voltage signal. SUMMARY

[0004] The embodiments of the present application provide a shift register and a driving method thereof, a gate drive circuit and a display panel, which can solve the problem of unstable output of the shift register when outputting a low-level voltage signal.

[0005] In a first aspect, the embodiments of the present application provide a shift register, which includes: a first output module, a control end of the first output module being electrically connected with a first node, a first end of the first output module being electrically connected with a first clock signal end, and a second end of the first output module being electrically connected with an output end of the shift register; a first node control module, the first node control module including a first switch unit and a second switch unit, a control end of the first switch unit being electrically connected with the first node, a first end of the first switch unit being electrically connected with a first power voltage signal end, and a second end of the first switch unit being electrically connected with a second node; a control end of the second switch unit being electrically connected with the second node, a first end of the second switch unit being electrically connected with the first power voltage signal end, and a second end of the second switch unit being electrically connected with the first node; in a low-level output phase, the first switch unit is turned on under the control of the first node to write the off level of the first power voltage signal end into the second node, and the second switch unit is turned off under the control of the second node.

[0006] In a second aspect, the embodiments of the present application provide a driving method of a shift register, the shift register including the shift register provided in the first aspect, and the driving method of the shift register includes: in a low-level output phase, providing a turn-on level to the first node to make the first switch unit turned on under the control of the first node to write the off level of the first power voltage signal end into the second node, and the second switch unit turned off under the control of the second node.

[0007] In a third aspect, the embodiments of the present application provide a gate drive circuit, which includes multiple cascaded shift registers provided in the first aspect.

[0008] In a fourth aspect, the embodiments of the present application provide a display panel, which comprises the gate drive circuit provided in the third aspect.

[0009] The shift register and the driving method thereof, the gate drive circuit and the display panel provided by the embodiments of the present application can avoid the influence of the off level of the first power voltage signal end on the potential of the first node through the second switch unit, and ensure the stable output of the low-level voltage signal; in addition, neither the first switch unit nor the second switch unit is connected with the clock signal end, so that the influence of the clock signal transmitted by the clock signal end on the first node can be avoided, and the stable output of the low-level voltage signal is further ensured. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced, and other drawings can be obtained by those of ordinary skill in the art without creative labor on the basis of these drawings.

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced, and other drawings can be obtained by those of ordinary skill in the art without creative labor on the basis of these drawings.

[0012] Figure 1 A partial circuit schematic diagram of the shift register;

[0013] Figure 2 A circuit schematic diagram of the shift register provided by the embodiments of the present application;

[0014] Figure 3 Another circuit schematic diagram of the shift register provided by the embodiments of the present application;

[0015] Figure 4 Another circuit schematic diagram of the shift register provided by the embodiments of the present application;

[0016] Figure 5 Another circuit schematic diagram of the shift register provided by the embodiments of the present application;

[0017] Figure 6 Another circuit schematic diagram of the shift register provided by the embodiments of the present application;

[0018] Figure 7 Another circuit schematic diagram of the shift register provided by the embodiments of the present application;

[0019] Figure 8Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6;

[0020] Figure 9 Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6;

[0021] Figure 10 Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6;

[0022] Figure 11 Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6;

[0023] Figure 12 Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6;

[0024] Figure 13 Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6; Figure 12 A driving timing schematic diagram corresponding to the shift register shown in FIG. 6 is shown in FIG. 7;

[0025] Figure 14 Another circuit schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6;

[0026] Figure 15 A flow schematic diagram of the driving method of the shift register provided by the embodiment of the present application is shown in FIG. 8;

[0027] Figure 16 Another flow schematic diagram of the driving method of the shift register provided by the embodiment of the present application is shown in FIG. 9;

[0028] Figure 17 A circuit schematic diagram of the gate driving circuit provided by the embodiment of the present application is shown in FIG. 10;

[0029] Figure 18 A structure schematic diagram of the display device provided by the embodiment of the present application is shown in FIG. 11. DETAILED DESCRIPTION

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0031] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0032] It should be understood that the term "and / or" used herein only describes an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases of A existing alone, A and B existing together, and B existing alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0033] It should be noted that the transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For the N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is high, the first pole and the second pole are turned on, and when the gate of the N-type transistor is low, the first pole and the second pole are turned off. For the P-type transistor, the on level is low and the off level is high. That is, when the control pole of the P-type transistor is low, the first pole and the second pole are turned on, and when the control end of the P-type transistor is high, the first pole and the second pole are turned off. In the specific implementation, the gate of each transistor is used as the control pole, and according to the signal of the gate of each transistor and the type of each transistor, the first pole can be used as the source pole and the second pole can be used as the drain pole, or the first pole can be used as the drain pole and the second pole can be used as the source pole, which is not distinguished here. In addition, the on level and the off level in the embodiment of the present application are generic, the on level refers to any level that can turn on the transistor, and the off level refers to any level that can turn off / turn off the transistor.

[0034] In the embodiment of the present application, the term "electrically connected" can refer to direct electrical connection between two components, or can refer to electrical connection between two components via one or more other components.

[0035] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not an actual circuit unit.

[0036] Various modifications and changes can be made to the application without departing from the spirit and scope thereof. Accordingly, it is intended that the application cover all such modifications and changes as fall within the scope of the corresponding claims (technical solutions claimed to be protected) and their equivalents. It should be noted that the implementation manners provided in the embodiments of the application can be combined with each other without contradiction, if necessary.

[0037] Before the technical solutions provided by the embodiments of the application are described, the problems in the related art are first described in detail to facilitate the understanding of the embodiments of the application.

[0038] Figure 1 A partial circuit schematic diagram of a shift register. As shown in Figure 1 , in the related art, the shift register can include a transistor M1, a transistor M2, and a transistor M3. The gate of the transistor M1 is electrically connected to a first node N1', the first electrode of the transistor M1 is electrically connected to a power voltage signal terminal VGH', and the second electrode of the transistor M1 is electrically connected to a second node N2'. The gate of the transistor M2 is electrically connected to a clock signal terminal XCK', the first electrode of the transistor M2 is electrically connected to the second node N2', and the second electrode of the transistor M2 is electrically connected to a third node N3'. The gate of the transistor M3 is electrically connected to the third node N3', the first electrode of the transistor M3 is electrically connected to the clock signal terminal XCK', and the second electrode of the transistor M3 is electrically connected to an output terminal OUT of the shift register.

[0039] In the shift register, the transistor M1 and the transistor M2 together constitute a high-potential maintaining unit of the third node N3'. When the first node N1' is at a low potential, the transistor M1 is turned on, and the second node N2' is written with a high level provided by the power voltage signal terminal VGH'. When the clock signal terminal XCK' outputs a low level, the transistor M2 is turned on, and the high level provided by the power voltage signal terminal VGH' is written to the third node N3', thereby maintaining the high level of the third node N3'. When the clock signal terminal XCK' outputs a high level, the transistor M2 is turned off, and the third node N3' is locked at a high potential, that is, the high level of the third node N3' is maintained.

[0040] However, the inventors of the present application have found that when the first node N1' is switched to high level, the transistor M1 is turned off, and the second node N2' remains at high level provided by the power voltage signal terminal VGH'. When the clock signal terminal XCK' outputs low level, the transistor M2 is turned on, and the high level of the second node N2' is transmitted to the third node N3' through the transistor M2, causing the low level of the third node N3' to fluctuate, thereby affecting the normal output of the low level voltage signal by the transistor M3. On the other hand, the clock signal provided by the clock signal terminal XCK' is a high-frequency signal, that is, the clock signal frequently switches between high level and low level, and is also affected by the parasitic capacitance of the transistor M2, causing the potential of the third node N3' to fluctuate, thereby affecting the normal output of the low level voltage signal by the transistor M3, and making the low level voltage signal output by the shift register unstable.

[0041] In view of the above research findings of the inventors, the embodiments of the present application provide a shift register and a driving method thereof, a gate drive circuit and a display panel, which can solve the technical problem of unstable output of the shift register in the related art when outputting a low level voltage signal.

[0042] The technical concept of the embodiments of the present application is to provide a new circuit connection structure, the control terminal of the first switch unit is electrically connected with the first node, the first terminal of the first switch unit is electrically connected with the first power voltage signal terminal, and the second terminal of the first switch unit is electrically connected with the second node; the control terminal of the second switch unit is electrically connected with the second node, the first terminal of the second switch unit is electrically connected with the first power voltage signal terminal, and the second terminal of the second switch unit is electrically connected with the first node. In the low level output stage, the first switch unit is turned on in response to the control of the first node, and the off level of the first power voltage signal terminal is written into the second node, so that the second switch unit is turned off under the control of the second node.

[0043] In this way, on the one hand, the off level of the first power voltage signal terminal can be prevented from being transmitted to the first node through the second switch unit to affect the potential of the first node, thereby ensuring stable output of the low level voltage signal; on the other hand, neither the first switch unit nor the second switch unit is connected with the clock signal terminal, so that the influence of the clock signal transmitted by the clock signal terminal on the first node can be avoided, thereby further ensuring stable output of the low level voltage signal.

[0044] First, the shift register provided by the embodiments of the present application will be introduced.

[0045] Figure 2 A circuit schematic diagram of the shift register provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the shift register comprises a plurality of shift register units 100, and each shift register unit 100 comprises a first node N1', a second node N2', a third node N3', a first transistor M1, a second transistor M2, a third transistor M3, a first switch unit S1, a second switch unit S2, and a clock signal terminal XCK'. Figure 2As shown, the shift register 20 provided by the embodiment of the present application can include a first output module 21 and a first node control module 22. The control end of the first output module 21 is electrically connected with the first node N1, the first end of the first output module 21 is electrically connected with the first clock signal end XCK, and the second end of the first output module 21 is electrically connected with the output end OUT of the shift register 20. The first output module 21 can be turned on under the control of the first node N1 to transmit the first clock signal of the first clock signal end XCK to the output end OUT of the shift register 20.

[0046] The first node control module 22 can include a first switch unit 221 and a second switch unit 222. The control end of the first switch unit 221 is electrically connected with the first node N1, the first end of the first switch unit 221 is electrically connected with the first power voltage signal end VGH, and the second end of the first switch unit 221 is electrically connected with the second node N2. The control end of the second switch unit 222 is electrically connected with the second node N2, the first end of the second switch unit 222 is electrically connected with the first power voltage signal end VGH, and the second end of the second switch unit 222 is electrically connected with the first node N1.

[0047] In the low-level output stage, i.e. the stage of outputting the low-level voltage signal by the shift register 20, the first switch unit 221 can be turned on under the control of the first node N1 to write the off level of the first power voltage signal end VGH into the second node N2, and the second switch unit 222 is turned off under the control of the second node N2.

[0048] Specifically, in the low-level output stage, the first clock signal provided by the first clock signal end XCK is at low level, the first output module 21 can be turned on under the control of the first node N1 to transmit the low level provided by the first clock signal end XCK to the output end OUT of the shift register 20, and the shift register 20 outputs the low-level voltage signal. The first switch unit 221 can be turned on under the control of the first node N1 to write the off level of the first power voltage signal end VGH into the second node N2, and the second switch unit 222 is turned off under the control of the second node N2.

[0049] In this way, on the one hand, since the second switch unit 222 is turned off under the control of the second node N2, the off level of the first power voltage signal end VGH can be prevented from being transmitted to the first node N1 through the second switch unit 222 to affect the potential of the first node N1, thereby ensuring the stable output of the low-level voltage signal; on the other hand, neither the first switch unit 221 nor the second switch unit 222 is connected with the clock signal end (such as the XCK’ shown in the figure), so that the influence of the clock signal transmitted by the clock signal end on the first node N1 can be avoided, thereby further ensuring the stable output of the low-level voltage signal. Figure 1 In this way, on the one hand, since the second switch unit 222 is turned off under the control of the second node N2, the off level of the first power voltage signal end VGH can be prevented from being transmitted to the first node N1 through the second switch unit 222 to affect the potential of the first node N1, thereby ensuring the stable output of the low-level voltage signal; on the other hand, neither the first switch unit 221 nor the second switch unit 222 is connected with the clock signal end (such as the XCK’ shown in the figure), so that the influence of the clock signal transmitted by the clock signal end on the first node N1 can be avoided, thereby further ensuring the stable output of the low-level voltage signal.

[0050] In order to better maintain the output of the high level voltage signal of the shift register 20, the shift register 20 can further comprise a third switch unit. In the high level output stage, the third switch unit and the second switch unit can cooperate to maintain the first node N1 at the off level, thereby ensuring that the shift register 20 can stably output the high level voltage signal.

[0051] Figure 3 Another circuit schematic diagram of the shift register provided by the embodiments of the present application is shown in FIG. 3. Specifically, according to some embodiments of the present application, the first node control module 22 can optionally comprise a third switch unit 223, and the third switch unit 223 is electrically connected with the second node N2. Figure 3

[0052] In the high level output stage, that is, the stage in which the shift register 20 outputs the high level voltage signal, the first node N1 is at the off level, the first switch unit 221 is off, and the third switch unit 223 can be used to write the on level to the second node N2. The second switch unit 222 is turned on under the control of the second node N2, and the off level of the first power voltage signal end VGH is written to the first node N1.

[0053] In this way, by adding the third switch unit 223, in the high level output stage, the third switch unit 223 writes the on level to the second node N2, so that the second switch unit 222 is turned on, and the off level of the first power voltage signal end VGH is written to the first node N1 through the second switch unit 222, thereby maintaining the first node N1 at the off level, and further ensuring that the first output module 21 can be turned off. The first clock signal of the first clock signal end XCK does not affect the normal output of the high level voltage signal, and the shift register 20 can output a stable high level voltage signal.

[0054] The embodiments of the present application do not limit the circuit structure for outputting the high level voltage signal, as shown in FIG. 3, for example, in some examples, the shift register 20 can further comprise a second output module 23, the control end of the second output module 23 is electrically connected with the third node N3, the first end of the second output module 23 is electrically connected with the first power voltage signal end VGH, and the second end of the second output module 23 is electrically connected with the output end OUT of the shift register 20. Figure 3 In the high level output stage, the second output module 23 can be turned on under the control of the third node N3, and the high level voltage signal of the first power voltage signal end VGH is transmitted to the output end OUT of the shift register 20, so that the shift register 20 outputs the high level voltage signal.

[0055]

[0056] ​​It should be noted that in some embodiments, the first clock signal terminal XCK can also provide a high level voltage signal in the high level output stage, and the high level voltage signal is output through the first output module 21, which is not limited in the embodiments of the present application.

[0057] Figure 4 Another circuit schematic diagram of the shift register provided by the embodiments of the present application is shown in FIG. 6. Figure 4 As shown in FIG. 6, in some specific embodiments, the control terminal of the third switch unit 223 and the first terminal of the third switch unit 223 can be electrically connected with the second power voltage signal terminal VGL, and the second terminal of the third switch unit 223 is electrically connected with the second node N2.

[0058] In the high level output stage, the third switch unit 223 is turned on under the control of the second power voltage signal terminal VGL, and the turn-on level of the second power voltage signal terminal VGL is written to the second node N2. The second switch unit 222 is turned on under the control of the second node N2, and the off level of the first power voltage signal terminal VGH is written to the first node N1, so as to maintain the first node N1 at the off level.

[0059] Without special instructions, the embodiments of the present application take the third switch unit 223 as a P-type transistor for example. When the third switch unit 223 is a P-type transistor, the second power voltage signal terminal VGL can provide a second power voltage signal, and the voltage value of the second power voltage signal is less than 0V, i.e., the second power voltage signal is a negative power voltage signal. Therefore, the third switch unit 223 can be in the turn-on state under the control of the second power voltage signal terminal VGL. In the high level output stage, the first node N1 is at the off level, the first switch unit 221 is turned off, and the third switch unit 223 is turned on under the control of the second power voltage signal terminal VGL, so as to write the turn-on level (such as low level) of the second power voltage signal terminal VGL to the second node N2, so as to turn on the second switch unit 222. In this way, the off level of the first power voltage signal terminal VGH can be written to the first node N1 through the second switch unit 222, so as to maintain the first node N1 at the off level, thereby ensuring that the first output module 21 can be turned off, avoiding the influence of the first clock signal of the first clock signal terminal XCK on the normal output of the high level voltage signal, and ensuring that the shift register 20 can output stable high level voltage signal.

[0060] In addition, since the control terminal of the third switch unit 223 and the first terminal of the third switch unit 223 are connected with the same signal terminal, the number of signal terminals and wires in the display panel can be reduced, which is conducive to simplifying the wiring design and reducing the production cost.

[0061] The inventors of the present application further realize that, in the high level output stage, the first switch unit 221 is turned off, and the third switch unit 223 is turned on under the control of the second power voltage signal terminal VGL, so as to write the turn-on level of the second power voltage signal terminal VGL to the second node N2, and the second switch unit 222 is turned on under the control of the second node N2, so as to write the off level of the first power voltage signal terminal VGH to the first node N1, thereby maintaining the first node N1 at the off level, and ensuring that the first output module 21 can be turned off, avoiding the influence of the first clock signal of the first clock signal terminal XCK on the normal output of the high level voltage signal, and ensuring that the shift register 20 can output stable high level voltage signal. Figure 4In the illustrated embodiment, since the control terminal of the third switching unit 223 is connected to the second power supply voltage signal terminal VGL, and the second power supply voltage signal terminal VGL continuously outputs a negative power supply voltage signal (i.e., a conduction level), the third switching unit 223 is always in a conducting state. During the low-level output phase, it is necessary to ensure that the second node N2 is at a cutoff level, thereby ensuring that the second switching unit 222 is turned off under the control of the second node N2. However, since the third switching unit 223 is always in a conducting state, during the low-level output phase, the conduction level of the second power supply voltage signal terminal VGL will be written into the second node N2, which may prevent the second node N2 from being properly at a cutoff level, thus resulting in the second switching unit 222 not being completely turned off.

[0062] In view of this, the embodiments of this application consider adjusting the width-to-length ratio of the channel regions of the first switching unit 221 and the third switching unit 223 to ensure that the second node N2 can be in a better cutoff level during the low-level output phase, thereby ensuring that the second switching unit 222 is turned off more thoroughly.

[0063] Figure 5 This is another circuit diagram of a shift register provided in an embodiment of this application. For example... Figure 5 As shown, in some specific embodiments, optionally, both the first switching unit 221 and the third switching unit 223 may include transistors. Figure 5 The following diagram illustrates the case where both the first switching unit 221 and the third switching unit 223 are P-type transistors. The width-to-length ratio (W / L) of the channel region of the first switching unit 221 can be greater than the width-to-length ratio (W / L) of the channel region of the third switching unit 223.

[0064] Thus, during the low-level output phase, although both the first switch unit 221 and the third switch unit 223 are turned on, the width-to-length ratio W / L of the channel region of the first switch unit 221 is greater than that of the channel region of the third switch unit 223. Therefore, the level written by the second node N2 is still dominated by the cutoff level written by the first switch unit 221, so that the second node N2 is still at the cutoff level, thereby ensuring that the second switch unit 222 is turned off more thoroughly.

[0065] After extensive research, the inventors of this application discovered that when the ratio of the width-to-length ratio W / L of the channel region of the first switching unit 221 to the width-to-length ratio W / L of the channel region of the third switching unit 223 is greater than or equal to 2:1, it can better ensure that the second node N2 is at the cutoff level during the low-level output stage, thereby ensuring that the second switching unit 222 is turned off more thoroughly.

[0066] In view of this, in some specific embodiments, optionally, the ratio of the width-to-length ratio W / L of the channel region of the first switching unit 221 to the width-to-length ratio W / L of the channel region of the third switching unit 223 can be greater than or equal to 2:1. For example, in some examples, the ratio of the width-to-length ratio W / L of the channel region of the first switching unit 221 to the width-to-length ratio W / L of the channel region of the third switching unit 223 can include 2:1, 3:1, 5:1, ..., 10:1, etc.

[0067] Thus, during the low-level output phase, although both the first switch unit 221 and the third switch unit 223 are turned on, the ratio of the width-to-length ratio W / L of the channel region of the first switch unit 221 to that of the third switch unit 223 is greater than or equal to 2:1. Therefore, the level written by the second node N2 is still dominated by the cutoff level written by the first switch unit 221, so that the second node N2 is still at the cutoff level, thereby ensuring that the second switch unit 222 is turned off more thoroughly.

[0068] Figure 6 This is another circuit diagram of a shift register provided in an embodiment of this application. For example... Figure 6 As shown, with Figure 4 Unlike the illustrated embodiment, in some other specific embodiments, optionally, the control terminal of the third switching unit 223 is electrically connected to the second power supply voltage signal terminal VGL, the first terminal of the third switching unit 223 is electrically connected to the second clock signal terminal CK', and the second terminal of the third switching unit 223 is electrically connected to the second node N2.

[0069] During the high-level output phase, the third switch unit 223 is turned on under the control of the second power supply voltage signal terminal VGL, and writes the on-level of the second clock signal terminal CK' into the second node N2.

[0070] Specifically, the third switching unit 223 can remain in the on state under the control of the second power supply voltage signal terminal VGL. During the high-level output phase, the first node N1 is at the off level, the first switching unit 221 is turned off, the second clock signal terminal CK' provides the on level, and the third switching unit 223 writes the on level of the second clock signal terminal CK' into the second node N2, so that the second switching unit 222 is turned on. In this way, the off level of the first power supply voltage signal terminal VGH can be written into the first node N1 through the second switching unit 222, thereby maintaining the first node N1 at the off level, thus ensuring that the first output module 21 can be turned off, avoiding the first clock signal of the first clock signal terminal XCK from affecting the normal output of the high-level voltage signal, and ensuring that the shift register 20 can output a stable high-level voltage signal.

[0071] See also Figure 6According to some embodiments of this application, optionally, during the low-level output phase, the third switching unit 223 can be turned on under the control of the second power supply voltage signal terminal VGL, and write the cutoff level of the second clock signal terminal CK' into the second node N2.

[0072] Specifically, during the low-level output phase, the first switching unit 221 can be turned on under the control of the first node N1, writing the cutoff level of the first power supply voltage signal terminal VGH into the second node N2. At the same time, the second clock signal terminal CK' can provide a cutoff level, and the third switching unit 223 writes the cutoff level of the second clock signal terminal CK' into the second node N2.

[0073] That is, during the low-level output phase, not only does the first switching unit 221 write the cutoff level of the first power supply voltage signal terminal VGH into the second node N2, but the third switching unit 223 also writes the cutoff level of the second clock signal terminal CK' into the second node N2, so that the second node N2 is in a better cutoff level, ensuring that the second switching unit 222 is turned off more thoroughly under the control of the second node N2, and to a large extent ensuring that the shift register 20 can output a stable low-level voltage signal.

[0074] It should be noted that the voltage values ​​of the cutoff level of the first power supply voltage signal terminal VGH and the voltage values ​​of the cutoff level of the second clock signal terminal CK' can be flexibly adjusted according to the actual situation, and this application embodiment does not limit this.

[0075] For example, in some examples, the cutoff voltage of the second clock signal terminal CK' can be lower than the cutoff voltage of the first power supply voltage signal terminal VGH, thereby reducing power consumption. For example, in other examples, the cutoff voltage of the second clock signal terminal CK' can be greater than or equal to the cutoff voltage of the first power supply voltage signal terminal VGH, thereby enabling the second node N2 to write a higher cutoff voltage, so that the second switching unit 222 is turned off more completely.

[0076] Figure 7 This is another circuit diagram of a shift register provided in an embodiment of this application. For example... Figure 7 As shown, with Figure 4 The illustrated embodiments and Figure 6 Unlike the illustrated embodiment, in some other specific embodiments, optionally, the control terminal of the third switching unit 223 is electrically connected to the second clock signal terminal CK', the first terminal of the third switching unit 223 is electrically connected to the second power supply voltage signal terminal VGL, and the second terminal of the third switching unit 223 is electrically connected to the second node N2.

[0077] In the high-level output stage, the third switch unit 223 is turned on under the control of the second clock signal terminal CK', and the on level of the second power voltage signal terminal VGL is written into the second node N2.

[0078] Specifically, in the high-level output stage, the first node N1 is at the off level, the first switch unit 221 is turned off, the second clock signal terminal CK' provides the on level, and the third switch unit 223 is turned on under the control of the second clock signal terminal CK' to write the on level of the second power voltage signal terminal VGL into the second node N2, so that the second switch unit 222 is turned on. In this way, the off level of the first power voltage signal terminal VGH can be written into the first node N1 through the second switch unit 222, so that the first node N1 is maintained at the off level, thereby ensuring that the first output module 21 can be turned off, avoiding the influence of the first clock signal of the first clock signal terminal XCK on the normal output of the high-level voltage signal, and ensuring that the shift register 20 can output stable high-level voltage signals.

[0079] Continuing to refer to Figure 7 According to some embodiments of the present application, optionally, in the low-level output stage, the second clock signal terminal CK' can provide the off level, and the third switch unit 223 can be turned off under the control of the second clock signal terminal CK'.

[0080] In this way, since the third switch unit 223 is turned off, the on level of the second power voltage signal terminal VGL cannot be written into the second node N2, thereby ensuring that the second node N2 can be better at the off level in the low-level output stage, so that the second switch unit 222 is turned off under the control of the second node N2, and the shift register 20 can output stable low-level voltage signals.

[0081] Figure 8 Another circuit schematic diagram of the shift register provided by the embodiments of the present application is provided. As shown in Figure 8 According to some embodiments of the present application, optionally, the first node N1 and the control terminal of the first output module 21 can further be connected with the first switch module 24. Specifically, the shift register 20 can further include the first switch module 24, the control terminal of the first switch module 24 is electrically connected with the second power voltage signal terminal VGL, the first end of the first switch module 24 is electrically connected with the first node N1, and the second end of the first switch module 24 is electrically connected with the control terminal of the first output module 21.

[0082] In some examples, the first switching module 24 can specifically be a transistor. Since the second power supply voltage signal terminal VGL continuously outputs the second power supply voltage signal (i.e., the on-level), the first switching module 24 is in the on state most of the time. However, during the low-level output phase, the potential of the control terminal of the first output module 21 can be pulled down to a lower potential. Due to the switching characteristics of the transistor itself, when the difference between the voltage value Vg at the control terminal of the first switching module 24 and the voltage value Vs at the second terminal of the first switching module 24 is less than or equal to the absolute value of the threshold voltage |Vg| of the first switching module 24, the voltage will be lower. th | at that time, i.e., V g -V s =|V th When the first switch module 24 is turned off, the potential of the first node N1 will not be pulled down further, thereby reducing the voltage difference between the gate drain or gate source of each transistor connected to the first node N1 and improving circuit stability.

[0083] Figure 9 This is another circuit diagram of a shift register provided in an embodiment of this application. For example... Figure 9 As shown, according to some embodiments of this application, optionally, the first node control module 22 may further include a fourth switch unit 224. The control terminal of the fourth switch unit 224 is electrically connected to the third clock signal terminal CK, the first terminal of the fourth switch unit 224 is electrically connected to the input terminal IN of the shift register, and the second terminal of the fourth switch unit 224 is electrically connected to the first node N1. The fourth switch unit 224 can be used to write the on-level or off-level of the input terminal IN of the shift register into the first node N1 under the control of the third clock signal terminal CK. For example, in the low-level output stage, the fourth switch unit 224 can write the on-level of the input terminal IN of the shift register into the first node N1 under the control of the third clock signal terminal CK. As another example, in the high-level output stage, the fourth switch unit 224 can write the off-level of the input terminal IN of the shift register into the first node N1 under the control of the third clock signal terminal CK.

[0084] In other words, the fourth switch unit 224 is mainly used to control the potential of the first node N1, that is, to control whether the first node N1 is at the on level or the off level.

[0085] Figure 10 This is another circuit diagram of a shift register provided in an embodiment of this application. For example... Figure 10As shown, in some specific embodiments, the fourth switch unit 224 can optionally include a first sub-transistor T1_1 and a second sub-transistor T1_2 connected in series, i.e., a double-gate transistor. The gate of the first sub-transistor T1_1 and the gate of the second sub-transistor T1_2 are both electrically connected to the third clock signal terminal CK, the first pole of the first sub-transistor T1_1 is electrically connected to the input terminal IN of the shift register, the second pole of the first sub-transistor T1_1 is electrically connected to the first pole of the second sub-transistor T1_2, and the second pole of the second sub-transistor T1_2 is electrically connected to the first node N1.

[0086] When the third clock signal terminal CK transmits a turn-on level, the first sub-transistor T1_1 and the second sub-transistor T1_2 are turned on, and the turn-on level or the turn-off level of the input terminal IN of the shift register is sequentially written into the first node N1 through the turned-on first sub-transistor T1_1 and the second sub-transistor T1_2.

[0087] Since the fourth switch unit 224 is a double-gate transistor, the leakage current of the first node N1 can be reduced, the stability of the potential of the first node N1 is maintained, and the stable voltage signal output by the shift register is ensured.

[0088] Figure 11 Another circuit schematic diagram of the shift register provided by the embodiments of the present application is shown in FIG. 6. Figure 11 As shown, according to some embodiments of the present application, the shift register 20 can further include a first coupling module 25, a first end of the first coupling module 25 being electrically connected to the output terminal OUT of the shift register, and a second end of the first coupling module 25 being electrically connected to the control terminal of the first output module 21.

[0089] When switching to the low-level output stage, the output terminal OUT of the shift register is switched from outputting a high level to outputting a low level, and thus the first coupling module 25 will be coupled. Under the coupling effect of the first coupling module 25, the potential of the control terminal of the first output module 21 can be further pulled down, and thus the first output module 21 is opened more fully, and the output terminal OUT of the shift register can output a lower low level.

[0090] When switching to the high-level output stage again, the output terminal OUT of the shift register is switched from outputting a low level to outputting a high level, and thus the first coupling module 25 will be coupled. Under the coupling effect of the first coupling module 25, the potential of the control terminal of the first output module 21 can be further pulled up, and thus the first output module 21 is turned off more thoroughly, and thus the output terminal OUT of the shift register can output a stable high-level voltage signal.

[0091] Figure 12 Another circuit schematic diagram of the shift register provided by the embodiments of the present application is shown in FIG. 6.Figure 12 As shown, the shift register 20 can include a second output module 23, a control end of the second output module 23 being electrically connected with the third node N3, a first end of the second output module 23 being electrically connected with the first power voltage signal end VGH, and a second end of the second output module 23 being electrically connected with the output end OUT of the shift register 20. In the high-level output stage, the second output module 23 can be turned on under the control of the third node N3, and a high-level voltage signal of the first power voltage signal end VGH is transmitted to the output end OUT of the shift register 20, so that the shift register 20 outputs a high-level voltage signal.

[0092] Continuing to refer to Figure 12 According to some embodiments of the present application, optionally, the shift register 20 can include a third node control module 26. The third node control module 26 can include a fifth switch unit 225 and a sixth switch unit 226. A control end of the fifth switch unit 225 is electrically connected with the first node N1, a first end of the fifth switch unit 225 is electrically connected with the third clock signal end CK, and a second end of the fifth switch unit 225 is electrically connected with the third node N3. A control end of the sixth switch unit 226 is electrically connected with the third clock signal end CK, a first end of the sixth switch unit 226 is electrically connected with the second power voltage signal end VGL, and a second end of the sixth switch unit 226 is electrically connected with the third node N3.

[0093] When the first node N1 is at the turn-on level, the fifth switch unit 225 is turned on under the control of the first node N1, and the turn-on level or the cut-off level of the third clock signal end CK is written to the third node N3. When the third clock signal end CK is at the turn-on level, the sixth switch unit 226 is turned on under the control of the third clock signal end CK, and the turn-on level of the second power voltage signal end VGL is written to the third node N3. That is, the fifth switch unit 225 and the sixth switch unit 226 are mainly used to control the potential of the third node N3.

[0094] Continuing to refer to Figure 12 According to some embodiments of the present application, optionally, the shift register 20 can further include a first storage module 27. A first end of the first storage module 27 is electrically connected with the output end OUT of the shift register, and a second end of the first storage module 27 is electrically connected with the control end (i.e., the third node N3) of the second output module 23. The first storage module 27 can be used to maintain the potential of the third node N3.

[0095] For the convenience of understanding, the working process of the shift register will be exemplified below in combination with some specific application embodiments.

[0096] Figure 13 A driving timing diagram corresponding to the shift register shown in FIG. 2 is shown in FIG. 3. In combination with FIG. 2, the working process of the shift register will be exemplified below in combination with some specific application embodiments. Figure 12 A driving timing diagram corresponding to the shift register shown in FIG. 2 is shown in FIG. 3. In combination with FIG. 2, the working process of the shift register will be exemplified below in combination with some specific application embodiments.Figure 12 and Figure 13 As shown in FIG. 2, according to some embodiments of the present application, one working period of the shift register 20 can include stages t1-t5. The stages t1, t3, t4 and t5 are high-level output stages, and the stage t2 is a low-level output stage. For the convenience of description, the stage t1 can be referred to as a first high-level output stage, the stage t3 can be referred to as a second high-level output stage, the stage t4 can be referred to as a third high-level output stage, and the stage t5 can be referred to as a fourth high-level output stage.

[0097] In the first high-level output stage t1, the third clock signal terminal CK and the input terminal IN of the shift register provide a conduction level, and the first clock signal terminal XCK provides a cutoff level. The fourth switch unit 224 is turned on in response to the conduction level of the third clock signal terminal CK, and writes the conduction level of the input terminal IN of the shift register into the first node N1. The first output module 21 is turned on in response to the conduction level of the first node N1, and transmits the high level of the first clock signal terminal XCK to the output terminal OUT of the shift register. The fifth switch unit 225 is turned on in response to the conduction level of the first node N1, and transmits the conduction level of the third clock signal terminal CK to the third node N3. The second output module 23 is turned on in response to the conduction level of the third node N3, and transmits the high level of the first power voltage signal terminal VGH to the output terminal OUT of the shift register.

[0098] In the first high-level output stage t1, the first switch unit 221 can be turned on under the control of the first node N1, and writes the cutoff level of the first power voltage signal terminal VGH into the second node N2. The third switch unit 223 is always in a conduction state, and writes the conduction level of the second power voltage signal terminal VGL into the second node N2. Since the width-length ratio W / L of the channel region of the first switch unit 221 is greater than the width-length ratio W / L of the channel region of the third switch unit 223, the level written into the second node N2 is still mainly the cutoff level written by the first switch unit 221, so that the second node N2 is still at the cutoff level, and the second switch unit 222 is turned off under the control of the second node N2. Figure 4 and Figure 12 In the first high-level output stage t1, the first switch unit 221 can be turned on under the control of the first node N1, and writes the cutoff level of the first power voltage signal terminal VGH into the second node N2. The third switch unit 223 is always in a conduction state, and writes the conduction level of the second power voltage signal terminal VGL into the second node N2. Since the width-length ratio W / L of the channel region of the first switch unit 221 is greater than the width-length ratio W / L of the channel region of the third switch unit 223, the level written into the second node N2 is still mainly the cutoff level written by the first switch unit 221, so that the second node N2 is still at the cutoff level, and the second switch unit 222 is turned off under the control of the second node N2.

[0099] In the low level output stage t2, the first clock signal terminal XCK provides a conducting level, the third clock signal terminal CK and the input terminal IN of the shift register provide a cut-off level. The fourth switch unit 224 is turned off in response to the cut-off level of the third clock signal terminal CK, and the first node N1 maintains the conducting level. The fifth switch unit 225 is turned on in response to the conducting level of the first node N1, and transmits the cut-off level of the third clock signal terminal CK to the third node N3. The second output module 23 is turned off in response to the cut-off level of the third node N3. The first output module 21 is turned on in response to the conducting level of the first node N1, and transmits the low level of the first clock signal terminal XCK to the output terminal OUT of the shift register.

[0100] In the low level output stage t2, the first clock signal terminal XCK provides a conducting level, the third clock signal terminal CK and the input terminal IN of the shift register provide a cut-off level. The fourth switch unit 224 is turned off in response to the cut-off level of the third clock signal terminal CK, and the first node N1 maintains the conducting level. The fifth switch unit 225 is turned on in response to the conducting level of the first node N1, and transmits the cut-off level of the third clock signal terminal CK to the third node N3. The second output module 23 is turned off in response to the cut-off level of the third node N3. The first output module 21 is turned on in response to the conducting level of the first node N1, and transmits the low level of the first clock signal terminal XCK to the output terminal OUT of the shift register. Figure 4 Figure 12 In the low level output stage t2, the first clock signal terminal XCK provides a conducting level, the third clock signal terminal CK and the input terminal IN of the shift register provide a cut-off level. The fourth switch unit 224 is turned off in response to the cut-off level of the third clock signal terminal CK, and the first node N1 maintains the conducting level. The fifth switch unit 225 is turned on in response to the conducting level of the first node N1, and transmits the cut-off level of the third clock signal terminal CK to the third node N3. The second output module 23 is turned off in response to the cut-off level of the third node N3. The first output module 21 is turned on in response to the conducting level of the first node N1, and transmits the low level of the first clock signal terminal XCK to the output terminal OUT of the shift register.

[0101] In the low level output stage t2, the first clock signal terminal XCK provides a conducting level, the third clock signal terminal CK and the input terminal IN of the shift register provide a cut-off level. The fourth switch unit 224 is turned off in response to the cut-off level of the third clock signal terminal CK, and the first node N1 maintains the conducting level. The fifth switch unit 225 is turned on in response to the conducting level of the first node N1, and transmits the cut-off level of the third clock signal terminal CK to the third node N3. The second output module 23 is turned off in response to the cut-off level of the third node N3. The first output module 21 is turned on in response to the conducting level of the first node N1, and transmits the low level of the first clock signal terminal XCK to the output terminal OUT of the shift register.

[0102] In the low level output stage t2, the first clock signal terminal XCK provides a conducting level, the third clock signal terminal CK and the input terminal IN of the shift register provide a cut-off level. The fourth switch unit 224 is turned off in response to the cut-off level of the third clock signal terminal CK, and the first node N1 maintains the conducting level. The fifth switch unit 225 is turned on in response to the conducting level of the first node N1, and transmits the cut-off level of the third clock signal terminal CK to the third node N3. The second output module 23 is turned off in response to the cut-off level of the third node N3. The first output module 21 is turned on in response to the conducting level of the first node N1, and transmits the low level of the first clock signal terminal XCK to the output terminal OUT of the shift register. Figure 4 Figure 12 ​​Taking the illustrated embodiment as an example, during the second high-level output stage t3, the first node N1 is at the cutoff level, the first switching unit 221 is turned off, and the third switching unit 223 is turned on under the control of the second power supply voltage signal terminal VGL, writing the on-state (e.g., low level) of the second power supply voltage signal terminal VGL to the second node N2, thereby turning on the second switching unit 222. In this way, the cutoff level of the first power supply voltage signal terminal VGH can be written to the first node N1 through the second switching unit 222, thus maintaining the first node N1 at the cutoff level, thereby ensuring that the first output module 21 can be turned off, preventing the first clock signal of the first clock signal terminal XCK from affecting the normal output of the high-level voltage signal, and ensuring that the shift register 20 can output a stable high-level voltage signal.

[0103] During the third high-level output phase t4, the first clock signal terminal XCK provides an on-level, while the third clock signal terminal CK and the input terminal IN of the shift register provide off-levels. The fourth switching unit 224 is turned off in response to the off-level of the third clock signal terminal CK, and the first coupling module 25 maintains the off-level of the first node N1. The first output module 21 is turned off in response to the off-level of the first node N1. The first storage module 27 maintains the on-level of the third node N3, and the second output module 23 is turned on in response to the on-level of the third node N3, transmitting the high level of the first power supply voltage signal terminal VGH to the output terminal OUT of the shift register.

[0104] by Figure 4 and Figure 12 Taking the illustrated embodiment as an example, in the third high-level output stage t4, the first node N1 is at the cutoff level, the first switching unit 221 is turned off, and the third switching unit 223 is turned on under the control of the second power supply voltage signal terminal VGL, writing the on-state level (e.g., low level) of the second power supply voltage signal terminal VGL to the second node N2, thereby turning on the second switching unit 222. In this way, the cutoff level of the first power supply voltage signal terminal VGH can be written to the first node N1 through the second switching unit 222, thus maintaining the first node N1 at the cutoff level, thereby ensuring that the first output module 21 can be turned off, preventing the first clock signal of the first clock signal terminal XCK from affecting the normal output of the high-level voltage signal, and ensuring that the shift register 20 can output a stable high-level voltage signal.

[0105] In the fourth high level output stage t5, the third clock signal terminal CK provides a conducting level, the first clock signal terminal XCK and the input terminal IN of the shift register provide a cut-off level. The fourth switch unit 224 is turned on in response to the conducting level of the third clock signal terminal CK, and writes the cut-off level of the input terminal IN of the shift register into the first node N1. The first output module 21 is turned off in response to the cut-off level of the first node N1. The first storage module 27 maintains the conducting level of the third node N3, and the second output module 23 is turned on in response to the conducting level of the third node N3, and transmits the high level of the first power voltage signal terminal VGH to the output terminal OUT of the shift register.

[0106] In the embodiment shown in Figure 4 and Figure 12 , in the fourth high level output stage t5, the first node N1 is at a cut-off level, the first switch unit 221 is turned off, and the third switch unit 223 is turned on under the control of the second power voltage signal terminal VGL, and writes the conducting level (e.g. low level) of the second power voltage signal terminal VGL into the second node N2, so as to make the second switch unit 222 conduct. In this way, the cut-off level of the first power voltage signal terminal VGH can be written into the first node N1 through the second switch unit 222, so as to maintain the first node N1 at a cut-off level, and further ensure that the first output module 21 can be turned off, avoid the influence of the first clock signal of the first clock signal terminal XCK on the normal output of the high level voltage signal, and ensure that the shift register 20 can output stable high level voltage signals.

[0107] Figure 14 Another circuit schematic diagram of the shift register provided in the embodiments of the present application is shown in Figure 12 and Figure 14 In some specific embodiments, the fourth switch unit 224 can include a first sub-transistor T1_1 and a second sub-transistor T1_2 connected in series, the first output module 21 can include a second transistor T2, the first switch unit 221 can include a third transistor T3, the second switch unit 222 can include a fourth transistor T4, the third switch unit 223 can include a fifth transistor T5, the second output module 23 can include a sixth transistor T6, the first switch module 24 can include a seventh transistor T7, the fifth switch unit 225 can include an eighth transistor T8, the sixth switch unit 226 can include a ninth transistor T9, and the first coupling module 25 can include a first coupling capacitor C1, and the first storage module 27 can include a first storage capacitor C2.

[0108] The connection modes of the transistors and the capacitors can refer to Figure 14 and the descriptions of the connection modes of the modules above, which will not be repeated here. In addition, Figure 14The working process of each transistor and capacitor in the shift register 20 is described in detail below. Figure 12 and Figure 13 The description of the driving timing is not repeated here.

[0109] Based on the shift register 20 provided in the above embodiments, the present application also provides a driving method of a shift register. The driving method of the shift register can be applied to the shift register 20 provided in the above embodiments, for example. Please refer to the following embodiments.

[0110] Figure 15 A flowchart of the driving method of the shift register provided in the embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, the driving method of the shift register provided in the embodiments of the present application includes the following steps. Figure 15

[0111] In the low-level output stage, the first node is provided with a conduction level to make the first switch unit conduct under the control of the first node, and the off level of the first power voltage signal end is written to the second node, and the second switch unit is turned off under the control of the second node.

[0112] The specific process of S101 has been described in detail above, and is not repeated here.

[0113] The driving method of the shift register provided in the embodiments of the present application, in the low-level output stage, the first switch unit is turned on in response to the control of the first node, and the off level of the first power voltage signal end is written to the second node, so that the second switch unit is turned off under the control of the second node. In this way, on the one hand, the off level of the first power voltage signal end can be prevented from being transmitted to the first node through the second switch unit to affect the potential of the first node, and the stable output of the low-level voltage signal is ensured. On the other hand, neither the first switch unit nor the second switch unit is connected with the clock signal end, so that the influence of the clock signal transmitted by the clock signal end on the first node can be avoided, and the stable output of the low-level voltage signal is further ensured.

[0114] According to some embodiments of the present application, the first node control module further includes a third switch unit, which is electrically connected with the second node.

[0115] Figure 16 Another flowchart of the driving method of the shift register provided in the embodiments of the present application is shown in FIG. 7. As shown in FIG. 7, the driving method of the shift register provided in the embodiments of the present application further includes the following steps. Figure 16

[0116] ​​S102, in the high level output stage, the third switch unit is controlled to write the conduction level into the second node, so that the second switch unit is turned on under the control of the second node, and the off level of the first power voltage signal end is written into the first node.

[0117] The specific process of S102 has been described in detail above, and will not be described here.

[0118] According to some embodiments of the present application, optionally, the first node control module further comprises a fourth switch unit, a control end of the fourth switch unit is electrically connected with the third clock signal end, a first end of the fourth switch unit is electrically connected with the input end of the shift register, and a second end of the fourth switch unit is electrically connected with the first node.

[0119] The shift register further comprises a second output module, a third node control module, a first coupling module and a first storage module. A control end of the second output module is electrically connected with the third node, a first end of the second output module is electrically connected with the first power voltage signal end, and a second end of the second output module is electrically connected with the output end of the shift register.

[0120] The third node control module comprises a fifth switch unit and a sixth switch unit. A control end of the fifth switch unit is electrically connected with the first node, a first end of the fifth switch unit is electrically connected with the third clock signal end, and a second end of the fifth switch unit is electrically connected with the third node. A control end of the sixth switch unit is electrically connected with the third clock signal end, a first end of the sixth switch unit is electrically connected with the second power voltage signal end, and a second end of the sixth switch unit is electrically connected with the third node.

[0121] The first coupling module comprises a first end and a second end. The first end of the first coupling module is electrically connected with the output end of the shift register, and the second end of the first coupling module is electrically connected with the control end of the first output module.

[0122] The first storage module comprises a first end and a second end. The first end of the first storage module is electrically connected with the output end of the shift register, and the second end of the first storage module is electrically connected with the control end of the second output module.

[0123] Correspondingly, the high-level output stage includes a first high-level output stage before the low-level output stage. In the first high-level output stage, the third clock signal end and the input end of the shift register are provided with a turn-on level, the first clock signal end is provided with a turn-off level, the fourth switch unit is turned on in response to the turn-on level of the third clock signal end, the turn-on level of the input end of the shift register is written to the first node, the first output module is turned on in response to the turn-on level of the first node, the high level of the first clock signal end is transmitted to the output end of the shift register, the fifth switch unit is turned on in response to the turn-on level of the first node, the turn-on level of the third clock signal end is transmitted to the third node, and the second output module is turned on in response to the turn-on level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register.

[0124] The specific process of the first high-level output stage has been described in detail above, and will not be described here again.

[0125] According to some embodiments of the present application, optionally, the high-level output stage further includes at least one of a second high-level output stage, a third high-level output stage and a fourth high-level output stage after the low-level output stage.

[0126] In the second high-level output stage, the third clock signal end is provided with a turn-on level, the first clock signal end and the input end of the shift register are provided with a turn-off level, the fourth switch unit is turned on in response to the turn-on level of the third clock signal end, the turn-off level of the input end of the shift register is written to the first node, the first output module is turned off in response to the turn-off level of the first node, the sixth switch unit is turned on in response to the turn-on level of the third clock signal end, the turn-on level of the second power voltage signal end is transmitted to the third node, and the second output module is turned on in response to the turn-on level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register;

[0127] In the third high-level output stage, the first clock signal end is provided with a turn-on level, the third clock signal end and the input end of the shift register are provided with a turn-off level, the fourth switch unit is turned off in response to the turn-off level of the third clock signal end, the first coupling module maintains the turn-off level of the first node, the first output module is turned off in response to the turn-off level of the first node, the first storage module maintains the turn-on level of the third node, and the second output module is turned on in response to the turn-on level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register;

[0128] In the fourth high-level output stage, the third clock signal end is provided with a turn-on level, the first clock signal end and the input end of the shift register are provided with a turn-off level, the fourth switch unit is turned on in response to the turn-on level of the third clock signal end, the turn-off level of the input end of the shift register is written to the first node, the first output module is turned off in response to the turn-off level of the first node, the first storage module maintains the turn-on level of the third node, and the second output module is turned on in response to the turn-on level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register.

[0129] The specific processes of the second high-level output stage, the third high-level output stage and the fourth high-level output stage have been described in detail above, and will not be described here again.

[0130] Based on the shift register 20 provided in the above embodiment, correspondingly, the embodiment of the present application further provides a gate drive circuit.

[0131] Figure 17 A circuit schematic diagram of the gate drive circuit provided in the embodiment of the present application is shown in FIG. 17. Figure 17 As shown in FIG. 17, the gate drive circuit 170 provided in the embodiment of the present application can include a plurality of cascaded shift registers 20 of the above embodiment.

[0132] In some embodiments, the gate drive circuit 170 can be specifically a scan drive circuit, which can be used to provide a scan signal to a pixel circuit, and the scan signal is used to control at least part of the transistors in the pixel circuit to be turned on / off.

[0133] In some embodiments, the gate drive circuit 170 can be specifically a light-emitting control drive circuit, which can be used to provide a light-emitting control signal to a pixel circuit, and the light-emitting control signal is used to control at least part of the transistors in the pixel circuit to be turned on / off.

[0134] In some embodiments, the gate drive circuit 170 can be located at the side frame of the display panel, or can be located at the side frames of both sides of the display panel, and the embodiment of the present application does not limit this.

[0135] Based on the shift register or the gate drive circuit provided in the above embodiment, correspondingly, the present application further provides a display device including the shift register or the gate drive circuit provided in the present application. Please refer to Figure 18 , Figure 18 A structural schematic diagram of the display device provided in the embodiment of the present application is shown in FIG. 18. Figure 18 The display device 1000 provided in the embodiment of the present application includes the shift register 20 or the gate drive circuit 170 provided in any of the above embodiments of the present application. Figure 18The embodiments are described by taking a mobile phone as an example, and the display device 1000 can be understood as a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with a display function. The display device provided by the embodiments of the present application has the beneficial effects of the shift register 20 or the gate drive circuit 170 provided by the embodiments of the present application. For details, refer to the specific description of the shift register 20 or the gate drive circuit 170 in the above embodiments. The embodiments will not be repeated here.

[0136] It should be understood that the specific structure of the circuit and the driving timing provided by the drawings of the embodiments of the present application are only some examples and are not used to limit the present application. In addition, the above embodiments provided by the present application can be combined with each other without contradiction.

[0137] It should be clear that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts of each embodiment can be referred to each other. Each embodiment focuses on the differences from other embodiments. According to the above-described embodiments of the present application, these embodiments do not describe all the details and do not limit the application to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. The embodiments are selected and described in the specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well use the present application and make modifications and uses on the basis of the present application. The present application is limited by the claims and their entire scope and equivalents.

[0138] Those skilled in the art should understand that the above embodiments are exemplary and not limiting. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art can understand and implement other changed embodiments of the disclosed embodiments based on the drawings, the specification and the claims. In the claims, the term "comprising" does not exclude other structures; the number "one" does not exclude multiple; the terms "first", "second" are used to mark names and not to represent any specific order. Any reference signs in the claims should not be understood as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A shift register, characterized by, include: The first output module has a control terminal electrically connected to the first node, a first terminal electrically connected to the first clock signal terminal, and a second terminal electrically connected to the output terminal of the shift register. The first node control module includes a first switch unit and a second switch unit. The control terminal of the first switch unit is electrically connected to the first node, the first terminal of the first switch unit is electrically connected to the first power supply voltage signal terminal, and the second terminal of the first switch unit is electrically connected to the second node. The control terminal of the second switch unit is electrically connected to the second node, the first terminal of the second switch unit is electrically connected to the first power supply voltage signal terminal, and the second terminal of the second switch unit is electrically connected to the first node. During the low-level output phase, the first switching unit is turned on under the control of the first node, writing the cutoff level of the first power supply voltage signal terminal into the second node, and the second switching unit is turned off under the control of the second node.

2. The shift register of claim 1, wherein, The first node control module further includes a third switch unit, which is electrically connected to the second node; During the high-level output phase, the third switching unit is used to write the conduction level into the second node. The second switching unit is turned on under the control of the second node to write the cutoff level of the first power supply voltage signal terminal into the first node.

3. The shift register of claim 2, wherein, The control terminal and the first terminal of the third switch unit are both electrically connected to the second power supply voltage signal terminal, and the second terminal of the third switch unit is electrically connected to the second node; During the high-level output phase, the third switching unit is turned on under the control of the second power supply voltage signal terminal, and writes the on-level of the second power supply voltage signal terminal into the second node.

4. The shift register of claim 3, wherein, Both the first switching unit and the third switching unit include transistors, and the aspect ratio of the channel region of the first switching unit is greater than that of the channel region of the third switching unit.

5. The shift register of claim 4, wherein, The ratio of the width-to-length ratio of the channel region of the first switching unit to the width-to-length ratio of the channel region of the third switching unit is greater than or equal to 2:

1.

6. The shift register of claim 2, wherein, The control terminal of the third switching unit is electrically connected to the second power supply voltage signal terminal, the first terminal of the third switching unit is electrically connected to the second clock signal terminal, and the second terminal of the third switching unit is electrically connected to the second node. During the high-level output phase, the third switching unit is turned on under the control of the second power supply voltage signal terminal, and writes the on-level of the second clock signal terminal into the second node.

7. The shift register of claim 6, wherein, During the low-level output phase, the third switching unit is turned on under the control of the second power supply voltage signal terminal, and writes the cutoff level of the second clock signal terminal into the second node.

8. The shift register of claim 2, wherein, The control terminal of the third switching unit is electrically connected to the second clock signal terminal, the first terminal of the third switching unit is electrically connected to the second power supply voltage signal terminal, and the second terminal of the third switching unit is electrically connected to the second node. In the high level output stage, the third switch unit is turned on under the control of the second clock signal end, and the on level of the second power voltage signal end is written into the second node.

9. The shift register of claim 8, wherein, In the low level output stage, the third switch unit is turned off under the control of the second clock signal end.

10. The shift register of claim 1, wherein, The shift register further comprises: The first switch module has a control end electrically connected with the second power voltage signal end, a first end electrically connected with the first node, and a second end electrically connected with the control end of the first output module.

11. The shift register of claim 1, wherein, The first node control module further comprises a fourth switch unit having a control end electrically connected with the third clock signal end, a first end electrically connected with the input end of the shift register, and a second end electrically connected with the first node, and the fourth switch unit is configured to write the on level or off level of the input end of the shift register into the first node under the control of the third clock signal end.

12. The shift register of claim 11, wherein, The fourth switch unit comprises a first sub-transistor and a second sub-transistor connected in series, the gate of the first sub-transistor and the gate of the second sub-transistor are electrically connected with the third clock signal end, the first pole of the first sub-transistor is electrically connected with the input end of the shift register, the second pole of the first sub-transistor is electrically connected with the first pole of the second sub-transistor, and the second pole of the second sub-transistor is electrically connected with the first node.

13. The shift register of claim 1, wherein, The shift register further comprises a first coupling module having a first end electrically connected with the output end of the shift register and a second end electrically connected with the control end of the first output module.

14. The shift register of claim 1, wherein, The shift register further comprises: The second output module has a control end electrically connected with the third node, a first end electrically connected with the first power voltage signal end, and a second end electrically connected with the output end of the shift register. The third node control module comprises a fifth switch unit and a sixth switch unit, the control end of the fifth switch unit is electrically connected with the first node, the first end of the fifth switch unit is electrically connected with the third clock signal end, and the second end of the fifth switch unit is electrically connected with the third node; the control end of the sixth switch unit is electrically connected with the third clock signal end, the first end of the sixth switch unit is electrically connected with the second power voltage signal end, and the second end of the sixth switch unit is electrically connected with the third node.

15. The shift register of claim 14, wherein, The shift register further comprises a first storage module having a first end electrically connected with the output end of the shift register and a second end electrically connected with the control end of the second output module.

16. A driving method of a shift register, characterized by, The driving method comprises: In the low-level output stage, the first node is provided with a turn-on level so that the first switch unit is turned on under the control of the first node, and a turn-off level of the first power voltage signal end is written into the second node, and the second switch unit is turned off under the control of the second node.

17. The driving method according to claim 16, wherein The first node control module further comprises a third switch unit electrically connected with the second node. The driving method further comprises: In the high-level output stage, the third switch unit is controlled to write a turn-on level into the second node so that the second switch unit is turned on under the control of the second node, and a turn-off level of the first power voltage signal end is written into the first node.

18. The driving method according to claim 17, wherein The first node control module further comprises a fourth switch unit, a control end of the fourth switch unit being electrically connected with a third clock signal end, a first end of the fourth switch unit being electrically connected with an input end of the shift register, and a second end of the fourth switch unit being electrically connected with the first node. The shift register further comprises: A second output module, a control end of the second output module being electrically connected with a third node, a first end of the second output module being electrically connected with a first power voltage signal end, and a second end of the second output module being electrically connected with an output end of the shift register; A third node control module, the third node control module comprising a fifth switch unit and a sixth switch unit, a control end of the fifth switch unit being electrically connected with the first node, a first end of the fifth switch unit being electrically connected with the third clock signal end, and a second end of the fifth switch unit being electrically connected with the third node; a control end of the sixth switch unit being electrically connected with the third clock signal end, a first end of the sixth switch unit being electrically connected with a second power voltage signal end, and a second end of the sixth switch unit being electrically connected with the third node; A first coupling module, a first end of the first coupling module being electrically connected with the output end of the shift register, and a second end of the first coupling module being electrically connected with the control end of the first output module; A first storage module, a first end of the first storage module being electrically connected with the output end of the shift register, and a second end of the first storage module being electrically connected with the control end of the second output module; The high-level output stage comprises a first high-level output stage located before the low-level output stage. In the first high-level output stage, the third clock signal end and the input end of the shift register are provided with a conducting level, the first clock signal end is provided with a cut-off level, the fourth switch unit is turned on in response to the conducting level of the third clock signal end, the conducting level of the input end of the shift register is written into the first node, the first output module is turned on in response to the conducting level of the first node, the high level of the first clock signal end is transmitted to the output end of the shift register, the fifth switch unit is turned on in response to the conducting level of the first node, the conducting level of the third clock signal end is transmitted to the third node, and the second output module is turned on in response to the conducting level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register.

19. The driving method according to claim 18, wherein The high-level output stage further comprises at least one of a second high-level output stage, a third high-level output stage and a fourth high-level output stage after the low-level output stage; In the second high-level output stage, the third clock signal end is provided with a conducting level, the first clock signal end and the input end of the shift register are provided with a cut-off level, the fourth switch unit is turned on in response to the conducting level of the third clock signal end, the cut-off level of the input end of the shift register is written into the first node, the first output module is turned off in response to the cut-off level of the first node, the sixth switch unit is turned on in response to the conducting level of the third clock signal end, the conducting level of the second power voltage signal end is transmitted to the third node, and the second output module is turned on in response to the conducting level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register; In the third high-level output stage, the first clock signal end is provided with a conducting level, the third clock signal end and the input end of the shift register are provided with a cut-off level, the fourth switch unit is turned off in response to the cut-off level of the third clock signal end, the first coupling module maintains the cut-off level of the first node, the first output module is turned off in response to the cut-off level of the first node, the first storage module maintains the conducting level of the third node, and the second output module is turned on in response to the conducting level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register; In the fourth high level output stage, the third clock signal end is provided with a turn-on level, the first clock signal end and the input end of the shift register are provided with a turn-off level, the fourth switch unit is turned on in response to the turn-on level of the third clock signal end, the turn-off level of the input end of the shift register is written into the first node, the first output module is turned off in response to the turn-off level of the first node, the first storage module maintains the turn-on level of the third node, and the second output module is turned on in response to the turn-on level of the third node, and the high level of the first power voltage signal end is transmitted to the output end of the shift register.

20. A gate drive circuit, characterized by A shift register comprising a plurality of cascaded shift registers as claimed in any one of claims 1-15.

21. A display panel, comprising: A gate drive circuit comprising a gate drive circuit as claimed in claim 20.

Images