A method for implanting oxygen atoms in a surface layer of a single crystal silicon and a preparation method and a detection method of a silicon nanochannel

Abstract

This invention provides a method for implanting oxygen atoms into the surface of single-crystal silicon, as well as a method for fabricating and detecting silicon nanochannels. The method for implanting oxygen atoms includes: irradiating single-crystal silicon with an oxide layer on its surface with helium ions and directly writing a pattern; oxygen atoms in the oxide layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide. The method for fabricating silicon nanochannels includes the following steps: 1) obtaining a silicon oxide pattern after helium ion beam direct writing using the method for implanting oxygen atoms into the surface of single-crystal silicon; 2) performing chemical wet etching on the silicon oxide pattern. The English title of this invention is *silicon high-aspect nano-grooves via He*. + Annealing implantation, abbreviated as SHANGHAI process. Inspection method: Before chemical wet etching, a vertical cross-section of the silicon oxide pattern is etched using a gallium ion beam. This invention enables the fabrication of silicon nanochannels with linewidths of only 10 nm or less and aspect ratios of 10 or higher on the surface of single-crystal silicon.

Description

Technical Field

[0001] This invention relates to the fields of silicon-based semiconductor materials and integrated circuit manufacturing technology, and in particular to a method for implanting oxygen atoms into the surface of single-crystal silicon, as well as a method for preparing and detecting silicon nanochannels. Background Technology

[0002] The evolution of the structural design and manufacturing technology of field-effect transistors (FETs) in silicon-based semiconductor integrated circuits can be understood by examining their evolution in conjunction with the development of semiconductor manufacturing technology nodes. The purpose of this evolution is to increase the density of FETs and improve the computing performance of IC chips to meet the rapidly growing demands of human civilization for digital applications and data processing. The FET structure currently used in the market is a FinFET, belonging to the 7-nanometer semiconductor manufacturing technology node and the most advanced 5-nanometer semiconductor manufacturing technology node. From a structural design perspective, FinFETs belong to the second generation; the earliest generation was planar FETs. For a silicon-based semiconductor integrated circuit manufacturing plant, the evolution from planar FETs to FinFETs involves approximately 5 to 7 manufacturing technology nodes and takes 15 to 20 years.

[0003] Over the next decade, semiconductor manufacturing processes will first advance to the 3-nanometer manufacturing technology node, followed by the 2-nanometer node. The primary focus will be on developing a new field-effect transistor (FET) structure design currently under testing and expected to be mass-produced: gate-all-around (GAANSFETs). The next generation after GAANSFETs, anticipated to occur within the next ten to twenty years, has been identified by leading international semiconductor integrated circuit research institutions, including the Interuniversity Microelectronics Centre (IMEC). This design will be a complementary, vertically stacked field-effect transistor (CFET) structure. It is generally accepted that semiconductor integrated circuit manufacturing must progress to the 1.4-nanometer to 0.2-nanometer manufacturing technology nodes, a process involving five advanced manufacturing technology nodes. However, to achieve the current development and market launch of GAANSFETs, and even the future three-dimensional structure of CFET field-effect transistors, current state-of-the-art micro / nano manufacturing technologies face numerous physical, chemical, and engineering bottlenecks. The market urgently needs more advanced and smaller-sized process technologies.

[0004] Etching silicon channels smaller than 10 nanometers is currently a major technological hurdle. The most advanced silicon channel manufacturing processes currently employ advanced photolithography techniques, such as deep ultraviolet (DUV) or extreme ultraviolet (EUV), to first create a pattern on a photoresist film. This pattern then serves as an etching template for physical etching of the silicon substrate or epitaxially grown thin film, such as argon or gallium ion bombardment. Another option is chemical etching, such as the well-known Bosch process, which uses alternating SF6 and C4F8 ions to etch silicon and protect the channel sidewalls. However, for channel widths of 10 nanometers or smaller, both physical and chemical methods face a common size bottleneck due to diffusion limitations: when etched products are transported outwards through channels 10 nanometers wide or smaller, they cause redeposition on the channel sidewalls; similarly, the transport of reactants through channels 10 nanometers wide or smaller suffers from severe diffusion attenuation. Therefore, even though the most advanced extreme ultraviolet lithography technology can produce patterns with linewidths of 5 to 10 nanometers, it is still limited by gas collision and diffusion limits when etching silicon channels with high aspect ratios and widths of 10 nanometers or narrower, making it difficult to achieve the three-dimensional structure of silicon channels with sub-10 nanometer dimensions in the future.

[0005] Commercial helium-ion microscopes, which can combine helium, neon, and gallium-ion beams into a single system, are crucial equipment in micro / nanostructure imaging and nanofabrication. Gallium-ion beams are the heaviest, possess the strongest ion beam bombardment capability, and offer relatively coarse processing precision, with a size limit of 50nm, making them suitable for rapidly cutting and processing large structures. Helium-ion beams are the lightest, with a beam spot size as low as 0.5nm, offering high processing precision and enabling the fabrication of sub-10nm fine structures. Focused ion beam technology is a maskless direct-write processing technique. Gallium-ion focused ion beams have been widely used in semiconductor micro / nano fabrication, primarily for direct-write dicing. However, the processing precision limit of gallium-ion beams is only 50nm, which cannot meet the scale limitations required in future silicon-based semiconductor integrated circuit manufacturing, especially for sub-10nm ion beam processing.

[0006] To date, focused helium ion beam technology is still unable to perform fine machining of sub-10nm structures on silicon wafer surfaces. When the helium ion beam interacts with the sample, it primarily generates electron / hole pairs or electronic state excitation defects. Only with increased helium ion irradiation dose does it produce disordering or amorphization effects on crystalline materials. As a cutting tool, a high helium ion irradiation dose is necessary. However, because the sputter yield (the number of target atoms that each helium ion can sputter) of a helium ion beam is far less than 1, practically zero, using helium ion beams for cutting is a very challenging task for most materials used in semiconductor chips. Some literature reports successful applications of helium ion beams as a direct-write cutting tool for cutting gold and graphene. However, for silicon-based semiconductor materials, high-energy helium ion beams generate lattice dislocations far from the sample surface, resulting in limited damage to surface atoms and preventing surface atom sputtering. Literature also reports that when helium ion beams generate lattice dislocations in deep silicon crystals, the continuous accumulation of these dislocations leads to further bulging of the sample.

[0007] The main reason why focused helium ion beam technology cannot be used as a silicon wafer etching tool is the channel effect of helium ions in the silicon lattice. Due to the light mass of helium atoms, helium ions can more easily penetrate the gaps in the silicon lattice, forming a channel effect. Therefore, when a helium ion beam interacts with silicon, the shape of the interaction volume resembles a teardrop, and the defects at the top and bottom of the interaction volume are different. The top region of the interaction volume is a high-aspect-ratio cylinder unique to helium ions. Due to the helium ion beam channel effect, compared with other ion beams (such as gallium ions) or electron beams, the ion beam scattering effect and secondary electron scattering effect formed by ions dragging electrons are minimized at the top of the interaction volume, which is a unique advantage for imaging applications, but cannot achieve the effect of surface physical bombardment etching. At the bottom region of the interaction volume, it is a spherical volume. Due to the deceleration of helium ions, the ion beam channel effect disappears, and low-energy helium ions generate lattice dislocations in the silicon crystal. The accumulation of lattice dislocations promotes the formation of amorphous silicon. Increased helium ion irradiation dose leads to the accumulation of lattice defects, further resulting in swelling or bubble formation at the bottom of the interaction volume. Because silicon atom dislocations occur far from the surface, the ideal effect of atoms being bombarded from the surface and escaping directly cannot be achieved, thus making it unsuitable for silicon wafer dicing. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, this invention develops a method for implanting oxygen atoms into the surface layer of single-crystal silicon based on focused helium ion beam processing technology, and then combines this with a wet etching method with high selectivity to fabricate silicon nanochannels. This invention utilizes the helium ion annealing implantation method (He... +Annealing implantation is used to fabricate high aspect ratio silicon nano-grooves, also known as silicon high aspect ratio nano-grooves via He. + Annealing implantation, abbreviated as SHANGHAI process. This invention provides a method for fabricating silicon nanochannels with linewidths of only 10 nm or less and aspect ratios of 10 or higher on the surface of single-crystal silicon.

[0009] To achieve the above and other related objectives, the first aspect of the present invention provides a method for implanting oxygen atoms on the surface of a single-crystal silicon, comprising the following steps: subjecting a single-crystal silicon with an oxide layer deposited on its surface to helium ion irradiation and directly writing a pattern, wherein oxygen atoms in the oxide layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide.

[0010] Preferably, it further includes at least one of the following technical features:

[0011] a1) The oxide layer is an oxide insulating film;

[0012] a2) The thickness of the oxide layer is 2-50 nm, such as 2-6 nm, 6-16 nm, 16-24 nm or 24-50 nm;

[0013] a3) The oxide layer is selected from one of aluminum oxide, silicon oxide, hafnium oxide, and zinc oxide;

[0014] a4) The monocrystalline silicon with an oxide layer deposited on its surface is obtained by a method comprising the following steps: depositing an oxide layer on the surface of the monocrystalline silicon using a chemical vapor deposition method to form an oxide layer;

[0015] a5) The helium ion beam is derived from the helium ion source in a focused helium ion beam microscope;

[0016] Specifically, a single-crystal silicon substrate coated with an oxide layer is placed in a focused helium ion beam microscope under vacuum, the helium ion source is turned on, helium ion irradiation is performed, and the pattern is directly written. The initial effect of helium ion beam irradiation is to amorphize the single-crystal silicon, such as... Figure 2 As shown in position ⑤, when the helium ion beam introduces oxygen atoms from the oxide layer into the amorphous silicon, silicon oxide is formed, as shown in... Figure 2 As shown in position ⑥, this causes a reduction in oxygen atoms in the oxide layer (such as the alumina layer), while oxygen atoms in the oxide layer (such as the alumina layer) near the ion beam spot move to the helium ion beam interaction region.

[0017] a6) The accelerating voltage of the helium ion beam is 10–30 kV;

[0018] a7) The beam spot of the helium ion beam is 0.5–2 nm;

[0019] a8) The current of the helium ion beam is 1 to 3 pA, such as 1 to 1.2 pA or 1.2 to 3 pA;

[0020] a9) The total irradiation dose of the helium ion beam is 5–15 pC / μm, such as 5–6 pC / μm, 6–7 pC / μm, 7–8 pC / μm, 8–9 pC / μm, 9–10 pC / μm, 10–11 pC / μm, 11–12 pC / μm, 12–13 pC / μm, 13–14 pC / μm or 14–15 pC / μm;

[0021] The speed of direct writing of a10) is 0.037 to 0.5 micrometers per second, that is, when writing a single line of 1 micrometer length with a helium ion beam, the irradiation time of the helium ion beam is 2 to 27 seconds.

[0022] More preferably, it also includes at least one of the following technical features:

[0023] In feature a4), before plating oxide, the single crystal silicon is cleaned of organic residues and then etched to remove the natural oxide layer on the silicon surface.

[0024] Specifically, the single-crystal silicon can be cleaned in a piranha solution, wherein the piranha solution is prepared by mixing high-concentration sulfuric acid (H2SO4, 98%) with hydrogen peroxide solution (H2O2, 30%) in a ratio between 10:1 and 4:1. After cleaning in the piranha solution, the silicon surface is etched away by immersion in a 1-5% vol HF solution.

[0025] In feature a4), the chemical vapor deposition method is selected from one of atomic layer deposition, plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, high-pressure chemical vapor deposition, and magnetron sputtering.

[0026] In feature a4), the chemical vapor deposition method is atomic layer deposition.

[0027] In feature a4), the temperature for plating oxides is 200–250 °C.

[0028] A second aspect of the present invention provides a method for preparing silicon nanochannels, comprising the following steps:

[0029] 1) The silicon oxide pattern obtained by helium ion irradiation and direct writing was obtained by implanting oxygen atoms into the surface layer of single-crystal silicon as described above;

[0030] 2) Perform chemical wet etching on the silicon oxide pattern obtained in step 1) to obtain the silicon nanochannel, abbreviated as SHANG, after removing the silicon oxide pattern and oxide layer.

[0031] Preferably, in step 1), the number of times the helium ion beam is used for direct writing is ≥1.

[0032] Preferably, ultrasonic treatment is performed after etching to remove the deoxidized aluminum wires, such as... Figure 2 As shown in position ⑦.

[0033] Preferably, it further includes at least one of the following technical features:

[0034] b1) In the method of implanting oxygen atoms into the surface layer of monocrystalline silicon in step 1), the thickness of the oxide layer is 2 to 50 nm.

[0035] b2) In step 2), the silicon oxide pattern and oxide layer are etched using chemical wet etching. The etching solution is one of hydrofluoric acid (HF) aqueous solution, buffered oxide etchant (BOE), and buffered oxide etchant containing surfactant.

[0036] The concentration of the etching solution is 1–5% vol (volume percentage).

[0037] b3) Step 2) Wet etching is performed using an aqueous hydrofluoric acid solution;

[0038] b4) In step 2), the etching temperature is 20-25℃;

[0039] In step 2) of b5), the etching time is 6 to 30 minutes.

[0040] More preferably, in feature b2), the concentration of the etching solution is 1 to 5% vol (volume percentage).

[0041] The third aspect of the present invention provides a method for detecting silicon nanochannels. In step 2) of the above-mentioned method for preparing silicon nanochannels, before chemical wet etching, a vertical cross section with a silicon oxide pattern on the surface is etched with a depth of 1.5 to 3 μm, such as 1.5 to 2 μm or 2 to 3 μm.

[0042] Preferably, it further includes at least one of the following technical features:

[0043] c1) The gallium ion beam is derived from a gallium ion source in a focused helium ion beam microscope;

[0044] c2) The accelerating voltage of the gallium ion beam is 2-30 kV;

[0045] c3) The beam spot of the gallium ion beam is 5-50 nm;

[0046] c4) The beam current of the gallium ion beam is 100-300 pA;

[0047] c5) The irradiation dose of the gallium ion beam is 1.5–3 nC / μm. 2 For example, 1.5~2nC / μm 2 Or 2-3 nC / μm 2 .

[0048] The above technical solution has at least one of the following beneficial effects:

[0049] 1) This invention is mainly used to solve the problem that when the width of silicon channel is too small, especially 10 nanometers or less, the diffusion of the product is hindered, resulting in a significant increase in the deposition effect on the channel sidewall, or the vertical etching effect is significantly weakened due to the hindered diffusion of the reactants. As a result, the current size limit of silicon channel etching cannot reach a channel width of sub-10 nanometers or less, and the channel aspect ratio of 10 or more can not be achieved. The silicon nanochannel preparation method of this invention can obtain silicon nanochannels with a width of 10 nanometers or less and a channel aspect ratio of 10 or more.

[0050] 2) This invention relates to a silicon-based semiconductor chip manufacturing process, a silicon etching process, a method for manufacturing etched channel structures without photoresist, a method for direct writing of patterns by irradiating silicon with a helium ion beam to implant oxygen atoms, and a manufacturing process for preparing silicon nanochannels by wet etching of silicon oxide with hydrofluoric acid. This invention is used to etch silicon nanochannels, the channel width of which can reach 10 nanometers or less, and the channel aspect ratio can reach 10 or more, and can be applied to the manufacture of future miniaturized three-dimensional field-effect transistors. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the method for fabricating silicon nanochannels according to the present invention: high aspect ratio silicon nanochannels are fabricated using the helium ion annealing implantation method, referred to as the SHANG-HAI process.

[0052] Figure 2 This is a schematic diagram of the method for implanting oxygen atoms into single-crystal silicon according to the present invention: direct-write helium ion annealing implantation method, the main function of which is to implant oxygen atoms into single-crystal silicon, abbreviated as HAI effect.

[0053] Figure 3 This is a schematic diagram of the helium ion imaging method.

[0054] Figure 4 Silicon nanochannel arrays etched for alumina layers of different thicknesses: (a, b) 2nm Al2O3; (c, d) 6nm Al2O3; (e, f) 16nm Al2O3; (g, h) 24nm Al2O3; (i, k) 50nm Al2O3.

[0055] Figure 5 This is a graph showing the relationship between the width and depth of silicon nanochannels and the thickness of the alumina layer.

[0056] Figure 6 Silicon nanochannels etched by helium ion beams with different irradiation doses: (a) 5 pC / μm; (b) 6 pC / μm; (c) 7 pC / μm; (d) 8 pC / μm; (e) 9 pC / μm; (f) 10 pC / μm.

[0057] Figure 7 This is a graph showing the relationship between the width and depth of silicon nanochannels and the irradiation dose from a helium ion beam.

[0058] Figure 8 The relationship between the secondary irradiation dose and the interaction volume of the helium ion beam is shown in the figure: (1) The red area was not irradiated with helium ions before etching with hydrofluoric acid solution; (2) The yellow area was irradiated with helium ions with an irradiation dose of 2.2 pC / μm before etching with hydrofluoric acid solution; (3) The blue area was irradiated with helium ions with an irradiation dose of 4.4 pC / μm before etching with hydrofluoric acid solution. Detailed Implementation

[0059] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0060] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of the invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0061] This invention combines a focused helium ion beam oxygen atom implantation method with chemical etching to form an innovative sub-10 nm silicon etching process. In silicon-based integrated circuits (ICs), the development and integration of three-dimensional structures for future novel field-effect transistors requires a novel, controllable silicon nanochannel etching process capable of producing widths below 10 nm with aspect ratios meeting the requirements of future device three-dimensional structures. This invention utilizes helium ion beam direct writing to generate localized oxygen atom-doped patterns with linewidths of 10 nm or less. Combined with wet etching, this produces silicon nanochannels with widths of 10 nm or narrower, achieving an aspect ratio (channel depth divided by channel width) of 10 or higher. This novel process can be applied to fabricate high-density, sub-10 nm silicon-based nanowire or nanosheet field-effect transistor three-dimensional structures. The focused helium ion beam (FHIB) or helium ion microscopy (HIM) technology was developed by ALIS in 2005. After ZEISS acquired ALIS, it launched the first commercially available focused helium ion beam microscope in 2007. Helium ion microscopy utilizes the electron beam focusing method of scanning electron microscopy, with a helium ion beam spot of only 0.5 nm, achieving a limiting imaging resolution of 0.5 nm. + The damage to the sample is much less than that of the commonly used gallium ion (Ga+) beam, and it has many advantages such as: (1) The interaction between helium ions and the sample surface produces a very small interaction volume, which only excites a rich secondary electron signal on the sample surface, and can obtain the morphological feature image of the sample's polar surface. (2) The helium atomic mass is small enough to quickly penetrate the sample surface, effectively reducing the proximity effect, which is particularly suitable for sub-10nm etching or metal deposition processing. (3) The helium ion beam is emitted by a single atom assisted by a needle tip, and the convergence angle is only about 0.3 milliradians, which is about 5 times smaller than the convergence angle of a scanning electron microscope, resulting in small beam divergence and a large depth of focus. (4) The helium ion microscope can be used in conjunction with Ga ions for three-dimensional reconstruction imaging, which is one of the most advanced three-dimensional morphological imaging technologies at present. (5) By controlling the FHIB beam current (usually between 0.1 and 35 pA) and controlling its irradiation linewidth to ≤10 nm, it can be used for irradiation direct writing modification of specific photoresists, or amorphization direct writing processing of specific materials, or cutting and etching direct writing processing of specific materials. It is an indispensable precision processing technology for 10-nanometer structures.

[0062] This invention provides a method for fabricating silicon nanochannels, combining focused helium ion beam irradiation and etching (such as chemical wet etching), which can be used to fabricate silicon nanochannels ≤10 nm wide and with a high aspect ratio ≥10. This invention uses focused helium ion beam irradiation, a novel process that uses physical collision dragging to implant oxygen atoms from a surface thin film into the underlying silicon wafer. Combined with wet etching of silicon oxide using absolute selectivity, this method fabricates silicon nanochannels with a width of only 10 nm or less and an aspect ratio of 10 or higher on a single-crystal silicon surface. Sub-10 nm wide, high aspect ratio silicon nanochannels represent a breakthrough in miniaturizing the three-dimensional structure of silicon nanochannels. These are products fabricated on silicon wafers using the processing technology described in this invention, and are named silicon high aspect nano-grooves, abbreviated as SHANG. Under focused helium ion beam irradiation, He... + Oxygen atoms from an oxide layer (such as an aluminum oxide layer) on the silicon surface are dragged down and implanted into the silicon crystal, controlled by He. + The irradiation dose is adjusted to produce oxygen implantation thin-film regions of varying depths and linewidths; simultaneously, in He... + Under the irradiation annealing effect, a silicon oxide sheet is formed in this region; the method of this invention is a helium ion annealing implantation method, named He in English: He + Annealing implantation, abbreviated as HAI, is a process for fabricating high aspect ratio silicon nanochannels using helium ion annealing implantation. The width and depth of the SHANG (shallow-HAI) can be controlled by adjusting key parameters in the HAI method: oxide layer thickness, helium ion beam accelerating voltage, beam spot size, beam current, helium ion beam irradiation dose, and irradiation time. The beam current and irradiation dose affect the irradiation time; for the same dose and the same pattern, a higher beam current requires a shorter time, while a higher irradiation dose requires a longer time. The SHANG-HAI process is expected to be used to develop nano-cutting applications of focused helium ion beams on silicon-based materials, and to develop and manufacture novel sub-10 nm field-effect transistor structures in silicon-based semiconductor integrated circuits.

[0063] This invention utilizes a helium ion annealing implantation method to fabricate high aspect ratio silicon nanochannels, namely the SHANG-HAI process described in this invention, which simplifies the fabrication process as follows: Figure 1Process diagram. The silicon wafer used in this invention has a (100) monocrystalline silicon crystal plane and a resistivity of 10-20 Ω·cm. Before helium ion implantation, a high-concentration concentrated sulfuric acid (H2SO4, 98%) plus hydrogen peroxide solution (H2O2, 30%) in a 10:1 ratio, commonly known as piranha solution, can be used to clean the particles and organic contaminants on the silicon wafer. Then, a 5% vol hydrofluoric acid (HF) solution is used to etch the native oxide layer on the silicon surface of the wafer. The above organic cleaning and removal of the native oxide layer are common methods used by semiconductor chip manufacturers. Other chemical agents or ratios with equivalent functions can also be used instead. In order to implant oxygen atoms into the silicon substrate, an oxide layer (such as an aluminum oxide layer) with a thickness of 2 nm to 50 nm is grown on the silicon surface using an atomic layer deposition (ALD) system. This oxide layer can be replaced by aluminum oxide, silicon oxide, hafnium oxide, zinc oxide, or other oxide insulating films. The next step is to use helium ion annealing implantation, i.e., HAI treatment, such as... Figure 1 As shown in Figure a, in a helium ion microscope, a focused helium ion beam is used for irradiation. The accelerating voltage of the helium ion beam is 10–30 kV, the beam spot size is 0.5–2 nm, the irradiation dose is 5–15 pC / μm, and the direct-write pattern is a linear array with a length of 3 μm and a width of 10 nm. Figure 1 As shown in Figure a. Under helium ion irradiation, in addition to silicon amorphization, oxygen atoms are implanted into silicon due to helium ion beam bombardment; simultaneously, under helium ion beam annealing, a silicon oxide thin-film structure is formed, such as... Figure 1 As shown in b, the silicon oxide flakes displayed in the figure are vertical, which is related to the angle of helium ion beam irradiation. The morphology of the silicon oxide flakes is also the morphology of the silicon nanochannels obtained in the end. For the uppermost oxide layer (such as the aluminum oxide layer), since oxygen atoms are carried away by the helium ion beam and implanted into the silicon, after HAI treatment, the oxygen atoms in the aluminum oxide layer are depleted, ultimately forming "deoxidized" aluminum wires, such as... Figure 1 As shown in b. In the process flow, to characterize the aspect ratio and sidewall roughness of the silicon nanochannels, a vertical cross-section is etched using a gallium ion beam, as shown in Figure b. Figure 1 As shown in b; the voltage during gallium ion beam etching is 30kV, and the beam current is 300pA. After etching a vertical cross-section with the gallium ion beam, the sample is finally immersed in an etching solution for etching, such as a 1% vol HF solution. The etching time can be 6–30 minutes. Due to the corrosion of the silicon oxide thin film by HF, silicon nanochannels are formed, with a channel width of 10nm and a depth of 100nm. Figure 1 As shown in c.

[0064] The SHANG-HAI process described in this invention mainly consists of two steps: (1) as follows Figure 1In sections a to b, a buffer layer is introduced between the helium ion beam and the surface of the single-crystal silicon sample. This buffer layer is an oxide layer with a thickness of nanometers, such as aluminum oxide, silicon oxide, hafnium oxide, or other commonly used oxide insulating thin film oxide layers. The helium ion beam passes through the oxide layer to reach the surface of the single-crystal silicon, causing part of the single-crystal silicon to become amorphous, and causing some oxygen atoms in the oxide layer to be implanted into the surface of the single-crystal silicon, thereby forming a silicon oxide sheet structure. (2) For example Figure 1 In sections b to c, the oxide is etched using hydrofluoric acid solution. Due to its excellent absolute etching selectivity (i.e., hydrofluoric acid can only etch silicon oxide, not silicon), high aspect ratio silicon nanochannels can be etched on the single-crystal silicon surface. In the helium ion beam irradiation area, oxygen atoms in the oxide layer are carried into the single-crystal silicon by the helium ion beam, i.e., oxygen atoms are implanted into the silicon. Therefore, the original oxide layer forms "deoxidized" aluminum. When the aluminum oxide is etched by 1% vol HF solution, incompletely etched "deoxidized" aluminum lines will remain. The "deoxidized" aluminum lines are a post-processing defect and can be completely removed by ultrasonic treatment.

[0065] The helium ion annealing implantation method, also known as HAI treatment, described in this invention has the following principles and features: Figure 2 As shown in Figure ①, the helium ion beam used has an accelerating voltage of 30 kV and a beam spot size of 0.5 nm. The sample structure is a single-crystal silicon with an aluminum oxide film deposited on it. The thickness of the aluminum oxide film is between 2 and 50 nm, as shown in Figure ②. The aluminum oxide film is deposited using an oxide atomic layer deposition system at a temperature of 250 °C. The aluminum oxide film is deposited on a single-crystal silicon substrate, as shown in Figure ③. Its orientation can be (100), (110), (111), or others. In this case, the substrate used is a (100) oriented single-crystal silicon. A focused helium ion beam is used to introduce sufficient oxygen atoms from the aluminum oxide layer into the silicon substrate. The interaction volume range between the helium ion beam and the single-crystal silicon is shown in Figure ④. The interaction depth is about 500 nm, resembling a teardrop shape. Under the HAI process, the initial interactive volume gradually increases, and the defects in silicon also increase. At the bottom of the interactive volume, i.e., the spherical volume of the lower half of the teardrop, the energy of helium ions weakens, causing lattice dislocations in the silicon crystal. The accumulation of lattice dislocations promotes the formation of amorphous silicon, as shown in Figure ⑤. At the top of the interactive volume, i.e., the high aspect ratio cylinder of the upper half of the teardrop, the energy of helium ions is higher, dragging oxygen atoms from the alumina layer to the surface of silicon, forming silicon oxide, as shown in Figure ⑥. Because oxygen atoms are introduced to the surface of silicon, and at the same time, oxygen atoms in the alumina layer near the ion beam spot move to the helium ion beam interaction region, the oxygen atoms in the alumina layer under and near the ion beam spot decrease, resulting in aluminum with low oxygen content, as shown in Figure ⑦.

[0066] After HAI treatment, a sang structure can be fabricated by treating the sample with hydrofluoric acid. The sang structure is imaged and its dimensions measured using FHIB. To observe the depth of the sang structure, the sample stage is intentionally tilted at 54°. Figure 3 As shown by angle θ. In a helium ion microscope, the angle between the helium ion beam and the gallium ion beam is 54°. In order to make the gallium ion beam cut perpendicularly to the sample surface, the sample stage needs to be tilted by 54°. At this time, the angle between the helium ion beam and the sample surface is 36°. When using the helium ion beam to measure the depth of the SHANG structure, the software can automatically convert the angle information to obtain the true depth of the SHANG.

[0067] Example 1

[0068] A method for fabricating silicon nanochannels by controlling the thickness of an oxide layer includes the following steps:

[0069] 1) The (100) single crystal silicon wafer was successively placed in piranha solution and 5% vol HF solution for cleaning and etching to remove the natural oxide layer on the silicon surface;

[0070] 2) Place the single-crystal silicon wafer obtained in step 1) into an oxide atomic layer deposition system to deposit an aluminum oxide layer, thereby obtaining a single-crystal silicon wafer with an aluminum oxide layer deposited on its surface. The deposition temperature is 250°C.

[0071] The thickness of the oxide layer (alumina layer) is 2nm, 6nm, 16nm, 24nm, and 50nm;

[0072] 3) Place the single-crystal silicon wafer obtained in step 2) into a focused helium ion beam microscope to evacuate the vacuum, turn on the helium ion source, perform helium ion irradiation and write the pattern directly. The oxygen atoms in the alumina layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide.

[0073] The accelerating voltage of the helium ion beam is 30 kV, the beam spot is 0.5 nm, the beam current is 1.2 pA, and the irradiation dose is 5 pC / μm.

[0074] 4) Turn on the gallium ion source and use the gallium ion beam to etch a vertical cross section with a depth of 2μm and a silicon oxide pattern on the surface;

[0075] The gallium ion beam accelerating voltage was 30 kV, the beam spot size was 5 nm, the beam current was 300 pA, and the irradiation dose was 2 nC / μm. 2 ;

[0076] 5) Take out the sample and etch it in a 1% vol hydrofluoric acid solution at a temperature of 25°C for 6 minutes. After etching away the silicon oxide pattern and oxide layer, the silicon nanochannel is obtained.

[0077] A series of six lines, each 3 μm long and 10 nm wide, were directly written onto the surface of five alumina thin film samples with different thicknesses (2 nm, 6 nm, 16 nm, 24 nm, and 50 nm) using a helium ion beam. The helium ion beam irradiation dose was 5 pC / μm. A cross-section was then cut using a gallium ion beam, followed by immersion in a 1% vol HF solution to etch a silicon nanochannel array.

[0078] Figure 4 Figure a shows the silicon nanochannel array etched when the aluminum oxide thickness is 2nm. Figure b is a magnified view of figure a, with a channel width of 8nm and a depth of 105nm.

[0079] Figure 4 Figure c shows the silicon nanochannel array etched when the alumina thickness is 6nm. Figure d is a magnified view of c, with a channel width of 10nm and a depth of 102nm.

[0080] Figure 4 e represents the silicon nanochannel array etched when the alumina thickness is 16 nm, and f is a magnified view of e, with a channel width of 24 nm and a depth of 108 nm.

[0081] Figure 4 g shows the silicon nanochannel array etched when the aluminum oxide thickness is 24 nm. h is a magnified view of g, with a channel width of 29 nm and a depth of 126 nm.

[0082] Figure 4 Image i shows the silicon nanochannel array etched when the aluminum oxide thickness is 50 nm. Image k is a magnified view of image i, with a channel width of 24 nm and a depth of 100 nm.

[0083] The SHANG-HAI process, which is the method for fabricating silicon nanochannels according to the present invention, produces SHANG structures, such as... Figure 4 As shown, the thickness of the alumina film is one of the parameters affecting the SHANG structure. The thickness of the alumina film affects the width and depth of the final etched silicon nanochannels. When the alumina thickness is 2 nm, the number of oxygen atoms introduced into the single-crystal silicon surface by helium ion beam direct writing is relatively small, resulting in silicon nanopores with high aspect ratios after etching with hydrofluoric acid solution. As the alumina film thickness increases, more oxygen atoms are introduced into the silicon surface during helium ion annealing implantation, forming more silicon oxide, and resulting in a wider SHANG structure after hydrofluoric acid etching. When the alumina thickness increases to 50 nm, although it can provide enough oxygen atoms for helium ion implantation, due to the limited energy of the helium ion beam, not all oxygen atoms in the alumina layer can be brought into the silicon surface. After etching with hydrofluoric acid solution, the width and aspect ratio of the silicon nanochannels decrease. Figure 4 As shown: Silicon nanochannel arrays etched from alumina layers of different thicknesses.

[0084] The aspect ratio of the SHANG structure generated by this invention can be used to etch silicon nanochannel arrays with different linewidths and aspect ratios by changing the thickness of the alumina layer. The irradiation dose of the helium ion beam has a significant impact on the width of the silicon nanochannels. This invention etches a channel array with a width of 10 nm by controlling the helium ion beam irradiation dose. The accelerating voltage during helium ion beam implantation is 30 kV, the beam spot is 0.5 nm, the beam current is 1.2 pA, and the irradiation dose is 5 pC / μm.

[0085] The thickness of the alumina film affects the performance of the SHANG structure, as summarized below. Figure 5 . Figure 5 The figure shows the relationship between the width and depth of silicon nanochannels and the thickness of the alumina layer:

[0086] When the alumina thickness is 2nm, the etched channel width can reach 8nm, the depth is 105nm, and the aspect ratio is 13:1;

[0087] When the alumina thickness is 6nm, the etched channel width can reach 10nm, the depth is 102nm, and the aspect ratio is 10:1.

[0088] When the alumina thickness is 16nm, the etched channel width is 24nm, the depth is 108nm, and the aspect ratio is 4.5:1.

[0089] When the alumina thickness is 24nm, the etched channel width is 29nm, the depth is 126nm, and the aspect ratio is 4.3:1.

[0090] When the alumina thickness is 50nm, the etched channel width is 24nm, the depth is 100nm, and the aspect ratio is 4.2:1.

[0091] As the thickness of the alumina layer increases, the width of the silicon nanochannels first increases and then decreases, while the aspect ratio decreases.

[0092] Example 2

[0093] A method for fabricating silicon nanochannels by controlling the dosage of helium ions includes the following steps:

[0094] 1) The (100) single crystal silicon wafer was successively placed in piranha solution and 5% vol HF solution for cleaning and etching to remove the natural oxide layer on the silicon surface;

[0095] 2) Place the single-crystal silicon wafer obtained in step 1) into an oxide atomic layer deposition system to deposit an aluminum oxide layer, thereby obtaining a single-crystal silicon wafer with an aluminum oxide layer deposited on its surface. The deposition temperature is 250°C.

[0096] The thickness of the oxide layer (alumina layer) is 6 nm;

[0097] 3) Place the single-crystal silicon wafer obtained in step 2) into a focused helium ion beam microscope to evacuate the vacuum, turn on the helium ion source, perform helium ion irradiation and write the pattern directly. The oxygen atoms in the alumina layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide.

[0098] The accelerating voltage of the helium ion beam is 30 kV, the beam spot is 0.5 nm, the beam current is 1.2 pA, and the irradiation dose is 5 pC / μm, 6 pC / μm, 7 pC / μm, 8 pC / μm, 9 pC / μm, and 10 pC / μm.

[0099] 4) Turn on the gallium ion source and use the gallium ion beam to etch a vertical cross section with a depth of 2μm and a silicon oxide pattern on the surface;

[0100] The gallium ion beam accelerating voltage was 30 kV, the beam spot size was 5 nm, the beam current was 300 pA, and the irradiation dose was 2 nC / μm. 2 ;

[0101] 5) Take out the sample and etch it in a 1% vol hydrofluoric acid solution at a temperature of 25°C for 6 minutes. After etching away the silicon oxide pattern and oxide layer, the silicon nanochannel is obtained.

[0102] Figure 6 The image shows silicon nanochannels etched with different helium ion irradiation doses of 5–10 pC / μm when the alumina thickness is 6 nm. At a helium ion irradiation dose of 5 pC / μm, the bottom of the silicon nanochannel is a vertical channel with a width of 10 nm and a depth of 102 nm. At an irradiation dose of 6 pC / μm, the bottom of the silicon nanochannel begins to exhibit a teardrop-shaped structure. With increasing irradiation dose, the volume of the teardrop-shaped structure at the bottom of the channel increases.

[0103] Helium ion irradiation dose is another important parameter affecting the structure of SHANG, such as Figure 6 As shown, the helium ion irradiation dose affects the width, depth, and interactive volume shape of the final etched silicon nanochannels. This invention, by changing the helium ion beam irradiation dose, can increase or decrease the amount of oxygen atoms introduced into the silicon substrate by the helium ion beam, thereby etching silicon nanochannels with different linewidths and shapes. The helium ion beam irradiation dose is set to 5–10 pC / μm, and can also be increased to 100 pC / μm or higher to etch wider silicon nanochannels.

[0104] The effect of helium ion irradiation dose on the SHANG structure is summarized as follows: Figure 7 . Figure 7 The figure shows the relationship between the width and depth of the silicon nanochannels and the helium ion beam irradiation dose when the alumina thickness is 6 nm:

[0105] When the irradiation dose is 5 pC / μm, the channel width is 10 nm, the depth is 102 nm, and the width of the interactive volume "teardrop" is 10 nm.

[0106] When the irradiation dose is 6 pC / μm, the channel width is 16 nm, the depth is 200 nm, and the width of the interactive volume "teardrop" is 55 nm.

[0107] When the irradiation dose reaches 7 pC / μm, the channel width is 22 nm, the depth is 218 nm, and the width of the interactive volume "teardrop" is 74 nm.

[0108] When the irradiation dose reaches 8 pC / μm, the channel width is 25 nm, the depth is 221 nm, and the width of the interactive volume "teardrop" is 97 nm.

[0109] When the irradiation dose reaches 9 pC / μm, the channel width is 30 nm, the depth is 246 nm, and the width of the interactive volume "teardrop" is 114 nm.

[0110] When the irradiation dose reaches 10 pC / μm, the channel width is 33 nm, the depth is 250 nm, and the width of the interactive volume "teardrop" is 120 nm.

[0111] Example 3

[0112] A method for fabricating a silicon nanochannel with a width of 10 nm and an aspect ratio of 10:1 includes the following steps:

[0113] 1) The (100) single crystal silicon wafer was successively placed in piranha solution and 5% vol HF solution for cleaning and etching to remove the natural oxide layer on the silicon surface;

[0114] 2) Place the single-crystal silicon wafer obtained in step 1) into an oxide atomic layer deposition system to deposit an aluminum oxide layer, thereby obtaining a single-crystal silicon wafer with an aluminum oxide layer deposited on its surface. The deposition temperature is 250°C.

[0115] The thickness of the oxide layer (alumina layer) is 2–50 nm;

[0116] 3) Place the single-crystal silicon wafer obtained in step 2) into a focused helium ion beam microscope to evacuate the vacuum, turn on the helium ion source, perform helium ion irradiation and write the pattern directly. The oxygen atoms in the alumina layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide.

[0117] The accelerating voltage of the helium ion beam is 30 kV, the beam spot is 0.5 nm, the beam current is 1–3 pA, and the irradiation dose is 5–10 pC / μm.

[0118] 4) Turn on the gallium ion source and use the gallium ion beam to etch a vertical cross section with a depth of 2μm and a silicon oxide pattern on the surface;

[0119] The gallium ion beam uses an accelerating voltage of 30 kV, a beam spot size of 5 nm, a beam current of 100–300 pA, and an irradiation dose of 1.5–3 nC / μm. 2 ;

[0120] 5) Take out the sample and etch it in a 1% vol hydrofluoric acid solution at a temperature of 25℃ for 6 minutes.

[0121] The SHANGHAI process for etching silicon nanochannels with a width of 10 nm and an aspect ratio of 10:1 on single-crystal silicon samples involves introducing an oxide layer as a buffer layer on the surface of the single-crystal silicon sample, followed by a combination of micro / nano fabrication and chemical wet etching. Micro / nano fabrication utilizes helium and gallium ion beams from a focused helium-ion microscope. Compared to traditional focused ion beams, helium atoms are lighter, allowing for higher processing precision and enabling sub-10 nm micro / nano fabrication. Gallium atoms are heavier, and gallium ion beams are primarily used for processing large-scale patterns. Chemical wet etching involves immersing the sample in a 1% vol hydrofluoric acid solution. Utilizing the etching properties of hydrofluoric acid, high aspect ratio silicon nanochannels are etched onto the single-crystal silicon sample.

[0122] In this embodiment, the oxide layer is a nanometer-thick oxide layer, with a thickness of 2–50 nm. The oxide layer can be selected from aluminum oxide, silicon oxide, hafnium oxide, zinc oxide, or other commonly used oxide insulating films. An oxide atomic layer deposition system is used for film deposition, with a chamber temperature of 250°C. The atomic layer deposition system deposits materials layer by layer onto the surface of a single-crystal silicon in the form of single-atom films. A continuous, self-limiting reaction occurs by alternately introducing different precursors and the single-crystal silicon surface. During atomic layer deposition, the chemical reaction of the new atomic layer is directly related to the previous layer, ensuring that only one atomic layer is deposited per reaction, guaranteeing a uniform film with precise and controllable thickness.

[0123] In this embodiment, the helium ion beam is implanted into the sample via direct-write annealing to amorphize part of the single-crystal silicon. The accelerating voltage is 30 kV, the beam spot size is 0.5 nm, the beam current is 1.2 pA, and the irradiation dose is 5–15 pC / μm. The gallium ion beam has an accelerating voltage of 30 kV, a beam spot size of 5 nm, a beam current of 300 pA, and an irradiation dose of 2 nC / μm. 2 The hydrofluoric acid solution concentration for chemical wet etching was 1% vol, the temperature was 25℃, and the etching time was 6 minutes.

[0124] In a specific embodiment, the oxide layer (alumina layer) is 6 nm thick, and the helium ion beam irradiation dose is 5 pC / μm. The alumina layer provides oxygen atoms for helium ion implantation into the sample. The oxygen atoms combine with amorphous silicon to form silicon oxide, which is then etched using hydrofluoric acid solution to obtain a silicon nanochannel with a width of 10 nm and an aspect ratio of 10:1. The SHANG structure is shown in the attached figure. Figure 4 As shown in c.

[0125] Example 4

[0126] A method for preparing high aspect ratio silicon nanopores includes the following steps:

[0127] 1) The (100) single crystal silicon wafer was successively placed in piranha solution and 5% vol HF solution for cleaning and etching to remove the natural oxide layer on the silicon surface;

[0128] 2) Place the single-crystal silicon wafer obtained in step 1) into an oxide atomic layer deposition system to deposit an aluminum oxide layer, thereby obtaining a single-crystal silicon wafer with an aluminum oxide layer deposited on its surface. The deposition temperature is 250°C.

[0129] The thickness of the oxide layer (alumina layer) is 2 nm;

[0130] 3) Place the single-crystal silicon wafer obtained in step 2) into a focused helium ion beam microscope to evacuate the vacuum, turn on the helium ion source, perform helium ion irradiation and write the pattern directly. The oxygen atoms in the alumina layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide.

[0131] The accelerating voltage of the helium ion beam is 30 kV, the beam spot is 0.5 nm, the beam current is 1.2 pA, and the irradiation dose is 5 pC / μm.

[0132] 4) Turn on the gallium ion source and use the gallium ion beam to etch a vertical cross section with a depth of 2μm and a silicon oxide pattern on the surface;

[0133] The gallium ion beam accelerating voltage was 30 kV, the beam spot size was 5 nm, the beam current was 300 pA, and the irradiation dose was 2 nC / μm. 2 , ;

[0134] 5) Take out the sample and etch it in a 1% vol hydrofluoric acid solution at a temperature of 25°C for 6 minutes. After etching away the silicon oxide pattern and oxide layer, the silicon nanochannel is obtained.

[0135] As shown in Example 1, the thickness of the oxide layer affects the width and aspect ratio of the final etched silicon nanochannels. In this example, the thickness of the alumina layer is 2 nm, and the helium ion beam irradiation dose is 5 pC / μm. The alumina layer provides oxygen atoms for helium ion implantation into the sample; the oxygen atoms combine with amorphous silicon to transform into silicon oxide. When the alumina layer is thin, the number of oxygen atoms brought into the single-crystal silicon surface by the helium ion beam is small. High aspect ratio silicon nanopores are etched using hydrofluoric acid solution, as shown in the SHANG structure. Figure 4 As shown in a.

[0136] Example 5

[0137] A method for preparing silicon nanochannels by secondary implantation of oxygen atoms includes the following steps:

[0138] 1) The (100) single crystal silicon wafer was successively placed in piranha solution and 5% vol HF solution for cleaning and etching to remove the natural oxide layer on the silicon surface;

[0139] 2) Place the single-crystal silicon wafer obtained in step 1) into an oxide atomic layer deposition system to deposit an aluminum oxide layer, thereby obtaining a single-crystal silicon wafer with an aluminum oxide layer deposited on its surface. The deposition temperature is 250°C.

[0140] The thickness of the oxide layer (alumina layer) is 24 nm;

[0141] 3) Place the single-crystal silicon wafer obtained in step 2) into a focused helium ion beam microscope to evacuate the vacuum, turn on the helium ion source, perform helium ion irradiation and write the pattern directly. The oxygen atoms in the alumina layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide.

[0142] The accelerating voltage of the helium ion beam is 30 kV, the beam spot is 0.5 nm, the beam current is 1.2 pA, and the irradiation dose is 10 pC / μm.

[0143] 4) Turn on the gallium ion source and use the gallium ion beam to etch a vertical cross section with a depth of 2μm and a silicon oxide pattern on the surface;

[0144] The gallium ion beam accelerating voltage was 30 kV, the beam spot size was 5 nm, the beam current was 300 pA, and the irradiation dose was 2 nC / μm. 2 ;

[0145] 5) Secondary irradiation with a helium ion beam is used to introduce oxygen atoms a second time;

[0146] The accelerating voltage of the helium ion beam is 30 kV, the beam spot is 0.5 nm, the beam current is 1.2 pA, and the secondary irradiation doses are 0 pC / μm, 2.2 pC / μm, and 4.4 pC / μm.

[0147] 6) Take out the sample and etch it in a 1% vol hydrofluoric acid solution at a temperature of 25°C for 6 minutes. After etching away the silicon oxide pattern and oxide layer, the silicon nanochannel is obtained.

[0148] Using a second helium ion beam irradiation, with surface-adsorbed oxygen molecules as the oxygen source, to generate secondary oxygen atom implantation is a processing method that alters the channel morphology. This also affects the width, depth, and interaction volume of silicon nanochannels, such as... Figure 8 As shown. Figure 8The alumina thickness on the sample surface is 24 nm. Six 10 nm wide lines were directly written on the sample surface using a helium ion beam at a helium ion irradiation dose of 10 pC / μm. A cross-section was then cut using a gallium ion beam. The six lines were divided into three groups (①②③), and each group underwent secondary helium ion irradiation to introduce oxygen atoms a second time. The secondary irradiation method involved using helium ion beams with different irradiation doses to... Figure 8 Yellow and blue areas were scanned. The secondary helium ion irradiation dose for group ① was 0 pC / μm, for group ② it was 2.2 pC / μm, and for group ③ it was 4.4 pC / μm. The samples were then immersed in 1% volHF solution for 6 minutes.

[0149] When the secondary helium ion irradiation dose is 0 (position ①), the etched silicon nanochannel has a width of 25 nm, a depth of 233 nm, and an interactive volume "teardrop" width of 86 nm.

[0150] When the secondary helium ion irradiation dose is 2.2 pC / μm (position ②), the etched silicon nanochannel has a width of 33 nm, a depth of 305 nm, and an interactive volume "teardrop" width of 157 nm.

[0151] When the secondary helium ion irradiation dose is 4.4 pC / μm (position ③), the width of the silicon nanochannel is 38 nm, the depth is 339 nm, and the width of the interactive volume "teardrop" is 248 nm.

[0152] After HAI treatment, the location of the helium ion writing line forms a silicon nanochannel, and the oxygen atoms in the alumina film are depleted to form a "deoxygenated aluminum line," such as... Figure 8 As shown in position ④ in the middle.

[0153] A secondary helium ion irradiation method was used to implant oxygen atoms. Before etching with a 1% vol HF solution, secondary helium ion irradiation was performed, introducing more oxygen atoms into the amorphous silicon. The amorphous silicon was then oxidized into silicon oxide, and after immersion in the 1% vol HF solution, a larger interactive volume was etched out.

[0154] In summary, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0155] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing silicon nanochannels, characterized in that, Includes the following steps: 1) Implanting oxygen atoms into the surface of a single-crystal silicon, comprising the following steps: irradiating a single-crystal silicon with an oxide layer on its surface with a helium ion beam and directly writing a pattern; oxygen atoms in the oxide layer are attracted and implanted into the surface of the single-crystal silicon by the kinetic energy transfer of helium ions to form silicon oxide; obtaining the silicon oxide pattern by helium ion irradiation and direct writing using the method of implanting oxygen atoms into the surface of the single-crystal silicon; the thickness of the oxide layer is 2~50 nm; the total irradiation dose of the helium ion beam is 5~15 pC / μm; 2) Perform chemical wet etching on the silicon oxide pattern obtained in step 1) to obtain the silicon nanochannel after removing the silicon oxide pattern and oxide layer.

2. The method for preparing silicon nanochannels as described in claim 1, characterized in that, Step 1) also includes at least one of the following technical features: a1) The oxide layer is an oxide insulating film; a2) The oxide layer is selected from one of aluminum oxide, silicon oxide, hafnium oxide, and zinc oxide; a3) The single-crystal silicon with an oxide layer deposited on its surface is obtained by a method comprising the following steps: depositing an oxide layer on the surface of the single-crystal silicon using a chemical vapor deposition method to form an oxide layer; wherein the chemical vapor deposition method is selected from one of atomic layer deposition, plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, high-pressure chemical vapor deposition, and magnetron sputtering. a4) The helium ion beam is derived from a helium ion source in a focused helium ion beam microscope; a5) The accelerating voltage of the helium ion beam is 10~30kV; a6) The beam spot of the helium ion beam is 0.5~2nm; a7) The current of the helium ion beam is 1~3pA; a8) The speed of direct writing of graphics is 0.037~0.5 micrometers / second.

3. The method for preparing silicon nanochannels as described in claim 2, characterized in that, Step 1) also includes at least one of the following technical features: In feature a3), before plating oxide, the single crystal silicon is cleaned of organic residues and then etched to remove the natural oxide layer on the silicon surface. In feature a3), the chemical vapor deposition method is atomic layer deposition. In feature a3), the temperature for plating oxides is 200~250℃.

4. The method for preparing silicon nanochannels as described in claim 1, characterized in that, In step 1), the number of times the helium ion beam is used for direct writing is ≥1.

5. The method for preparing silicon nanochannels as described in claim 1, characterized in that, Ultrasonic treatment is performed after etching.

6. The method for preparing silicon nanochannels according to any one of claims 1 to 5, characterized in that, It also includes at least one of the following technical features: b1) In the method of implanting oxygen atoms into the surface layer of monocrystalline silicon in step 1), the thickness of the oxide layer is 2~50nm; b2) In step 2), chemical wet etching is used to etch the silicon oxide pattern and oxide layer. The etching solution is one of hydrofluoric acid aqueous solution, buffered oxide etchant, and buffered oxide etchant containing surfactant. b3) In step 2), the etching temperature is 20~25℃; b4) In step 2), the etching time is 6~30min.

7. The method for preparing silicon nanochannels as described in claim 6, characterized in that, In feature b2), the concentration of the etching solution is 1~5% vol.

8. The method for preparing silicon nanochannels as described in claim 6, characterized in that, In feature b2), step 2) uses hydrofluoric acid aqueous solution for chemical wet etching.

9. A method for detecting silicon nanochannels, characterized in that, In step 2) of the method for preparing silicon nanochannels according to any one of claims 1 to 8, before chemical wet etching, a vertical cross section with a depth of 1.5~3μm and a silicon oxide pattern on the surface is etched using a gallium ion beam.

10. The method for detecting silicon nanochannels as described in claim 9, characterized in that, It also includes at least one of the following technical features: c1) The gallium ion beam is derived from a gallium ion source in a focused helium ion beam microscope; c2) The accelerating voltage of the gallium ion beam is 2~30kV; c3) The beam spot of the gallium ion beam is 5~50nm; c4) The beam current of the gallium ion beam is 100~300pA; c5) The irradiation dose of the gallium ion beam is 1.5~3 nC / μm. 2 .

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