A method for fabricating an LDMOS device

Abstract

The application provides a LDMOS device manufacturing method, multiple dummy gates are formed above the drift region beside the main gate, and the interval distance between the dummy gates is set to be less than twice the width of the gate side wall, so that when the gate side wall is formed, the gate side wall can fill the gap between the adjacent dummy gates, so that the gap between the dummy gates is completely covered. Then, ion implantation of the source-drain region is carried out based on the main gate, the dummy gate and the gate side wall, so that the ion implantation of the source-drain region is completely self-aligned, without additional mask, the process complexity is reduced, the dependence of the ion implantation of the source-drain region on CDU / OVL is reduced, and the performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a LDMOS device manufacturing method. BACKGROUND

[0002] LDMOS (laterally-diffused metal-oxide semiconductor) transistors are excellent in performance in key device characteristics and are compatible with CMOS (Complementary Metal Oxide Semiconductor) processes, and thus are widely applied.

[0003] Taking SAB type field plate nLDMOS as an example, the prior art forms a drain offset region and a P body region of a source before a gate, then performs LDD / N+ source-drain level doping after the gate, and finally forms a SAB field plate to complete the device structure of the LDMOS. In this structure, the drain needs to shield the SAB field plate region during N+ implantation, so as to avoid offset region and field plate function failure. The CDU (Critical Dimension Uniformity) of the implantation layer and the SAB layer and the accuracy of the OVL (Overlay) between the two layers will affect the actual distance from the drain to the gate, and further affect the uniformity of the device performance.

[0004] Therefore, how to provide a process for realizing source-drain implantation self-alignment and reducing the dependence of source-drain implantation on CDU / OVL has become an important technical problem to be solved by the person skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and for the convenience of understanding by the person skilled in the art. The above technical scheme cannot be considered as known to the person skilled in the art only because it is described in the background section of the present application. SUMMARY

[0006] In view of the above defects in the prior art LDMOS device manufacturing process, the present application provides a LDMOS device manufacturing method to solve one or more of the above problems.

[0007] In order to achieve the above purpose, the present application provides a LDMOS device manufacturing method, which comprises the following steps:

[0008] providing a substrate;

[0009] A drift region, a body region, and a gate are formed on the substrate. The drift region and the body region are both located in the substrate and are spaced apart. The gate is located on the substrate and includes a main gate and a plurality of dummy gates. The main gate spans between the drift region and the body region, with one end of the main gate extending above the drift region and the other end extending above the body region. The dummy gates are located above the drift region and are spaced apart from the main gate. The plurality of dummy gates are spaced apart from each other.

[0010] Gate sidewalls are formed on both sides of the main gate and between adjacent virtual gates, and the gate sidewalls completely fill the gaps between adjacent virtual gates;

[0011] Based on the virtual gate and the gate sidewall, the drift region and the body region are subjected to the first ion implantation and annealing, forming the drain in the drift region and the source in the body region.

[0012] Optionally, the spacing between adjacent virtual gates is less than twice the width of the gate sidewall.

[0013] Optionally, the spacing between the main gate and the virtual gate is less than twice the width of the gate sidewall.

[0014] Optionally, the spacing between adjacent virtual gates may be the same, or the spacing between adjacent virtual gates may not all be the same.

[0015] Optionally, the LDMOS device fabrication method further includes:

[0016] A field plate is formed above the virtual gate and the gate sidewall;

[0017] A second ion implantation and annealing are performed on the drift region based on the field plate to form a doped region in the drift region; or

[0018] A second ion implantation and annealing are performed on the drift region based on the virtual gate and the gate sidewall to form a doped region in the drift region.

[0019] Optionally, the drift region, the drain, the source, and the doped region are all of a first conductivity type, and the body region is of a second conductivity type opposite to the first conductivity type. The first conductivity type is either P-type or N-type.

[0020] Optionally, the energy range of the first ion implantation is 0.1 keV to 100 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 14 cm -2 ~1×10 16cm -2 .

[0021] Optionally, the energy range of the second ion implantation is 20 keV to 800 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 13 cm -2 ~1×10 15 cm -2 .

[0022] Optionally, the field plate also extends to the surface of the main gate.

[0023] Optionally, the fabrication of the LDMOS device further includes forming metal leads above the gate, source, and drain regions, respectively.

[0024] As described above, the LDMOS device fabrication method of the present invention has the following beneficial effects:

[0025] In this invention, when forming the main gate, multiple dummy gates are formed above the drift region adjacent to the main gate, and the spacing between the dummy gates is set to be less than twice the width of the gate sidewall. This ensures that the gate sidewall fills the gap between adjacent dummy gates during gate sidewall formation, completely covering the gap. Then, source / drain ion implantation is performed based on the gate, dummy gates, and gate sidewalls. This achieves complete self-alignment of source / drain ion implantation, eliminating the need for additional masks, reducing process complexity, and decreasing the dependence of source / drain ion implantation on CDU / OVL. The aforementioned dummy gates and gate sidewalls ensure the distance from the drain to the main gate, which helps improve the uniformity of device performance. Attached Figure Description

[0026] Figure 1a and Figure 1b The diagram shows a schematic of an nLDMOS structure with an SAB-type field plate in the prior art.

[0027] Figure 2 The diagram shows the steps of the LDMOS device fabrication method of the present invention in Embodiment 1.

[0028] Figure 3 The diagram shown is a schematic representation of the structure presented in step S1 of the LDMOS device fabrication method of the present invention in Embodiment 1.

[0029] Figure 4 The diagram shown is a structural schematic of step S2 in Embodiment 1 of the LDMOS device fabrication method of the present invention.

[0030] Figure 5 Displayed as Figure 4 A partially enlarged schematic diagram of the multiple virtual gates shown.

[0031] Figure 6 The diagram shown is a structural schematic of step S3 in Embodiment 1 of the LDMOS device fabrication method of the present invention.

[0032] Figure 7 The diagram shown is a structural schematic of step S4 in Embodiment 1 of the LDMOS device fabrication method of the present invention.

[0033] Figure 8 The diagram shown is a structural schematic of the field plate formation step in an optional embodiment of the LDMOS device fabrication method of the present invention.

[0034] Figure 9 The diagram shown illustrates the structure of the LDMOS device fabrication method of the present invention during the formation of metal leads.

[0035] Component designation explanation

[0036] 100, Substrate; 101, Isolation structure; 102, Body region; 103, Drift region; 104, Main gate; 105, Virtual gate; 106, Gate sidewall; 107, Mask; 108, Source; 109, Drain; 110, Field plate; 111, Doped region; 112, Metal lead; S1~S4, Steps; D1~D5, Spacing between adjacent virtual gates. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] like Figure 1a As shown, in the prior art, when forming an SAB-type field plate nLDMOS device, after forming the body region, drift region, and gate on the substrate, a mask is formed above the substrate to form the ion implantation windows for the source and drain. This mask also needs to block the field plate region above the drift region next to the gate to prevent the drift region and field plate region from failing. Then, as... Figure 1b As shown, ion implantation is performed based on the aforementioned mask to form the source and drain. In the above method, the accuracy of the CDU between the drain and the field plate region, as well as the OVL between the mask and the substrate, will affect the actual distance from the drain to the gate, thereby affecting the uniformity of device performance.

[0039] To address the aforementioned problems, this invention provides a method for fabricating LDMOS devices. This method enables self-alignment of source and drain ion implantation, improving the performance uniformity of the device. The following specific examples will be used to describe this method in detail.

[0040] Example 1

[0041] This embodiment provides a method for fabricating an LDMOS device, such as... Figure 2 As shown, the manufacturing method includes the following steps:

[0042] S1: Provides a first substrate;

[0043] First, please refer to Figure 3 The following step S1 is performed: providing a substrate 100. The substrate 100 can be an N-type substrate or a P-type substrate, which can be selected according to the actual situation. In this embodiment, the substrate 100 is a P-type substrate. For example, the substrate 100 can be bulk silicon, silicon-on-insulator, germanium silicon, or strained silicon, etc. In this embodiment, a bulk silicon substrate is used as an example. For example, a P-type silicon substrate can be formed by doping boron ions into a single-crystal silicon substrate.

[0044] S2: A drift region, a body region, and a gate are formed based on the substrate. The drift region and the body region are both located in the substrate and are spaced apart. The gate is located on the substrate and includes a main gate and a plurality of dummy gates. The main gate spans between the drift region and the body region, and one end of the main gate extends above the drift region and the other end of the main gate extends above the body region. The dummy gates are located above the drift region and are spaced apart from the main gate. The plurality of dummy gates are spaced apart from each other.

[0045] like Figure 4 As shown, the substrate 100 has a device region A, and an isolation structure 101 is formed between adjacent device regions A. This isolation structure 101 can be a trench isolation structure 101, for example, by etching along the surface of the substrate 100 to form shallow trenches in the substrate 100, and then filling the shallow trenches with an insulating material, such as SiO2, to form the isolation structure 101. The isolation structure 101 isolates the device region A of the substrate 100.

[0046] Similarly, Figure 4As shown, in device region A, a body region 102, a drift region 103, and a gate are formed based on a substrate 100. The body region 102 and the drift region 103 are both located in the substrate 100 and spaced apart. The gate is located above the substrate 100 and includes a main gate 104 and a dummy gate 105. The main gate 104 spans between the drift region 103 and the body region 102, with one end extending above the drift region 103 and the other end extending above the body region 102. The dummy gate 105 is formed above the drift region 103 and spaced apart from the main gate 104. Optionally, there are multiple dummy gates 105, which are also spaced apart. These multiple dummy gates 105 cover a portion of the drift region 103, which is where the drain region 109 will be formed later (see [link to documentation]). Figure 7 The virtual gate 105 can be formed simultaneously with the main gate 104, and both can be formed from the same material, such as polysilicon. Thus, the fabrication of the main gate 104 and the virtual gate 105 can be completed without adding any additional processes.

[0047] like Figure 5 As shown, the specific distribution of the virtual gates 105 is illustrated in magnified view. Taking a configuration of six virtual gates 105 as an example, the spacing between adjacent virtual gates 105 can be the same or different, i.e., Figure 5 The values ​​D1, D2, D3, D4, and D5 shown may be equal, or all may be unequal, or at least two of D1, D2, D3, D4, and D5 may be equal. Furthermore, the aforementioned spacing distances D1, D2, D3, D4, and D5 are all set to be greater than or equal to twice the width of the subsequently formed gate sidewalls. This spacing setting ensures that the gaps between adjacent dummy gates are completely filled by the gate sidewalls during subsequent gate sidewall formation, acting as a mask.

[0048] S3: Gate sidewalls are formed on both sides of the main gate and between adjacent virtual gates, and the gate sidewalls completely fill the gaps between adjacent virtual gates.

[0049] like Figure 6As shown, after forming the dummy gate 105, gate sidewalls 106 are formed on both sides of the main gate 104 and between adjacent dummy gates 105. For example, the structure with the dummy gates 105 can be placed in an oxidation furnace, and the gate sidewalls 106 are grown by oxidation. Since the spacing between adjacent dummy gates 105 is less than twice the width of the gate sidewall 106, the gate sidewall 106 can completely fill the gap between adjacent dummy gates 105, so that the dummy gates 105 and the gate sidewalls 106 form a continuous structure. This continuous structure can act as a mask, blocking ions from entering the substrate during ion implantation. Furthermore, it enables self-alignment of ion implantation, improves the accuracy of the ion implantation region, and ensures the uniformity of device performance.

[0050] In an optional embodiment, the area covered by the virtual gate 105 is the ion implantation window region of the doped region for the drift region 103. This ensures the accuracy of this region, guarantees the distance from the subsequently formed drain to the main gate, and thus ensures the uniformity of device performance.

[0051] S4: Based on the virtual gate and the gate sidewall, the drift region and the body region are subjected to the first ion implantation and annealing, forming the drain in the drift region and the source in the body region respectively.

[0052] like Figure 7 As shown, a mask 107 is first formed above the substrate, which shields the source and drain regions, forming an ion implantation window. Due to the presence of the dummy gate and gate sidewalls, the field plate region is shielded; therefore, it is not necessary to... Figure 1a The mask shown forms the shielding field plate area. This reduces the processing difficulty of mask 107 and improves the alignment accuracy of the ion implantation window.

[0053] exist Figure 7 The first ion implantation is performed within the ion implantation window shown, forming a source 108 in the body region and a drain 109 in the drift region. The distance between the drain 109 and the main gate 104 is, for example, for N+ ion implantation, where the N+ ion can be a B ion. In an optional embodiment, the energy range of this first ion implantation is 0.1 keV to 100 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 14 cm -2 ~1×10 16 cm -2Under the action of the virtual gate 105, gate sidewall 106, main gate 104, and mask 107, the source 108 and drain 109 are formed by the first ion implantation. The formation of the virtual gate 105 and gate sidewall 106 reduces the dependence on CDU / OVL in the process, while ensuring the precise distance between the drain 109 and the main gate 104, which helps to improve the uniformity of device performance.

[0054] In an optional embodiment of this example, in addition to the steps described above, a second ion implantation is performed on the drift region 103 under the action of the virtual gate 105, gate sidewall 106, main gate 104, and mask 107, to form a doped region 111 within the drift region 103 below the virtual gate 105 and gate sidewall 106. This second ion implantation can also be N+ ion implantation, but differs from the first ion implantation in implantation energy and concentration, thereby ensuring the functional integrity of each region. Optionally, the energy range of the second ion implantation is between 20 keV and 800 keV, and the dose range of the ion implantation is between 1 × 10⁻⁶. 13 cm -2 ~1×10 15 cm -2 .

[0055] In another optional embodiment of this embodiment, in addition to the steps described above, it further includes: forming a field plate above the virtual gate and the gate sidewall; performing a second ion implantation and annealing on the drift region based on the field plate to form a doped region in the drift region.

[0056] like Figure 8 As shown, a field plate 110 is formed above the virtual gate 105 and the gate sidewall 106. Preferably, the field plate 110 also extends to a portion of the region above the main gate 104. A second ion implantation is then performed based on the field plate 110 to form a doped region 111 within the drift region 103 below the field plate 110. This second ion implantation can also be N+ ion implantation, but differs from the first ion implantation in implantation energy and concentration, thereby ensuring the functional integrity of each region. Optionally, the energy range of the second ion implantation is between 20 keV and 800 keV, and the dose range of the ion implantation is between 1 × 10⁻⁶. 13 cm -2 ~1×10 15 cm -2 .

[0057] like Figure 9 As shown, the method in this embodiment further includes forming metal leads 112 above the main gate 104, source 108 and drain 109, wherein the metal leads form the gate electrode, source electrode and drain electrode respectively.

[0058] This embodiment also provides an LDMOS device formed by the above method, similarly as described above. Figure 9 As shown, the distance between the drain 109 and the main gate 104 of the LDMOS device can be precisely controlled, ensuring the dimensional accuracy of the doped region 111 and improving the uniformity of device performance.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an LDMOS device, characterized in that, Includes the following steps: Provide a substrate; A drift region, a body region, and a gate are formed on the substrate. The drift region and the body region are both located in the substrate and are spaced apart. The gate is located on the substrate and includes a main gate and a plurality of dummy gates. The main gate spans between the drift region and the body region, with one end of the main gate extending above the drift region and the other end extending above the body region. The dummy gates are located above the drift region and are spaced apart from the main gate. The plurality of dummy gates are spaced apart from each other. Gate sidewalls are formed on both sides of the main gate and between adjacent virtual gates. The spacing between adjacent virtual gates is less than twice the width of the gate sidewall. The gate sidewall completely fills the gap between adjacent virtual gates. The virtual gate and the gate sidewall form a mask with a continuous structure. Based on the virtual gate and the gate sidewall, the drift region and the body region are subjected to the first ion implantation and annealing, forming the drain in the drift region and the source in the body region.

2. The method for fabricating an LDMOS device according to claim 1, characterized in that, The distance between the main gate and the virtual gate is less than twice the width of the gate sidewall.

3. The method for fabricating an LDMOS device according to claim 1, characterized in that, The spacing between adjacent virtual gates is the same, or the spacing between adjacent virtual gates is not all the same.

4. The method for fabricating an LDMOS device according to claim 1, characterized in that, Also includes: A field plate is formed above the virtual gate and the gate sidewall; A second ion implantation and annealing are performed on the drift region based on the field plate to form a doped region in the drift region; or A second ion implantation and annealing are performed on the drift region based on the virtual gate and the gate sidewall to form a doped region in the drift region.

5. The method for fabricating an LDMOS device according to claim 4, characterized in that, The drift region, the drain, the source, and the doped region are all of the first conductivity type, and the body region is of the second conductivity type, which is opposite to the first conductivity type. The first conductivity type is either P-type or N-type.

6. The method for fabricating an LDMOS device according to claim 1, characterized in that, The energy range of the first ion implantation is 0.1 keV to 100 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 14 cm -2 ~1×10 16 cm -2 .

7. The method for fabricating an LDMOS device according to claim 4, characterized in that, The energy range of the second ion implantation is 20 keV to 800 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 13 cm -2 ~1×10 15 cm -2 .

8. The method for fabricating an LDMOS device according to claim 4, characterized in that, The field plate also extends to the surface of the main gate.

9. The method for fabricating an LDMOS device according to claim 1, characterized in that, Also includes: Metal leads are formed above the main gate, source region, and drain region, respectively.

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