GaN HEMT Device and Its Manufacturing Method

Abstract

The present invention provides a GaN HEMT device and a method for manufacturing the same. By epitaxially forming a plurality of superlattice structures on an isolation layer, a first portion of the isolation layer is missing, so that a cavity is formed between the plurality of superlattice structures and the isolation layer. A portion of the plurality of superlattice structures located above the cavity forms superlattice nanowires, and the gate metal wraps around the superlattice nanowires from all around. Each layer of the superlattice structure includes an AlN layer and a GaN layer formed in sequence along the direction away from the substrate. Each layer of the GaN / AlN superlattice structure corresponds to form a conductive channel, thereby increasing the output current of the GaN HEMT device. At the same time, the annular gate metal can completely turn off all the conductive channels corresponding to the plurality of superlattice structures from all around, improving the gate control ability and switching performance of the GaN HEMT device, thus achieving the effect of improving the performance of the GaN HEMT device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a GaN HEMT device and a method for manufacturing the same. Background Art

[0002] Due to the advantages of GaN materials such as stable chemical properties, high electron mobility, high temperature resistance, and high breakdown voltage, in recent years, GaN HEMT devices have been widely used in the field of integrated circuits, especially in the field of high-frequency power circuits.

[0003] Currently, GaN HEMT devices often adopt an AlGaN / GaN heterojunction structure. By increasing the Al component in the AlGaN / GaN heterojunction, the concentration of 2DEG can be effectively increased, thereby increasing the output current of the device. However, with the increase of the Al component, the crystal quality of the AlGaN barrier layer will deteriorate, and at the same time, the surface morphology will also deteriorate, resulting in leakage. If a GaN / AlN heterostructure is adopted, its electron mobility is higher and the device output current is higher. However, current GaN / AlN HEMT devices often adopt a planar structure, and its gate control ability is poor, while gate leakage will seriously affect the device turn-off ability, thereby making the device reliability worse.

[0004] Therefore, how to improve the gate control ability of the device while increasing the output current of the GaN HEMT device has become a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0005] The present invention provides a GaN HEMT device and a method for manufacturing the same to solve the problem of how to improve the gate control ability of the GaN HEMT device while increasing the output current of the GaN HEMT device.

[0006] According to a first aspect of the present invention, there is provided a method for manufacturing a GaN HEMT device, including:

[0007] Providing a substrate;

[0008] Epitaxially forming a buffer layer, an interface layer, and an isolation layer on the substrate in a direction away from the substrate in sequence;

[0009] Epitaxially growing a plurality of superlattice structures on the isolation layer, each superlattice structure including an AlN layer and a GaN layer formed in sequence in a direction away from the substrate;

[0010] Selectively etching the plurality of superlattice structures to form isolation mesa surfaces on both sides of the isolation layer along a first direction;

[0011] Remove the first part of the isolation layer to form a cavity between the plurality of superlattice structures and the interface layer; wherein, the cavity is located below a partial area of the plurality of superlattice structures, and a part of the plurality of superlattice structures above the cavity forms superlattice nanowires;

[0012] Epitaxially form a source electrode and a drain electrode on the plurality of superlattice structures, wherein the source electrode and the drain electrode are located on both sides of the cavity along the first direction;

[0013] Deposit gate metal on the outer periphery of the superlattice nanowires, and the gate metal wraps the superlattice nanowires from all around.

[0014] Optionally, removing the first part of the isolation layer to form a cavity between the plurality of superlattice structures and the interface layer includes:

[0015] Coat photoresist on the exposed isolation layer, expose and develop the photoresist to form patterned photoresist;

[0016] Etch the first part of the isolation layer using the patterned photoresist as a mask to form a cavity between the plurality of superlattice structures and the interface layer;

[0017] Remove the patterned photoresist to form the isolation layer covering a part of the interface layer.

[0018] Optionally, forming a gate specifically includes:

[0019] Deposit the gate metal in the gate region of the cavity to form the gate.

[0020] Optionally, before forming the gate, it further includes:

[0021] Deposit a gate dielectric in the gate region of the cavity, and the gate dielectric wraps the superlattice nanowires from all around.

[0022] According to a second aspect of the present invention, a GaN HEMT device is provided, including:

[0023] A substrate, and a buffer layer, an interface layer, and an isolation layer are sequentially epitaxially formed on the substrate in a direction away from the substrate;

[0024] A plurality of superlattice structures are formed on the isolation layer, and the first part of the isolation layer is missing, so that a cavity is formed between the plurality of superlattice structures and the isolation layer; wherein, each superlattice structure includes an AlN layer and a GaN layer sequentially formed in a direction away from the substrate, and a part of the plurality of superlattice structures above the cavity forms superlattice nanowires;

[0025] A source electrode and a drain electrode are formed on the plurality of superlattice structures; wherein, the source electrode and the drain electrode are located on both sides of the cavity along a first direction;

[0026] A gate metal wraps around the periphery of the superlattice nanowire.

[0027] Optionally, the surface of the isolation layer in a second direction is wider than the width of the plurality of superlattice structures.

[0028] Optionally, the gate metal fills in the gate region of the cavity and wraps around the periphery of the superlattice nanowire.

[0029] Optionally, a gate dielectric is further included;

[0030] The gate dielectric is wrapped between the gate metal and the superlattice nanowire.

[0031] Optionally, the materials of the interface layer and the gate metal are AlN, and the material of the isolation layer is Al2O3.

[0032] According to a third aspect of the present invention, a manufacturing method of an electronic device is provided, including the preparation method of the GaN HEMT device according to any one of the first aspects of the present invention.

[0033] According to a fourth aspect of the present invention, an electronic device is provided, including the GaN HEMT device according to any one of the second aspects of the present invention.

[0034] In the GaN HEMT device and its preparation method provided by the present invention, by epitaxially forming a plurality of superlattice structures on an isolation layer, a first part of the isolation layer is missing, so that a cavity is formed between the plurality of superlattice structures and the isolation layer, and a part of the plurality of superlattice structures located above the cavity forms superlattice nanowires, and the gate metal wraps around the superlattice nanowires from all around. Each superlattice structure includes an AlN layer and a GaN layer formed in sequence along a direction away from the substrate; each GaN / AlN superlattice structure correspondingly forms a conductive channel, thereby increasing the output current of the GaN HEMT device. At the same time, the annular gate metal can completely turn off all the conductive channels corresponding to the plurality of superlattice structures from all around, improving the gate control ability and switching performance of the GaN HEMT device, and thus achieving the effect of improving the performance of the GaN HEMT device. Description of the Drawings

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic flowchart of a preparation method of a GaN HEMT device provided by an embodiment of the present invention;

[0037] Figure 2 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 1 ;

[0038] Figure 3 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 2 ;

[0039] Figure 4 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 3 ;

[0040] Figure 5 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 4 ;

[0041] Figure 6 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 5 ;

[0042] Figure 7 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 6 ;

[0043] Figure 8 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 7 ;

[0044] Figure 9 It is a schematic diagram of the device structure at different process stages fabricated according to the fabrication method of the GaN HEMT device structure provided by an embodiment of the present invention Figure 8 ;

[0045] Description of the reference numerals:

[0046] 101 - Substrate;

[0047] 102 - Buffer layer;

[0048] 103 - Interface layer;

[0049] 104 - Isolation layer;

[0050] 105 - Superlattice layer;

[0051] 106 - Gate metal;

[0052] 107 - Gate dielectric;

[0053] 108 - Source electrode;

[0054] 109 - Drain electrode;

[0055] 1051 - First superlattice structure;

[0056] 1052 - Second superlattice structure;

[0057] 1053 - Third superlattice structure;

[0058] 1054 - Fourth superlattice structure; Detailed implementation manners

[0059] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0060] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0061] Due to the advantages of GaN materials such as stable chemical properties, high electron mobility, high temperature resistance, and high breakdown voltage, they have great application value in power devices. High electron mobility transistors based on GaN and their power integrated circuits are candidates for the next generation of ultra-high density power converters. They have now been applied to AC adapters for high-density power stages in consumers and data centers, and also have great advantages in applications such as motor drives;

[0062] Also, in the GaN / AlN heterojunction, due to the stronger polarization ability of AlN, when the thickness of AlN is very thin (i.e., d < 5 nm), the concentration of 2DEG at the interface can exceed 3*10 13 cm -2 . A GaN high electron mobility transistor (HEMT) with a GaN / AlN superlattice (SL) channel. This superlattice structure has better voltage blocking ability and thermal stability than traditional GaN channels, and higher electron mobility than AlGaN channels. Its conductivity is higher than that of AlGaN / GaN heterojunctions. However, the gate control ability of traditional GaN / AlN HEMT devices is poor, and gate leakage will seriously affect the device turn-off ability, thereby deteriorating the device reliability.

[0063] In view of the prior art, it is difficult to improve the gate control ability of a device while increasing the output current of a GaN HEMT device. The present invention provides a GaN HEMT device and a preparation method thereof. By epitaxially forming several layers of superlattice structures on an isolation layer, a first part of the isolation layer is missing, so that a cavity is formed between the several layers of superlattice structures and the isolation layer. A part of the several layers of superlattice structures above the cavity forms superlattice nanowires, and the gate metal wraps the superlattice nanowires from all around. Each layer of the superlattice structure includes an AlN layer and a GaN layer formed in sequence along the direction away from the substrate; while increasing the output current of the GaN HEMT device by the several layers of superlattice structures, the annular gate metal can ensure that the conductive channels of the several layers of superlattice structures are completely turned off from all around, improving the gate control ability and switching performance of the GaN HEMT device, thereby achieving the effect of improving the performance of the GaN HEMT device.

[0064] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0065] Please refer to Figure 7 , according to an embodiment of the present invention, a GaN HEMT device is provided, including:

[0066] Substrate 101, and a buffer layer 102, an interface layer 103, and an isolation layer 104 are sequentially epitaxially formed on the substrate 101 in a direction away from the substrate 101;

[0067] A superlattice layer 105, the superlattice layer 105 includes several layers of superlattice structures, formed on the isolation layer 104, a first part of the isolation layer 104 is missing, so that a cavity is formed between the several layers of superlattice structures and the isolation layer 104; wherein, each layer of superlattice structure includes an AlN layer and a GaN layer sequentially formed in a direction away from the substrate 101, and a part of the several layers of superlattice structures located above the cavity forms superlattice nanowires;

[0068] A source electrode 108 and a drain electrode 109 are formed on the several layers of superlattice structures; wherein, the source electrode and the drain electrode 109 are located on both sides of the cavity along a first direction;

[0069] A gate metal 106 wraps around the periphery of the superlattice nanowires.

[0070] Wherein, the gate metal 106 wrapping around the periphery of the superlattice nanowires can completely turn off the conductive channel of the GaN HEMT device from all around, increasing the control area of the gate over the channel, greatly enhancing the gate control ability, thereby effectively suppressing the short-channel effect, suppressing the gate leakage current, reducing the subthreshold swing and device power consumption, and improving the switching speed and performance of the GaN HEMT device.

[0071] In an example, the material of the interface layer 103 and the gate metal 106 is AlN, and the material of the isolation layer 104 is Al2O3. Of course, the foregoing several structural layers can also be composed of other materials, and the present invention is not limited thereto. Any implementation form of the materials of the corresponding structural layers is within the protection scope of the present invention;

[0072] Since each layer of superlattice structure has one 2DEG as a conductive channel, and the 2DEG electrons are basically not affected by impurity scattering, the electron mobility in the channel is relatively high and has an ultra-high channel mobility. Also, the several 2DEG conductive channels corresponding to the several layers of superlattice structures are connected in parallel, that is, the several 2DEG conductive channels share the same gate voltage and source voltage, so that each 2DEG conductive channel can contribute a certain proportion of the channel current. The more 2DEG conductive channels, the greater the output current of the GaN HEMT device.

[0073] Specifically, in Figure 7In the illustrated example, taking the superlattice layer 105 including the stacked first superlattice structure 1051, second superlattice structure 1052, third superlattice structure 1053, and fourth superlattice structure 1054, a total of 4 superlattice structures as an example for illustration.

[0074] In one embodiment, please refer to Figure 8 , Figure 8 is the cross-section of the GaN HEMT device at the superlattice nanowire. The isolation layer 104 is wider than the width of the several superlattice structures along the surface in the second direction, and is used to provide space for the gate metal 106 to contact the 2DEG corresponding to the 4 superlattice structures on the sidewall of the mesa, and also provides electrical isolation when multiple GaN HEMT devices are connected.

[0075] In a preferred embodiment, please refer to Figure 7 , the gate metal 106 fills the gate region of the cavity and wraps around the periphery of the superlattice nanowire to form a gate; wherein, the gate metal 106 does not contact the interface layer 103.

[0076] To increase the reliability of the device, in a further preferred embodiment, please refer to Figure 9 , Figure 9 is the cross-section of the GaN HEMT device at the superlattice nanowire, and the GaN HEMT device further includes a gate dielectric 107;

[0077] The gate dielectric 107 is wrapped between the gate metal 106 and the superlattice nanowire. The gate dielectric 107 serves as an insulating layer to isolate the gate and the channel, and protects the GaN HEMT device when the gate voltage is too high;

[0078] In an example, the material of the gate dielectric 107 is Al2O3. Of course, the gate dielectric 107 can also be composed of other materials. The present invention is not limited thereto, and can also be SiO2, SiON, HfO2, etc. Those skilled in the art can select a suitable gate dielectric according to actual needs, and any implementation form of the corresponding gate dielectric material is within the protection scope of the present invention.

[0079] In addition, please refer to Figures 1 - 9 , according to other embodiments of the present invention, a method for manufacturing a GaN HEMT device is further provided, and the method includes:

[0080] Providing a substrate;

[0081] Epitaxially forming a buffer layer, an interface layer, and an isolation layer on the substrate in a direction away from the substrate in sequence;

[0082] Epitaxially grow several layers of superlattice structures on the isolation layer, and each layer of superlattice structure includes an AlN layer and a GaN layer formed in sequence along the direction away from the substrate;

[0083] Selectively etch the several layers of superlattice structures to form isolation mesa surfaces on both sides of the isolation layer along the first direction;

[0084] Remove the first part of the isolation layer to form a cavity between the several layers of superlattice structures and the interface layer; wherein, the cavity is located below a partial area of the several layers of superlattice structures, and a part of the several layers of superlattice structures located above the cavity forms superlattice nanowires;

[0085] Epitaxially grow a source electrode and a drain electrode on the several layers of superlattice structures, wherein the source electrode and the drain electrode are located on both sides of the cavity along the first direction;

[0086] Deposit a gate metal on the outer periphery of the superlattice nanowires, and the gate metal wraps the superlattice nanowires from all around.

[0087] Now, taking the material of the isolation layer 104 and the material of the gate dielectric 107 as Al2O3 and the material of the gate metal 106 as TiN as an example for further illustration:

[0088] As a specific implementation manner, please refer to Figure 1 , in actual use, when fabricating a GaN HEMT device provided by the embodiment of the present invention as shown in Figures 2 - 9 , this method includes steps S11 - S17, which are specifically as follows:

[0089] S11: Provide a substrate 101;

[0090] S12: Epitaxially grow a buffer layer 102, an interface layer 103, and an isolation layer 104 in sequence on the substrate 101 along the direction away from the substrate 101; the device after forming the buffer layer 102, the interface layer 103, and the isolation layer 104 is as shown in Figure 2 ;

[0091] S13: Epitaxially grow several layers of superlattice structures on the isolation layer 104;

[0092] Specifically, each layer of superlattice structure includes an AlN layer and a GaN layer formed in sequence along the direction away from the substrate 101; the device after forming the superlattice layer 105 is as shown in Figure 3 ;

[0093] S14: Selectively etch the several layers of superlattice structures;

[0094] Specifically, selectively etch the plurality of superlattice structures to form isolation mesa surfaces on both sides of the isolation layer 104 along the first direction;

[0095] This is because space needs to be provided for the gate metal 106 to contact the 2DEG conductive channel corresponding to the plurality of superlattice structures on the sidewall of the mesa, while providing electrical isolation when connecting multiple GaN HEMT devices; The device after forming the isolation mesa is as Figure 4 shown;

[0096] S15: Remove the first part of the isolation layer 104;

[0097] Specifically, remove the first part of the isolation layer 104 to form a cavity between the plurality of superlattice structures and the interface layer 103; wherein, the cavity is located below a partial region of the plurality of superlattice structures, and a partial region of the plurality of superlattice structures located above the cavity forms superlattice nanowires; The device after removing the first part of the isolation layer 104 is as Figure 5 shown;

[0098] Since removing the isolation layer 104 does not require microfabrication, in one example, the first part of the isolation layer 104 can be removed by wet etching (for example, an HF solution), so that all the materials of the first part of the isolation layer 104 are removed;

[0099] S16: Epitaxially form a source electrode 108 and a drain electrode 109 on the plurality of superlattice structures;

[0100] Wherein, the source electrode 108 and the drain electrode 109 are located on both sides of the cavity along the first direction; The device after forming the source electrode 108 and the drain electrode 109 is as Figure 6 shown;

[0101] S17: Deposit a gate metal 106 on the outer periphery of the superlattice nanowires;

[0102] Specifically, deposit a gate metal 106 on the outer periphery of the superlattice nanowires, and the gate metal 106 wraps around the superlattice nanowires from all around; The device after the gate metal 106 wraps around the superlattice nanowires from all around is as Figure 7 shown.

[0103] Wherein, as an implementation manner, step S15 may specifically include coating a photoresist on the exposed isolation layer 104, exposing and developing the photoresist to form a patterned photoresist;

[0104] Using the patterned photoresist as a mask, etch the first part of the isolation layer 104 to form a cavity between the plurality of superlattice structures and the interface layer 103;

[0105] Remove the patterned photoresist to form the isolation layer 104 covering a part of the interface layer 103.

[0106] In a preferred embodiment, the selective etching of the plurality of superlattice structures in step S14 includes steps S141 - S142, specifically as follows:

[0107] S141: Clean the sample of the GaN HEMT device;

[0108] This is because in actual production, there will be impurities such as organic substances, metals, and particles on the surface of the GaN HEMT device. These impurities will affect the yield, performance, and reliability of the device. At the same time, cleaning the sample of the GaN HEMT device can also remove the surface oxide layer and the oxide deposited by CVD;

[0109] S142: Selectively etch the plurality of superlattice structures.

[0110] In order to optimize the performance of the GaN HEMT device, as a further preferred embodiment, step S17 may specifically further include depositing the gate metal 106 in the gate region of the cavity to form the gate; the device after depositing the gate metal 106 in the gate region of the cavity is as Figure 7 shown. In a preferred embodiment, the specific steps of depositing the gate metal 106 on the outer periphery of the superlattice nanowire in step S17 include steps S171 - S172, specifically as follows:

[0111] S171: Deposit a gate dielectric 107 in the gate region of the cavity, and the gate dielectric 107 wraps the superlattice nanowire from all around.

[0112] S172: Deposit the gate metal 106 in the gate region of the cavity, and the gate metal 106 wraps the gate dielectric 107 from all around; the device after depositing the gate dielectric 107 and depositing the gate metal 106 is as Figure 9 shown.

[0113] In addition, according to other embodiments of the present invention, there is also provided a manufacturing method of an electronic device, including the preparation method of the GaN HEMT device according to any one of the first aspects of the present invention.

[0114] According to another embodiment of the present invention, there is also provided an electronic device, including the GaN HEMT device according to any one of the second aspects of the present invention.

[0115] In summary, in a GaN HEMT device and a preparation method thereof provided by the present invention, by epitaxially forming a plurality of superlattice structures on an isolation layer, a first part of the isolation layer is missing, so that a cavity is formed between the plurality of superlattice structures and the isolation layer, and a part of the plurality of superlattice structures located above the cavity forms superlattice nanowires, and the gate metal wraps the superlattice nanowires from all around. Each superlattice structure includes an AlN layer and a GaN layer formed in sequence along the direction away from the substrate; each GaN / AlN superlattice structure forms a conductive channel correspondingly, thereby increasing the output current of the GaN HEMT device. At the same time, the annular gate metal can completely turn off all the conductive channels corresponding to the plurality of superlattice structures from all around, improving the gate control ability and switching performance of the GaN HEMT device, thus achieving the effect of improving the performance of the GaN HEMT device.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A preparation method of a GaN HEMT device, characterized in that, Comprising: Providing a substrate; Epitaxially forming a buffer layer, an interface layer, and an isolation layer on the substrate in a direction away from the substrate in sequence; Epitaxially growing a plurality of superlattice structures on the isolation layer, each superlattice structure including an AlN layer and a GaN layer formed in sequence in a direction away from the substrate; Selectively etching the plurality of superlattice structures to form isolation mesa surfaces on both sides of the isolation layer along a first direction; Removing a first portion of the isolation layer to form a cavity between the plurality of superlattice structures and the interface layer; wherein, the cavity is located below a partial region of the plurality of superlattice structures, and a partial portion of the plurality of superlattice structures located above the cavity forms superlattice nanowires; Epitaxially forming a source electrode and a drain electrode on the plurality of superlattice structures, wherein the source electrode and the drain electrode are located on both sides of the cavity along the first direction; Depositing a gate dielectric in a gate region of the cavity, the gate dielectric surrounding the superlattice nanowires from all around; After the gate dielectric surrounds the superlattice nanowires from all around, depositing a gate metal on the outer periphery of the superlattice nanowires, the gate metal surrounding the superlattice nanowires from all around.

2. The manufacturing method of the GaN HEMT device according to claim 1, wherein Removing the first portion of the isolation layer to form a cavity between the plurality of superlattice structures and the interface layer, including: Coating a photoresist on the exposed isolation layer, exposing and developing the photoresist to form a patterned photoresist; Etching the first portion of the isolation layer using the patterned photoresist as a mask to form a cavity between the plurality of superlattice structures and the interface layer; Removing the patterned photoresist to form the isolation layer covering a partial portion of the interface layer.

3. The manufacturing method of the GaN HEMT device according to claim 2, characterized in that Forming a gate electrode, specifically including: Depositing the gate metal in the gate region of the cavity to form the gate electrode.

4. A GaN HEMT device, characterized in that, Comprising: A substrate, and a buffer layer, an interface layer, and an isolation layer are epitaxially formed on the substrate in a direction away from the substrate in sequence; A plurality of superlattice structures, formed on the isolation layer, a first portion of the isolation layer is missing, such that a cavity is formed between the plurality of superlattice structures and the isolation layer; wherein, each superlattice structure includes an AlN layer and a GaN layer formed in sequence in a direction away from the substrate, and a partial portion of the plurality of superlattice structures located above the cavity forms superlattice nanowires; A source electrode and a drain electrode, formed on the plurality of superlattice structures; wherein, the source electrode and the drain electrode are located on both sides of the cavity along a first direction; A gate metal, surrounding the superlattice nanowires from all around; A gate dielectric, the gate dielectric being wrapped between the gate metal and the superlattice nanowires.

5. The GaN HEMT device according to claim 4, wherein The surface of the isolation layer along a second direction is wider than the width of the plurality of superlattice structures.

6. The GaN HEMT device according to claim 4, wherein The gate metal is filled in the gate region of the cavity and surrounds the superlattice nanowires from all around.

7. The GaN HEMT device according to claim 4, characterized in that, The materials of the interface layer and the gate metal are AlN, and the material of the isolation layer is Al2O3.

8. A method for preparing an electronic device, characterized in that, Including the preparation method of the GaN HEMT device according to any one of claims 1 to 3.

9. An electronic device, characterized in that, Including the GaN HEMT device according to any one of claims 4 - 7.

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