Method and apparatus for monitoring a semiconductor manufacturing process

Abstract

The present disclosure relates to a method and a device for monitoring a semiconductor manufacturing process. The method comprises the following steps: providing a semiconductor structure comprising a material layer to be removed; obtaining a theoretical mass M T of the material layer to be removed; removing the material layer; obtaining an actual mass M R of the material layer that has been removed; and monitoring the residual condition of the material layer in the semiconductor structure according to the actual mass M R and the theoretical mass M T . The present disclosure uses a non-destructive method to monitor the residual condition of the material layer, ensuring the smooth progress of the semiconductor manufacturing process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method and apparatus for monitoring semiconductor manufacturing processes. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes an access transistor and a capacitor. The gate of the access transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage controls the on and off states of the access transistor, allowing data stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] In the fabrication of semiconductor structures such as DRAM, sacrificial layer materials are often used to support the semiconductor structure. In subsequent processes, these sacrificial layer materials need to be removed to ensure smooth process execution. However, due to factors such as the size of the semiconductor structure and the precision of overlay, the sacrificial layer material cannot be completely removed, resulting in residue. This residual sacrificial layer material not only severely impacts the performance of the capacitor, leading to a decrease in semiconductor structure yield, but also hinders the smooth progress of subsequent processes. However, since there is no effective method to monitor the residual sacrificial layer material, destructive methods must be used to determine its condition.

[0004] Therefore, how to monitor the removal of sacrificial layer material using a non-destructive method, so as to understand the removal status in a timely manner and ensure the smooth progress of semiconductor manufacturing processes, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a method and apparatus for monitoring semiconductor manufacturing processes, enabling non-destructive monitoring of sacrificial layer material removal. This allows for timely understanding of the sacrificial layer material removal status, ensuring the smooth operation of the semiconductor manufacturing process and improving the performance of the semiconductor structure.

[0006] According to some embodiments, this disclosure provides a method for monitoring a semiconductor manufacturing process, comprising the following steps:

[0007] A semiconductor structure is provided, the semiconductor structure including a material layer to be removed;

[0008] Obtain the theoretical mass M of the material layer to be removed. T;

[0009] Remove the material layer;

[0010] Obtain the actual mass M of the removed material layer. R ;

[0011] According to the actual mass M R With the theoretical mass M T Monitor the residual status of the material layer in the semiconductor structure.

[0012] In some embodiments, the semiconductor structure includes a substrate, and the material layer is located on the top surface of the substrate; the specific steps for obtaining the theoretical mass of the material layer to be removed include:

[0013] Obtain the projected area S1 of the material layer on the top surface of the substrate, the thickness H of the material layer, and the density D of the material layer;

[0014] The theoretical mass M of the material layer to be removed is calculated using the following formula (1). T :

[0015] M T = S1×H×T (1).

[0016] In some embodiments, the specific steps for obtaining the projected area S1 of the material layer on the top surface of the substrate include:

[0017] Obtain the area S2 of the top surface of the substrate;

[0018] Obtain the area percentage X of the material layer on the top surface of the substrate;

[0019] The projected area S1 of the material layer on the top surface of the substrate is calculated using the following formula (2):

[0020] S1= X×S2 (2).

[0021] In some embodiments, the semiconductor structure further includes a second material layer penetrating the material layer in a direction perpendicular to the top surface of the substrate; the specific steps for obtaining the area percentage X of the material layer on the top surface of the substrate include:

[0022] Obtain the area percentage Y of the second material layer on the top surface of the substrate;

[0023] The area ratio X of the material layer on the top surface of the substrate is calculated using the following formula (3):

[0024] X = 1-Y (3).

[0025] In some embodiments, the specific steps for obtaining the area percentage Y of the second material layer on the top surface of the substrate include:

[0026] Obtain the projected area S3 of the second material layer on the top surface of the substrate;

[0027] The area ratio Y of the second material layer on the top surface of the substrate is calculated based on the area S2 of the top surface of the substrate and the projected area S3 of the second material layer on the top surface of the substrate.

[0028] In some embodiments, the semiconductor structure includes vias penetrating the material layer along a direction perpendicular to the top surface of the substrate, and N vias are spaced apart along a direction parallel to the top surface of the substrate, where N is an integer greater than or equal to 2, and the second material layer covers the inner wall of the vias; the specific steps for obtaining the projected area S3 of the second material layer on the top surface of the substrate include:

[0029] Obtain the diameter D of the through hole;

[0030] The projected area S3 of the second material layer on the top surface of the substrate is calculated using the following formula (4):

[0031] S3 = N×(πD) 2 / 4) (4).

[0032] In some embodiments, the top surface of the substrate includes an array region and a peripheral region located outside the array region. The semiconductor structure includes vias penetrating the material layer along a direction perpendicular to the top surface of the substrate. A plurality of vias are arranged in a hexagonal array along a direction parallel to the top surface of the substrate, and the distance between the centers of adjacent vias is L. The specific steps for obtaining the projected area S3 of the second material layer on the top surface of the substrate include:

[0033] Obtain the area percentage Z of the array region on the top surface of the substrate;

[0034] The projected area S3 of the second material layer on the top surface of the substrate is obtained using the following formula (5):

[0035] S3 = πZS2D 2 / (4L 2 sin60°) (5).

[0036] In some embodiments, the specific steps for obtaining the actual mass of the removed material layer include:

[0037] The mass of the semiconductor structure before the material layer is removed is obtained as a first mass M1;

[0038] The mass of the semiconductor structure after the material layer is removed is obtained as the second mass M2;

[0039] The actual mass M of the material layer removed by the following formula (6) R :

[0040] M R = M1 - M2 (6).

[0041] In some embodiments, based on the actual mass M R With the theoretical mass M T The specific steps for monitoring the residual status of the material layer in the semiconductor structure include:

[0042] The monitoring variable α is calculated using the following formula (7):

[0043] α = M R / M T (7);

[0044] Determine whether the monitored variable α is higher than a preset range. If so, confirm that there is no residue in the material layer of the semiconductor structure.

[0045] According to other embodiments, this disclosure also provides a monitoring device for a semiconductor manufacturing process, comprising:

[0046] Memory, used to store the theoretical mass M of a material layer that needs to be removed from a semiconductor structure. T ;

[0047] Acquisition circuitry for acquiring the actual mass M of the removed material layer. R ;

[0048] A monitoring circuit, connected to the memory and the acquisition circuit, is used to monitor the actual mass M. R With the theoretical mass M T Monitor the residual status of the material layer in the semiconductor structure.

[0049] In some embodiments, the semiconductor structure includes a substrate, and the material layer is located on the top surface of the substrate; the semiconductor manufacturing process monitoring device further includes:

[0050] A computing circuit, connected to the memory, is used to calculate the theoretical mass M of the material layer to be removed using the following formula (1). T :

[0051] M T = S1×H×T (1)

[0052] Wherein, S1 is the projected area of ​​the material layer on the top surface of the substrate, H is the thickness of the material layer, and D is the density of the material layer.

[0053] In some embodiments, the computing circuit is further configured to calculate the projected area S1 of the material layer on the top surface of the substrate using the following formula (2):

[0054] S1 = X×S2 (2)

[0055] Where X is the area ratio of the material layer on the top surface of the substrate, and S2 is the area of ​​the top surface of the substrate.

[0056] In some embodiments, the top surface of the substrate includes an array region and a peripheral region located outside the array region. The semiconductor structure includes vias penetrating the material layer along a direction perpendicular to the top surface of the substrate. A plurality of vias are arranged in a hexagonal array along a direction parallel to the top surface of the substrate. The distance between the centers of adjacent vias is L. The inner walls of the vias are covered with a second material layer. The calculation circuit is further configured to calculate the projected area S1 of the material layer on the top surface of the substrate using the following formulas (5) and (8):

[0057] S3 = πZS2D 2 / (4L 2 (sin60°) (5)

[0058] S1 = S2 – S3 (8)

[0059] Wherein, S3 is the projected area of ​​the second material layer on the top surface of the substrate, Z is the area ratio of the array region on the top surface of the substrate, S2 is the area of ​​the top surface of the substrate, and D is the diameter of the via.

[0060] In some embodiments, the acquisition circuit is used to remove the actual mass M of the material layer using the following formula (6). R :

[0061] M R = M1 - M2 (6)

[0062] Wherein, M1 is the mass of the semiconductor structure before the material layer is removed, and M2 is the mass of the semiconductor structure after the material layer is removed.

[0063] In some embodiments, the monitoring circuit is used to calculate the monitoring variable α using the following formula (7), and to determine whether the monitoring variable α is higher than a preset range. If so, it is confirmed that there is no residue in the material layer of the semiconductor structure.

[0064] α = MR / M T (7).

[0065] This disclosure provides a method and apparatus for monitoring semiconductor manufacturing processes, based on some embodiments, and according to the actual quality M of the removed material layer. R With respect to the theoretical mass M of the material layer that needs to be removed T This method monitors the residual state of the material layer in the semiconductor structure, employing a non-destructive approach to monitor the residual state of the material layer. This allows for timely understanding of the material layer removal process and ensures the smooth operation of the semiconductor manufacturing process. Other embodiments of this disclosure calculate the theoretical mass M of the material layer to be removed through pre-designed layout. T The actual mass M of the removed material layer is confirmed by measuring the mass of the semiconductor structure before and after the removal of the material layer. R It is easy to operate and has a high accuracy rate, thereby improving the monitoring efficiency and accuracy of semiconductor manufacturing processes. Attached Figure Description

[0066] Appendix Figure 1 This is a flowchart of a semiconductor manufacturing process monitoring method according to a specific embodiment of this disclosure;

[0067] Appendix Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure before the material layer is removed;

[0068] Appendix Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure after the material layer has been removed;

[0069] Appendix Figure 4 This is a schematic diagram showing the arrangement of the semiconductor structure array region and the peripheral region in a specific embodiment of this disclosure;

[0070] Appendix Figure 5 This is a schematic diagram of the array region in a specific embodiment of this disclosure;

[0071] Appendix Figure 6 This is a structural block diagram of a monitoring device for semiconductor manufacturing processes according to a specific embodiment of this disclosure;

[0072] Appendix Figure 7 This refers to the change of the monitored variable over time as shown on the display screen in a specific embodiment of this disclosure. Detailed Implementation

[0073] The following detailed description, in conjunction with the accompanying drawings, illustrates the specific implementation methods and devices for monitoring semiconductor manufacturing processes provided in this disclosure.

[0074] This specific embodiment provides a method for monitoring semiconductor manufacturing processes, with appendix... Figure 1 This is a flowchart of a monitoring method for semiconductor manufacturing processes according to a specific embodiment of this disclosure, attached. Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure before the material layer is removed, with attached... Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure after the material layer has been removed. Figures 1-3 As shown, the monitoring method for the semiconductor manufacturing process includes the following steps:

[0075] Step S11: Provide a semiconductor structure, the semiconductor structure including a material layer 22 to be removed;

[0076] Step S12: Obtain the theoretical mass M of the material layer 22 to be removed. T ;

[0077] Step S13: Remove the material layer 22;

[0078] Step S14: Obtain the actual mass M of the removed material layer 22. R ;

[0079] Step S15, based on the actual mass M R With the theoretical mass M T Monitor the residual status of the material layer in the semiconductor structure.

[0080] In some embodiments, the semiconductor structure includes a substrate 20, and the material layer 22 is located on the top surface of the substrate 20; the specific steps for obtaining the theoretical quality of the material layer 22 to be removed include:

[0081] The projected area S1 of the material layer 22 on the top surface of the substrate 20, the thickness H of the material layer 22, and the density D of the material layer 22 are obtained.

[0082] The theoretical mass M of the material layer 22 to be removed is calculated using the following formula (1). T :

[0083] M T = S1×H×T (1).

[0084] The semiconductor structure can be, but is not limited to, DRAM. This specific embodiment uses DRAM as an example for illustration. For instance, the semiconductor structure includes a substrate 20 and a support structure located on the top surface of the substrate 20. The support structure includes a first support layer 21, a second support layer 23, and a third support layer 25 spaced apart along a direction perpendicular to the top surface of the substrate 20. A material layer 22 is located between the first support layer 21 and the second support layer 23. The material layer 22 can be a BPSG (Boro-phospho-silicate Glass) layer. The density D of the material layer 22 is a constant value, which can be calculated based on the material and formation process of the material layer 22, or measured using optical methods. The thickness of the material layer 22 refers to its height along a direction perpendicular to the top surface of the substrate 20. The thickness H of the material layer 22 can be measured using a film thickness measuring device. The projected area S1 of the material layer 22 on the top surface of the substrate 20 can be obtained through layout design, online measurement, or calculation. The theoretical mass M of the material layer 22 to be removed is calculated using the above formula (1). T It is easy to operate and has high accuracy.

[0085] In this specific embodiment, the theoretical mass M of the material layer 22 to be removed is obtained by acquiring the projected area S1 of the material layer 22 on the top surface of the substrate 20, the thickness H of the material layer 22, and the density D of the material layer 22, and by combining the calculation method of formula (1). T This will be illustrated using an example to further improve the accuracy of monitoring the semiconductor manufacturing process. In other specific embodiments, the theoretical mass M can also be obtained by measuring the difference between the weight of the semiconductor structure before the formation of the material layer 22 and the weight of the semiconductor structure after the formation of the material layer 22. T To further simplify the acquisition of the theoretical mass M T The operation.

[0086] In some embodiments, the specific steps for obtaining the projected area S1 of the material layer 22 on the top surface of the substrate 20 include:

[0087] Obtain the area S2 of the top surface of the substrate 20;

[0088] Obtain the area percentage X of the material layer 22 on the top surface of the substrate 20;

[0089] The projected area S1 of the material layer 22 on the top surface of the substrate 20 is calculated using the following formula (2):

[0090] S1= X×S2 (2).

[0091] Specifically, when the projection of the material layer 22 onto the top surface of the substrate 20 is irregular or discrete, the area ratio X of the material layer 22 on the top surface of the substrate 20 can be obtained through layout design and other information. This eliminates the need to directly measure the projected area S1 of the material layer 22 on the top surface of the substrate 20, simplifying the process and further improving the real-time performance of semiconductor manufacturing process monitoring. The area ratio of the material layer 22 on the top surface of the substrate 20 refers to the ratio between the area occupied by the material layer 22 on the top surface of the substrate 20 and the area of ​​the top surface of the substrate 20.

[0092] In some embodiments, the semiconductor structure further includes a second material layer 24 extending through the material layer 22 in a direction perpendicular to the top surface of the substrate 20, such as... Figure 2 As shown; the specific steps for obtaining the area ratio X of the material layer 22 on the top surface of the substrate 20 include:

[0093] Obtain the area percentage Y of the second material layer 24 on the top surface of the substrate 20;

[0094] The area ratio X of the material layer 22 on the top surface of the substrate 20 is calculated using the following formula (3):

[0095] X = 1-Y (3).

[0096] Specifically, the semiconductor structure further includes a second material layer 24 that penetrates the material layer 22 along a direction perpendicular to the top surface of the substrate 20. Since a portion of the material layer 22 is removed during the formation of the second material layer 24, and the second material layer 24 disperses the material layer 22 into discrete parts, directly obtaining the projected area S1 of the material layer 22 on the top surface of the substrate 20, or directly obtaining the area percentage X of the material layer 22 on the top surface of the substrate 20, is difficult. Therefore, the area percentage Y of the second material layer 24 on the top surface of the substrate 20 can be obtained through layout design and other information. Then, the area percentage X of the material layer 22 on the top surface of the substrate 20 can be indirectly calculated according to formula (3), thereby further simplifying the acquisition of the theoretical mass M. T The operation.

[0097] In some embodiments, the semiconductor structure further includes a second material layer 24 extending through the material layer 22 in a direction perpendicular to the top surface of the substrate 20; the specific steps for obtaining the area percentage Y of the second material layer 24 on the top surface of the substrate 20 include:

[0098] Obtain the projected area S3 of the second material layer 24 on the top surface of the substrate 20;

[0099] The area ratio Y of the second material layer 24 on the top surface of the substrate 20 is calculated based on the area S2 of the top surface of the substrate 20 and the projected area S3 of the second material layer 24 on the top surface of the substrate 20.

[0100] In some embodiments, the semiconductor structure includes a through-hole 26 penetrating the material layer 22 along a direction perpendicular to the top surface of the substrate 20, and N through-holes 26 are spaced apart along a direction parallel to the top surface of the substrate 20, where N is an integer greater than or equal to 2, and the second material layer 24 covers the inner wall of the through-hole 26; the specific steps for obtaining the projected area S3 of the second material layer 24 on the top surface of the substrate 20 include:

[0101] Obtain the diameter D of the through hole 26;

[0102] The projected area S3 of the second material layer 24 on the top surface of the substrate 20 is calculated using the following formula (4):

[0103] S3 = N×(πD) 2 / 4) (4).

[0104] The following description uses a DRAM semiconductor structure and the second material layer 24 as the lower electrode layer as an example. For instance, the semiconductor structure includes multiple vias 26 penetrating the support structure along a direction perpendicular to the top surface of the substrate 20, and N vias 26 are spaced apart along a direction parallel to the top surface of the substrate 20, with the projection of each via 26 onto the top surface of the substrate 20 being circular. N second material layers 24 cover the inner walls (including the sidewalls and bottom walls) of the N vias 26. In one example, the diameter of the vias 26 and the number of vias 26 (i.e., the specific value of N) can be directly obtained from layout design and other information to further improve the efficiency of obtaining the projected area S3 of the second material layer 24 on the top surface of the substrate 20. In another example, the diameter of the via 26 can be obtained by measuring the characteristic dimensions of the formed via 26, and the specific number of the formed via 26 in the semiconductor structure can also be obtained by measurement. This avoids the problem of inaccurate calculation of the projected area S3 of the second material layer 24 on the top surface of the substrate 20 due to errors between the layout design and the actual manufacturing process, thereby further improving the accuracy and reliability of semiconductor manufacturing process monitoring.

[0105] Appendix Figure 4This is a schematic diagram showing the arrangement of the semiconductor structure array region and the peripheral region in a specific embodiment of this disclosure, with appended... Figure 5 This is a schematic diagram of the array region in a specific embodiment of this disclosure. In some embodiments, the top surface of the substrate 20 includes an array region 40 and a peripheral region 41 located outside the array region 40. The semiconductor structure includes vias 26 penetrating the material layer 22 along a direction perpendicular to the top surface of the substrate 20. A plurality of vias 26 are arranged in a hexagonal array along a direction parallel to the top surface of the substrate 20, and the distance between the centers of adjacent vias 26 is L. The specific steps for obtaining the projected area S3 of the second material layer 24 on the top surface of the substrate 20 include:

[0106] Obtain the area percentage Z of the array region 40 on the top surface of the substrate 20;

[0107] The projected area S3 of the second material layer 24 on the top surface of the substrate 20 is obtained using the following formula (5):

[0108] S3 = πZS2D 2 / (4L 2 sin60°) (5).

[0109] The following description uses a DRAM semiconductor structure and the second material layer 24 as the lower electrode layer as an example. The top surface of the substrate 20 includes a plurality of array regions 40 spaced apart along a direction parallel to the top surface of the substrate 20, and a peripheral region 41 located outside the array regions 40, such as... Figure 4 As shown. The array region 40 is used for information storage, and the peripheral region 41 is used for transmitting control signals to the array region 40. The support structure and the second material layer 24 are both located in the array region 40. The area ratio Z of the array region 40 on the top surface of the substrate 20 can be obtained through information such as layout design, or by measuring the formed semiconductor structure. In one example, after obtaining the area ratio Z of the array region 40 on the top surface of the substrate 20 through information such as layout design, the projected area S4 of the array region 41 on the top surface of the substrate 20 can be obtained using the following formula (9):

[0110] S4 = Z×S2 (9).

[0111] by Figure 5 Taking one of the array regions 40 shown as an example, the array region 40 includes a plurality of through holes 26 arranged in a hexagonal array. Figure 5Taking the four through holes 26 connected by dashed lines to form a rhombus as an example, the distance L between the centers of two adjacent through holes 26 is taken as the side length of the rhombus, then the area of ​​the rhombus is L. 2 sin60°, the area of ​​the through hole 26 located inside the rhombus is πD 2 / 4. Since the array region 40 is composed of a plurality of rhombuses, the ratio between the area of ​​the rhombus and the area occupied by the through-hole inside the rhombus is equal to the ratio between the array region 40 and the area occupied by the second material layer 24 within the array region 40. Therefore, formula (5) can be obtained according to the following formula (10) and the above formula (9):

[0112] S3 / S4 = πD 2 / 4(4L 2 sin60°) (10).

[0113] This specific embodiment is illustrated using the example of the through holes arranged in a hexagonal array in the array region. In other specific embodiments, the through holes can also be arranged in a quadrilateral array in the array region. In this case, four adjacent through holes inside the array region are arranged in a square, and the ratio between the area of ​​the square and the area occupied by the through holes inside the square is equal to the ratio between the array region 40 and the area occupied by the second material layer 24 within the array region 40.

[0114] In some embodiments, the specific steps for obtaining the actual mass of the removed material layer 22 include:

[0115] The mass of the semiconductor structure before the material layer 22 is removed is obtained as a first mass M1;

[0116] The mass of the semiconductor structure after removing the material layer 22 is obtained as the second mass M2;

[0117] The actual mass M of the material layer 22 removed using the following formula (6) R :

[0118] M R = M1 - M2 (6).

[0119] In one example, the second mass M2 can be obtained after the removal process of the material layer 22 is completed, further simplifying the monitoring method of the semiconductor manufacturing process. In another example, the second mass M2 of the semiconductor structure can also be obtained in real time during the removal of the material layer 22, so as to timely understand the actual mass M of the removed material layer 22. R This helps to enable online, real-time monitoring of semiconductor manufacturing processes.

[0120] In some embodiments, based on the actual mass M R With the theoretical mass M T The specific steps for monitoring the residual status of the material layer 22 in the semiconductor structure include:

[0121] The monitoring variable α is calculated using the following formula (7):

[0122] α = M R / M T (7);

[0123] Determine whether the monitored variable α is higher than the preset range T. If so, confirm that there is no residue in the material layer 22 in the semiconductor structure.

[0124] Appendix Figure 7 This refers to the change of the monitored variable α over time displayed on the screen in this specific embodiment. For example, the change of the monitored variable α over time can be displayed on the screen in real time, so that the user can intuitively and promptly know the residual status of the material layer 22. If the monitored variable α is higher than the preset range T, it is confirmed that there is no residue of the material layer 22 in the semiconductor structure; if the monitored variable α is lower than the preset range T, it is confirmed that there is residue of the material layer 22 in the semiconductor structure, and the material layer 22 needs to be further removed. The specific value of the preset range T can be determined according to the specific type of the material layer 22 and the specific type of subsequent process steps, and this specific embodiment does not limit it in this way.

[0125] This specific embodiment also provides a semiconductor manufacturing process monitoring device. (See attached document) Figure 6 This is a structural block diagram of a monitoring device for a semiconductor manufacturing process according to a specific embodiment of this disclosure. The monitoring device for the semiconductor manufacturing process provided in this specific embodiment can employ, for example... Figures 1-5 and Figure 7 The semiconductor manufacturing process monitoring method shown is used to monitor the semiconductor manufacturing process. For example... Figures 1-7 As shown, the monitoring device for the semiconductor manufacturing process includes:

[0126] Memory 61 is used to store the theoretical mass M of the material layer 22 that needs to be removed in the semiconductor structure. T ;

[0127] Acquisition circuit 63 is used to acquire the actual mass M of the removed material layer 22. R ;

[0128] Monitoring circuit 64, connected to memory 61 and acquisition circuit 63, is used to monitor the actual mass M. RWith the theoretical mass M T Monitor the residual status of the material layer 22 in the semiconductor structure.

[0129] The semiconductor structure can be, but is not limited to, DRAM. This specific embodiment uses DRAM as an example for illustration. For instance, the monitoring device for the semiconductor manufacturing process includes a processor 60, and the memory 61, the acquisition circuit 63, and the monitoring circuit 64 are all electrically connected to the processor 60. The memory 61 stores the theoretical quality M. T The actual mass M is transmitted through the processor 60 to the monitoring circuit 64 and the acquisition circuit 63. R The data is transmitted through the processor to the monitoring circuit 64, enabling the monitoring circuit 64 to determine the actual mass M. R With the theoretical mass M T Monitor the residual status of the material layer 22 in the semiconductor structure.

[0130] In one example, the monitoring device for the semiconductor manufacturing process further includes a display screen 65 connected to the monitoring circuit 64, for displaying in real time, in graphical and / or character form, the residual status of the material layer 22 in the semiconductor structure based on the monitoring results of the monitoring circuit 64.

[0131] In some embodiments, the semiconductor structure includes a substrate 20, and the material layer 22 is located on the top surface of the substrate 20; the semiconductor manufacturing process monitoring device further includes:

[0132] The computing circuit 62, connected to the memory 61, is used to calculate the theoretical mass M of the material layer 22 to be removed using the following formula (1). T :

[0133] M T = S1×H×T (1)

[0134] Wherein, S1 is the projected area of ​​the material layer 22 on the top surface of the substrate 20, H is the thickness of the material layer 22, and D is the density of the material layer 22.

[0135] Specifically, the density D of the material layer 22 is a constant value, which can be calculated based on the material and forming process of the material layer 22, or measured using optical methods. The thickness of the material layer 22 refers to the height of the material layer 22 in the direction perpendicular to the top surface of the substrate 20. The thickness H of the material layer 22 can be measured using a film thickness measuring device. The projected area S1 of the material layer 22 on the top surface of the substrate 20 can be obtained through layout design, online measurement, or calculation. The theoretical mass M of the material layer 22 to be removed is calculated using the above formula (1). T It is easy to operate and has high accuracy.

[0136] In some embodiments, the computing circuit 62 is further configured to calculate the projected area S1 of the material layer 22 on the top surface of the substrate 20 using the following formula (2):

[0137] S1 = X×S2 (2)

[0138] Wherein, X is the area ratio of the material layer 22 on the top surface of the substrate 20, and S2 is the area of ​​the top surface of the substrate 20.

[0139] Specifically, when the projection of the material layer 22 onto the top surface of the substrate 20 is irregular or discrete, the area ratio X of the material layer 22 on the top surface of the substrate 20 can be obtained through layout design and other information. This eliminates the need to directly measure the projected area S1 of the material layer 22 on the top surface of the substrate 20, simplifying the process and further improving the real-time performance of semiconductor manufacturing process monitoring. The area ratio of the material layer 22 on the top surface of the substrate 20 refers to the ratio between the area occupied by the material layer 22 on the top surface of the substrate 20 and the area of ​​the top surface of the substrate 20.

[0140] In some embodiments, the top surface of the substrate 20 includes an array region 40 and a peripheral region 41 located outside the array region 40. The semiconductor structure includes vias 26 penetrating the material layer 22 along a direction perpendicular to the top surface of the substrate 20. A plurality of vias 26 are arranged in a hexagonal array along a direction parallel to the top surface of the substrate 20. The distance between the centers of adjacent vias 26 is L. The inner wall of the via 26 is covered with a second material layer 24. The calculation circuit 62 is further used to calculate the projected area S1 of the material layer 22 on the top surface of the substrate 20 using the following formulas (5) and (8):

[0141] S3 = πZS2D 2 / (4L 2(sin60°) (5)

[0142] S1 = S2 – S3 (8)

[0143] Wherein, S3 is the projected area of ​​the second material layer 24 on the top surface of the substrate 20, Z is the area ratio of the array region 40 on the top surface of the substrate 20, S2 is the area of ​​the top surface of the substrate 20, and D is the diameter of the through hole 26.

[0144] In some embodiments, the acquisition circuit 63 is used to remove the actual mass M of the material layer using the following formula (6). R :

[0145] M R = M1 - M2 (6)

[0146] Wherein, M1 is the mass of the semiconductor structure before the material layer 22 is removed, and M2 is the mass of the semiconductor structure after the material layer 22 is removed.

[0147] In one example, the second mass M2 can be obtained after the removal process of the material layer 22 is completed, further simplifying the monitoring method of the semiconductor manufacturing process. In another example, the second mass M2 of the semiconductor structure can also be obtained in real time during the removal of the material layer 22, so as to timely understand the actual mass M of the removed material layer 22. R This helps to enable online, real-time monitoring of semiconductor manufacturing processes.

[0148] In some embodiments, the monitoring circuit 64 is used to calculate the monitoring variable α using the following formula (7), and to determine whether the monitoring variable α is higher than a preset range. If so, it is confirmed that there is no residue in the material layer 22 in the semiconductor structure.

[0149] α = M R / M T (7).

[0150] For example, the changes of the monitored variable α over time can be displayed on a screen in real time, such as... Figure 7As shown, this allows users to intuitively and promptly understand the residual status of the material layer 22. If the monitored variable α is higher than the preset range T, it is confirmed that there is no residue of the material layer 22 in the semiconductor structure; if the monitored variable α is lower than the preset range T, it is confirmed that there is residue of the material layer 22 in the semiconductor structure, and the material layer 22 needs to be further removed. The specific value of the preset range T can be determined based on the specific type of the material layer 22 and the specific type of subsequent process steps, and this specific embodiment does not limit this.

[0151] This specific embodiment provides a semiconductor manufacturing process monitoring method and device, based on the actual quality M of the removed material layer. R With respect to the theoretical mass M of the material layer that needs to be removed T This method monitors the residual state of the material layer in the semiconductor structure using a non-destructive approach, allowing for timely understanding of the material layer removal process and ensuring smooth semiconductor manufacturing. In other embodiments of this specific implementation, the theoretical mass M of the material layer to be removed is calculated through pre-designed layout. T The actual mass M of the removed material layer is confirmed by measuring the mass of the semiconductor structure before and after the removal of the material layer. R It is easy to operate and has a high accuracy rate, thereby improving the monitoring efficiency and accuracy of semiconductor manufacturing processes.

[0152] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for monitoring a semiconductor manufacturing process, comprising the steps of: providing a semiconductor structure comprising a material layer to be removed; removing the material layer; acquiring a theoretical mass M of the material layer to be removed T ; the semiconductor structure comprising a substrate, the material layer being on a top surface of the substrate; acquiring an actual mass M of the removed material layer R ; According to the actual mass M R With the theoretical mass M T Monitoring the residual situation of the material layer in the semiconductor structure; the specific step of obtaining a theoretical mass of the material layer to be removed comprising: obtaining a projected area S1 of the material layer on the top surface of the substrate, a thickness H of the material layer, and a density D of the material layer. 2.The method for monitoring a semiconductor manufacturing process according to claim 1, wherein the specific step of obtaining the projected area S1 of the material layer on the top surface of the substrate comprises: The theoretical mass M of the material layer to be removed is calculated using the following equation (1) T : M T = S1x H x D (1). obtaining an area S2 of the top surface of the substrate; obtaining an area ratio X of the material layer on the top surface of the substrate; calculating the projected area S1 of the material layer on the top surface of the substrate using the following formula (2) : S1= X×S2(2). 3.The method for monitoring a semiconductor manufacturing process according to claim 2, wherein the semiconductor structure further comprises a second material layer penetrating the material layer in a direction perpendicular to the top surface of the substrate; the specific step of obtaining the area ratio X of the material layer on the top surface of the substrate comprises: obtaining an area ratio Y of the second material layer on the top surface of the substrate; calculating the area ratio X of the material layer on the top surface of the substrate using the following formula (3) : X = 1-Y(3). 4.The method for monitoring a semiconductor manufacturing process according to claim 3, wherein the specific step of obtaining the area ratio Y of the second material layer on the top surface of the substrate comprises: obtaining a projected area S3 of the second material layer on the top surface of the substrate; calculating the area ratio Y of the second material layer on the top surface of the substrate according to the area S2 of the top surface of the substrate and the projected area S3 of the second material layer on the top surface of the substrate. 5.The method for monitoring a semiconductor manufacturing process according to claim 4, wherein the semiconductor structure comprises a via penetrating the material layer in a direction perpendicular to the top surface of the substrate, and N of the vias are arranged in a direction parallel to the top surface of the substrate with a spacing, wherein N is an integer greater than or equal to 2, and the second material layer covers an inner wall of the via; the specific step of obtaining the projected area S3 of the second material layer on the top surface of the substrate comprises: obtaining a diameter d of the via; calculating the projected area S3 of the second material layer on the top surface of the substrate using the following formula (4) : 6.The method for monitoring a semiconductor manufacturing process according to claim 4, wherein the top surface of the substrate comprises an array region and a peripheral region outside the array region, the semiconductor structure comprises a via penetrating the material layer in a direction perpendicular to the top surface of the substrate, and a plurality of the vias are arranged in a hexagonal array in a direction parallel to the top surface of the substrate, and a distance between centers of adjacent vias is L. ​ ​ ​ ​ S3= N x (πd 2 / 4)(4). ​ ​ The specific step of obtaining the projection area S3 of the second material layer on the top surface of the substrate comprises: obtaining an area proportion Z of the array region on the top surface of the substrate; The projection area S3 of the second material layer on the top surface of the substrate is obtained by using the following formula (5): S3= πZS2d 2 / (4L 2 sin60°)(5).

7. A semiconductor manufacturing process monitoring device, characterized in that, comprises: a memory for storing a theoretical mass M of a material layer to be removed in the semiconductor structure T ; acquisition circuit for acquiring the actual mass M of the removed material layer R ; a monitoring circuit, connected to the memory and to the acquisition circuit, for determining the actual mass M R in accordance with the theoretical mass M T monitoring the residual condition of the material layer in the semiconductor structure; The semiconductor structure comprises a substrate, and the material layer is located on the top surface of the substrate; The semiconductor manufacturing process monitoring device further comprises: A computing circuit, connected to the memory, for calculating a theoretical mass M of the material layer to be removed using the following equation (1) T : M T = S1×H×D(1) wherein S1 is the projection area of the material layer on the top surface of the substrate, H is the thickness of the material layer, and D is the density of the material layer.

8. The semiconductor manufacturing process monitoring device according to claim 7, characterized in that, The top surface of the substrate comprises an array region and a peripheral region outside the array region, the semiconductor structure comprises a through hole penetrating through the material layer in a direction perpendicular to the top surface of the substrate, a plurality of through holes are arranged in a hexagonal array in a direction parallel to the top surface of the substrate, the distance between the centers of adjacent through holes is L, the inner wall of the through hole is covered with a second material layer; the calculation circuit is further used to calculate the projection area S1 of the material layer on the top surface of the substrate by using the following formulas (5) and (8): S3= πZS2d 2 / (4L 2 sin60°)(5) S1= S2– S3(8) Wherein S3 is the projection area of the second material layer on the top surface of the substrate, Z is the area proportion of the array region on the top surface of the substrate, S2 is the area of the top surface of the substrate, and d is the diameter of the through hole.

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