Method for avoiding de-bonding marks and method for manufacturing a power device

Abstract

Embodiments of the present application relate to a method for avoiding debonding marks and a preparation method of a power device. The method comprises the following steps: providing a bonded wafer pair, the bonded wafer pair comprising a first wafer and a second wafer bonded to each other, the first wafer having a bonding surface facing the second wafer and a back surface away from the second wafer, and a first metal layer formed on the back surface of the first wafer; performing an oxidation process to oxidize a surface layer of the first metal layer into a metal oxide layer; placing the bonded wafer pair on a debonding machine, and contacting the metal oxide layer with a stage of the debonding machine; and debonding the bonded wafer pair by using the debonding machine under heating. In this way, the generation of debonding marks is avoided, and the material of the back surface of the first wafer is consistent and the surface color is uniform. Moreover, the scheme provided by the embodiments of the present application has little influence on packaging and meets the packaging requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a method for avoiding unbonding marks and a preparation method of a power device. BACKGROUND

[0002] With the development of the requirement of electronic products towards miniaturization, semiconductor chips also develop towards thinner and thinner. However, the wafer is prone to have a high breakage rate in the transmission process. In addition, a certain support needs to be provided when the wafer is processed, otherwise the wafer is prone to be bent and deformed due to stress. Therefore, in order to process and treat such ultra-thin wafers and improve the yield and performance of products, the functional wafer needs to be temporarily bonded with a carrier wafer first. After bonding, the functional wafer and the carrier wafer are bonded together to form a bonded wafer pair, and then the functional wafer can be thinned, an ohmic contact layer is formed on the back surface, and the like. After the related processes are completed, the functional wafer and the carrier wafer are separated, which is called unbonding. Finally, the thinned functional wafer is cleaned, cut, packaged, and the like, and the processing process of the ultra-thin functional wafer is completed.

[0003] In order to meet the functional needs and packaging needs of semiconductor chips, a back surface of the functional wafer is formed with an ohmic contact layer by a deposition process. The outermost metal of the ohmic contact layer is exposed and is prone to be oxidized. The unbonding process usually needs to be performed at a certain temperature. The outermost metal of the ohmic contact layer is in contact with a chuck of an unbonding machine, which causes the back surface of the functional wafer to be unevenly heated, and finally causes the outermost metal to be unevenly oxidized, and a concentric circle color difference corresponding to the pattern of the chuck of the unbonding machine is formed on the surface. SUMMARY

[0004] Therefore, the embodiments of the present application provide a method for avoiding unbonding marks and a preparation method of a power device to solve at least one problem in the background art.

[0005] In a first aspect, the embodiments of the present application provide a method for avoiding unbonding marks, which comprises the following steps.

[0006] providing a bonded wafer pair, the bonded wafer pair comprising a first wafer and a second wafer bonded to each other, the first wafer having a bonding surface facing the second wafer and a back surface away from the second wafer, and a first metal layer formed on the back surface of the first wafer;

[0007] performing an oxidation process to oxidize a surface layer of the first metal layer into a metal oxide layer;

[0008] The bonded wafer pair is arranged on a debonding machine, the metal oxide layer is in contact with a stage of the debonding machine, and the bonded wafer pair is debonded by the debonding machine under heating.

[0009] In an optional embodiment of the first aspect of the present application, the material of the first metal layer comprises silver.

[0010] In an optional embodiment of the first aspect of the present application, the oxidation process is performed at a first temperature, and the debonding of the bonded wafer pair is performed at a second temperature, the first temperature being not higher than the second temperature.

[0011] In an optional embodiment of the first aspect of the present application, the oxidation process is performed at a temperature of 130-148°C, and the oxidation process is performed for a time of 1.5-2.5H.

[0012] In an optional embodiment of the first aspect of the present application, the first wafer is used to prepare a transistor, and the first metal layer is a drain electrode layer of the transistor.

[0013] In an optional embodiment of the first aspect of the present application, the back surface of the first wafer further comprises a second metal layer and a third metal layer, the third metal layer, the second metal layer and the first metal layer are arranged in a sequence of being away from the back surface of the first wafer, the material of the third metal layer comprises titanium, and the material of the second metal layer comprises nickel.

[0014] In an optional embodiment of the first aspect of the present application, the first wafer is a silicon carbide wafer, and / or the second wafer is a sapphire wafer.

[0015] In an optional embodiment of the first aspect of the present application, in the bonded wafer pair, the first wafer and the second wafer are temporarily bonded by an organic bonding glue.

[0016] In a second aspect, the embodiments of the present application provide a method for preparing a power device, the method comprising the steps in the method for avoiding debonding marks according to any one of the first aspect.

[0017] In an optional embodiment of the second aspect of the present application, after the bonded wafer pair is debonded by the debonding machine, the method further comprises:

[0018] forming a solder layer on the metal oxide layer;

[0019] under heating, the first metal layer and the solder layer are fused through the metal oxide layer.

[0020] The method for avoiding debonding marks and the method for fabricating power devices provided in this application embodiment provide a bonding wafer pair, which includes a first wafer and a second wafer bonded together. The first wafer has a bonding surface facing the second wafer and a back surface away from the second wafer, and a first metal layer is formed on the back surface of the first wafer. An oxidation process is performed to oxidize the surface of the first metal layer into a metal oxide layer. The bonding wafer pair is placed on a debonding machine, with the metal oxide layer in contact with the stage of the debonding machine. The bonding wafer pair is debonded using the debonding machine under heating conditions. In this way, the generation of debonding marks is avoided, ensuring that the back surface material of the first wafer is consistent and the surface color is uniform. Furthermore, the solution provided in this application embodiment has almost no impact on packaging and meets packaging requirements.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 The back-side topography of the silicon carbide wafer after the formation of the back-side ohmic contact layer;

[0024] Figure 2 This is a back-side topography image of a silicon carbide wafer after debonding in a related technology.

[0025] Figure 3 To deconstruct the surface structure diagram of the bonding machine stage;

[0026] Figure 4 A flowchart illustrating the method for avoiding unbonded imprints provided in this application embodiment;

[0027] Figures 5 to 9 This is a schematic diagram of the cross-sectional structure of a power device during its fabrication process. Detailed Implementation

[0028] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0035] Please refer to Figure 1 and Figure 2 When fabricating power devices using ultrathin silicon carbide (SiC) wafers, the inventors discovered that after debonding, the morphology of the back side of the silicon carbide wafer changed significantly, producing multiple concentric color differences.

[0036] After comparing the surface structure with that of the debonding machine's stage, it was found that the color difference generated on the back side of the silicon carbide wafer corresponds to the pattern of the surface structure of the debonding machine's stage. For example... Figure 3 As shown, the debonding machine's stage has multiple concentric rings of protrusions. During debonding, these protrusions contact the back side of the silicon carbide wafer and heat the bonded wafer pair. However, in the region between the protrusions, the bonded wafer pair, especially the outermost metal of the back ohmic contact layer, receives significantly less heat than it does at the protrusion locations. This uneven heating also leads to uneven oxidation of the outermost metal.

[0037] Based on this, embodiments of this application provide a method for avoiding the unbonding of imprints. Please refer to [link / reference]. Figure 4 The method includes:

[0038] Step S01, providing a bonding wafer pair, the bonding wafer pair including a first wafer and a second wafer bonded to each other, the first wafer having a bonding surface facing the second wafer and a back surface away from the second wafer, a first metal layer being formed on the back surface of the first wafer;

[0039] Step S02: Perform an oxidation process to oxidize the surface of the first metal layer into a metal oxide layer;

[0040] Step S03: The bonded wafer pair is placed on the debonding machine, the metal oxide layer is in contact with the stage of the debonding machine, and the bonded wafer pair is debonded under heating conditions using the debonding machine.

[0041] Understandably, the embodiments of this application add an oxidation process before debonding, so that the surface of the first metal layer is oxidized into a metal oxide layer. Thus, during the debonding process, the metal oxide layer can act as a protective layer to prevent the surface of the first metal layer from oxidizing unevenly due to uneven heating, thereby avoiding the formation of color differences, that is, avoiding the generation of debonding marks, and ensuring that the back material of the first wafer is consistent and the surface color is uniform. Furthermore, the solution provided by the embodiments of this application has almost no impact on packaging and meets packaging requirements.

[0042] Below, we will combine Figures 5 to 9 The diagram shown is a cross-sectional view of the power device during its fabrication process. Figure 4 The method for avoiding unbonded imprints will be explained in further detail.

[0043] First, please refer to Figure 5 Step S01 is performed to provide a bonding wafer pair, which includes a first wafer 100 and a second wafer 200 bonded to each other.

[0044] The first wafer 100 can also be called a functional wafer, and the second wafer 200 can also be called a carrier wafer. The second wafer 200 is used to support the first wafer 100, thereby preventing the first wafer 100 from bending and deforming, and also preventing the first wafer 100 from breaking.

[0045] In a specific example, the first wafer 100 is a silicon carbide wafer, used for fabricating silicon carbide devices. Silicon carbide, as one of the important third-generation semiconductor materials, exhibits excellent performance in high temperature, high frequency, high power, and radiation resistance. Ultra-thin silicon carbide wafers are beneficial to the electrical parameter VF.

[0046] The second wafer 200 can specifically be a sapphire wafer. Furthermore, a high-temperature resistant wax can be used for temporary bonding between the silicon carbide wafer and the sapphire wafer.

[0047] Of course, this application is not limited to this; the material of the second wafer 200 can also be glass, silicon, etc. The material of the first wafer 100 is also not limited to silicon carbide. Other organic bonding agents can also be used to form a temporary bond between the first wafer 100 and the second wafer 200.

[0048] Understandably, when the first wafer 100 and the second wafer 200 are temporarily bonded using wax or other organic bonding adhesives, the debonding process needs to be carried out at a certain temperature. That is, the bonded wafer pair needs to be debonded using a debonding machine under heated conditions.

[0049] The second wafer 200 can be selected as a wafer with a diameter similar to that of the first wafer 100.

[0050] The first wafer 100 has a bonding surface 101 facing the second wafer 200 and a back surface 102 away from the second wafer 200.

[0051] Since the back surface 102 of the first wafer 100 may be thinned in subsequent processes, the back surface 102 may vary in each step. It does not refer to a specific fixed surface, but rather to the exposed surface opposite the bonding surface 101 in the corresponding step.

[0052] Next, please refer to Figure 6 The back surface 102 of the first wafer 100 is thinned.

[0053] Specifically, the thickness of the first wafer 100 can be reduced to the target thickness by methods such as grinding.

[0054] Understandably, whether or not to thin the back side 102 of the first wafer 100 can be selected according to actual needs, and this embodiment does not necessarily include the step of thinning the back side 102 of the first wafer 100.

[0055] Next, please refer to Figure 7 A first metal layer 111 is formed on the back side of the first wafer 100.

[0056] In actual fabrication, an ohmic contact layer is formed on the back side of the first wafer 100, and the outermost metal layer of the ohmic contact layer is the aforementioned first metal layer 111. The ohmic contact layer formed on the back side of the wafer can also be called the backside metal (BM), or simply "back gold". Back gold is very important for signal transmission between the device and external circuits.

[0057] The ohmic contact layer (including the first metal layer 111) can be formed using a PVD (Physical Vapor Deposition) process.

[0058] As an optional specific example, the first wafer 100 is used to fabricate transistors. Further, the first wafer 100 is a silicon carbide wafer, and the first wafer 100 is used to fabricate power devices, such as silicon carbide Schottky diodes (SBDs), silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs), etc.

[0059] The first metal layer 111 is specifically the drain electrode layer (or a part of the drain electrode layer) of the transistor.

[0060] Understandably, in some specific scenarios, the ohmic contact layer, the back metal layer, the back gold layer, and the drain electrode layer represent the same structure.

[0061] Considering cost issues, the material of the first metal layer 111 includes silver (Ag). Further, the first metal layer 111 is a silver layer.

[0062] Understandably, silver is easily oxidized, thus the problem of unbonding marks is more pronounced. The method provided in this application can effectively avoid the generation of unbonding marks. However, this does not mean that this application is only applicable to cases where the material of the first metal layer 111 includes silver. Strictly speaking, metal materials will undergo some degree of oxidation when heated and in the presence of oxygen in the environment. Therefore, even if the material of the first metal layer 111 includes other metal materials, the method provided in this application can be used to oxidize the surface of the first metal layer 111 before unbonding to form a metal oxide layer, thereby serving as a protective layer to avoid the generation of unbonding marks.

[0063] Please continue to refer to this. Figure 7 In addition to the first metal layer 111, a second metal layer 112 and a third metal layer 113 may also be formed on the back side of the first wafer 100; the third metal layer 113, the second metal layer 112, and the first metal layer 111 are arranged in a sequence away from the back side of the first wafer 100; the material of the third metal layer 113 includes titanium (Ti); the material of the second metal layer 112 includes nickel (Ni). In this way, a Ti / Ni / Ag composite drain electrode layer is formed, which allows it to be bonded to the chip using lead-free solder during subsequent chip packaging.

[0064] Next, please refer to Figure 8 The method proceeds to step S02, where an oxidation process is performed to oxidize the surface of the first metal layer 111 into a metal oxide layer 120.

[0065] Understandably, the oxidation process can relatively uniformly oxidize the surface of the first metal layer 111, thereby forming a relatively uniform metal oxide layer 120.

[0066] Considering that excessively high temperatures may cause the bonding adhesive between the first wafer 100 and the second wafer 200 to volatilize, especially when organic bonding adhesives (such as wax temporary bonding) are used, as wax is easily volatilized at high temperatures, the oxidation process may contaminate the first wafer 100. Therefore, in practice, the oxidation process can be carried out at a first temperature, and the debonding of the bonded wafer pair can be carried out at a second temperature, with the first temperature not exceeding the second temperature.

[0067] It should be noted that the "first temperature" and "second temperature" here do not refer to specific temperature values, i.e., they are not temperature point values. In actual operation, the temperature of the oxidation process and the temperature of the debonding process may fluctuate within a certain range. Therefore, even if carried out within a certain temperature range, the maximum value of the first temperature will still not be higher than the minimum value of the second temperature.

[0068] Optionally, the first temperature is less than 150°C.

[0069] Considering that the lower the initial temperature, the longer the oxidation process requires, in actual operation, the oxidation process is carried out at a temperature of, for example, 130℃ to 148℃, and the corresponding execution time is, for example, 1.5H to 2.5H. This ensures both a suitable process time and the formation of a suitable oxidation thickness.

[0070] Next, please refer to Figure 9 In step S03, the bonded wafer pair is placed on the debonding machine, and the metal oxide layer 120 is in contact with the stage 310 of the debonding machine. The bonded wafer pair is debonded under heating conditions using the debonding machine.

[0071] like Figure 9 As shown, after debonding, the first wafer 100 and the second wafer 200 separate.

[0072] Based on this, the present application also provides a method for fabricating a power device, which includes the steps of the method for avoiding debonding imprints in any of the above embodiments.

[0073] After debonding the bonded wafer pair using a debonding machine, the method may further include: forming a solder layer (not shown) on the metal oxide layer 120; and fusing the first metal layer 111 and the solder layer through the metal oxide layer 120 under heating conditions.

[0074] Experiments have verified that the above-mentioned scheme does not affect the electrical parameters of the power device. Furthermore, push-pull force and void ratio data also show that the void ratio and push-pull force meet the packaging requirements after adding the oxidation process. In addition, the power device prepared in the comparative example has a yield of 91.83%, while the power device prepared in the specific example of this application has a yield of 94.17%. The only difference between the comparative example and the specific example is that the specific example adds an oxidation process step (i.e., step S02) before the debonding step; otherwise, the other process conditions are the same.

[0075] Therefore, this embodiment adds an oxidation process after the back-side thinning and back-side metallization processes and before debonding to oxidize the surface of the first metal layer into a metal oxide layer. Thus, during the debonding process, the metal oxide layer can serve as a protective layer, and the uneven stage temperature of the debonding machine will no longer affect the back side of the first wafer, thereby preventing the formation of concentric circle color differences corresponding to the stage pattern.

[0076] The method for avoiding debonding marks and the method for fabricating power devices provided in this application not only ensure that the electrical parameters of the wafer remain unchanged after the temporary bonding and debonding processes, but also solve the problem of concentric circle color difference on the back side of the first wafer, without affecting chip packaging.

[0077] It should be noted that the embodiments of the power device fabrication method provided in this application and the embodiments of the method for avoiding debonding imprints belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0078] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for avoiding unbonding imprints, characterized in that, The method includes: A bonding wafer pair is provided, the bonding wafer pair comprising a first wafer and a second wafer bonded to each other, the first wafer having a bonding surface facing the second wafer and a back surface away from the second wafer, a first metal layer being formed on the back surface of the first wafer; An oxidation process is performed to oxidize the surface of the first metal layer into a metal oxide layer; The bonded wafer pair is placed on a debonding machine, the metal oxide layer is in contact with the stage of the debonding machine, and the bonded wafer pair is debonded using the debonding machine under heating conditions. After debonding the bonded wafer pair using the debonding machine, the method further includes: A solder layer is formed on the metal oxide layer; Under heating conditions, the first metal layer and the solder layer are fused together through the metal oxide layer.

2. The method for avoiding unbonding imprints according to claim 1, characterized in that, The material of the first metal layer includes silver.

3. The method for avoiding unbonding imprints according to claim 1, characterized in that, The oxidation process is performed at a first temperature, and the debonding of the bonded wafer pairs is performed at a second temperature, wherein the first temperature is not higher than the second temperature.

4. The method for avoiding unbonding imprints according to claim 1, characterized in that, The oxidation process is carried out at a temperature of 130℃~148℃, and the execution time of the oxidation process is 1.5H~2.5H.

5. The method for avoiding unbonding imprints according to claim 1, characterized in that, The first wafer is used to fabricate a transistor, and the first metal layer is the drain electrode layer of the transistor.

6. The method for avoiding unbonding imprints according to claim 1, characterized in that, A second metal layer and a third metal layer are also formed on the back side of the first wafer; the third metal layer, the second metal layer and the first metal layer are arranged in a sequence away from the back side of the first wafer; the material of the third metal layer includes titanium; the material of the second metal layer includes nickel.

7. The method for avoiding unbonding imprints according to claim 1, characterized in that, The first wafer is a silicon carbide wafer; and / or, the second wafer is a sapphire wafer.

8. The method for avoiding unbonding imprints according to claim 1, characterized in that, In the bonded wafer pair, the first wafer and the second wafer are temporarily bonded together using an organic bonding adhesive.

9. A method for fabricating a power device, characterized in that, The method includes the steps of the method for avoiding unbonded imprints as described in any one of claims 1 to 8.

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