Chip to-be-bonded piece and chip bonding structure
By adding a larger bonding auxiliary layer on the chip to be bonded, the problem of excessive loss of small conductive pillars in CMP planarization is solved, thereby improving the bonding power and the interconnection rate of the conductive pillars.
Patent Information
- Application Number
- CN202422789436.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2034-11-14
AI Technical Summary
In the CMP planarization process of chip components to be bonded, excessive loss of small-sized conductive pillars leads to a decrease in bonding power.
Adding a bonding auxiliary layer larger than the conductive pillar to the chip to be bonded increases the cross-sectional area of the conductive pillar's end face, improves the controllability and planarization effect of CMP polishing, and reduces the probability of conductive pillar breakage.
It improves the surface smoothness after CMP polishing, reduces the probability of unevenness in conductive pillars, and enhances bonding power and interconnectivity of conductive pillars.
Smart Images
Figure CN223912815U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to wafer bonding technical field especially, it relates to a chip to be bonded spare and chip bonding structure. BACKGROUND
[0002] At present, whether it is display device or sensing device, its structure is all array arrangement work chip (such as pixel chip or sensor chip) on base, and work chip is electrically connected with other circuit structure stacked in thickness direction through conductive column.
[0003] With the development of technology, various electronic devices and electronic equipment, such as display or sensor, all face the market demand of continuous miniaturization, due to the continuous reduction of work chip size and the continuous increase of arrangement density, the size of conductive column also decreases. But in the chemical mechanical grinding (CMP grinding) before bonding, the size of conductive column is too small to cause the etching speed of grinding fluid to the conductive column to increase rapidly, and then the surface height difference of the chip to be bonded after grinding is difficult to control, and the fine conductive column is also easy to break during grinding, finally the conductive column is seriously lower than the surface of the surrounding oxide layer, and the conductive column interconnection between the two chip to be bonded after bonding is difficult to realize, that is, the bonding success rate is lowered.
[0004] Therefore, how to solve the problem of small size conductive column on the chip to be bonded, which is lost too much in CMP planarization process before bonding and leads to the decrease of subsequent bonding success rate, is a problem to be solved by the person skilled in the art. INVENTION CONTENTS
[0005] The utility model aims at providing a chip to be bonded spare and chip bonding structure to solve the problem of small size conductive column on the chip to be bonded in the prior art, which is lost too much in CMP planarization process before bonding and leads to the decrease of subsequent bonding success rate.
[0006] To solve the above technical problem, the utility model provides a chip to be bonded spare, which comprises, in order from a first surface to a second surface, an epitaxial substrate, a chip array, a conductive column, an oxidation filling layer and a bonding auxiliary sheet layer.
[0007] The chip array is arranged on the surface of the epitaxial substrate, and the bonding auxiliary sheet layer and the chip array are connected by the conductive column.
[0008] The first surface and the second surface are a pair of opposite surfaces of the chip to be bonded.
[0009] The oxidation filling layer is filled between adjacent conductive columns and different chips in the chip array.
[0010] The bonding auxiliary sheet layer is connected with the conductive column, and a projection area of the bonding auxiliary sheet layer on the epitaxial substrate is greater than a projection area of the corresponding conductive column on the epitaxial substrate.
[0011] Optionally, in the chip-to-be-bonded structure, the chip array comprises at least one of an LED chip array and a CMOS chip array.
[0012] Optionally, in the chip-to-be-bonded structure, the bonding auxiliary sheet layer comprises a plurality of column expansion unit sheets arranged in insulation with each other.
[0013] The column expansion unit sheets correspond to the conductive columns one by one.
[0014] Optionally, in the chip-to-be-bonded structure, the bonding auxiliary sheet layer comprises a column connection unit sheet.
[0015] The column connection unit sheet covers a plurality of the conductive columns, so that the plurality of the conductive columns are electrically connected.
[0016] Optionally, in the chip-to-be-bonded structure, the bonding auxiliary sheet layer comprises only one column connection unit sheet.
[0017] Optionally, in the chip-to-be-bonded structure, the conductive column is a copper column, and the bonding auxiliary sheet layer is a copper layer.
[0018] Optionally, in the chip-to-be-bonded structure, a surface of the bonding auxiliary sheet layer is lower than a surface of the oxide filling layer.
[0019] A chip bonding structure, comprising two chip-to-be-bonded structures as described in any one of the above.
[0020] Second surfaces of the two chip-to-be-bonded structures are bonded with each other.
[0021] Optionally, in the chip bonding structure, the bonding auxiliary sheet layer of at least one of the two chip-to-be-bonded structures comprises the column connection unit sheet.
[0022] The chip bonding structure further comprises an isolation unit, one end of the isolation unit is arranged on the first surface of the chip-to-be-bonded structure.
[0023] The isolation unit is used for isolating different regions of the column connection unit sheet, so that each conductive column is insulated from other conductive columns in the same chip-to-be-bonded structure.
[0024] Optionally, in the chip bonding structure, the chip array of at least one of the chip-to-be-bonded structures is an LED chip array.
[0025] The isolation unit is a light shielding unit.
[0026] The chip to be bonded provided by the utility model, from the first surface to the second surface successively includes epitaxial substrate, chip array, conductive column, oxidation filling layer and bonding auxiliary sheet layer, the chip array is arranged on the surface of the epitaxial substrate, and the bonding auxiliary sheet layer is connected with the chip array through the conductive column, the first surface and the second surface are a group of opposite surfaces of the chip to be bonded, the oxidation filling layer is filled between adjacent conductive columns and different chips in the chip array, the bonding auxiliary sheet layer is connected with the conductive column, and the projection area of the bonding auxiliary sheet layer on the epitaxial substrate is greater than the projection area of the corresponding conductive column on the epitaxial substrate.
[0027] The utility model discloses to the chip to be bonded makes improvement, and the bonding auxiliary sheet layer of the larger section area than the section area of conductive column is additionally arranged to the one end of conductive column on the bonding surface (also namely the second surface), which is equivalent to expanding the end surface section of conductive column on the second surface, and the controllability of the grinding rate ratio of conductive column / oxidation filling layer in the CMP grinding stage can be improved significantly by the larger section, which is favorable for height difference control, can improve the surface flatness after the bonding surface CMP grinding better, reduces the appearance probability of the situation that the height of conductive column is much lower than the oxidation filling layer, simultaneously reduces the possibility of conductive column fracture, finally improves the interconnection rate of conductive column after bonding, improves the bonding success rate. The utility model also provides a chip bonding structure with the beneficial effect. BRIEF DESCRIPTION OF DRAWINGS
[0028] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, the drawings needed to be used in the embodiment or the prior art description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the utility model, and those skilled in the art can also obtain other drawings according to these drawings without creating creative labor.
[0029] Figure 1-a 、 Figure 1-b 、 Figure 1-c And Figure 1-d It is the process structure schematic view of the chip to be bonded provided by the utility model;
[0030] Figure 2-a 、 Figure 2-b 、 Figure 2-c 、 Figure 2-d 、 Figure 2-e And Figure 2-f It is the process structure schematic view of the chip to be bonded provided by the utility model;
[0031] Figure 3-a 、 Figure 3-b 、 Figure 3-c And Figure 3-dThe utility model provides a chip to be bonded piece's process structure schematic diagram;
[0032] Figure 4-a 、 Figure 4-b 、 Figure 4-c 、 Figure 4-d 、 Figure 4-e And Figure 4-f The utility model provides a chip to be bonded piece's process structure schematic diagram;
[0033] Figure 5 The utility model provides a chip bonding structure's process flow structure diagram of one specific embodiment;
[0034] Figure 6 The utility model provides a chip bonding structure's structure schematic diagram of one specific embodiment.
[0035] In the drawing, including 01-epitaxial substrate, 02-chip array, 03-conductive column, 04-oxidation filling layer, 05-bonding auxiliary layer, 10-isolation unit. Specific embodiments
[0036] In order to make the personnel in the technical field better understand the utility model scheme, the utility model is further explained in detail below with the specific embodiments and the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all. Based on the embodiment in the utility model, all other embodiments obtained by the ordinary skill in the art without making creative labor belong to the range of the utility model protection.
[0037] The core of the utility model provides a chip to be bonded piece, and its structure schematic diagram of one specific embodiment is as shown in Figure 1-d 、 Figure 2-f 、 Figure 3-d And Figure 4-f The first surface to the second surface includes epitaxial substrate 01, chip array 02, conductive column 03, oxidation filling layer 04 and bonding auxiliary sheet layer 05 in proper order, and is called specific embodiment one;
[0038] Chip array 02 is arranged on the surface of epitaxial substrate 01, and the bonding auxiliary sheet layer 05 is connected with chip array 02 through conductive column 03;
[0039] The first surface and the second surface are a group of opposite surfaces of the chip to be bonded piece;
[0040] Oxidation filling layer 04 is filled between adjacent conductive column 03 and different chips in chip array 02;
[0041] The bonding auxiliary sheet layer 05 is connected with the conductive column 03, and the projection area of the bonding auxiliary sheet layer 05 on the epitaxial substrate 01 is greater than the projection area of the corresponding conductive column 03 on the epitaxial substrate 01.
[0042] As a specific embodiment, the chip array 02 includes at least one of an LED chip array 02 and a CMOS chip array 02.
[0043] The chip-to-be-bonded is often used in pairs in actual use. For this specific embodiment, the chip array 02 can be an LED chip array 02 or a CMOS chip array 02, both of which are bonded together to connect the LED chip array 02 and the CMOS chip array 02, so that each CMOS chip is connected with a corresponding LED chip to realize one-to-one control of the CMOS chip over the LED chip. Of course, it can also be other types of chip arrays 02, which are not limited in the present application.
[0044] As one of the preferred embodiments, the bonding auxiliary sheet layer 05 includes a plurality of column expansion unit sheets arranged in insulation with each other.
[0045] The column expansion unit sheet corresponds to the conductive column 03 one by one.
[0046] Please refer to Figure 1-d and Figure 2-f In this preferred embodiment, the bonding auxiliary sheet layer 05 is composed of a plurality of column expansion unit sheets, and each bonding auxiliary sheet layer 05 is arranged at the top (i.e., at the second surface) of the conductive column 03, which is equivalent to expanding the cross-sectional area of the end of each conductive column 03 that is ground, thereby improving the controllability of the grinding rate ratio of the conductive column 03 / oxidation filling layer 04.
[0047] The following provides a specific embodiment of a manufacturing method of the chip-to-be-bonded in the present preferred embodiment, wherein the conductive column 03 is a copper column, including the following steps:
[0048] 1-1. Prepare a conventional chip-to-be-bonded, which includes, from bottom to top, an epitaxial substrate 01, a chip array 02, and a copper column, and the copper column is filled with an oxidation filling layer 04.
[0049] 1-2. Use CMP to grind the top of the conventional chip-to-be-bonded until the copper column is protruding, which can be referred to in Figure 1-a .
[0050] 1-3. Set an oxidation filling layer 04 on the top of the conventional chip-to-be-bonded to cover the copper column, which can be referred to in Figure 1-b .
[0051] 1-4. Etch the oxide fill layer 04 on the top of the regular chip-to-be-bonded until the copper pillars are exposed, leaving a groove larger than the size of the corresponding copper pillar; the groove corresponds to the copper pillar one by one and is not interconnected, which can be referred to as Figure 1-c .
[0052] 1-5. Fill copper into the groove to obtain the column expansion unit piece, and perform CMP on the top of the regular chip-to-be-bonded to ensure that the copper surface is slightly lower than the surface of the oxide fill layer 04, which can be referred to as Figure 1-d .
[0053] Of course, in addition to the above method, there are other specific embodiments of the manufacturing method of the chip-to-be-bonded in the preferred embodiment, in which the conductive column 03 is a copper column, including the following steps:
[0054] 2-1. Prepare a regular chip-to-be-bonded, which includes an epitaxial substrate 01, a chip array 02, and a copper column from bottom to top, and the copper column is filled with an oxide fill layer 04.
[0055] 2-2. Grind the top of the regular chip-to-be-bonded by CMP until the copper column is protruding, which can be referred to as Figure 2-a .
[0056] 2-3. Copper plating on the top of the regular chip-to-be-bonded, which can be referred to as Figure 2-b .
[0057] 2-4. Set an oxide fill layer 04 on the surface of the entire copper, which can be referred to as Figure 2-c .
[0058] 2-5. Etch the copper layer and the oxide fill layer 04 in the area between the copper columns to obtain the column expansion unit piece, which can be referred to as Figure 2-d .
[0059] 2-6. Continue to cover the oxide fill layer 04 on the top of the regular chip-to-be-bonded until it completely covers the column expansion unit piece, which can be referred to as Figure 2-e .
[0060] 2-7. Perform CMP on the top of the regular chip-to-be-bonded to ensure that the copper surface is slightly lower than the surface of the oxide fill layer 04, which can be referred to as Figure 2-f .
[0061] As another preferred embodiment, the bonding auxiliary piece layer 05 includes a column connection unit piece;
[0062] The column connection unit piece covers a plurality of conductive columns 03, so that a plurality of conductive columns 03 are electrically connected.
[0063] In the preferred embodiment, the bonding auxiliary sheet layer 05 is composed of column connecting unit sheets, which are different from the column expanding unit sheets in the previous preferred embodiment. The column connecting unit sheets in the preferred embodiment cover the end faces of the plurality of conductive columns 03 at the second surface, connecting the plurality of conductive columns 03 together. It can be considered that the plurality of column expanding unit sheets in the previous preferred embodiment are connected to obtain the column connecting unit sheets. In the preferred embodiment, the top ends of the plurality of conductive columns 03 are connected and covered by the column connecting unit sheets, which can further improve the area ratio of the conductive columns 03 to the oxidation filling layer 04, making it closer to 1:1, and further improving the controllability of the conductive column 03 / oxidation filling layer 04 grinding rate ratio. Figure 3-d and Figure 4-f It can be considered that the plurality of column expanding unit sheets in the previous preferred embodiment are connected to obtain the column connecting unit sheets. In the preferred embodiment, the top ends of the plurality of conductive columns 03 are connected and covered by the column connecting unit sheets, which can further improve the area ratio of the conductive columns 03 to the oxidation filling layer 04, making it closer to 1:1, and further improving the controllability of the conductive column 03 / oxidation filling layer 04 grinding rate ratio.
[0064] Of course, the bonding auxiliary sheet layer 05 can include a plurality of column connecting unit sheets, or only one column connecting unit sheet.
[0065] The following provides a specific embodiment of a method for manufacturing a chip to be bonded in the preferred embodiment, wherein the conductive column 03 is a copper column, including the following steps:
[0066] 3-1. Prepare a conventional chip to be bonded, which includes, from bottom to top, an epitaxial substrate 01, a chip array 02, and a copper column, and the copper column is filled with an oxidation filling layer 04.
[0067] 3-2. Use CMP to grind the top of the conventional chip to be bonded until the copper column is protruding, which can be referred to as Figure 3-a .
[0068] 3-3. Set an oxidation filling layer 04 on the top of the conventional chip to be bonded to cover the copper column, which can be referred to as Figure 3-b .
[0069] 3-4. Etch the oxidation filling layer 04 on the top of the conventional chip to be bonded until the copper column is exposed, leaving a groove larger than the size of the corresponding copper column; the same groove exposes a plurality of copper columns at the bottom, which can be referred to as Figure 3-c .
[0070] 3-5. Fill copper into the groove to obtain the column connecting unit sheet, and use CMP to grind the top of the conventional chip to be bonded to ensure that the copper surface is slightly lower than the surface of the oxidation filling layer 04, which can be referred to as Figure 3-d .
[0071] Of course, in addition to the above method, there are other specific embodiments of the method for manufacturing a chip to be bonded in the preferred embodiment, wherein the conductive column 03 is a copper column, including the following steps:
[0072] 4-1. Prepare a conventional chip-to-be-bonded piece, which includes, from bottom to top, an epitaxial substrate 01, a chip array 02, and a copper column, the copper column being filled with an oxide filling layer 04.
[0073] 4-2. Grind the top of the conventional chip-to-be-bonded piece by CMP until the copper column is protruding, which can be referred to as Figure 4-a .
[0074] 4-3. Copperize the top of the conventional chip-to-be-bonded piece, which can be referred to as Figure 4-b .
[0075] 4-4. Set an oxide filling layer 04 on the surface of the copper layer, which can be referred to as Figure 4-c .
[0076] 4-5. Etch the copper layer and the oxide filling layer 04 in the area between the copper columns to obtain the column-connected unit piece, which can be referred to as Figure 4-d .
[0077] 2-6. Continue to cover the oxide filling layer 04 on the top of the conventional chip-to-be-bonded piece until the column-connected unit piece is completely covered, which can be referred to as Figure 4-e .
[0078] 2-7. Perform CMP on the top of the conventional chip-to-be-bonded piece to ensure that the copper surface is slightly lower than the surface of the oxide filling layer 04, which can be referred to as Figure 4-f .
[0079] As another preferred embodiment, the bonding auxiliary piece layer 05 only includes one column-connected unit piece.
[0080] That is, the entire bonding auxiliary piece layer 05 is a continuous piece layer, which can be understood as the bonding auxiliary piece layer 05 in the present embodiment is the case where the bonding auxiliary piece layer 05 in the previous preferred embodiment only includes one column-connected unit piece, which can further greatly simplify the process and reduce the process cost. The process structure diagram can be referred to as Figure 2-c . The manufacturing method of the chip-to-be-bonded piece in the present preferred embodiment can be referred to as the previous one, and the process will not be described below until step 2-4, that is, the bonding auxiliary piece layer 05 in the present preferred embodiment can be obtained.
[0081] Furthermore, the conductive post 03 is a copper post, and the bonding auxiliary layer 05 is a copper layer. The bonding auxiliary layer 05 can be seen as an extension structure that increases the cross-sectional area of the conductive post 03. Therefore, the material of the conductive post 03 is preferably the same as that of the bonding auxiliary layer 05 to increase the connection stability between the conductive post 03 and the bonding auxiliary layer 05. Copper is easy to process and has strong conductivity. Using a combination of copper posts and the same layer can further improve the bonding quality and reduce the production difficulty. Of course, conductive posts 03 and bonding auxiliary layers 05 of other materials can also be used, and this invention is not limited thereto.
[0082] Furthermore, the epitaxial substrate 01 is a silicon substrate, and the oxide filling layer 04 is a silicon oxide layer. The silicon oxide layer is a dense and non-conductive material, which is suitable as a low-cost insulating filling layer. The silicon oxide layer can be epitaxially grown on the silicon substrate at low cost and high efficiency. Of course, other materials can also be used to combine the epitaxial substrate 01 and the oxide filling layer 04, such as sapphire substrate or GaAs (gallium arsenide) substrate. This utility model is not limited here.
[0083] Specifically, the surface of the bonding auxiliary layer 05 is lower than the surface of the oxide filling layer 04. The surface height of the oxide filling layer 04 is set slightly higher than the bonding auxiliary layer, causing the bonding auxiliary layer 05 to form a slightly recessed groove on the second surface. This allows the oxide filling layers 04 of the two chip components to be bonded to contact first during the bonding process, performing pre-bonding. The surface roughness of the oxide filling layer 04 is more suitable for bonding. After pre-bonding for a period of time, the bonding proceeds to the conductive post 03, significantly improving the bonding success rate.
[0084] The chip to be bonded provided by the utility model successively comprises an epitaxial substrate 01, a chip array 02, a conductive column 03, an oxidation filling layer 04 and a bonding auxiliary sheet layer 05 from a first surface to a second surface; the chip array 02 is arranged on the surface of the epitaxial substrate 01, and the bonding auxiliary sheet layer 05 is connected with the chip array 02 through the conductive column 03; the first surface and the second surface are a group of opposite surfaces of the chip to be bonded; the oxidation filling layer 04 is filled between adjacent conductive columns 03 and different chips in the chip array 02; the bonding auxiliary sheet layer 05 is connected with the conductive column 03, and the projection area of the bonding auxiliary sheet layer 05 on the epitaxial substrate 01 is greater than the projection area of the corresponding conductive column 03 on the epitaxial substrate 01. The utility model improves the chip to be bonded, and the bonding auxiliary sheet layer 05 with a larger cross-sectional area than the conductive column 03 is additionally arranged at one end of the conductive column 03 on the bonding surface (namely the second surface), which is equivalent to enlarging the end surface cross section of the conductive column 03 on the second surface. The controllability of the conductive column 03 / oxidation filling layer 04 grinding rate in the CMP grinding stage can be improved, the high-low difference control is facilitated, the surface flatness after the bonding surface is ground by CMP can be better improved, the possibility of the conductive column 03 breaking is reduced, the interconnection rate of the conductive column 03 after bonding is improved, and the bonding success rate is improved.
[0085] The utility model further provides a chip bonding structure, and the structure schematic diagram of one specific embodiment thereof can refer to Figure 6 The chip bonding structure comprises two chip to be bonded as described in the preceding.
[0086] The second surfaces of the two chip to be bonded are bonded to each other.
[0087] The chip bonding structure in the specific embodiment corresponds to the chip to be bonded in the preceding, and is a structure obtained after the chip to be bonded in the preceding is bonded, so the specific technical details refer to the preceding, and will not be described herein again.
[0088] As a preferred embodiment, the bonding auxiliary sheet layer 05 of at least one of the two chip to be bonded comprises the column connecting unit sheet.
[0089] The chip bonding structure further comprises an isolation unit 10, and one end of the isolation unit 10 is arranged on the first surface of the chip to be bonded.
[0090] The isolation unit 10 is used for isolating different regions of the column connecting unit sheet, so that each conductive column 03 is insulated from other conductive columns 03 in the same chip to be bonded.
[0091] In this preferred embodiment, the characteristics of the structure of the chip to be bonded, including the pillar-connecting unit sheet, are given. That is, in order to increase the area of the conductive pillar 03 structure on the bonding surface, the pillar-connecting unit sheet covers and connects multiple conductive pillars 03. This results in multiple conductive pillars 03 belonging to the same chip to be bonded being electrically connected to each other. However, even after bonding, it cannot be used directly. In order to ensure that the chips of the chip to be bonded on both sides are connected one-to-one in the chip bonding structure obtained after bonding, the pillar-connecting unit sheet needs to be cut to end the electrical connection of different conductive pillars 03 in the same chip to be bonded. Therefore, after the two chip to be bonded are bonded, a hole can be opened from the first surface of either chip to be bonded to cut off the pillar-connecting unit sheet, thereby obtaining the isolation unit 10 on the chip bonding structure. This ensures a high bonding success rate without affecting the use after bonding. Of course, after the hole is opened, the corresponding insulating material can be filled into the hole to form a columnar isolation unit 10, such as filling with oxide material to obtain an oxide isolation unit, etc. This utility model does not limit this.
[0092] You can refer to this. Figure 5 , Figure 5 This is a schematic diagram of the structure of two chips, including the aforementioned pillar-connecting unit sheets, after bonding. Clearly, at this point, the pillar-connecting unit sheets electrically connect adjacent conductive pillars 03, preventing one-to-one signal transmission. At this stage, [the signal can be transmitted in a specific way]. Figure 5 The isolation unit 10 is formed on the upper or lower surface of the structure (both are the original first surfaces of the chip to be bonded), cutting off the electrical connection between different conductive pillars 03. The structural schematic diagram after setting the isolation unit 10 is shown below. Figure 6 As shown.
[0093] In a preferred embodiment, at least one of the chip arrays 02 of the chip to be bonded is an LED chip array 02;
[0094] The isolation unit 10 is a light-shielding unit.
[0095] In this preferred embodiment, at least one of the chip arrays 02 of the chip to be bonded is defined as an LED chip array 02. In other words, the chip bonding structure is a structure in a display device. At this time, the isolation unit 10 is further defined as a light-shielding unit, that is, the isolation unit 10 is neither conductive nor transparent. While ensuring that there is no conduction between adjacent conductive pillars 03, it also avoids light leakage between different pixels (that is, different LED chips in the LED chip array), further improving the display effect.
[0096] Various embodiments are described herein with reference to the drawings, wherein each embodiment is shown in a progressive manner. Each embodiment is described in detail to highlight the differences from other embodiments, and the same or similar parts among various embodiments can be mutually referred to. For the apparatus disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method.
[0097] It should be noted that, in the specification, the relational terms such as first and second and the like are used only to differentiate one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. In addition, the terms "comprises", "comprising", or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article, or device including the element.
[0098] The chip-to-be-bonded member and the chip bonding structure provided by the present application are described in detail above. In this paper, specific examples are applied to describe the principles and implementation modes of the present application. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for ordinary skilled persons in the technical field, without departing from the principles of the present application, the present application can be improved and modified in many ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.
Claims
1. A chip-to-be-bonded member, characterized by, The chip-to-be-bonded structure comprises a first surface and a second surface, and sequentially comprises an epitaxial substrate, a chip array, a conductive column, an oxidation filling layer and a bonding auxiliary sheet layer from the first surface to the second surface. The chip array is arranged on a surface of the epitaxial substrate, and the bonding auxiliary sheet layer is connected with the chip array through the conductive column. The first surface and the second surface are a pair of opposite surfaces of the chip-to-be-bonded structure. The oxidation filling layer fills between adjacent conductive columns and between different chips in the chip array. The bonding auxiliary sheet layer is connected with the conductive column, and a projection area of the bonding auxiliary sheet layer on the epitaxial substrate is greater than a projection area of the corresponding conductive column on the epitaxial substrate.
2. The chip-to-be-bonded according to claim 1, wherein, The chip array comprises at least one of an LED chip array and a CMOS chip array.
3. The chip-to-be-bonded according to claim 1, wherein, The bonding auxiliary sheet layer comprises a plurality of column expansion unit sheets arranged in insulation with each other. The column expansion unit sheet corresponds to the conductive column one by one.
4. The chip-to-be-bonded according to Claim 1, wherein, The bonding auxiliary sheet layer comprises a column connecting unit sheet. The column connecting unit sheet covers a plurality of the conductive columns, so that the plurality of the conductive columns are electrically connected.
5. The chip-to-be-bonded according to claim 4, wherein, The bonding auxiliary sheet layer comprises only one column connecting unit sheet.
6. The chip-to-be-bonded according to claim 1, wherein, The conductive column is a copper column, and the bonding auxiliary sheet layer is a copper layer.
7. The chip-to-be-bonded according to any one of claims 1 to 6, wherein A surface of the bonding auxiliary sheet layer is lower than a surface of the oxidation filling layer.
8. A die bonding structure, characterized by, The chip bonding structure comprises two chip-to-be-bonded structures as claimed in any one of claims 1 to 7. Second surfaces of the two chip-to-be-bonded structures are bonded with each other.
9. The die bonding structure of claim 8, wherein, The bonding auxiliary sheet layer of at least one of the two chip-to-be-bonded structures comprises the column connecting unit sheet. The chip bonding structure further comprises an isolation unit, and one end of the isolation unit is arranged on the first surface of the chip-to-be-bonded structure. The isolation unit is used for isolating different regions of the column connecting unit sheet, so that each conductive column is insulated from other conductive columns in the same chip-to-be-bonded structure.
10. The die bonding structure of claim 9, wherein, The chip array of at least one of the chip-to-be-bonded structures is an LED chip array. The isolation unit is a light shielding unit.