A semiconductor structure and a method of manufacturing the same

Abstract

Disclosed are a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate and forming a gate stack on the substrate; adsorbing a first plasma on a surface of the gate stack; forming a plasma layer covering at least a side wall of the gate stack; and forming a first dielectric layer covering at least a side wall of the plasma layer. The plasma layer and the first dielectric layer are formed in the same furnace tube.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor structures, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), typically include a gate stack and a dielectric layer located on the sidewalls of the gate stack. The dielectric layer serves to protect the gate stack.

[0003] However, in actual processes, due to the different properties of each layer in the gate stack, the thickness of the dielectric layer formed on the sidewall of the gate stack is often uneven, which affects the stability of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, including:

[0005] Provide substrate;

[0006] A gate stack layer is formed on the substrate;

[0007] A first plasma is adsorbed on the surface of the gate stack layer to form a plasma layer that at least covers the sidewalls of the gate stack layer;

[0008] A first dielectric layer is formed, which at least covers the sidewall of the plasma layer; wherein the plasma layer and the first dielectric layer are formed in the same furnace tube.

[0009] In some embodiments, forming a plasma layer includes:

[0010] A furnace tube is provided, the furnace tube comprising: a reaction chamber and at least one embedded cavity disposed on the inner wall of the reaction chamber, wherein at least one pair of parallel radio frequency electrodes are disposed in the embedded cavity, the radio frequency electrodes being used to dissociate gas introduced into the embedded cavity into plasma;

[0011] The substrate, including the gate stack layer, is placed inside the reaction chamber;

[0012] A first source gas is introduced into the embedded cavity, and a radio frequency signal is applied to the radio frequency electrode to dissociate the first source gas into a first plasma. The first plasma is adsorbed onto the sidewalls and upper surface of the gate stack layer to form the plasma layer.

[0013] In some embodiments, a plurality of spray nozzles are provided on the sidewall of the embedded cavity, and the size of the spray nozzle located on the upper part of the sidewall of the embedded cavity is larger than the size of the spray nozzle located on the lower part of the sidewall of the embedded cavity.

[0014] In some embodiments, the number of embedded cavities is multiple, and the multiple embedded cavities are equally spaced on the inner wall of the reaction chamber.

[0015] In some embodiments, forming a first dielectric layer includes:

[0016] A second source gas is introduced into the reaction chamber, and the second source gas is adsorbed on the surface of the plasma layer and the upper surface of the substrate;

[0017] A third source gas is introduced into the embedded cavity, and a radio frequency signal is applied to the radio frequency electrode to dissociate the third source gas into a second plasma. The second plasma reacts with the third source gas to form a first sublayer, and the first sublayer covers the plasma layer and the substrate.

[0018] The steps of introducing a second source gas into the reaction chamber, introducing a third source gas into the embedded cavity, and applying a radio frequency signal to the radio frequency electrode are performed again until a first sublayer with a first preset thickness is formed.

[0019] In some embodiments, after forming a first sublayer having a first preset thickness, the method further includes:

[0020] A fourth source gas is introduced into the reaction chamber, and the fourth source gas is adsorbed onto the surface of the first sublayer.

[0021] A fifth source gas is introduced into the reaction chamber, and the fifth source gas reacts with the fourth source gas to form a second sublayer, which covers the first sublayer.

[0022] The steps of introducing a third source gas and a fourth source gas into the reaction chamber are repeated until a second sub-layer with a second preset thickness is formed. The first sub-layer and the second sub-layer constitute the first dielectric layer.

[0023] In some embodiments, after forming the first dielectric layer, the method further includes:

[0024] Remove the first dielectric layer and the plasma layer covering the upper surface of the substrate and the top of the gate stack layer, with the plasma layer remaining covering the sidewalls of the gate stack layer and the first dielectric layer remaining covering the sidewalls of the plasma layer;

[0025] A second dielectric layer is formed, which covers the upper surface of the substrate, the sidewalls and top of the first dielectric layer, and the top of the gate stack layer and the plasma layer;

[0026] A portion of the second dielectric layer is removed, leaving the second dielectric layer located on the substrate and covering the sidewalls of the first dielectric layer;

[0027] Alternatively, after forming the first dielectric layer, the method further includes:

[0028] A second dielectric layer is formed, which covers the first dielectric layer;

[0029] A portion of the second dielectric layer and a portion of the first dielectric layer are removed, with the remaining first dielectric layer covering a portion of the upper surface of the substrate and the plasma layer, and the remaining second dielectric layer located on the first dielectric layer and covering a portion of the sidewall of the first dielectric layer.

[0030] This disclosure also provides a semiconductor structure, including:

[0031] Substrate;

[0032] A gate stack layer is located on the substrate;

[0033] The plasma layer includes at least a first plasma adsorbed onto the sidewalls of the gate stack layer;

[0034] A first dielectric layer covers at least the sidewalls of the plasma layer; wherein the plasma layer and the first dielectric layer are formed in the same furnace tube.

[0035] In some embodiments, the gate stack layer includes a non-metallic conductive layer and a metallic conductive layer covering the non-metallic conductive layer. The first dielectric layer located on two opposite sidewalls of the metallic conductive layer has a first thickness a and a second thickness b, respectively. The first dielectric layer located on two opposite sidewalls of the non-metallic conductive layer has a third thickness c and a fourth thickness d, respectively. A thickness deviation Δt is defined between the portion of the first dielectric layer located on the sidewall of the metallic conductive layer and the portion located on the sidewall of the non-metallic conductive layer.

[0036] Δt = ((a+b)-(c+d)) / 2;

[0037] The thickness deviation Δt ranges from 0 to 0.2 nm.

[0038] In some embodiments, the first dielectric layer includes a first sublayer and a second sublayer covering the first sublayer; the thickness of the first sublayer ranges from 0.3 nm to 0.5 nm, and the thickness of the second sublayer ranges from 5 nm to 15 nm.

[0039] The semiconductor structure and its manufacturing method provided in this disclosure include: providing a substrate; forming a gate stack layer on the substrate; adsorbing a first plasma on the surface of the gate stack layer to form a plasma layer that at least covers the sidewalls of the gate stack layer; and forming a first dielectric layer that at least covers the sidewalls of the plasma layer. The plasma layer and the first dielectric layer are formed in the same furnace tube. In this disclosure, before depositing the first dielectric layer, the first plasma is adsorbed on the sidewalls of the gate stack layer to form a plasma layer. The first plasma replaces impurity atoms such as H, Cl, and O located on the surface of the gate stack layer, making the surface properties of different materials in the gate stack layer more uniform. Thus, the first dielectric layer formed on the sidewalls of the gate stack layer has a more uniform thickness. Furthermore, forming the plasma layer and the first dielectric layer in the same furnace tube improves process stability, further increases the uniformity of the first dielectric layer, and reduces costs.

[0040] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0043] Figures 2 to 13 A process flow diagram of a method for manufacturing a semiconductor structure provided in this disclosure embodiment;

[0044] Figures 14 to 16 A process flow diagram of a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0045] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] Semiconductor structures, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), typically include a gate stack and a dielectric layer located on the sidewalls of the gate stack. The dielectric layer serves to protect the gate stack.

[0052] However, in actual manufacturing processes, due to the different properties of each layer in the gate stack, the thickness of the dielectric layer formed on the sidewalls of the gate stack is often uneven, thus affecting the stability of the semiconductor structure. Specifically, the gate stack typically includes a metal conductive layer and a non-metal conductive layer. Due to the different surface properties of the two, the thickness of the dielectric layer located on the sidewalls of the metal conductive layer is usually greater than the thickness of the dielectric layer located on the sidewalls of the non-metal conductive layer, and the two thicknesses often have a large difference, reducing the stability of the semiconductor structure.

[0053] Based on this, the following technical solutions for embodiments of this disclosure are proposed:

[0054] This disclosure provides a method for manufacturing a semiconductor structure; please refer to the following for details. Figure 1 As shown in the figure, the method includes the following steps:

[0055] Step S101: Provide a substrate;

[0056] Step S102: Form a gate stack layer on the substrate;

[0057] Step S103: Adsorb the first plasma on the surface of the gate stack layer to form a plasma layer that at least covers the sidewalls of the gate stack layer;

[0058] Step S104: Form a first dielectric layer, which at least covers the sidewall of the plasma layer; wherein the plasma layer and the first dielectric layer are formed in the same furnace tube.

[0059] In practice, the semiconductor structure provided in this disclosure can be an N-type transistor or a P-type transistor. However, it is not limited to this; the semiconductor structure provided in this disclosure can also be any semiconductor structure containing N-type transistors or P-type transistors.

[0060] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure.

[0061] Figures 2 to 13 This is a process flow diagram of a semiconductor structure manufacturing method provided in an embodiment of the present disclosure. Figures 14 to 16 A process flow diagram of a method for manufacturing a semiconductor structure according to another embodiment of this disclosure; wherein, Figure 6 This is a schematic diagram of the structure of the furnace tube provided in an embodiment of this disclosure. Figure 7 For along Figure 6 A schematic diagram of the cross-sectional structure taken by line AA′ in the diagram.

[0062] First, execute step S101, as follows: Figure 2 As shown, a substrate 10 is provided.

[0063] Here, substrate 10 can be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 10 is a silicon substrate, which may be doped or undoped.

[0064] Next, proceed to step S102, as follows: Figures 3 to 4 As shown, a gate stack layer 11 is formed on the substrate 10.

[0065] Specifically, a gate stack layer 11 is formed on the substrate 10, including:

[0066] A non-metallic conductive material layer 111' is formed on the substrate 10;

[0067] A metallic conductive material layer 113' is formed on the non-metallic conductive material layer 111';

[0068] The metal conductive material layer 113′ and the non-metal conductive material layer 111′ are etched to form the metal conductive layer 113 and the non-metal conductive layer 111 respectively, and the metal conductive layer 113 covers the non-metal conductive layer 111.

[0069] See you again Figure 3 and Figure 4The method further includes forming a gate stack layer 11 on a substrate 10, and further includes forming a barrier material layer 112' on a non-metallic conductive material layer 111', the barrier material layer 112' being located between the non-metallic conductive material layer 111' and the metallic conductive material layer 113'; forming an insulating material layer 114' on the metallic conductive material layer 113'; and simultaneously etching the metallic conductive material layer 113' and the non-metallic conductive material layer 111' to form the metallic conductive layer 113 and the non-metallic conductive layer 111 respectively, while also etching the insulating material layer 114' to form a capping layer 114, and etching the barrier material layer 112' to form the barrier layer 112. The non-metallic conductive layer 111, the barrier layer 112, the metallic conductive layer 113, and the capping layer 114 constitute the gate stack layer 11. The barrier layer 112 prevents the material of the metallic conductive layer 113 from diffusing downwards, and the capping layer 114 protects other structures located below it.

[0070] In practice, the non-metallic conductive material layer 111′, the barrier material layer 112′, the metallic conductive material layer 113′, and the insulating material layer 114′ can be deposited by one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

[0071] In one embodiment, the material of the non-metallic conductive layer 111 includes one or a combination of monocrystalline silicon, polycrystalline silicon, germanium, and silicon-germanium, and the non-metallic conductive layer 111 may be doped or undoped, for example, doped polycrystalline silicon. The materials of the barrier layer 112 and the metallic conductive layer 113 include tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, and silicide (WSi). x CoSi x NiSi x AlSi x Materials include, etc., metal alloys, or any combination thereof. In some embodiments, the material of the barrier layer 112 includes titanium nitride, and the material of the metal conductive layer 113 includes tungsten. The material of the capping layer 114 includes, but is not limited to, nitrides, such as silicon nitride.

[0072] Next, proceed to step S103, as follows: Figures 5 to 7 As shown, a first plasma is adsorbed on the surface of the gate stack layer 11 to form a plasma layer 12 that at least covers the sidewalls of the gate stack layer 11.

[0073] Specifically, forming plasma layer 12 includes:

[0074] A furnace tube 20 is provided, the furnace tube 20 includes: a reaction chamber 21 and at least one embedded cavity 22 disposed on the inner wall of the reaction chamber 21, the embedded cavity 22 is provided with at least one pair of parallel radio frequency electrodes 24, the radio frequency electrodes 24 are used to dissociate the gas introduced into the embedded cavity 22 into plasma.

[0075] The substrate 10, including the gate stack layer 11, is placed inside the reaction chamber 21;

[0076] A first source gas is introduced into the embedded cavity 22, and a radio frequency signal is applied to the radio frequency electrode 24 to dissociate the first source gas into a first plasma. The first plasma is adsorbed onto the sidewalls and upper surface of the gate stack layer 11 to form a plasma layer 12.

[0077] More specifically, the plasma layer 12 covers the sidewalls of the non-metallic conductive layer 111, the barrier layer 112, the metallic conductive layer 113, and the sidewalls and upper surface of the capping layer 114. In some embodiments, the first plasma is also adsorbed onto the upper surface of the substrate 10, that is, the plasma layer 12 also covers the upper surface of the substrate 10, and the plasma layer 12 located on the upper surface of the substrate 10 can be removed subsequently.

[0078] In actual operation, after the first source gas is introduced into the furnace tube 20, a purge gas is introduced into the furnace tube 20 to remove excess first source gas or reaction byproducts. This purge gas can be an inert gas such as nitrogen or argon.

[0079] In one embodiment, the first source gas is a nitrogen source gas, and the first plasma is a nitrogen-containing plasma; wherein, the first source gas includes, but is not limited to, one or a combination of nitrogen (N2), nitrogen oxides (N2O), and ammonia (NH3), such as ammonia (NH3). In actual operation, during the process step of forming the plasma layer 12, the flow rate of the first source gas introduced into the embedded cavity 22 is between 5 L / min and 8 L / min, for example, 5 L / min, 6 L / min, 7 L / min, 8 L / min; the power of the radio frequency signal applied to the radio frequency electrode 24 is between 100 W and 500 W, for example, 100 W, 200 W, 300 W, 400 W, 500 W; and the process time is between 3 and 5 min, for example, 3 min, 4 min, 5 min.

[0080] like Figure 6 As shown, in one embodiment, the furnace tube 20 is a vertical furnace tube, and a crystal boat 23 is disposed inside the furnace tube 20. Multiple substrates 10 can be placed on the crystal boat 23 at a predetermined vertical spacing so as to process multiple substrates 10 simultaneously.

[0081] An embedded cavity 22 is provided inside the furnace tube 20. The embedded cavity 22 has a small space. The radio frequency electrode 24 is placed inside the embedded cavity 22, which can improve the dissociation effect of the process gas, save reaction time, and reduce the damage of plasma (e.g., the first plasma) to the semiconductor structure.

[0082] In one embodiment, there are multiple embedded cavities 22, which are equally spaced on the inner wall of the reaction chamber 21. Each embedded cavity 22 is provided with at least one pair of radio frequency electrodes 24. Thus, by increasing the number of embedded cavities 22 and radio frequency electrodes 24, the dissociation effect of the process gas can be further improved, the process time can be reduced, and the embedded cavities 22 are equally spaced in the reaction chamber 21, which helps to improve the concentration uniformity of the plasma (e.g., the first plasma) in the reaction chamber 21. Figure 7 The furnace tube 20 shown has four equally spaced embedded cavities 22, and each embedded cavity 22 has a pair of radio frequency electrodes 24. However, it is not limited to this. The number of embedded cavities 22 can be more or less, such as 2, 3, 5, 6, 7, etc., and any embedded cavity 22 can have multiple pairs of radio frequency electrodes 24, such as 2 pairs, 3 pairs, 4 pairs, etc.

[0083] In one embodiment, a plurality of spray nozzles H are provided on the sidewall of the embedded cavity 22. For example... Figure 7 As shown, in some embodiments, the embedded cavity 22 includes a first sidewall S1 opposite to the substrate 10, a second sidewall S2 and a third sidewall S3 located on both sides of the first sidewall S1, and the first sidewall S1, the second sidewall S2 and the third sidewall S3 together with the sidewall of the furnace tube 20 to form a space for placing the radio frequency electrode 24. In a specific embodiment, the first sidewall S1, the second sidewall S2 and the third sidewall S3 are each provided with a plurality of spray ports H, which are used to rapidly release plasma (e.g., first plasma) into the reaction chamber 21 to improve process efficiency.

[0084] In one embodiment, the size of the spray nozzle H located on the upper part of the sidewall of the embedded cavity 22 is larger than the size of the spray nozzle H located on the lower part of the sidewall of the embedded cavity 22. This increases the concentration of plasma (e.g., the first plasma) at a higher position in the reaction chamber 21, reduces the concentration difference of plasma within the reaction chamber 21, and makes the plasma concentration at different heights within the reaction chamber 21 more uniform. This ensures that the plasma layer 12 formed from top to bottom on the multiple substrates 10 and the first sublayer 131 formed in subsequent processes (see...) Figure 8 It has a more uniform thickness.

[0085] It should be noted that the plasma mentioned in the above embodiments includes the first plasma and the second plasma formed in subsequent processes.

[0086] Next, proceed to step S104, as follows: Figures 8 to 9 As shown, a first dielectric layer 13 is formed, which at least covers the sidewall of the plasma layer 12; wherein the plasma layer 12 and the first dielectric layer 13 are formed in the same furnace tube 20.

[0087] Specifically, firstly, see again Figure 8 Forming a first dielectric layer 13, comprising:

[0088] A second source gas is introduced into the reaction chamber 21, and the second source gas is adsorbed on the surface of the plasma layer 12 and the upper surface of the substrate 10.

[0089] A third source gas is introduced into the embedded cavity 22, and a radio frequency signal is applied to the radio frequency electrode 24 to dissociate the third source gas into a second plasma. The second plasma reacts with the third source gas to form a first sublayer 131, which covers the plasma layer 12 and the substrate 10.

[0090] The steps of introducing a second source gas into the reaction chamber 21, introducing a third source gas into the embedded cavity 22, and applying a radio frequency signal to the radio frequency electrode 24 are performed again until a first sublayer 131 with a first preset thickness is formed.

[0091] In one embodiment, in the step of applying a radio frequency signal to the radio frequency electrode 24 to dissociate the third source gas into a second plasma, the frequency of the radio frequency signal is in the range of 100W to 600W, for example, 100W, 200W, 300W, 400W, 500W, 600W.

[0092] In one embodiment, the second source gas is a silicon source gas, including silane or silane-derived materials. Here, silane includes SiH4, Si2H6, or Si... n H 2n+2 (n is greater than 2), silane-derived materials include chlorosilanes or iodosilanes, such as dichlorosilane (SiH2Cl2). In some embodiments, the third source gas is a nitrogen source gas, and the second plasma is a nitrogen-containing plasma; wherein, the third source gas includes, but is not limited to, one or a combination of nitrogen (N2), nitrogen oxides (N2O), and ammonia (NH3), such as ammonia (NH3). The material of the first sublayer 131 includes, but is not limited to, nitrides, such as silicon nitride.

[0093] Next, see you again. Figure 9 After forming the first sublayer 131 with a first preset thickness, the method further includes:

[0094] A fourth source gas is introduced into the reaction chamber 21, and the fourth source gas is adsorbed onto the surface of the first sublayer 131.

[0095] A fifth source gas is introduced into the reaction chamber 21. The fifth source gas reacts with the fourth source gas to form a second sub-layer 132, which covers the first sub-layer 131.

[0096] The steps of introducing a third source gas and a fourth source gas into the reaction chamber 21 are performed again until a second sub-layer 132 with a second preset thickness is formed. The first sub-layer 131 and the second sub-layer 132 constitute the first dielectric layer 13.

[0097] In actual operation, after introducing the second, third, fourth, and fifth source gases into the furnace tube 20, a purge gas is introduced into the furnace tube 20 to remove excess second, third, fourth, and fifth source gases or reaction byproducts. This purge gas can be an inert gas such as nitrogen or argon.

[0098] In one embodiment, the fourth source gas is a silicon source gas, and the fourth source gas can be the same as the second source gas, such as dichlorosilane (SiH2Cl2). However, it is not limited to this, and the fourth source gas can also be different from the second source gas. In some embodiments, the fifth source gas is a nitrogen source gas (e.g., ammonia (NH3)), and the fifth source gas can be the same as or different from the first and third source gases. The material of the second sublayer 132 includes, but is not limited to, nitrides, such as silicon nitride.

[0099] In actual operation, the fifth source gas and the fourth source gas undergo a thermochemical reaction in the reaction chamber 21 to form the second sublayer 132. The reaction temperature is between 300°C and 600°C, for example, 300°C, 400°C, 500°C, and 600°C. In this embodiment, the second plasma reacts with the second source gas to generate a first sublayer 131 with a first predetermined thickness. The first sublayer 131 thus formed has better density and fewer impurities. Then, the fifth source gas and the fourth source gas undergo a thermochemical reaction to generate the second sublayer 132 with a second predetermined thickness. Compared to using only the second plasma to react with the second source gas to form the first dielectric layer 13, this reduces the damage of the second plasma to the semiconductor structure. The first dielectric layer 13 thus formed has better density, fewer impurities, and less damage. In one embodiment, the first preset thickness is between 0.3nm and 0.5nm, for example, 0.3nm, 0.4nm, and 0.5nm; the second preset thickness is between 5nm and 15nm, for example, 5nm, 7nm, 9nm, 11nm, 13nm, and 15nm.

[0100] In this embodiment, a first plasma is adsorbed on the sidewall of the gate stack layer 11 to form a plasma layer 12. The first plasma replaces impurity atoms such as H, Cl, and O on the surface of the gate stack layer 11, making the surface properties of different materials in the gate stack layer 11 more uniform. This allows the first dielectric layer 13 formed on the sidewall of the gate stack layer 11 in subsequent processes to have a more uniform thickness. Furthermore, the furnace tube 20 provided in this embodiment includes an embedded cavity 22 with an internally disposed radio frequency electrode 24. Thus, the processes for forming the plasma layer 12 and the first dielectric layer 13 can be performed within the same furnace tube 20 without replacing the furnace tube 20, which helps improve the stability of the semiconductor structure and saves costs.

[0101] To characterize the uniformity of the thickness of the first dielectric layer 13 located on the sidewalls of the gate stack 11, a thickness deviation Δt is defined. Specifically, the first dielectric layer 13 located on the two opposite sidewalls of the metal conductive layer 113 has a first thickness a and a second thickness b, respectively, and the first dielectric layer 13 located on the two opposite sidewalls of the non-metal conductive layer 111 has a third thickness c and a fourth thickness d, respectively. The thickness deviation Δt between the portion of the first dielectric layer 13 located on the sidewall of the metal conductive layer 113 and the portion located on the sidewall of the non-metal conductive layer 111 is defined as: Δt = ((a+b)-(c+d)) / 2. It can be understood that the value of the thickness deviation Δt can reflect the uniformity of the thickness of the first dielectric layer 13 located on the sidewalls of the gate stack 11; the more uniform the thickness of the first dielectric layer 13, the smaller the value of the thickness deviation Δt. In one specific embodiment, the thickness deviation Δt of the first dielectric layer 13 formed by the manufacturing method provided in this disclosure is in the range of 0 to 0.2 nm, for example 0, 0.05 nm, 0.1 nm, 0.15 nm, 0.2 nm. That is, the first dielectric layer 13 formed by the manufacturing method provided in this disclosure has better uniformity, thereby improving the stability of the semiconductor structure.

[0102] Next, as Figures 10 to 12 As shown, after forming the first dielectric layer 13, the process further includes:

[0103] Remove the first dielectric layer 13 and the plasma layer 12 covering the upper surface of the substrate 10 and the top of the gate stack 11. The remaining plasma layer 12 covers the sidewalls of the gate stack 11, and the remaining first dielectric layer 13 covers the sidewalls of the plasma layer 12 (e.g., Figure 10 );

[0104] A second dielectric layer 14 is formed, which covers the upper surface of the substrate 10, the sidewalls and top of the first dielectric layer 13, and the top of the gate stack layer 11 and the plasma layer 12 (e.g., Figure 11 );

[0105] Part of the second dielectric layer 14 is removed, leaving the second dielectric layer 14 located on the substrate 10 and covering the sidewalls of the first dielectric layer 13 (e.g., Figure 12 ).

[0106] Specifically, the first sublayer 131 in the retained first dielectric layer 13 covers the sidewall of the plasma layer 12 and part of the upper surface of the substrate 10, and the second sublayer 132 is located on the first sublayer 131 and covers part of the sidewall of the first sublayer 131.

[0107] More specifically, removing a portion of the second dielectric layer 14 includes: removing the second dielectric layer 14 located on the upper surface of the substrate 10 and on top of the first dielectric layer 13, the plasma layer 12 and the gate stack layer 11.

[0108] Next, as Figure 13 As shown, after removing part of the second dielectric layer 14, the method further includes forming a third dielectric layer 15. The third dielectric layer 15 covers the upper surface of the substrate 10, the sidewalls and top of the second dielectric layer 14, and the top of the first dielectric layer 13, the plasma layer 12, and the gate stack layer 11. The first dielectric layer 13, the second dielectric layer 14, and the third dielectric layer 15 together protect the gate stack layer 11 and provide good isolation.

[0109] The second dielectric layer 14 and the third dielectric layer 15 can be deposited using one or more thin-film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the second dielectric layer 14 includes, but is not limited to, oxides, such as silicon oxide. The material of the third dielectric layer 15 includes, but is not limited to, nitrides, such as silicon nitride.

[0110] Figures 10 to 13 The second dielectric layer 14 shown is formed after an etching process is performed to remove a portion of the first dielectric layer 13 and the plasma layer 12. Then, another etching process is performed to remove a portion of the second dielectric layer 14, leaving the second dielectric layer 14 covering the sidewalls of the first dielectric layer 13. However, this is not the only possibility. Figures 14 to 15 As shown, in another embodiment of this disclosure, the second dielectric layer 14 can be formed directly after the first dielectric layer 13 is formed, and then a portion of the first dielectric layer 13 and a portion of the second dielectric layer 14 can be removed in the same process step.

[0111] Specifically, after forming the first dielectric layer 13, the process also includes:

[0112] A second dielectric layer 14 is formed, which covers the first dielectric layer 13 (e.g., Figure 14 );

[0113] Part of the second dielectric layer 14 and part of the first dielectric layer 13 are removed. The retained first dielectric layer 13 covers part of the upper surface of the substrate 10 and the plasma layer 12. The retained second dielectric layer 14 is located on the first dielectric layer 13 and covers part of the sidewall of the first dielectric layer 13.

[0114] Specifically, the first sublayer 131 of the retained first dielectric layer 13 covers part of the upper surface of the substrate 10 and the plasma layer 12, the second sublayer 132 covers the first sublayer 131, and the retained second dielectric layer 14 is located on the second sublayer 132 and covers part of the sidewall of the second sublayer 132.

[0115] In practice, a dry etching process can be used to remove part of the second dielectric layer 14 and part of the first dielectric layer 13. Since the materials of the second dielectric layer 14 and the first dielectric layer 13 are different, the process gases used to remove part of the second dielectric layer 14 and part of the first dielectric layer 13 are different. Therefore, the process gas needs to be changed during the etching process.

[0116] In this embodiment, the second dielectric layer 14 is formed directly after the first dielectric layer 13 is formed. Then, in the same process step, a portion of the first dielectric layer 13 and a portion of the second dielectric layer 14 are removed. Therefore, when etching the second dielectric layer 14, the first dielectric layer 13 protects the substrate 10. Figures 10 to 12 Compared to the process steps shown, this method can reduce the damage to the surface of the substrate 10 caused by the etching process.

[0117] Next, as Figure 16 As shown, a third dielectric layer 15 is formed, which covers the upper surface of the substrate 10, the sidewalls and top of the second dielectric layer 14, and the top of the first dielectric layer 13.

[0118] It should be noted that those skilled in the art can make possible changes to the order of the above steps without departing from the scope of protection of this disclosure.

[0119] This disclosure also provides a semiconductor structure, such as... Figure 13 As shown, the semiconductor structure includes: a substrate 10; a gate stack layer 11 located on the substrate 10; a plasma layer 12 including a first plasma at least adsorbed on the sidewalls of the gate stack layer 11; and a first dielectric layer 13 at least covering the sidewalls of the plasma layer 12; wherein the plasma layer 12 and the first dielectric layer 13 are formed in the same furnace tube.

[0120] Here, substrate 10 can be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 10 is a silicon substrate, which may be doped or undoped.

[0121] In one embodiment, the gate stack layer 11 includes a non-metallic conductive layer 111 and a metallic conductive layer 113 covering the non-metallic conductive layer 111. The material of the non-metallic conductive layer 111 includes one or a combination of monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, etc., and the non-metallic conductive layer 111 may be doped or undoped, for example, doped polycrystalline silicon. The material of the metallic conductive layer 113 includes tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, and silicide (WSi). x CoSi x NiSi x AlSi x (etc.), metal alloys or any combination thereof, such as tungsten.

[0122] In some embodiments, the gate stack 11 further includes a barrier layer 112 located between the non-metallic conductive layer 111 and the metallic conductive layer 113, and a capping layer 114 covering the metallic conductive layer 113. The barrier layer 112 is made of materials including, but not limited to, titanium nitride, and its function is to prevent the material of the metallic conductive layer 113 from diffusing downwards; the capping layer 114 is made of materials including, but not limited to, nitrides, such as silicon nitride, and its function is to protect other structures located below it.

[0123] like Figure 13 As shown, in one embodiment, the plasma layer 12 only covers the sidewalls of the gate stack layer 11. In actual operation, the plasma layer 12 can be as follows: Figures 6 to 7 The plasma is formed in the furnace tube 20 shown. Specifically, firstly, a furnace tube 20 is provided, comprising: a reaction chamber 21 and at least one embedded cavity 22 disposed on the inner wall of the reaction chamber 21. At least one pair of parallel radio frequency electrodes 24 are disposed in the embedded cavity 22, and the radio frequency electrodes 24 are used to dissociate the gas introduced into the embedded cavity 22 into plasma. Next, a substrate 10 including a gate stack layer 11 is placed in the reaction chamber 21. Then, a first source gas is introduced into the embedded cavity 22, and a radio frequency signal is applied to the radio frequency electrodes 24 to dissociate the first source gas into first plasma. The first plasma is adsorbed onto the sidewalls and upper surface of the gate stack layer 11 to form a plasma layer 12. In subsequent processes, an etching process can be performed on the plasma layer 12 so that the plasma layer 12 only covers the sidewalls of the gate stack layer 11.

[0124] Here, the first source gas is a nitrogen source gas, and the first plasma is a nitrogen-containing plasma; wherein, the first source gas includes, but is not limited to, one or a combination of nitrogen (N2), nitrogen oxides (N2O), and ammonia (NH3), such as ammonia (NH3).

[0125] In one embodiment, the first dielectric layer 13 includes a first sublayer 131 and a second sublayer 132 covering the first sublayer 131. For example... Figure 13 As shown, in one specific embodiment, a first sublayer 131 in the first dielectric layer 13 covers the sidewall of the plasma layer 12 and part of the upper surface of the substrate 10, and a second sublayer 132 is located on the first sublayer 131 and covers the sidewall of the first sublayer 131.

[0126] In the actual process, the first sublayer 131 can be formed in the same furnace tube 20 by the following method: First, a second source gas is introduced into the reaction chamber 21, and the second source gas is adsorbed on the surface of the plasma layer 12; then, a third source gas is introduced into the embedded cavity 22, and a radio frequency signal is applied to the radio frequency electrode 24 to dissociate the third source gas into a second plasma, and the second plasma reacts with the third source gas to form the first sublayer 131, which covers the plasma layer 12 and the substrate 10; then, the steps of introducing the second source gas into the reaction chamber 21, introducing the third source gas into the embedded cavity 22, and applying a radio frequency signal to the radio frequency electrode 24 are repeated until the first sublayer 131 is formed.

[0127] Here, the second source gas is a silicon source gas, including silanes or silane-derived materials, such as SiH4, Si2H6, or Si. n H 2n+2 (n is greater than 2), silane-derived materials include chlorosilanes or iodosilanes, such as dichlorosilane (SiH2Cl2). In some embodiments, the third source gas is a nitrogen source gas, and the second plasma is a nitrogen-containing plasma; wherein, the third source gas includes, but is not limited to, one or a combination of nitrogen (N2), nitrogen oxides (N2O), and ammonia (NH3), such as ammonia (NH3). The material of the first sublayer 131 includes, but is not limited to, nitrides, such as silicon nitride.

[0128] Next, the second sublayer 132 is formed in the same furnace tube 20 using the following method: First, a fourth source gas is introduced into the reaction chamber 21, and the fourth source gas is adsorbed onto the surface of the first sublayer 131; then, a fifth source gas is introduced into the reaction chamber 21, and the fifth source gas reacts with the fourth source gas to form the second sublayer 132, which covers the first sublayer 131; then, the steps of introducing a third source gas and a fourth source gas into the reaction chamber 21 are repeated until the second sublayer 132 is formed. In actual operation, an etching process can be subsequently performed on the first sublayer 131 and the second sublayer 132 so that the first sublayer 131 only covers the sidewalls of the plasma layer 12 and part of the upper surface of the substrate 10, and the second sublayer 132 is located on the first sublayer 131 and covers the sidewalls of the first sublayer 131.

[0129] Here, the fourth source gas is a silicon source gas, and the fourth source gas can be the same as the second source gas, such as dichlorosilane (SiH2Cl2). However, it is not limited to this, and the fourth source gas can also be different from the second source gas. In some embodiments, the fifth source gas is a nitrogen source gas (e.g., ammonia (NH3)), and the fifth source gas can be the same as or different from the first and third source gases. The material of the second sublayer 132 includes, but is not limited to, nitrides, such as silicon nitride.

[0130] In actual operation, the fifth source gas and the fourth source gas undergo a thermochemical reaction within the reaction chamber 21 to form the second sublayer 132. In this embodiment, the second plasma reacts with the second source gas to generate the first sublayer 131. The first sublayer 131 thus formed has better density and fewer impurities. Then, the fifth source gas and the fourth source gas undergo a thermochemical reaction to generate the second sublayer 132. Compared to using only the second plasma to react with the second source gas to form the first dielectric layer 13, this reduces the damage of the second plasma to the semiconductor structure. The first dielectric layer 13 thus formed has better density, fewer impurities, and less damage. In one embodiment, the thickness of the first sublayer 131 ranges from 0.3 nm to 0.5 nm, for example, 0.3 nm, 0.4 nm, or 0.5 nm; the thickness of the second sublayer 132 ranges from 5 nm to 15 nm, for example, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, or 15 nm.

[0131] As can be seen, in this embodiment of the present disclosure, before forming the first dielectric layer 13, a first plasma is adsorbed on the sidewall of the gate stack layer 11 to form a plasma layer 12. The first plasma replaces impurity atoms such as H, Cl, and O on the surface of the gate stack layer 11, making the surface properties of different materials in the gate stack layer 11 more consistent. Thus, the first dielectric layer 13 formed on the sidewall of the gate stack layer 11 in subsequent processes can have a more uniform thickness. In addition, the furnace tube 20 provided in this embodiment of the present disclosure includes an embedded cavity 22 with an internally disposed radio frequency electrode 24. Thus, the processes of forming the plasma layer 12 and the first dielectric layer 13 can be performed in the same furnace tube 20 without replacing the furnace tube, which helps to improve the stability of the semiconductor structure and save costs.

[0132] To characterize the uniformity of the thickness of the first dielectric layer 13 located on the sidewalls of the gate stack 11, a thickness deviation Δt is defined. Specifically, the first dielectric layer 13 located on the two opposite sidewalls of the metal conductive layer 113 has a first thickness a and a second thickness b, respectively, and the first dielectric layer 13 located on the two opposite sidewalls of the non-metal conductive layer 111 has a third thickness c and a fourth thickness d, respectively. The thickness deviation Δt between the portion of the first dielectric layer 13 located on the sidewall of the metal conductive layer 113 and the portion located on the sidewall of the non-metal conductive layer 111 is defined as: Δt = ((a+b)-(c+d)) / 2. It can be understood that the value of the thickness deviation Δt can reflect the uniformity of the thickness of the first dielectric layer 13 located on the sidewalls of the gate stack 11; the more uniform the thickness of the first dielectric layer 13, the smaller the value of the thickness deviation Δt. In one specific embodiment, the thickness deviation Δt of the first dielectric layer 13 formed by the manufacturing method provided in this disclosure is in the range of 0 to 0.2 nm, for example 0, 0.05 nm, 0.1 nm, 0.15 nm, 0.2 nm. That is, the first dielectric layer 13 formed by the manufacturing method provided in this disclosure has better uniformity, thereby improving the stability of the semiconductor structure.

[0133] In one embodiment, the semiconductor structure further includes a second dielectric layer 14, which is located on the substrate 10 and covers the sidewalls of the first dielectric layer 13. The material of the second dielectric layer 14 includes, but is not limited to, oxides, such as silicon oxide.

[0134] In one embodiment, the semiconductor structure further includes a third dielectric layer 15, which covers the upper surface of the substrate 10, the sidewalls and top of the second dielectric layer 14, and the top of the first dielectric layer 13, the plasma layer 12, and the gate stack layer 11. The first dielectric layer 13, the second dielectric layer 14, and the third dielectric layer 15 together protect the gate stack layer 11, providing good isolation. The material of the third dielectric layer 15 includes, but is not limited to, nitrides, such as silicon nitride.

[0135] Figure 13 The plasma layer 12 and the first dielectric layer 13 shown are located only on the sidewalls of the gate stack layer 11. However, this is not the only limitation; for example... Figure 16 As shown, in another embodiment of this disclosure, the plasma layer 12 further covers the top of the gate stack layer 11, and the first dielectric layer 13 covers a portion of the upper surface of the substrate 10 and the plasma layer 12. Specifically, a first sublayer 131 in the first dielectric layer 13 covers a portion of the upper surface of the substrate 10 and the plasma layer 12, a second sublayer 132 covers the first sublayer 131, a second dielectric layer 14 is located on the second sublayer 132 and covers the sidewalls of the second sublayer 132, and a third dielectric layer 15 covers the upper surface of the substrate 10, the sidewalls and top of the second dielectric layer 14, and the top of the first dielectric layer 13.

[0136] It should be noted that the above are merely optional embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A gate stack layer is formed on the substrate; A first plasma is adsorbed on the surface of the gate stack layer to form a plasma layer that at least covers the sidewalls of the gate stack layer; A first dielectric layer is formed, which at least covers the sidewalls of the plasma layer; wherein the plasma layer and the first dielectric layer are formed in the same furnace tube; Forming a plasma layer includes: A furnace tube is provided, the furnace tube comprising: a reaction chamber and at least one embedded cavity disposed on the inner wall of the reaction chamber, wherein at least one pair of parallel radio frequency electrodes are disposed in the embedded cavity, the radio frequency electrodes being used to dissociate gas introduced into the embedded cavity into plasma; The substrate, including the gate stack layer, is placed inside the reaction chamber; A first source gas is introduced into the embedded cavity, and a radio frequency signal is applied to the radio frequency electrode to dissociate the first source gas into a first plasma. The first plasma is adsorbed onto the sidewalls and upper surface of the gate stack layer to form the plasma layer.

2. The manufacturing method according to claim 1, characterized in that, The inner cavity has multiple spray nozzles on its sidewall, and the size of the spray nozzles located on the upper part of the inner cavity sidewall is larger than the size of the spray nozzles located on the lower part of the inner cavity sidewall.

3. The manufacturing method according to claim 1, characterized in that, The number of embedded cavities is multiple, and the multiple embedded cavities are equally spaced on the inner wall of the reaction chamber.

4. The manufacturing method according to claim 1, characterized in that, Forming a first dielectric layer includes: A second source gas is introduced into the reaction chamber, and the second source gas is adsorbed on the surface of the plasma layer and the upper surface of the substrate; A third source gas is introduced into the embedded cavity, and a radio frequency signal is applied to the radio frequency electrode to dissociate the third source gas into a second plasma. The second plasma reacts with the third source gas to form a first sublayer, and the first sublayer covers the plasma layer and the substrate. The steps of introducing a second source gas into the reaction chamber, introducing a third source gas into the embedded cavity, and applying a radio frequency signal to the radio frequency electrode are performed again until a first sublayer with a first preset thickness is formed.

5. The manufacturing method according to claim 4, characterized in that, After forming a first sublayer with a first preset thickness, the method further includes: A fourth source gas is introduced into the reaction chamber, and the fourth source gas is adsorbed onto the surface of the first sublayer. A fifth source gas is introduced into the reaction chamber, and the fifth source gas reacts with the fourth source gas to form a second sublayer, which covers the first sublayer. The steps of introducing a third source gas and a fourth source gas into the reaction chamber are repeated until a second sub-layer with a second preset thickness is formed. The first sub-layer and the second sub-layer constitute the first dielectric layer.

6. The manufacturing method according to claim 5, characterized in that, After forming the first dielectric layer, the process further includes: Remove the first dielectric layer and the plasma layer covering the upper surface of the substrate and the top of the gate stack layer, with the plasma layer remaining covering the sidewalls of the gate stack layer and the first dielectric layer remaining covering the sidewalls of the plasma layer; A second dielectric layer is formed, which covers the upper surface of the substrate, the sidewalls and top of the first dielectric layer, and the top of the gate stack layer and the plasma layer; A portion of the second dielectric layer is removed, leaving the second dielectric layer located on the substrate covering the sidewalls of the first dielectric layer; Alternatively, after forming the first dielectric layer, the method further includes: A second dielectric layer is formed, which covers the first dielectric layer; A portion of the second dielectric layer and a portion of the first dielectric layer are removed, with the remaining first dielectric layer covering a portion of the upper surface of the substrate and the plasma layer, and the remaining second dielectric layer located on the first dielectric layer and covering a portion of the sidewall of the first dielectric layer.

7. A semiconductor structure formed by the method according to any one of claims 1-6, characterized in that, include: Substrate; A gate stack layer is located on the substrate; The plasma layer includes at least a first plasma adsorbed onto the sidewalls of the gate stack layer; A first dielectric layer covers at least the sidewalls of the plasma layer; wherein the plasma layer and the first dielectric layer are formed in the same furnace tube.

8. The semiconductor structure according to claim 7, characterized in that, The gate stack layer includes a non-metallic conductive layer and a metallic conductive layer covering the non-metallic conductive layer. The first dielectric layer located on two opposite sidewalls of the metallic conductive layer has a first thickness a and a second thickness b, respectively. The first dielectric layer located on two opposite sidewalls of the non-metallic conductive layer has a third thickness c and a fourth thickness d, respectively. The thickness deviation Δt between the portion of the first dielectric layer located on the sidewall of the metallic conductive layer and the portion located on the sidewall of the non-metallic conductive layer is defined as follows: Δt=((a+b)-(c+d)) / 2; The thickness deviation Δt ranges from 0 to 0.2 nm.

9. The semiconductor structure according to claim 7, characterized in that, The first dielectric layer includes a first sublayer and a second sublayer covering the first sublayer; the thickness of the first sublayer ranges from 0.3 nm to 0.5 nm, and the thickness of the second sublayer ranges from 5 nm to 15 nm.

Images