Method of forming a semiconductor structure and semiconductor structure

Abstract

This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself, relating to the semiconductor field. The method for forming the semiconductor structure includes: providing a substrate; performing a first etching on the substrate to form an array of openings, the openings exposing a target region of the substrate; performing a first cleaning of the openings with deionized water; depositing a first conductive layer, the first conductive layer at least covering the sidewalls and bottom surface of the openings; doping the first conductive layer covering the bottom surface of the openings to form a first implantation layer; performing a second cleaning of the openings to remove the first implantation layer and the first conductive layer, exposing the target region; oxidizing the exposed target region with a strongly oxidizing chemical substance to form an oxide layer; and performing a third cleaning of the openings to remove the oxide layer. By combining deionized water, the second cleaning, the strongly oxidizing oxidation, and the third cleaning, damage to the semiconductor structure is reduced, ensuring the electrical and structural performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Technology

[0002] With technological advancements, integrated circuit manufacturing processes have continuously improved, enabling the integration of various electronic circuits onto a single chip. Semiconductor manufacturing processes for chips involve numerous steps, such as thin-film deposition and etching processes for patterning thin films. To meet product demands, the size of circuits and components on chips continues to shrink, leading to increasingly stringent requirements on the process windows of various manufacturing processes.

[0003] In related technologies, due to the miniaturization of the critical dimension (CD), the existing bit line contact area formation process is prone to damage to the active area, resulting in a decrease in the electrical and structural performance of the device, which affects the yield and reliability of integrated circuit chips. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself.

[0006] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0007] Provide a base;

[0008] The substrate is first etched to form an array of openings, the openings exposing a target area of ​​the substrate;

[0009] The opening was first cleaned using deionized water;

[0010] A first conductive layer is deposited, which at least covers the sidewalls and bottom surface of the opening;

[0011] The first conductive layer covering the bottom surface of the opening is doped to form a first implantation layer;

[0012] The opening is then subjected to a second cleaning to remove the first injection layer, exposing the target area;

[0013] The exposed target area is oxidized using a chemical substance with strong oxidizing properties to form an oxide layer;

[0014] The opening is then subjected to a third cleaning to remove the oxide layer.

[0015] According to some embodiments of this disclosure, doping the first conductive layer covering the bottom surface of the opening includes:

[0016] The first conductive layer covering the bottom surface of the opening is doped using ion implantation.

[0017] According to some embodiments of this disclosure, the dopant ions used when doping the first conductive layer covering the bottom surface of the opening with ion implantation include arsenic ions or phosphorus ions.

[0018] According to some embodiments of this disclosure, while the first conductive layer covering the bottom surface of the opening is doped by ion implantation, an ion implantation damage layer is formed on the surface of the target region located at the bottom of the first conductive layer.

[0019] According to some embodiments of this disclosure, the exposed target area is oxidized using a chemical substance with strong oxidizing properties, including:

[0020] The target area is oxidized using a solution containing ozone or hydrogen peroxide.

[0021] According to some embodiments of this disclosure, both the second cleaning and the third cleaning are performed using a dry cleaning method;

[0022] The dry cleaning process includes a mixture of nitrogen-containing and fluorine-containing gases.

[0023] According to some embodiments of this disclosure, the method for forming the semiconductor structure further includes:

[0024] A second conductive layer is deposited, which fills the opening.

[0025] According to some embodiments of this disclosure, the first conductive layer and the second conductive layer are made of the same material.

[0026] According to some embodiments of this disclosure, before the first etching is performed on the substrate to form the opening of the array, the method further includes:

[0027] A first isolation layer and a second isolation layer covering the first isolation layer are deposited on the substrate.

[0028] According to some embodiments of this disclosure, the method for forming the semiconductor structure further includes:

[0029] The second conductive layer is etched back to the preset position, completely exposing the second isolation layer.

[0030] According to some embodiments of this disclosure, the preset position is lower than the top surface of the first isolation layer, or the preset position is flush with the top surface of the first isolation layer.

[0031] According to some embodiments of this disclosure, the method for forming the semiconductor structure includes:

[0032] Remove the second isolation layer to expose the top surface of the first isolation layer.

[0033] According to a second aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure being fabricated using the semiconductor structure formation method described in the first aspect of the present disclosure;

[0034] The substrate includes several active regions arranged in an array, and the openings in the substrate include bit line contact holes. The target area exposed by the openings is located at the middle position of each of the active regions.

[0035] The semiconductor structure formation method and semiconductor structure disclosed herein are processed by a combination of deionized water, second cleaning, strong oxidizing oxidation and third cleaning to avoid damage to the semiconductor structure and ensure the electrical and structural performance of the semiconductor structure.

[0036] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0038] Figure 1 This is a schematic diagram of a semiconductor structure.

[0039] Figure 2 This is a schematic diagram of a semiconductor structure.

[0040] Figure 3 This is a schematic diagram of a semiconductor structure.

[0041] Figure 4 This is a schematic flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0042] Figure 5 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0043] Figure 6 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0044] Figure 7 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0045] Figure 8 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0046] Figure 9 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0047] Figure 10 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0048] Figure 11 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0049] Figure 12 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0050] Figure 13 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0051] Figure 14 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0052] Figure 15 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment.

[0053] Figure label:

[0054] 1. Substrate; 2. Column; 20. Particle residue; 21. First isolation layer; 22. Second isolation layer; 23. Active region; 3. Opening; 4. Target region; 5. First conductive layer; 6. First implantation layer; 61. Ion implantation damage layer; 7. Oxide layer; 8. Second implantation layer; 9. Second conductive layer; 10. Preset position. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0056] With technological advancements, integrated circuit manufacturing processes have continuously improved, enabling the integration of various electronic circuits onto a single chip. Semiconductor manufacturing processes for chips involve numerous steps, such as thin-film deposition and etching processes for patterning thin films. To meet product demands, the size of circuits and components on chips continues to shrink, leading to increasingly stringent requirements on the process windows of various manufacturing processes.

[0057] In related technologies, due to the miniaturization of the critical dimension (CD), the existing bit line contact region formation process first etches the substrate 1 to form an array of pillars 2. Adjacent pillars 2 form openings 3, which expose the target region 4. When forming the bit line contact region on the substrate 1, the target region 4 is located on the top surface of the active region, i.e., the bottom surface of the opening 3. During the etching process, particulate matter remains in the target region 4, and oxidation can damage the target region 4. To remove the particulate matter and mitigate the damage to the target region 4, wet cleaning is typically used to clean the target region 4. During the wet cleaning process to remove particulate matter and damaging substances from the target region 4, the chemical agents used in the wet cleaning can cause the following damage to the semiconductor structure:

[0058] 1. The chemical agent comes into contact with and reacts with the first isolation layer 21 on the column 2 forming the opening 3, causing damage to the sidewall of the first isolation layer 21. (Refer to...) Figure 1 ;

[0059] 2. Due to damage such as cracks on the sidewalls of the first isolation layer 21, the cleaning solution can easily penetrate from the damaged area A of the first isolation layer 21 into the underlying active region 23. This causes the active region 23 to be affected by the chemical agents, thereby affecting the electrical and structural properties of the semiconductor structure. (Refer to...) Figure 2 ;

[0060] 3. During the etching process of substrate 1 to form opening 3, the isolation layer on the side of pillar 2 may become thinner due to factors such as positional displacement. (Refer to...) Figure 3 As shown, during the wet cleaning process to remove particulate matter and damaging substances from the target area 4, the cleaning solution easily reacts with the isolation layer on the pillar 2 on the side of the opening 3, thereby exposing the active region 23 in the pillar 2. The contact between the cleaning solution and the active region 23 causes damage to the active region 23. Moreover, because the size of the opening 3 is offset relative to the target size, the dimensional accuracy of the opening 3 changes, which further reduces the processing accuracy in subsequent processes, resulting in a decline in the electrical and structural performance of the semiconductor structure.

[0061] Based on this, the present disclosure provides a method for forming a semiconductor structure, comprising: providing a substrate; performing a first etching on the substrate to form an array of openings, the openings exposing a target region of the substrate; performing a first cleaning of the openings with deionized water; depositing a first conductive layer, the first conductive layer at least covering the sidewalls and bottom surface of the openings; doping the first conductive layer covering the bottom surface of the openings to form a first implantation layer; performing a second cleaning of the openings to remove the first implantation layer and the first conductive layer, exposing the target region; oxidizing the exposed target region with a chemical substance with strong oxidizing properties to form an oxide layer; and performing a third cleaning of the openings to remove the oxide layer. By combining deionized water, the second cleaning, strong oxidizing, and the third cleaning, damage to the target region is avoided, ensuring the electrical and structural performance of the semiconductor device.

[0062] In exemplary embodiments of this disclosure, such as Figures 4 to 12 The diagram illustrates a method for forming a semiconductor structure. This method can be used to form openings during the fabrication of a semiconductor structure. To provide a detailed explanation of the formation method, this embodiment uses the process of forming bit line contact holes as a specific scenario. The semiconductor structure formation method in this embodiment includes:

[0063] Step S101, provide a substrate;

[0064] Step S102: The substrate is first etched to form an opening for the array configuration, and the opening exposes the target area of ​​the substrate;

[0065] Step S103: The opening is first cleaned with deionized water;

[0066] Step S104: Deposit a first conductive layer, the first conductive layer at least covering the sidewalls and bottom surface of the opening;

[0067] Step S105: Doping the first conductive layer covering the bottom surface of the opening to form the first implantation layer;

[0068] Step S106: Perform a second cleaning on the opening to remove the first injection layer and expose the target area;

[0069] Step S107: The exposed target area is oxidized using a chemical substance with strong oxidizing properties to form an oxide layer;

[0070] Step S108: Perform a third cleaning on the opening to remove the oxide layer.

[0071] In step S101, see Figure 5The substrate 1 includes a plurality of active regions 23 arranged in an array for forming active devices thereon. In this embodiment, the material of the active regions 23 includes one or more of silicon, single crystal silicon, single crystal silicon germanium, and amorphous silicon; the substrate 1 may also be, for example, a silicon on insulator (SOI) substrate.

[0072] In step S102, the first etching is performed on the substrate 1 to form the opening 3 of the array configuration, see [link to relevant documentation]. Figure 6 The first etching process can be, for example, dry etching, which can include physical etching, chemical etching, and physicochemical etching. Physical etching, also known as sputtering etching, uses energy to bombard atoms that act on the substrate 1, forming openings 3 and pillars 2 between adjacent openings 3. Chemical etching utilizes chemically active atomic groups in a plasma gas to react chemically with the material being etched, thereby achieving the etching purpose. Depending on the material being etched, for example, for the first isolation layer 21, the second isolation layer 22, and the active region 23, gases with different etching selectivity ratios can be selected to react with the material more quickly. Etching gases used in chemical etching include, but are not limited to, carbon tetrafluoride (CF4), trifluoromethane (CHF3), chlorine (Cl2), sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), or hexafluorobutadiene (C4F6). Physicochemical etching can include reactive ion etching (RIE) and high-density plasma etching (HDP), which etch the substrate through the dual action of physical bombardment by active ions and chemical reaction, while also having the advantages of anisotropy and good selectivity.

[0073] The opening 3 in the array configuration can increase the arrangement density of memory cells. Through the first etching, the opening 3 in the array configuration is formed, and the opening 3 exposes the target region 4 in the substrate 1. The target region 4 is the middle position of the active region 23, so that the opening 3 forms a bit line contact hole. The bit line contact plug is subsequently formed in the bit line contact hole, and the bit line contact plug is in contact with the target region 4 (i.e., the middle position of the active region 23) to form an electrical connection.

[0074] After performing the first etching to expose the target region 4 in the substrate 1 through the opening 3, see [link to original text]. Figure 6There may be some particulate residue 20 on the surface of the exposed target area 4 and the side wall of the pillar 2. The particulate residue 20 mainly includes silicon residue and silicon dioxide residue generated by etching. If it is not cleaned, it can easily damage the circuit function inside the wafer, form short circuits or open circuits, and cause the failure of integrated circuits and affect the formation of geometric features.

[0075] In step S103, since there may be some particulate residue 20 on the surface of the target area 4 and the side wall of the column 2, see... Figure 6 and Figure 7 The opening 3 is first cleaned with deionized water (DIW) to obtain a clean opening 3 and avoid the particulate residue 20 from affecting the electrical performance of the semiconductor structure.

[0076] For example, the opening 3 is first cleaned using deionized water. This can be achieved by using a scrubber, a machine with a specific cleaning method, primarily using DIW to rinse or brush the surface of the substrate 1 to remove particulate residue 20 adhering to the sidewalls of the opening 3 and the column 2, resulting in a clean opening 3. Alternatively, the substrate 1 can be immersed in a water tank filled with DIW, and the substrate 1 can be rinsed using circulating water to remove particulate residue 20. Another method is to use DIW as a cleaning solution, adding it to an ultrasonic container and using high-frequency ultrasonic oscillation to compress or expand the solution. The expansion of the solution creates gaps similar to cavities within the solution molecules. These cavities draw in gas molecules already dissolved in the solution, forming bubbles. Simultaneously, the solution is compressed, and the bubbles burst, creating a near-explosive effect that blasts the particulate residue 20 from the opening 3, causing it to detach and thus achieving the cleaning purpose, resulting in a clean opening 3. Using DIW to clean the opening 3 can avoid damage to the first isolation layer 21 and the second isolation layer 22, and prevent the target area 4 from being contaminated, thereby ensuring the electrical and structural performance of the semiconductor device.

[0077] In step S104, after cleaning the opening 3, a first conductive layer 5 is deposited (DEP) on the substrate 1, see [link to step S104]. Figure 8The first conductive layer 5 covers at least the sidewalls and bottom surface of the opening 3. The material of the first conductive layer 5 includes a silicon-containing dielectric material, such as one or more of silicon, polysilicon, single crystal silicon, single crystal silicon germanium, and amorphous silicon. In one embodiment, the first conductive layer 5 is made of polysilicon. The first conductive layer 5 is deposited on the substrate 1 such that it covers at least the sidewalls and bottom surface of the opening 3, protecting these surfaces. Simultaneously, because the first conductive layer 5 is thin, it can completely adhere to the sidewalls and bottom surface of the opening 3, minimizing the presence of air gaps within it, thereby preventing air gaps from affecting the electrical performance of the semiconductor structure. Since the deposition process deposits the substrate 1 indiscriminately, the first conductive layer 5 also covers the top surface of the pillar 2. The first conductive layer 5 covering the top surface of the pillar 2 will be removed in subsequent steps, and the first conductive layer 5 covering the top surface of the pillar 2 will not affect the process of semiconductor structure.

[0078] In step S105, after depositing the first conductive layer 5, see... Figure 9 The first conductive layer 5 covering the bottom surface of the opening 3 is doped to form the first implanted layer 6. Doping typically involves incorporating small amounts of other elements or compounds into a material or substance to improve its properties. Doping methods can include vapor deposition or ion implantation. By doping the first conductive layer 5 covering the bottom surface of the opening 3, the structural properties of the first conductive layer 5 are altered, forming the first implanted layer 6, making the first implanted layer 6 on the bottom surface of the opening 3 easier to remove.

[0079] In some possible implementations, ion implantation is used to dope the first conductive layer 5 covering the bottom surface of the opening 3. Ion implantation is a material performance modification technique that accelerates ions under vacuum and low temperature conditions, for example, by applying voltage. An ion beam with an energy on the order of 100 keV can be directly incident on the first conductive layer 5 covering the bottom surface of the opening 3. The ion beam undergoes a series of physical and chemical interactions with the atoms in the first conductive layer 5. The incident ions gradually lose energy and eventually remain in the first conductive layer 5, causing a change in the structural properties of the first conductive layer 5, forming the first implanted layer 6, thereby obtaining new structural properties and making the first implanted layer 6 on the bottom surface of the opening 3 easier to remove.

[0080] In some possible implementations, see 9. Since the depth of ion implantation is difficult to control, while the first conductive layer 5 covering the bottom surface of the opening 3 is doped by ion implantation, some incident ions will also be injected into the target region 4, which will have a certain impact on the target region 4. An ion implantation damage layer 61 is formed on the surface of the target region 4 located at the bottom of the first conductive layer 5. The presence of the implantation damage layer 61 will have an adverse effect on the semiconductor structure. Therefore, the implantation damage layer 61 will be removed in subsequent steps.

[0081] In some possible implementations, when the first conductive layer 5 covering the bottom surface of the opening 3 is doped by ion implantation, the selected dopant ions are arsenic (As) ions or phosphorus (P) ions.

[0082] For example, since the first conductive layer 5 is made of polycrystalline silicon and the target region 4 is also made of silicon-containing material, when the dopant ion is arsenic ion, the first implantation layer 6 is made of arsenic-doped silicon (As-doped Si). When the dopant ion is phosphorus ion, the first implantation layer 6 is made of phosphorus-doped silicon (P-doped Si).

[0083] In step S106, after the first injection layer 6 is formed, see [link to step S106]. Figure 9 and Figure 10 As shown, a second cleaning is performed on opening 3 to remove the first implantation layer 6, exposing the target region 4. Since the target region 4 is located in the middle of the active region 23, the bit line contact plugs formed in the subsequent opening 3 need to be connected to the target region 4. In order to ensure the electrical performance of the semiconductor structure, the first implantation layer 6 needs to be removed to expose the target region 4.

[0084] In this step, the target area 4 exposed during the second cleaning of the opening 3 to remove the first injection layer 6 is larger than the target area 4 exposed by the first etching in step S102, so that the contact area between the bit line contact plug formed in the opening 3 and the target area 4 is larger, so as to form a bit line contact plug with a more stable electrical connection signal.

[0085] The second cleaning process can employ a dry cleaning method to remove the first injection layer 6, such as plasma cleaning. During plasma cleaning, the gas within the vacuum chamber is ionized by a radio frequency power supply to generate plasma. This high-energy plasma can physically bombard the first injection layer 6, causing it to detach from the surface of the target region 4. Furthermore, the ionization of the gas within the vacuum chamber generates corresponding active particles. These particles react chemically with the first injection layer 6 to form volatile substances, which are then expelled from the reaction chamber by a vacuum pump, thus removing the first injection layer 6 and exposing the target region 4.

[0086] In some possible implementations, the gas used for the second cleaning of the first implanted layer 6 may include a mixture of nitrogen-containing and fluorine-containing gases, such as a combination of nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), and ammonia (NH3). In one embodiment, NF3 and NH3 are selected as the gases used for plasma cleaning. When the dopant ions used for ion implantation are arsenic ions, during the plasma cleaning process, NF3, NH3, and As-doped Si react to generate As. (x) H (y) The reaction principle with SiF4 is as follows:

[0087] NF3 + NH3 + As doped Si → As (x) H (y) +SiF4

[0088] When phosphorus ions are used for ion implantation, NF3, NH3, and Pdoped Si react to generate P during plasma cleaning. (x) H (y) The reaction principle with SiF4 is as follows:

[0089] NF3+NH3+P doped Si→P (x) H (y) +SiF4

[0090] Due to As (x) H (y) P (x) H (y) Both SiF4 and SiF4 are gases. After the reaction occurs, the gas dissipates and no impurities that affect the target region 4 are generated. The first injection layer 6 and the first conductive layer 5 are removed, exposing the target region 4.

[0091] In another embodiment, NF3, N2, and H2 are selected as the gases used for plasma cleaning. N2 and H2 react to produce NH3. The reaction principle is as follows:

[0092] N2 + H2 → NH3

[0093] This allows NF3, NH3, and As doped Si or P doped Si to undergo the aforementioned reactions during plasma cleaning, thereby removing the first implanted layer 6 and exposing the target region 4.

[0094] During the first etching and the first and second cleaning processes, see Figure 10As shown, when target region 4 comes into contact with water and oxygen, an oxide layer called the native oxide layer will form on the surface of target region 4. When the material of target region 4 is Si, the reaction principle is as follows:

[0095] Si + O₂ → SiO₂, or

[0096] Si + H₂O → SiO₂ + H₂.

[0097] The presence of the native oxide layer can also affect the electrical performance of the semiconductor structure, such as increasing the contact resistance between the formed bit line contact plug and the active region. Therefore, the native oxide layer needs to be removed in subsequent steps.

[0098] In step S107, due to the presence of the native oxide layer and the fact that some incident ions will enter the target region 4 during ion implantation, causing damage to the surface of the target region 4 (damaged silicon) and forming an ion implantation damage layer 61. Therefore, in order to ensure the quality of the target region 4, after exposing the target region 4, see [the relevant documentation]. Figure 11 As shown, a chemical substance with strong oxidizing properties is used to oxidize the exposed target area 4, forming an oxide layer 7. Specifically, a chemical substance with strong oxidizing properties is used to oxidize the ion implantation damage layer 61 and the original oxide layer on the surface of the target area 4, which is damaged by ion implantation. The chemical substance with strong oxidizing properties has the ability to increase the oxidation state of other elements and has a strong electron-withdrawing ability. After gaining electrons, it is reduced, its oxidation state decreases, and the oxidation state of the oxidized substance increases, thereby forming an oxide layer 7, which is then removed to obtain a clean and uncontaminated target area 4.

[0099] When the exposed target area 4 is oxidized using a strong oxidizing chemical, the first conductive layer 5 on the sidewall of the opening 3 will also be partially oxidized. However, since the ion implantation damage layer 61 on the surface of the target area 4 is more easily oxidized, the oxidation rate of the first conductive layer 5 will be lower than that of the ion implantation damage layer 61. An oxide layer (not shown in the figure) with a thickness less than that of the oxide layer 7 will be formed on the surface of the first conductive layer 5. The oxide formed on the surface of the first conductive layer 5 will be removed along with the oxide layer 7 in the subsequent removal process.

[0100] In some possible implementations, the exposed target area is oxidized using a solution containing ozone or hydrogen peroxide. In one embodiment, the exposed target area 4 is oxidized using an ozone-containing solution. The ozone gas can be mixed with the solution, which can be sulfuric acid or deionized water, to oxidize the ion-implanted damage layer 61 in the exposed target area 4, forming silicon dioxide, i.e., the oxide layer 7. Ozone (O3) dissolves in water (H2O) and can react to generate hydrogen superoxide (HO2). The reaction principle is as follows:

[0101] H₂O + O₃ → H₂O

[0102] HO2 contains superoxide ions and has strong oxidizing properties, which can oxidize the ion implantation damaged layer 61, making it easier to remove later.

[0103] The exposed target area 4 is oxidized using a solution containing hydrogen peroxide, which has strong oxidizing properties. In one embodiment, the solution containing hydrogen peroxide may include, for example, SC1 cleaning solution. SC1 cleaning solution is used to oxidize the target area 4. SC1 cleaning solution is also called APM (Ammonium hydroxide / hydrogen peroxide / deionized water mixture), which is a mixture of ammonia, hydrogen peroxide, and water. Its formula is NH4OH:H2O2:H2O = 1:1:5 to 1:2:7, and the reaction temperature is 65 to 80°C. Due to the strong oxidizing properties of hydrogen peroxide, the ion implantation damage layer 61 in the exposed target area 4 is oxidized to form silicon dioxide, i.e., oxide layer 7, which facilitates subsequent removal of oxide layer 7.

[0104] In another embodiment, the solution containing hydrogen peroxide may also include, for example, SPM cleaning solution. SPM (Sulfuric acid / hydrogen peroxide / deionized water mixture) is a mixed solution of sulfuric acid and hydrogen peroxide, wherein the volume ratio of sulfuric acid to water is 1:3, and the reaction temperature is 100-130°C. Since both hydrogen peroxide and concentrated sulfuric acid have strong oxidizing properties, they oxidize the ion implantation damage layer 61 in the exposed target region 4 to form silicon dioxide, i.e., oxide layer 7, so that the oxide layer 7 can be removed subsequently.

[0105] In step S108, after forming oxide layer 7, bonding Figure 11 and Figure 12 As shown, a second cleaning can be performed on the opening 3 to remove the oxide layer 7, resulting in a clean target area 4, so that the target area 4 can form bit line contact with the bit line through the opening 3. The third cleaning may include wet cleaning or dry cleaning.

[0106] In one embodiment, the oxide layer 7 is removed by dry cleaning. Dry cleaning can be plasma cleaning. The gas used for the second cleaning of the oxide layer 7 can include a mixture of nitrogen-containing and fluorine-containing gases, such as one or more of nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), and ammonia (NH3). For example, when NF3 and NH3 are selected as the gases used for plasma cleaning to remove the oxide layer 7, NF3 and NH3 can react to generate NH4F or NH4F·HF. The reaction principle is as follows:

[0107] NF3 + NH3 → NH4F, or,

[0108] NF3 + NH3 → NH4F·HF.

[0109] NH4F or NH4F·HF can react with silicon dioxide (SiO2), the component of oxide layer 7, to produce (NH4)2SiF6 and water. The reaction principle is as follows:

[0110] NH4F + SiO2 → (NH4)2SiF6 + H2O, or

[0111] NH4F·HF+SiO2→(NH4)2SiF6+H2O.

[0112] (NH4)2SiF6 can sublimate at temperatures above 100°C, and water evaporates simultaneously, thus preventing the generation of impurities that could affect the target region 4, resulting in a clean target region 4.

[0113] When NF3, N2, and H2 are selected as the gases used for plasma cleaning to remove oxide layer 7, N2 and H2 react to generate NH3. The reaction principle is as follows:

[0114] N2 + H2 → NH3

[0115] This allows NH3 to react with NF3 to generate NH4F or NH4F·HF, and to react with SiO2 as described above, thereby removing the oxide layer 7 and obtaining a clean target area 4.

[0116] In one embodiment, the oxide layer 7 is removed by wet cleaning. Wet cleaning is a cleaning method that introduces a solution, and can include steam cleaning, solution immersion cleaning, or rotary spray cleaning. Since the oxide layer 7 is composed of silicon dioxide, the solution used for wet cleaning can be, for example, hydrofluoric acid (HF) or diluted hydrofluoric acid (DHF). HF can react with SiO2 to generate SiF4, and the reaction principle is as follows:

[0117] SiO2 + HF → SiF4 + H2O

[0118] Since SiF4 is a gas, it will not produce impurities that affect the target region 4, thus resulting in a clean target region 4.

[0119] In one exemplary embodiment, the method for forming a semiconductor structure provided in this disclosure further includes:

[0120] S201. While doping the first conductive layer covering the bottom surface of the opening using ion implantation, the first conductive layer covering the top surface of the pillar is also doped to form a second implantation layer.

[0121] S202. The opening is cleaned a second time to remove the first injection layer, and the second injection layer is removed at the same time.

[0122] In step S201, for the sake of simplicity in the manufacturing process, refer to Figure 9 As shown, when performing step S105, step S201 is also performed simultaneously to form a second injection layer 8 so as to change the structure and properties of the first conductive layer 5 covering the top surface of the column 2. The second injection layer 8 makes it easier to remove the first conductive layer 5 on the top surface of the column 2.

[0123] In step S202, refer to Figure 9 and Figure 10 The column 2 is then cleaned a second time to remove the second injection layer 8 from the top surface of the column 2, exposing the top surface of the column 2. The implementation of step S202 can be the same as step S106, and for the sake of simplicity in the manufacturing process, step S202 is performed simultaneously with step S106.

[0124] In one exemplary embodiment, see Figure 13 , Figure 14 and Figure 15 As shown, the method for forming a semiconductor structure provided in this disclosure further includes:

[0125] Step S101, provide a substrate;

[0126] Step S102: The substrate is first etched to form an opening for the array configuration, and the opening exposes the target area of ​​the substrate;

[0127] Step S103: The opening is first cleaned with deionized water;

[0128] Step S104: Deposit a first conductive layer, the first conductive layer at least covering the sidewalls and bottom surface of the opening;

[0129] Step S105: Doping the first conductive layer covering the bottom surface of the opening to form the first implantation layer;

[0130] Step S106: Clean the area through the opening to remove the first injection layer and the first conductive layer, exposing the target area;

[0131] Step S107: The exposed target area is oxidized using a chemical substance with strong oxidizing properties to form an oxide layer;

[0132] Step S108: Perform a third cleaning on the opening to remove the oxide layer;

[0133] Step S109: Deposit a second conductive layer, the second conductive layer fills the opening;

[0134] Step S110: Write the second conductive layer back to the preset position to fully expose the second isolation layer;

[0135] Step S111: Remove the second isolation layer to expose the top surface of the first isolation layer.

[0136] In this embodiment, steps S101 to S108 are the same as those in the above implementation method, and will not be described again here.

[0137] In step S109, see Figure 13 The second conductive layer 9 can be deposited using chemical vapor deposition or physical vapor deposition. For ease of fabrication, the deposited second conductive layer 9 fills the opening 3, so that the opening 3 is enclosed within the second conductive layer 9. The material of the second conductive layer 9 includes, for example, one or more of silicon, polycrystalline silicon, monocrystalline silicon, monocrystalline silicon-germanium, and amorphous silicon.

[0138] In some possible implementations, the first conductive layer 5 and the second conductive layer 9 are made of the same material. For example, when the material of the first conductive layer 5 is silicon, the material of the second conductive layer 9 can also be silicon. When the material of the first conductive layer 5 is polycrystalline silicon, the material of the second conductive layer 9 can also be polycrystalline silicon. Since the first conductive layer 5 has been deposited in step S104, the first conductive layer 5 is completely attached to the top surface and sidewalls of the pillar 2, and air gaps are not easily generated in the first conductive layer 5. When the materials of the first conductive layer 5 and the second conductive layer 9 are the same, the deposited second conductive layer 9 is also less prone to bubble formation, increasing the electrical stability of the formed bit line contact plug. Moreover, the fact that the materials of the first conductive layer 5 and the second conductive layer 9 are the same ensures that the dielectric properties of the first conductive layer 5 and the second conductive layer 9 are the same, guaranteeing the stability of the bit line contact.

[0139] In some possible implementations, such as Figure 5 As shown, before the first etching of the substrate to form the opening for the array configuration, the method further includes:

[0140] A first isolation layer and a second isolation layer covering the first isolation layer are deposited on the substrate.

[0141] In this embodiment, a plurality of active regions 23 spaced apart are first formed in the substrate 1, with adjacent active regions 23 being mutually insulated. Then, a first isolation layer 21 and a second isolation layer 22 covering the first isolation layer 21 are deposited above the active regions 23. The first isolation layer 21 and the second isolation layer 22 covering the first isolation layer 21 can protect and mask the active regions 23. The material of the first isolation layer 21 can be an insulating material, such as silicon nitride (Si3N4), and the material of the second isolation layer 22 can be an insulating material, such as silicon oxide (SiO2), but is not limited thereto.

[0142] In step S110, see Figure 14 Since the substrate 1 includes an active region 23 and is deposited with a first isolation layer 21 and a second isolation layer 22 covering the first isolation layer 21, after the substrate 1 is etched to form the array-configured openings 3, the pillars 2 adjacent to the openings 3 may also include the retained first isolation layer 21 and the retained second isolation layer 22. The first isolation layer 21 can provide isolation and masking for the active region 23.

[0143] Etching back refers to etching a portion of the second conductive layer 9 to a predetermined position 10 to expose the second isolation layer 22. The predetermined position 10 is, for example, located on the sidewall of the pillar 2. Since the second conductive layer 9 and the second isolation layer 22 are made of different materials, wet etching can be used to etch the second conductive layer 9 to the predetermined position 10. This allows the second conductive layer 9 retained in the opening 3 and the first conductive layer 5 to together form a bit line contact plug, enabling the target area 4 to contact the bit line through the bit line contact plug.

[0144] In some possible implementations, the preset position 10 is lower than the top surface of the first isolation layer 21, or the preset position 10 is flush with the top surface of the first isolation layer 21. This allows the first isolation layer 21 to be fully exposed after the second isolation layer 22 is subsequently removed, facilitating the deposition of a smooth masking layer on the second conductive layer 9 during the formation of the bit line contact plug.

[0145] In step S111, see Figure 15 The second isolation layer 22 is removed, for example by wet etching or dry etching, to expose the top surface of the first isolation layer 21, so as to form a flat masking layer on the plane formed by the first isolation layer 21 and the second conductive layer 9, thereby forming a complete bit line contact plug in the opening 3.

[0146] In one exemplary embodiment, this disclosure also provides a semiconductor structure, see [link to example]. Figures 5 to 15 As shown, the semiconductor structure is formed using the semiconductor structure formation method of any of the above embodiments.

[0147] The semiconductor structure in this embodiment includes a substrate 1, which includes a plurality of active regions 23 arranged in an array. An opening 3 in the substrate 1 can be used as a bit line contact hole, and the target area 4 exposed by the opening 3 is located in the middle of each active region 23.

[0148] The semiconductor structure in this embodiment is formed using the above-described semiconductor structure formation method, which effectively avoids damage to the semiconductor structure caused by chemical reagents used in the wet cleaning process, thereby improving the electrical performance of the semiconductor structure.

[0149] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0150] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0151] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0152] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0153] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0154] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method for forming the semiconductor structure includes: Provide a base; The substrate is first etched to form an array of openings, the openings exposing a target area of ​​the substrate; The opening was first cleaned using deionized water; A first conductive layer is deposited, which at least covers the sidewalls and bottom surface of the opening; The first conductive layer covering the bottom surface of the opening is doped to form a first implantation layer; The opening is then subjected to a second cleaning to remove the first injection layer, exposing the target area; The exposed target area is oxidized using a chemical substance with strong oxidizing properties to form an oxide layer; The opening is then subjected to a third cleaning to remove the oxide layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Doping the first conductive layer covering the bottom surface of the opening includes: The first conductive layer covering the bottom surface of the opening is doped using ion implantation.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The dopant ions used when doping the first conductive layer covering the bottom surface of the opening with ion implantation include arsenic ions or phosphorus ions.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The method for forming the semiconductor structure further includes: While doping the first conductive layer covering the bottom surface of the opening using ion implantation, an ion implantation damage layer is formed on the surface of the target region located at the bottom of the first conductive layer.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The exposed target area is oxidized using a chemical substance with strong oxidizing properties, including: The target area is oxidized using a solution containing ozone or hydrogen peroxide.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, Both the second and third cleaning methods employ dry cleaning techniques. The dry cleaning process includes a mixture of nitrogen-containing and fluorine-containing gases.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the semiconductor structure further includes: A second conductive layer is deposited, which fills the opening.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The first conductive layer is made of the same material as the second conductive layer.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, Before the first etching of the substrate to form the openings of the array, the method further includes: A first isolation layer and a second isolation layer covering the first isolation layer are deposited on the substrate.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The method for forming the semiconductor structure further includes: The second conductive layer is etched back to the preset position, completely exposing the second isolation layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The preset position is lower than the top surface of the first isolation layer, or the preset position is flush with the top surface of the first isolation layer.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The method for forming the semiconductor structure includes: Remove the second isolation layer to expose the top surface of the first isolation layer.

13. A semiconductor structure, characterized in that, The semiconductor structure is formed using the semiconductor structure forming method as described in any one of claims 1 to 12; The substrate includes several active regions arranged in an array, and the openings in the substrate include bit line contact holes. The target area exposed by the openings is located at the middle position of each of the active regions.

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