Semiconductor device having integrated decoupling features and alignment features

Abstract

This disclosure provides a semiconductor device having integrated decoupling and alignment features. The semiconductor device has a first wafer and a second marker; the first marker includes a first substrate, a decoupling feature, and a plurality of first alignment marks. The first substrate has a dielectric stack, and the decoupling feature is disposed in the dielectric stack below one of the first alignment marks. The plurality of first alignment marks are disposed on the first substrate and are parallel to each other. A second wafer is disposed on the first wafer and includes a plurality of second alignment marks disposed on the plurality of first alignment marks. In a top view, the plurality of second alignment marks are parallel to and adjacent to the plurality of first alignment marks. The plurality of first and second alignment marks include a fluorescent material. The decoupling feature has a bottle-shaped cross-sectional profile and includes a porous low-dielectric-constant material.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Applications No. 17 / 556,149 and No. 17 / 555,712 (i.e., priority date "December 20, 2021"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. More particularly, it relates to a semiconductor device having integrated decoupling features and alignment features. Background Technology

[0004] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasing problems, both in number and complexity. Therefore, the challenge of improving quality, yield, performance, and reliability, while reducing complexity, continues.

[0005] The description of the "prior art" above is only for background information and does not constitute an admission that the description of the "prior art" above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the "prior art" above should be considered part of this disclosure. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device including a first wafer, including a first substrate; and a plurality of first alignment marks disposed on the substrate and parallel to each other; and a second wafer disposed on the first wafer and including a plurality of second alignment marks disposed on the plurality of first alignment marks. In a top view, the plurality of second alignment marks are disposed parallel to and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material. The plurality of first alignment marks and the plurality of second alignment marks are configured together to form a first set of alignment marks.

[0007] Another embodiment of this disclosure provides a semiconductor device including a substrate; a dielectric stack disposed on the substrate; two conductive features disposed in the dielectric stack; a decoupling feature disposed in the dielectric stack between the two second conductive features and including a bottle-shaped cross-sectional profile; and an alignment mark disposed on the decoupling feature. The alignment mark includes a fluorescent material.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a first substrate; forming a plurality of first alignment marks on the first substrate and parallel to each other, wherein the first substrate and the plurality of first alignment marks are configured together on a first wafer; providing a second wafer, the second wafer including a plurality of second alignment marks parallel to each other; and bonding the second wafer to the first wafer. In a top view, the plurality of second alignment marks are disposed parallel to and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming two second conductive features on the second dielectric layer; forming an intermediate dielectric layer on the second dielectric layer and surrounding the two second conductive features; performing an extended etching process to form an extended opening in the intermediate dielectric layer; forming a decoupling feature in the extended opening; and forming an alignment mark on the decoupling feature. The alignment mark includes a fluorescent material.

[0010] Due to the design of the semiconductor device disclosed herein, the plurality of alignment marks, including the fluorescent material, improve optical recognition during the wafer bonding process. Furthermore, during bonding, the complementary design allows the plurality of first alignment marks and the plurality of second alignment marks to become mutually referential. Therefore, the yield and reliability of the semiconductor device can be improved.

[0011] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the same purpose as this disclosure can be achieved quite readily by utilizing the concepts and specific embodiments disclosed below as modifications or designs to other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0013] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0014] Figures 2 to 5This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 6 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0016] Figure 7 and Figure 8 This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Figure 6 The section along line A-A'.

[0017] Figure 9 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0018] Figure 10 This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Figure 9 The section along line A-A'.

[0019] Figure 11 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0020] Figure 12 This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Figure 11 The section along line A-A'.

[0021] Figure 13 This is a top view schematic diagram illustrating a semiconductor element according to another embodiment of the present disclosure.

[0022] Figure 14 This is a flowchart illustrating a method for fabricating a semiconductor element according to another embodiment of the present disclosure.

[0023] Figures 15 to 25 This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0024] Figure 26 This is a cross-sectional schematic diagram illustrating a semiconductor element according to another embodiment of the present disclosure.

[0025] Explanation of reference numerals in the attached figures:

[0026] 1A: Semiconductor components

[0027] 1B: Semiconductor components

[0028] 1C: Semiconductor components

[0029] 1D: Semiconductor components

[0030] 1S: First set of alignment marks

[0031] 10: Preparation method

[0032] 100: First Wafer

[0033] 101: First basement

[0034] 103: First electrical conductivity characteristic

[0035] 105: First alignment mark

[0036] 107: First underlay

[0037] 109: First upper pad

[0038] 2S: Second set of alignment marks

[0039] 20: Preparation method

[0040] 200: Second wafer

[0041] 201: Second basement

[0042] 203: Second conductivity characteristic

[0043] 205: Second alignment mark

[0044] 207: Second underlay

[0045] 209: Second upper pad

[0046] 3S: Third set of alignment marks

[0047] 301: Third basement

[0048] 303: First dielectric layer

[0049] 305: Second dielectric layer

[0050] 307: Intermediate dielectric layer

[0051] 307E: Expanded opening

[0052] 307O: Open

[0053] 309: Third dielectric layer

[0054] 311: Fourth dielectric layer

[0055] 311O: Marking an opening

[0056] 313: Second conductivity characteristic

[0057] 315: Lower Barrier Layer

[0058] 315SW: Sidewall

[0059] 317: Intermediate conductive layer

[0060] 317SW: Sidewall

[0061] 319: Upper Barrier Layer

[0062] 319SW: Sidewall

[0063] 321: Spacer barrier layer

[0064] 323: Decoupling Features

[0065] 323BS: Lower surface

[0066] 323SW: Sidewall

[0067] 323V: Recessed area

[0068] 325: Third alignment mark

[0069] 325BS: Lower surface

[0070] 325TS: Top surface

[0071] 4S: Fourth Alignment Marker

[0072] 5S: Fifth Alignment Marker

[0073] 501: First Material

[0074] 503: Second Material

[0075] 505: Third Material

[0076] 507: Fourth Material

[0077] 509: The Fifth Material

[0078] 511: Isolation Layer

[0079] 601: First mask layer

[0080] 603: Second mask layer

[0081] 605: Third mask layer

[0082] 607: Fourth mask layer

[0083] DS: Dielectric Stack

[0084] S: Direction

[0085] S11: Steps

[0086] S13: Steps

[0087] S15: Steps

[0088] S17: Steps

[0089] S19: Steps

[0090] S21: Steps

[0091] S23: Steps

[0092] S25: Steps

[0093] T1: Thickness

[0094] T2: Thickness

[0095] T3: Thickness

[0096] T4: Thickness

[0097] T5: Thickness

[0098] T6: Thickness

[0099] T7: Thickness

[0100] W1: Width

[0101] W2: Width

[0102] W3: Width

[0103] W4: Width

[0104] W5: Width

[0105] X: Direction

[0106] Y: direction

[0107] Z: Direction Detailed Implementation

[0108] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0109] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0110] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0111] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0112] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term “substantially” may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0113] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0114] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0115] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0116] It should be understood that the functions or steps mentioned in this disclosure may occur in a different order than that shown in the accompanying drawings. For example, two drawings shown consecutively may actually be performed substantially simultaneously, or sometimes in reverse order, depending on the functions or steps included.

[0117] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 5 This is a cross-sectional schematic diagram illustrating part of a process for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figure 6 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 and Figure 8 This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figure 6 The cross-section along line A-A'. It should be understood that, for clarity, some components of semiconductor element 1A are omitted in the top view.

[0118] Please refer to Figures 1 to 3 In step S11, a first substrate 101 may be provided, and a plurality of first conductive features 103 may be formed on the first substrate 101.

[0119] Please refer to Figure 2The first substrate 101 may include a bulk semiconductor substrate, which is entirely composed of at least one semiconductor material, multiple device elements (not shown for clarity), multiple dielectric layers (not shown for clarity), and multiple conductive features (not shown for clarity). For example, the bulk semiconductor substrate may include an elemental semiconductor, a compound semiconductor, or a combination thereof; and the elemental semiconductor may be such as silicon or germanium; the compound semiconductor may be such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors.

[0120] In some embodiments, the first substrate 101 may include an insulator-on-semiconductor structure comprising, from bottom to top, a handle substrate, an isolation layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may contain the same materials as the aforementioned bulk semiconductor substrate. The isolation layer may be a crystalline or amorphous dielectric material, such as an oxide and / or nitride. For example, the isolation layer may be a dielectric oxide, such as silicon oxide. As another example, the isolation layer may be a dielectric nitride, such as silicon nitride or boron nitride. As yet another example, the isolation layer may include a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The isolation layer may have a thickness between approximately 10 nm and approximately 200 nm.

[0121] It should be understood that the term "about" modifies an ingredient, a quantity of a component, or a reactant of this disclosure, indicating a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of the components or the implementation of such methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0122] Please refer to Figure 2 Multiple device elements may be formed on a bulk semiconductor substrate or on the topmost semiconductor material layer. Some portions of the multiple device elements may be formed within the bulk semiconductor substrate or the topmost semiconductor material layer. The multiple device elements may be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect semiconductors, the like, or combinations thereof.

[0123] Please refer to Figure 2 Multiple dielectric layers may be formed on a bulk semiconductor substrate or on the topmost semiconductor material layer, covering multiple device elements. In some embodiments, for example, the multiple dielectric layers may comprise silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, a low-dielectric-constant dielectric material, the like, or combinations thereof. The low-dielectric-constant material may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-dielectric-constant material may have a dielectric constant less than 2.0. The fabrication technique for the multiple dielectric layers may include multiple deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes. Multiple planarization processes may be performed after these deposition processes to remove excess material and provide a generally flat surface for subsequent processing steps.

[0124] Please refer to Figure 2 The multiple conductive features may include multiple interconnect layers and multiple conductive vias. The interconnect layers may be spaced apart from each other and may be horizontally disposed within the multiple dielectric layers along the Z-direction. The conductive vias may connect adjacent interconnect layers along the Z-direction, and connect adjacent device elements to the interconnect layers. In some embodiments, the conductive vias may improve heat dissipation and provide structural support. In some embodiments, for example, the multiple conductive features may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The multiple conductive features may be formed during the formation of the multiple dielectric layers.

[0125] In some embodiments, the plurality of device elements and the plurality of conductive features may be configured together as a plurality of functional units in the first substrate 101. In the description of this disclosure, a functional unit generally represents a functionally related circuit that has been partitioned into a single unit according to its functional purpose. In some embodiments, such functional units may typically be highly complex circuits, such as processor cores, memory controllers, or accelerator units. In some embodiments, the complexity and functionality of a functional circuit may be more or less complex.

[0126] Please refer to Figure 2A first material 501 may be formed on the first substrate 101. In some embodiments, for example, the first material 501 may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. For example, the fabrication technique of the first material 501 may include physical vapor deposition, sputtering, chemical vapor deposition, or other applicable deposition processes.

[0127] Please refer to Figure 2 A first mask layer 601 may be formed on the first material 501. The first mask layer 601 may be a photoresist layer and may include a pattern of a plurality of first conductive features 103.

[0128] Please refer to Figure 3 An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the first material 501, while simultaneously forming a plurality of first conductive features 103 on the first substrate 101. During the etching process, the etch rate ratio of the first material 501 to the first substrate 101 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. After the etching process, the first mask layer 601 can be removed. In some embodiments, the plurality of first conductive features 103 can be electrically coupled to a plurality of device elements, but are not limited thereto. In some embodiments, the plurality of first conductive features 103 can be configured as a test circuit.

[0129] Please refer to Figure 1 and Figure 4 In step S13, a first underpad 107 may be formed to cover the first substrate 101 and a plurality of first conductive features 103.

[0130] Please refer to Figure 4A first underlay 107 can be conformally formed to cover the first substrate 101 and a plurality of first conductive features 103. In some embodiments, for example, the fabrication technique of the first underlay 107 may include atomic layer deposition. Typically, atomic layer deposition involves supplying two (or more) different source gases one after another alternately to a workpiece (e.g., the first substrate 101 and the plurality of first conductive features 103) under multiple predetermined fabrication conditions, so that a plurality of chemical substances are adsorbed onto the workpiece at a single atomic level and deposited on the workpiece via multiple surface reactions. For example, a first and a second source gas are alternately supplied to a workpiece to flow along its surface, whereby a plurality of molecules contained in the first source gas are adsorbed onto the surface, and a plurality of molecules contained in the second source gas react with the molecules adsorbed from the first source gas to form a single-molecule-level film of a certain thickness. The above process steps are repeated to form a high-quality film on the workpiece.

[0131] In some embodiments, for example, the first lower liner 107 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, the like, or combinations thereof. It should be understood that, in the description of this disclosure, silicon oxynitride represents a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide represents a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0132] It should be understood that the first lower pad 107 completely covers the plurality of first conductive features 103, and in Figure 1 The first substrate 101 is for illustrative purposes only, and some first conductive features 103 may be exposed to be electrically coupled to other components.

[0133] Please refer to Figure 1 and Figures 5 to 7 In step S15, a plurality of first alignment marks 105 may be formed between a first underpad 107 and a plurality of first conductive features 103.

[0134] Please refer to Figure 5 An isolation layer 511 may be formed on the first lower liner 107 and completely fill the space between the first conductive features 103. The isolation layer 511 may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, for example, the fabrication technique of the isolation layer 511 may include chemical vapor deposition.

[0135] Please refer to Figure 6 and Figure 7A planarization process, such as chemical mechanical polishing, can be performed until the first underpainting 107 is exposed to remove excess material, providing a generally flat surface for subsequent processing steps, and simultaneously converting the insulating layer 511 into a plurality of first alignment marks 105. In a cross-sectional view, a plurality of first conductive features 103 may horizontally surround a plurality of first alignment marks 105, and the plurality of first alignment marks 105 may be parallel to each other. In a top view, a plurality of first alignment marks 105 located in the upper left region may extend along the Y direction and be parallel to each other. A plurality of first alignment marks 105 located in the upper right region may extend along the X direction and be parallel to each other. A plurality of first alignment marks 105 located in the lower right region may extend along the Y direction and be parallel to each other.

[0136] During the subsequent wafer bonding process, multiple first alignment marks 105, including fluorescent material, can improve optical recognition.

[0137] Please refer to Figure 1 and Figure 8 In step S17, a first upper pad 109 may be formed on a first lower pad 107 and a plurality of first alignment marks 105.

[0138] Please refer to Figure 8 The first upper pad 109 is conformally formed on the first lower pad 107 and the plurality of first alignment marks 105. In some embodiments, for example, the first upper pad 109 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, for example, the fabrication technique of the first upper pad 109 may include atomic layer deposition. The first upper pad 109 may serve as a protective layer to prevent the fluorescent material in the plurality of first alignment marks 105 from being damaged in subsequent semiconductor processes. Furthermore, the first upper pad 109 may serve as a barrier layer to prevent the fluorescent material in the plurality of first alignment marks 105 from diffusing out and contaminating adjacent components.

[0139] A first substrate 101, a plurality of first conductive features 103, a plurality of first alignment marks 105, a first lower pad 107, and a first upper pad 109 are configured together to form a first wafer 100. The first wafer 100 may be configured as a logic chip or a memory chip.

[0140] Figure 9 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 10 This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figure 9 The section along line A-A'. Figure 11 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 12This is a cross-sectional schematic diagram illustrating a portion of a process for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figure 11 The section along line A-A'.

[0141] Please refer to Figure 1 and Figures 9 to 12 In step S19, a second wafer 200 may be provided, and the second wafer 200 may be bonded to the first upper pad 109 to form a semiconductor device 1A.

[0142] Please refer to Figure 9 and Figure 10 The second wafer 200 may include a second substrate 201, a plurality of second conductive features 203, a plurality of second alignment marks 205, a second lower pad 207, and a second upper pad 209. The second substrate 201, the plurality of second conductive features 203, the plurality of second alignment marks 205, the second lower pad 207, and the second upper pad 209 may each contain elements corresponding to similar features as shown below. Figures 2 to 8 The procedure for the first substrate 101, the plurality of first conductive features 103, the plurality of first alignment marks 105, the first lower pad 107, and the first upper pad 109 is described herein, and will not be repeated hereafter.

[0143] In some embodiments, the plurality of second alignment marks 205 may include a fluorescent material. For example, the fluorescent material may be azobenzene. During subsequent wafer bonding processes, the plurality of second alignment marks 205 including the fluorescent material can improve optical recognition.

[0144] In some embodiments, in a cross-sectional view, a plurality of second conductive features 203 may horizontally surround a plurality of second alignment marks 205, and the plurality of second alignment marks 205 may be parallel to each other. In a top view, a plurality of second alignment marks 205 located in the upper left region may extend in the Y direction and be parallel to each other. A plurality of second alignment marks 205 located in the upper right region may extend in the X direction and be parallel to each other. A plurality of second alignment marks 205 located in the lower left region may extend in the X direction and be parallel to each other. A plurality of second alignment marks 205 located in the lower right region may extend in the Y direction and be parallel to each other.

[0145] In some embodiments, the second wafer 200 may be configured as a memory chip.

[0146] Please refer to Figure 11 and Figure 12 The second wafer 200 can be flipped and bonded to the first wafer 100. In some embodiments, for example, the bonding of the second wafer 200 to the first wafer 100 may be via an oxide bonding of a first upper pad 109 containing oxide to an oxide bonding of a second upper pad 209 containing oxide.

[0147] In the top view, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 are arranged complementaryly to each other. That is, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 do not overlap each other. The complementary design allows the plurality of first alignment marks 105 and the plurality of second alignment marks 205 to become mutually referenced during the bonding process. Therefore, the yield and reliability of semiconductor device 1A can be improved.

[0148] In some embodiments, a plurality of first alignment marks 105 and a plurality of second alignment marks 205 located in the upper left region may be represented as a first set of alignment marks 1S. The alignment marks of the first set of alignment marks 1S (e.g., the first alignment marks 105 and the second alignment marks 205) may extend in the direction X and be parallel to each other.

[0149] In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 located in the upper right region may be represented as a second set of alignment marks 2S. The second set of alignment marks 2S may be located away from the first set of alignment marks 1S along the direction X. The alignment marks of the second set of alignment marks 2S may extend along the direction X and be parallel to each other.

[0150] In some embodiments, a plurality of first alignment marks 105 and a plurality of second alignment marks 205 located in the lower left region may be represented as a third set of alignment marks 3S. The third set of alignment marks 3S may be located away from the first set of alignment marks 1S along the Y direction. The alignment marks of the third set of alignment marks 3S may extend along the X direction and be parallel to each other.

[0151] In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 located in the lower right region may be represented as a fourth set of alignment marks 4S. The fourth set of alignment marks 4S may be located away from the first set of alignment marks 1S along a direction S. The direction S may be tilted relative to directions X and Y. The alignment marks of the fourth set of alignment marks 4S may extend along direction Y and be parallel to each other.

[0152] Figure 13 This is a top view schematic diagram illustrating a semiconductor element 1B according to another embodiment of the present disclosure.

[0153] Please refer to Figure 13 Semiconductor element 1B may have similar characteristics to, for example... Figure 11 The aforementioned structure. In Figure 13 The same or similar to Figure 11 The components have been labeled with similar component numbers, and their repetitive descriptions have been omitted. Semiconductor component 1B may include a fifth set of alignment marks 5S. The fifth set of alignment marks 5S may be located away from the first set of alignment marks 1S along the direction S. The alignment marks of the fifth set of alignment marks 5S (e.g., the first alignment marks 105 and the second alignment marks 205) may extend along the direction X and be parallel to each other.

[0154] Figure 14 This is a flowchart illustrating a method 20 for fabricating a semiconductor element 1C according to another embodiment of the present disclosure. Figures 15 to 25 This is a cross-sectional schematic diagram illustrating part of a process for fabricating a semiconductor device 1C according to another embodiment of the present disclosure.

[0155] Please refer to Figures 14 to 18 In step S21, a third substrate 301 may be provided, a first dielectric layer 303 may be formed on the third substrate 301, a second dielectric layer 305 may be formed on the first dielectric layer 303, and a plurality of second conductive features 313 may be formed on the second dielectric layer 305.

[0156] Please refer to Figure 15 The third substrate 301 may contain components similar to, for example Figure 2 The procedure of the first substrate 101 is described herein, and its description will not be repeated here.

[0157] Please refer to Figure 15 In some embodiments, for example, the first dielectric layer 303 may comprise fluorosilicate glass, borosilicate glass, a spin-coated low-dielectric-constant dielectric layer, a chemical vapor-deposited low-dielectric-constant dielectric layer, or a combination thereof. In some embodiments, the first dielectric layer 303 may comprise a self-planarizing material or a spin-coated dielectric material, wherein the self-planarizing material is, for example, a spin-coated glass, and the spin-coated low-dielectric-constant dielectric material is, for example, SiLK. TM The use of a self-planarizing dielectric material avoids the need for a further planarization step. In some embodiments, the fabrication technique of the first dielectric layer 303 may include a deposition process, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0158] Please refer to Figure 15 In some embodiments, for example, the second dielectric layer 305 may comprise silicon nitride, silicon oxynitride, silicon oxynitride, the like, or combinations thereof. For example, the fabrication technique of the second dielectric layer 305 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, the second dielectric layer 305 may serve as a barrier layer to prevent moisture from penetrating multiple underlying layers (e.g., the first dielectric layer 303 and the third substrate 301). In some embodiments, the thickness T1 of the first dielectric layer 303 is greater than the thickness T2 of the second dielectric layer 305.

[0159] Please refer to Figure 15A second material 503 may be formed on the second dielectric layer 305. For example, the second material 503 may be titanium, titanium nitride, tantalum, tantalum nitride, or the like. For example, the fabrication technique of the second material 503 may include chemical vapor deposition, physical vapor deposition, sputtering, or similar processes. A third material 505 may be formed on the second material 503. For example, the third material 505 may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. For example, the fabrication technique of the third material 503 may include physical vapor deposition, sputtering, or similar processes. A fourth material 507 may be formed on the third material 505. In some embodiments, the fourth material 507 and the second material 503 may include the same material. In some embodiments, for example, the fourth material 507 may be titanium, titanium nitride, tantalum, tantalum tantalide, or the like. For example, the fabrication technology of the fourth material 507 in this layer may include chemical vapor deposition, physical vapor deposition, sputtering or similar processes.

[0160] Please refer to Figure 15 A second mask layer 603 may be formed on the fourth material 507. The second mask layer 603 may be a photoresist layer and may include a pattern of a plurality of second conductive features 313.

[0161] Please refer to Figure 16 An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the second material 503, the third material 503, and the fourth material 507. After the etching process, the remaining second material 503 can be represented as a plurality of lower barrier layers 315, the remaining third material 505 can be represented as a plurality of intermediate conductive layers 317, and the remaining fourth material 507 can be represented as a plurality of upper barrier layers 319. In some embodiments, the etching process can be a multi-step etching process and can be anisotropic.

[0162] For the sake of brevity, clarity, and ease of description, only a lower barrier layer 315, an intermediate conductive layer 317, and an upper barrier layer 319 are described. In some embodiments, the thickness T3 of the lower barrier layer 315 and the thickness T4 of the upper barrier layer 319 may be approximately the same. In some embodiments, the thickness T3 of the lower barrier layer 315 may be greater than the thickness T4 of the upper barrier layer 319. In some embodiments, the thickness T5 of the intermediate conductive layer 317 may be greater than the thickness T3 of the lower barrier layer 315 or the thickness T4 of the upper barrier layer 319.

[0163] Please refer to Figure 17 A fifth material 509 can be conformally formed in such a layer Figure 16On the intermediate semiconductor element. For example, the fifth material 509 may be titanium, titanium nitride, tantalum, tantalum nitride, or the like. For example, the fabrication technique of the fourth material 507 layer may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, or similar processes. In some embodiments, the fifth material 509 and the upper barrier layer 319 may include the same material.

[0164] Please refer to Figure 18 A process, such as an anisotropic dry etching process, can be performed to remove portions of the fifth material 509. After the etching process, the remaining fifth material 509 can be represented as a plurality of spacer barrier layers 321. A plurality of spacer barrier layers 321 can be formed to cover the sidewalls 319SW of the upper barrier layer 319, the sidewalls 317SW of the intermediate conductive layer 317, and the sidewalls 315SW of the lower barrier layer 315.

[0165] Multiple spacer barrier layers 321, multiple upper barrier layers 319, multiple intermediate conductive layers 317, and multiple lower barrier layers 315 are configured together to form multiple second conductive features 313.

[0166] Please refer to Figure 14 and Figures 19 to 22 In step S23, an intermediate dielectric layer 307 may be formed on the second dielectric layer 305 and surround a plurality of second conductive features 313, and a plurality of decoupling features 323 may be formed in the intermediate dielectric layer 307.

[0167] Please refer to Figure 19 An intermediate dielectric layer 307 may be formed on the second dielectric layer 305 and cover a plurality of second conductive features 313. A planarization process, such as chemical mechanical polishing, may be performed until the upper surfaces of the plurality of second conductive features 313 are exposed to remove excess material and provide a generally flat surface for subsequent processing steps. In some embodiments, the intermediate dielectric layer 307 may comprise a material having a different etch rate relative to the second dielectric layer 305. In some embodiments, for example, the intermediate dielectric layer 307 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorosilicate glass, borosilicate glass, or a combination thereof. In some embodiments, for example, the fabrication technique of the intermediate dielectric layer 307 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0168] It should be understood that, in the description of this disclosure, a surface of an element (or feature) located at the highest vertical plane along the Z-direction is referred to as an upper surface of the element (or feature). A surface of an element (or feature) located at the lowest vertical plane along the Z-direction is referred to as a lower surface of the element (or feature).

[0169] Please refer to Figure 19A third mask layer 605 may be formed on the intermediate dielectric layer 307. In some embodiments, the third mask layer 605 may be a photoresist layer and may include a pattern of a plurality of decoupling features 323.

[0170] Please refer to Figure 20 An anisotropic etching process can be performed to remove portions of the intermediate dielectric layer 307 and simultaneously form a plurality of openings 307O. In some embodiments, the anisotropic etching process may be an anisotropic dry etching process. In some embodiments, during the anisotropic etching, the etch rate of the intermediate dielectric layer 307 to the second dielectric layer 305 may be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1.

[0171] Please refer to Figure 21 An extended etching process can be performed to extend the plurality of openings 307O into a plurality of extended openings 307E. In some embodiments, the extended etching process may be an isotropic etching process. In some embodiments, the extended etching process may be a wet etching process. In some embodiments, between extended etching processes, the etch rate of the intermediate dielectric layer 307 to the second dielectric layer 305 may be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. In some embodiments, the sidewalls of the plurality of extended openings 307E may be curved.

[0172] Please refer to Figure 22 The third mask layer 605 can be removed, an isolation material can be deposited to completely fill the plurality of extended openings 307E, and a planarization process, such as chemical mechanical polishing, can then be performed until the upper surfaces of the plurality of second conductive features 313 are exposed to remove excess material, providing a generally flat surface for subsequent processing steps, and simultaneously forming the plurality of decoupling features 323. In some embodiments, the plurality of decoupling features 323 may have a bottle-shaped cross-sectional profile.

[0173] In some embodiments, for example, the insulating material may be a porous material with a low dielectric constant.

[0174] In some embodiments, the insulating layer may be an energy-removable material. The energy-removable material may include a material such as a thermally degradable material, a photodegradable material, an electron beam degradable material, or a combination thereof. For example, the energy-removable material may include a base material and a degradable porous material that is sacrificially removed upon exposure to an energy source. The base material may include a methylsilsesquioxane-based material. The degradable porous material may include a porous organic compound that provides porosity to the base material of the energy-removable material. After the planarization process, an energy treatment is performed by providing an energy source. The energy treatment may include heat, light, or a combination thereof. When heat is used as the energy source, a temperature for the energy treatment may be between approximately 800°C and approximately 900°C. When light is used as the energy source, ultraviolet light may be provided. The energy treatment may remove the degradable porous material from the energy-removable material to create multiple empty spaces (pores), while the base material remains in situ. The space (hole) of such space can reduce the dielectric constant of multiple decoupling features 323.

[0175] Please refer to Figure 22 Multiple decoupling features 323 may be formed, respectively and correspondingly, between adjacent pairs of second conductive features 313. In some embodiments, multiple decoupling features 323 having a low dielectric constant may implement decoupling feature functionality. In some embodiments, multiple decoupling features 323 may reduce the parasitic capacitance of multiple second conductive features 313.

[0176] Please refer to Figure 14 and Figures 23 to 25 In step S25, a third dielectric layer 309 may be formed on the intermediate dielectric layer 307, a fourth dielectric layer 311 may be formed on the third dielectric layer 309, and a plurality of third alignment marks 325 may be formed on a plurality of decoupling features 232.

[0177] Please refer to Figure 23 In some embodiments, for example, the third dielectric layer 309 may comprise fluorosilicate glass, borosilicate glass, a spin-coated low-dielectric-constant dielectric layer, a chemical vapor deposition low-dielectric-constant dielectric layer, or a combination thereof. In some embodiments, the third dielectric layer 309 may comprise a self-planarizing material or a spin-coated dielectric material, wherein the self-planarizing material is, for example, a spin-coated glass, and the spin-coated low-dielectric-constant dielectric material is, for example, SiLK. TMThe use of a self-planarizing dielectric material avoids the need for a further planarization step. In some embodiments, for example, the fabrication technique of the third dielectric layer 309 may include a deposition process, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, the third dielectric layer 309 and the first dielectric layer 303 may contain the same material.

[0178] Please refer to Figure 23 In some embodiments, for example, the fourth dielectric layer 311 may comprise silicon nitride, silicon oxynitride, silicon oxynitride, the like, or combinations thereof. For example, the fabrication technique of the fourth dielectric layer 311 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, the fourth dielectric layer 311 may serve as a barrier layer to prevent moisture from penetrating multiple underlying layers (e.g., the third dielectric layer 309 and the intermediate dielectric layer 307). In some embodiments, the thickness T6 of the third dielectric layer 309 is greater than the thickness T7 of the fourth dielectric layer 311.

[0179] Please refer to Figure 23 The first dielectric layer 303, the second dielectric layer 305, the intermediate dielectric layer 307, the third dielectric layer 309, and the fourth dielectric layer 311 can be configured together as a dielectric stack DS.

[0180] Please refer to Figure 23 A fourth mask layer 607 may be formed on the dielectric stack DS. The fourth mask layer 607 may be a photoresist layer and may include a pattern of multiple third alignment marks 325.

[0181] Please refer to Figure 24 An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the fourth dielectric layer 311, portions of the third dielectric layer 309, and portions of the multiple decoupling features 323 to form multiple marker openings 311O. Each sidewall of the multiple marker openings 311O may be tapered.

[0182] Please refer to Figure 25 An isolation layer can be formed to completely fill the plurality of marker openings 311O. The isolation layer may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, for example, the fabrication technique of the isolation layer may include chemical vapor deposition. A planarization process, such as chemical mechanical polishing, may be performed until the fourth dielectric layer 311 is exposed to remove excess material, provide a generally flat surface for subsequent processing steps, and simultaneously convert the isolation layer into a plurality of third alignment marks 325. Since the contours of the plurality of third alignment marks 325 are defined by the plurality of marker openings 311O, each sidewall of the plurality of third alignment marks 325 may be tapered.

[0183] For the sake of brevity, clarity and ease of description, only a decoupling feature 323 and a third alignment mark 325 will be described.

[0184] In some embodiments, the width W1 between the two recesses 323V of the sidewalls 323SW of the decoupling feature 232 may be greater than the width W2 of the upper surface 325TS of the third alignment mark 325. In some embodiments, the width W2 of the upper surface 325TS of the third alignment mark 325 may be greater than the width W3 of the third alignment mark 325 at an interface between the intermediate dielectric layer 307 and the third dielectric layer 309. In some embodiments, the width W3 of the third alignment mark 325 at an interface between the intermediate dielectric layer 307 and the third dielectric layer 309 may be greater than the width W4 of the lower surface 325BS of the third alignment mark 325. In some embodiments, the width W3 of the third alignment mark 325 at an interface between the intermediate dielectric layer 307 and the third dielectric layer 309 may be greater than the width W5 of the lower surface 323BS of the decoupling feature 323. In some embodiments, the width ratio between width W1 and width W5 may be between approximately 1.5:1 and approximately 1.1:1 or between approximately 1.3:1 and approximately 1.1:1.

[0185] Multiple third alignment marks 325, including fluorescent materials, can improve optical recognition in subsequent wafer bonding processes.

[0186] Figure 26 This is a cross-sectional schematic diagram illustrating a semiconductor element according to another embodiment of the present disclosure.

[0187] Please refer to Figure 26 Semiconductor element 1D can have similar characteristics to, for example... Figure 25 The aforementioned structure. In Figure 26 The same or similar to Figure 25 The components have been labeled with similar component numbers, and their redundant descriptions have been omitted.

[0188] In semiconductor element 1D, the lower surface 325BS of the third alignment mark 325 may be disposed on the decoupling feature 323, rather than extending to the decoupling feature 323.

[0189] One embodiment of this disclosure provides a semiconductor device including a first wafer, including a first substrate; and a plurality of first alignment marks disposed on the substrate and parallel to each other; and a second wafer disposed on the first wafer and including a plurality of second alignment marks disposed on the plurality of first alignment marks. In a top view, the plurality of second alignment marks are disposed parallel to and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material. The plurality of first alignment marks and the plurality of second alignment marks are configured together to form a first set of alignment marks.

[0190] Another embodiment of this disclosure provides a semiconductor device including a substrate; a dielectric stack disposed on the substrate; two conductive features disposed in the dielectric stack; a decoupling feature disposed in the dielectric stack between the two second conductive features and including a bottle-shaped cross-sectional profile; and an alignment mark disposed on the decoupling feature. The alignment mark includes a fluorescent material.

[0191] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a first substrate; forming a plurality of first alignment marks on the first substrate and parallel to each other, wherein the first substrate and the plurality of first alignment marks are configured together on a first wafer; providing a second wafer, the second wafer including a plurality of second alignment marks parallel to each other; and bonding the second wafer to the first wafer. In a top view, the plurality of second alignment marks are disposed parallel to and adjacent to the plurality of first alignment marks. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

[0192] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming two second conductive features on the second dielectric layer; forming an intermediate dielectric layer on the second dielectric layer and surrounding the two second conductive features; performing an extended etching process to form an extended opening in the intermediate dielectric layer; forming a decoupling feature in the extended opening; and forming an alignment mark on the decoupling feature. The alignment mark includes a fluorescent material.

[0193] Due to the design of the semiconductor device disclosed herein, the plurality of alignment marks 105, 205, and 325, including the fluorescent material, can improve optical recognition during the wafer bonding process. Furthermore, during bonding, the complementary design makes the plurality of first alignment marks 105 and the plurality of second alignment marks 205 mutually referential. Therefore, the yield and reliability of the semiconductor device 1A can be improved.

[0194] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be used to replace many of the processes described above.

[0195] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A first wafer, comprising: A first basis; and Multiple first alignment marks are disposed on the substrate and are parallel to each other; and A decoupling feature is disposed below one of the first alignment marks and located in the dielectric stack and having a bottle-shaped profile, wherein the decoupling feature comprises a porous low dielectric constant material; A second wafer, disposed on the first wafer, and comprising: Multiple second alignment marks are set on the multiple first alignment marks; In the top view, the plurality of second alignment marks are set parallel to and adjacent to the plurality of first alignment marks; The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material; The plurality of first alignment marks, together with the plurality of second alignment marks, are configured into a first set of alignment marks.

2. The semiconductor device of claim 1, wherein the fluorescent material comprises azobenzene.

3. The semiconductor element of claim 2, further comprising a second set of alignment marks separated from the first set of alignment marks along a first direction; wherein the first set of alignment marks extends along a second direction perpendicular to the first direction, and the second set of alignment marks extends along the first direction.

4. The semiconductor element of claim 3, further comprising a third set of alignment marks separated from the first set of alignment marks along the second direction; wherein the third set of alignment marks extends along the first direction.

5. The semiconductor element of claim 4, further comprising a fourth set of alignment marks separated from the first set of alignment marks along a direction inclined relative to the first direction and the second direction; wherein the fourth set of alignment marks extends along the second direction.

6. The semiconductor element of claim 4, further comprising a fifth set of alignment marks separated from the first set of alignment marks along a direction inclined relative to the first direction and the second direction; wherein the fifth set of alignment marks extends along the first direction.

7. The semiconductor device of claim 2, wherein the first wafer includes a plurality of first conductive features disposed perpendicularly around the plurality of first alignment marks.

8. The semiconductor device of claim 7, wherein the first wafer includes a first underpad disposed between the plurality of first conductive features and the plurality of first alignment marks.

9. The semiconductor device of claim 8, wherein the first wafer includes a first upper pad disposed on the plurality of first alignment marks and on the first lower pad.

10. The semiconductor device of claim 9, wherein the second wafer includes a second upper pad disposed between the plurality of second alignment marks and the first upper pad.

11. The semiconductor device of claim 10, wherein the second wafer includes a plurality of second conductive features perpendicularly surrounding the plurality of second alignment marks and disposed on the second upper pad.

12. The semiconductor device of claim 11, wherein the second wafer includes a second lower pad disposed between the plurality of second alignment marks and the plurality of second conductive features, and between the plurality of second conductive features and the second upper pad.

13. The semiconductor device of claim 2, wherein the first wafer is configured as a plurality of logic chips and the second wafer is configured as a plurality of memory chips.

14. The semiconductor device of claim 2, wherein the first wafer is configured as a plurality of memory chips, and the second wafer is configured as a plurality of memory chips.

15. The semiconductor device of claim 11, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer, an intermediate dielectric layer, a third dielectric layer, and a fourth dielectric layer, the first dielectric layer being disposed on the substrate, the second dielectric layer being disposed on the first dielectric layer, the intermediate dielectric layer being disposed on the second dielectric layer, the third dielectric layer being disposed on the intermediate dielectric layer, the fourth dielectric layer being disposed on the third dielectric layer, and the plurality of second conductive features and the decoupling feature being disposed in the intermediate dielectric layer.

16. The semiconductor device of claim 15, wherein the alignment mark is disposed along the fourth dielectric layer and the third dielectric layer, and is disposed on the decoupling feature.

17. The semiconductor device of claim 15, further comprising a third set of alignment marks, wherein the third set of alignment marks is disposed along the fourth dielectric layer and the third dielectric layer and extends to the decoupling feature.

18. The semiconductor element of claim 15, further comprising a third set of alignment marks, wherein a width between two recesses of the plurality of sidewalls of the decoupling feature is greater than a width of an upper surface of the third set of alignment marks.

19. A method for fabricating a semiconductor element, comprising: A first substrate is provided, the first substrate having a dielectric stack; A decoupling feature is formed in the dielectric stack, and the decoupling feature has a bottle-shaped cross-sectional profile, wherein the decoupling feature includes a porous low dielectric constant material. A plurality of first alignment marks are formed on the decoupling feature of the first substrate and are parallel to each other, wherein the first substrate and the plurality of first alignment marks are configured together to form a first wafer; A second wafer is provided, the second wafer including a plurality of mutually parallel second alignment marks; and The second wafer is bonded to the first wafer; In the top view, the plurality of second alignment marks are set parallel to and adjacent to the plurality of first alignment marks; The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

20. The method for fabricating a semiconductor element as claimed in claim 19, wherein the fluorescent material comprises azobenzene, and the plurality of first alignment marks and the plurality of second alignment marks are configured together to form a first set of alignment marks.

21. The method of fabricating a semiconductor element as claimed in claim 20, further comprising forming a second set of alignment marks separated from the first set of alignment marks along a first direction; wherein the first set of alignment marks extends along a second direction perpendicular to the first direction, and the second set of alignment marks extends along the first direction.

22. The method of fabricating a semiconductor element as claimed in claim 21, further comprising forming a third set of alignment marks separated from the first set of alignment marks along the second direction; wherein the third set of alignment marks extends along the first direction.

23. The method for fabricating a semiconductor element as claimed in claim 22, further comprising forming a fourth set of alignment marks separated from the first set of alignment marks along a direction inclined relative to the first direction and the second direction; wherein the fourth set of alignment marks extends along the second direction.

24. The method of fabricating a semiconductor element as claimed in claim 22, further comprising forming a fifth set of alignment marks separated from the first set of alignment marks along a direction inclined relative to the first direction and the second direction; wherein the fifth set of alignment marks extends along the first direction.

25. The method for fabricating a semiconductor element as claimed in claim 20, wherein the first wafer includes a plurality of first conductive features disposed perpendicularly around the plurality of first alignment marks.

26. The method for fabricating a semiconductor element as claimed in claim 25, wherein the first wafer includes a first underpad disposed between the plurality of first conductive features and the plurality of first alignment marks.

27. The method of fabricating a semiconductor device as claimed in claim 26, wherein the first wafer includes a first upper pad disposed on the plurality of first alignment marks and on the first lower pad.

28. The method for fabricating a semiconductor device as claimed in claim 27, wherein the second wafer includes a second upper pad disposed between the plurality of second alignment marks and the first upper pad.

29. The method of fabricating a semiconductor element as claimed in claim 28, wherein the second wafer includes a plurality of second conductive features perpendicularly surrounding the plurality of second alignment marks and disposed on the second upper pad.

30. The method for fabricating a semiconductor element as claimed in claim 29, wherein the second wafer includes a second lower pad disposed between the plurality of second alignment marks and the plurality of second conductive features, and between the plurality of second conductive features and the second upper pad.

31. The method for fabricating a semiconductor element as claimed in claim 20, wherein the first wafer is configured as a plurality of logic chips, and the second wafer is configured as a plurality of memory chips.

32. The method for fabricating a semiconductor element as claimed in claim 20, wherein the first wafer is configured as a plurality of memory chips, and the second wafer is configured as a plurality of memory chips.

33. The method for fabricating a semiconductor device as claimed in claim 29, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer, an intermediate dielectric layer, a third dielectric layer, and a fourth dielectric layer, the first dielectric layer being disposed on the substrate, the second dielectric layer being disposed on the first dielectric layer, the intermediate dielectric layer being disposed on the second dielectric layer, the third dielectric layer being disposed on the intermediate dielectric layer, the fourth dielectric layer being disposed on the third dielectric layer, and the plurality of second conductive features and the decoupling feature being disposed in the intermediate dielectric layer.

34. The method of fabricating a semiconductor element as claimed in claim 33, wherein the alignment mark is disposed along the fourth dielectric layer and the third dielectric layer, and is disposed on the decoupling feature.

35. The method of fabricating a semiconductor element as claimed in claim 33, further comprising forming a third set of alignment marks, wherein the third set of alignment marks is disposed along the fourth dielectric layer and the third dielectric layer, and extends to the decoupling feature.

36. The method of fabricating a semiconductor element as claimed in claim 33, further comprising forming a third set of alignment marks, wherein a width between two recesses of a plurality of sidewalls of the decoupling feature is greater than a width of an upper surface of the third set of alignment marks.

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